A universal data acquisition and signal processing system and processing method thereof

Abstract

The invention relates to a universal data acquisition and signal processing system and a processing method thereof, belonging to the fields of data acquisition and dynamic storage technology and signal processing technology. Specifically, a data acquisition card is connected to a host computer, a signal output end of a voltage follower circuit in the data acquisition card is connected to a signal input end of a first-order low-pass filter circuit, the signal output end of the first-order low-pass filter circuit is connected to an A / D conversion circuit, the signal output end of the A / D conversion circuit is connected to a signal input end of an FPGA control unit, a Flash storage circuit and an RS485 communication circuit are further connected to the signal input end of the FPGA control unit, a USB communication circuit is connected to the signal output end of the FPGA control unit, and an energy storage battery power supply device is further connected to the data acquisition card. The invention is suitable for different test needs, and realizes functions such as high-precision signal acquisition, signal processing, display, communication with a host computer, and portable storage.

Description

Technical Field

[0001] The invention relates to a universal data acquisition and signal processing system and a processing method thereof, belonging to the technical fields of data acquisition and dynamic storage technology and signal processing technology. Background Art

[0002] Data acquisition technology is widely used as an engineering method to obtain parameter data such as environment and equipment. It has entered various fields such as industrial sites, geological surveys, medical equipment, electronic communications, and aerospace. Some important parameter testing and acquisition determine the performance of the entire system. Data acquisition (DAQ) refers to the automatic collection of non-electrical or electrical signals from analog and digital units such as sensors and other devices under test, and sending them to the host computer for analysis and processing.

[0003] At present, there are many general-purpose data acquisition devices, such as China Patent Publication (Public) No.: CN102176210B, named "A general data acquisition system", which is mainly aimed at data acquisition of mining electromechanical equipment. China Patent Publication (Public) No.: CN103336667A, named "A general multi-channel data acquisition system", does not have flexible configuration in terms of measurement voltage range and sampling frequency. Some data acquisition occasions require flexible filter settings, but most data acquisition devices currently use hardware for filtering, which increases the cost of the equipment and has a single method. In addition, although most data acquisition devices use a combination of data acquisition cards and host computers, the user interface is relatively simple, which is inconvenient for staff to monitor data.

[0004] An important indicator of data acquisition technology is the data transmission rate. The transmission rate through the serial port is too slow. Although the transmission rate through the PCI bus is very fast, the development difficulty is too great. At present, the USB interface is widely used for data transmission. Many USB interface chips such as CY7C68013 can reach a speed of 480 Mbps (in high-speed mode), but it is difficult to write firmware for different operating systems, which increases the development cycle and reduces program portability.

[0005] In some measurement situations where it is inconvenient to connect to a microcomputer, the data storage device is required to have a large storage capacity and a fast storage rate. This requires the data acquisition storage device to be able to record data for a long time. Summary of the invention

[0006] In order to solve the technical problems existing in the prior art, the present invention provides a universal data acquisition and signal processing system and its processing method which are suitable for different test needs and realize functions such as high-precision signal acquisition, signal processing, display, communication with a host computer and portable storage.

[0007] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is a universal data acquisition and signal processing system, including a host computer and an energy storage battery power supply device, the host computer is connected to a data acquisition card, the data acquisition card includes a voltage follower circuit, a first-order low-pass filter circuit, an A / D conversion circuit, an FPGA control unit, a Flash storage circuit, an RS485 communication circuit and a USB communication circuit, the signal output end of the voltage follower circuit is connected to the signal input end of the first-order low-pass filter circuit, the signal output end of the first-order low-pass filter circuit is connected to the A / D conversion circuit, the signal output end of the A / D conversion circuit is connected to the signal input end of the FPGA control unit, the signal input end of the FPGA control unit is also connected to the Flash storage circuit and the RS485 communication circuit, the signal output end of the FPGA control unit is connected to the USB communication circuit, the USB communication circuit is used to transmit the collected data, Flash storage data and RS485 bus data to the host computer, the data acquisition card is also connected to the energy storage battery power supply device, and the energy storage battery power supply device is used to power the data acquisition card when it does not use the power provided by the host computer.

[0008] Preferably, the voltage follower circuit and the first-order low-pass filter circuit both use high-speed, low-noise operational amplifiers to process 8-channel input signals.

[0009] Preferably, the A / D conversion circuit is used to implement 8-channel signal sampling, the data acquisition bit number is 12 bits plus a sign bit, the maximum sampling rate is 1MHZ, the sampling rate is adjustable, and the measured voltage range has four options: ±10V, ±5V, ±2.5V and a unipolar input range of 0V~+10V.

[0010] Preferably, the FPGA control unit adopts XC3S400 of XILINX company.

[0011] Preferably, the Flash storage circuit has 32GB of storage space, which is used to store the collected data into the Flash storage circuit when the acquisition card is not connected to a host computer.

[0012] Preferably, the RS485 communication circuit serves as a bus interface expansion function, and is used to implement data input of one RS485 bus and data output of one RS485 bus.

[0013] Preferably, the host computer has a virtual oscilloscope function and can directly print and record data.

[0014] A universal data acquisition and signal processing method includes the above-mentioned universal data acquisition and signal processing system, wherein the host computer realizes data reading and writing of the USB interface through a dynamic link library, and is specifically carried out according to the following steps:

[0015] The host computer opens the USB device by accessing the FT_OpenEx function and returns a handle, through which subsequent functions identify the USB device;

[0016] Read a byte array of a specified length from an interface chip in the USB communication circuit by accessing the FT_Read function;

[0017] Sending a byte array of a specified length to the interface chip in the USB communication circuit by accessing the FT_Write function;

[0018] Accessing the FT_Purge function to clear the sending and receiving buffers of the interface chip in the USB communication circuit;

[0019] The status information of the interface chip in the USB communication circuit is obtained by accessing the FT_GetStatus function.

[0020] Preferably, the host computer realizes flexible FIR filtering processing by setting filtering parameters by the user. Taking low-pass FIR filtering as an example, the user sets the sampling period of the signal through the host computer. , Stopband attenuation index , stopband edge frequency , passband edge frequency , cutoff frequency , transition bandwidth , filter order (in is the exponential attenuation through the stopband After determining the window function, look up the table to obtain it), and the filter sequence is determined by the window function and the filter order , the filter sequence To quantify: , after filtering output .

[0021] Compared with the prior art, the present invention has the following technical effects: the present invention has the advantages of strong versatility, high sampling rate, variable sampling rate, fast transmission rate, large storage capacity, flexible configuration of FIR filter, high cost performance and easy use. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is an overall block diagram of the universal data acquisition and signal processing system of the present invention.

[0023] Figure 2 It is the principle diagram of the A / D conversion circuit in the present invention.

[0024] Figure 3 It is the principle diagram of the USB communication circuit in the present invention.

[0025] Figure 4 The upper computer program flow chart of the present invention is

[0026] Figure 5 This is the Flash storage data frame format in the present invention.

[0027] Figure 6 This is a flow chart of the upper computer realizing the FIR filter in the present invention. DETAILED DESCRIPTION

[0028] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] like Figure 1 As shown, a universal data acquisition and signal processing system includes a host computer and an energy storage battery power supply device, the host computer is connected to a data acquisition card, the data acquisition card includes a voltage follower circuit, a first-order low-pass filter circuit, an A / D conversion circuit, an FPGA control unit, a Flash storage circuit, an RS485 communication circuit and a USB communication circuit, the signal output end of the voltage follower circuit is connected to the signal input end of the first-order low-pass filter circuit, the signal output end of the first-order low-pass filter circuit is connected to the A / D conversion circuit, the signal output end of the A / D conversion circuit is connected to the signal input end of the FPGA control unit, the signal input end of the FPGA control unit is also connected to the Flash storage circuit and the RS485 communication circuit, the signal output end of the FPGA control unit is connected to the USB communication circuit, the USB communication circuit is used to transmit the collected data, the Flash storage data and the RS485 bus data to the host computer, the data acquisition card is also connected to the energy storage battery power supply device, the energy storage battery power supply device is used to power the data acquisition card when it does not use the power provided by the host computer.

[0030] The energy storage battery power supply device outputs 5V voltage and connects to the power interface of the data acquisition card. After the user presses the "portable mode" button, the data acquisition card samples according to the default 8-channel cyclic acquisition and a single-channel 120kHz sampling rate, and stores the A / D conversion data in a Flash storage circuit according to a certain frame format. The frame format is as follows: Figure 5 As shown. A0 is the frame header, BD is the frame tail, ~ It is the high byte of A / D conversion for channels 0~7. ~ It is the high byte of A / D conversion for channels 0~7.

[0031] Among them, the voltage follower circuit and the first-order low-pass filter circuit both use high-speed, low-noise operational amplifiers to process 8-channel input signals. The A / D conversion circuit is used to realize 8-channel signal sampling. The data acquisition bit number is 12 bits plus the sign bit. The maximum sampling rate is 1MHZ. The sampling rate is adjustable. The measured voltage range has four options: ±10V, ±5V, ±2.5V, and unipolar input range 0V~+10V. The FPGA control unit uses XILINX's XC3S400. The Flash uses Samsung's NAND FlashK9WBG08U1M. The storage circuit has 32GB storage space. When the acquisition card is not connected to the host computer, it is used to store the collected data in the Flash storage circuit. The RS485 communication circuit uses MAX3087 as a bus interface expansion function. The full speed can reach 10Mbps, which is used to realize the data input of one RS485 bus and the data output of one RS485 bus.

[0032] like Figure 2 As shown in the figure, in the A / D conversion circuit, CS is the chip select pin of AD7328, SCLK is the clock pin of AD7328, DIN is the data input pin of AD7328, the controller writes control commands to the internal register of AD7328 through this pin, and DOUT is the serial output pin after the analog-to-digital conversion of AD7328. These four pins of AD7328 are connected to the FPGA control unit to realize the A / D conversion function.

[0033] like Figure 3 As shown, the USB communication circuit uses FTDI's FT232H, which is a USB interface chip, and 93LC56B is an EEPROM. The EEPROM can be used to configure the communication mode of FT232H, and can also configure OEM information such as the VID, PID, and product description string of the USB device. This chip eliminates the tedious driver development and firmware writing, and can be downloaded directly from the official website. Its speed can reach 12Mbps in full-speed mode, 480Mbps in high-speed mode, and 8MBps in asynchronous 245FIFO mode.

[0034] like Figure 4As shown in the figure, it is the program flow chart of the host computer. After the program is initialized and reset, the user sets the sampling point of the analog signal, the FIR filter, and the baud rate and frame flag of the RS-485 bus signal through the host computer. After starting the test and data receiving commands, the lower computer packages the data of the analog signal and the RS-485 bus signal data and uploads them to the host computer via USB. The analog acquisition signal obtained after decoding by the host computer is displayed after FIR filtering, and the RS-485 data is displayed in frames. At the same time, the sampling rate of the analog acquisition signal can be adjusted through the sampling rate slider on the display interface to make the sampling rate suitable for different sampling requirements.

[0035] The specific data acquisition and signal processing method is as follows. The host computer is written in VB. The host computer realizes data reading and writing of USB interface through dynamic link library. The specific steps are as follows: the host computer opens the USB device by accessing FT_OpenEx function and returns a handle. Subsequent functions identify the USB device through the handle; reads a byte array of specified length from the interface chip in the USB communication circuit by accessing FT_Read function; sends a byte array of specified length to the interface chip in the USB communication circuit by accessing FT_Write function; clears the sending and receiving buffers of the interface chip in the USB communication circuit by accessing FT_Purge function; obtains the status information of the interface chip in the USB communication circuit by accessing FT_GetStatus function.

[0036] like Figure 6 As shown in the figure, the host computer realizes flexible FIR filtering processing by setting the filtering parameters by the user. Taking low-pass FIR filtering as an example, the user sets the sampling period of the signal through the host computer. , Stopband attenuation index , stopband edge frequency , passband edge frequency , cutoff frequency , transition bandwidth , filter order (in is the exponential attenuation through the stopband After determining the window function, look up the table to obtain it), and the filter sequence is determined by the window function and the filter order , the filter sequence To quantify: , after filtering output .

[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A universal data acquisition and signal processing system, comprising a host computer and an energy storage battery power supply device, characterized in that: The host computer is connected with a data acquisition card, which includes a voltage follower circuit, a first-order low-pass filter circuit, an A / D conversion circuit, an FPGA control unit, a Flash storage circuit, an RS485 communication circuit and a USB communication circuit. The signal output end of the voltage follower circuit is connected to the signal input end of the first-order low-pass filter circuit, the signal output end of the first-order low-pass filter circuit is connected to the A / D conversion circuit, the signal output end of the A / D conversion circuit is connected to the signal input end of the FPGA control unit, the signal input end of the FPGA control unit is also connected to the Flash storage circuit and the RS485 communication circuit, the signal output end of the FPGA control unit is connected to the USB communication circuit, the USB communication circuit is used to transmit the collected data, the Flash storage data and the RS485 bus data to the host computer, and the data acquisition card is also connected with an energy storage battery power supply device, and the energy storage battery power supply device is used to power the data acquisition card when the data acquisition card does not use the power provided by the host computer; The host computer realizes data reading and writing of the USB interface through the dynamic link library, specifically according to the following steps: the host computer opens the USB device by accessing the FT_OpenEx function and returns a handle, and the subsequent function identifies the USB device through the handle; reads a byte array of a specified length from the interface chip in the USB communication circuit by accessing the FT_Read function; sends a byte array of a specified length to the interface chip in the USB communication circuit by accessing the FT_Write function; clears the sending and receiving buffers of the interface chip in the USB communication circuit by accessing the FT_Purge function; obtains the status information of the interface chip in the USB communication circuit by accessing the FT_GetStatus function; The host computer realizes flexible FIR filtering processing by setting filtering parameters by the user. Taking low-pass FIR filtering as an example, the user sets the sampling period t, stopband attenuation index as1, stopband boundary frequency ω of the signal through the host computer. s , with boundary frequency ω p , cut-off frequency ω c =2π*ω p *t, transition bandwidth Δω=2π*(ω s -ω p )*T, filter order N = 2π*X / Δω, where X is obtained by looking up the table after determining the window function through the stopband attenuation index as1, and the filter sequence h(n) is determined by the window function and the filter order, and the filter sequence is quantized h(n): h(n)′ = (h(n) / max(h(n)))*(2 11 -1), output after filtering The voltage follower circuit and the first-order low-pass filter circuit both use high-speed, low-noise operational amplifiers to process 8-channel input signals; The A / D conversion circuit is used to realize 8-channel signal sampling, the data acquisition bit number is 12 bits plus a sign bit, the maximum sampling rate is 1MHZ, the sampling rate is adjustable, and the measured voltage range has four options of ±10V, ±5V, ±2.5V and a unipolar input range of 0V to +10V.

2. A universal data acquisition and signal processing system according to claim 1, characterized in that: The FPGA control unit adopts XC3S400 of XILINX Company.

3. A universal data acquisition and signal processing system according to claim 1, characterized in that: The Flash storage circuit has 32GB of storage space, and is used to store the collected data into the Flash storage circuit when the acquisition card is not connected to a host computer.

4. A universal data acquisition and signal processing system according to claim 1, characterized in that: The RS485 communication circuit serves as a bus interface expansion function, and is used to realize data input of one RS485 bus and data output of one RS485 bus.

5. A universal data acquisition and signal processing system according to claim 1, characterized in that: The host computer has a virtual oscilloscope function and can directly print and record data.

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