Mesa structure PNP type Schottky collector region SOI SiGe HBT structure and preparation method thereof

Abstract

The present invention provides a mesa structure PNP type Schottky collector region SOI SiGe HBT structure, comprising a single crystal silicon substrate and an SOI substrate composed of a buried oxide layer stacked on the surface of the single crystal silicon substrate, wherein a P-type heavily doped single crystal silicon layer, a metal silicide thin layer, an N-type heavily doped Si 1‑x Ge x The base layer, the P-type doped single crystal silicon emitter cap layer and the P-type heavily doped polycrystalline silicon emitter layer, the P-type heavily doped polycrystalline silicon emitter layer to the P-type doped single crystal silicon emitter cap layer are etched to form an emitter and base electrode contact table, the P-type heavily doped polycrystalline silicon emitter layer to the metal silicide thin layer are etched to form a collector electrode contact table, the table structure surface is covered with an oxide film layer, the electrode window is formed with a corresponding metal electrode, and the base electrode contact area is deposited with N-type heavily doped Si 1‑ y Ge y The present invention also provides a method for preparing the aforementioned structure. The present application can improve the device cutoff frequency and gain and reduce the base region transit time and is compatible with conventional silicon-based processes.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a mesa structure PNP type Schottky collector region SOISiGe HBT structure and a preparation method thereof. Background Art

[0002] At present, the market demand for high-performance devices such as high speed, high frequency, and low cost is increasingly strong. However, due to the limitations of the physical properties of Si materials themselves, it is difficult to improve the high speed and high frequency performance of conventional Si devices; although III-V compound semiconductor devices (such as GaAs, InP, etc.) are much better than Si devices in high speed and high frequency performance, they have disadvantages such as incompatibility with Si device processes and high costs. The silicon-germanium heterojunction bipolar transistor (SiGe HBT) is a silicon-based bipolar junction transistor (SiBJT) with a small amount of Ge added to the base region. The use of SiGe material in the base region significantly improves the device performance, making SiGe HBT a standard bipolar transistor in high-speed applications. The key indicator of ultra-high frequency semiconductor devices is the cutoff frequency (f T ), SiGe HBT developed on the basis of mature silicon technology takes advantage of the "band engineering" to fundamentally solve the contradiction between increasing the amplification factor and improving the frequency characteristics. Due to its full compatibility with mature silicon technology and the development and maturity of process technologies such as molecular beam epitaxy (MBE) and chemical vapor deposition (CVD), SiGe HBT is widely used in high-performance microwave RF devices and circuits with its unique advantages.

[0003] SOI (Silicon On Insulator) technology is an ideal platform for developing new devices and integrated circuits with low power consumption, radiation resistance, and high temperature resistance, and it also expands the application prospects of CMOS technology. In SOI substrate technology, SiGe HBT devices use the insulator substrate in the SOI substrate to reduce parasitic capacitance effects, reduce device power consumption, and avoid latch-up effects. In recent years, SiGe HBT based on SOI substrate technology has gradually become one of the hot topics in the field of microelectronics research.

[0004] It is also worth noting that under the same doping conditions, since the minority carrier (hole) mobility of the PNP base region is lower than that of the NPN SiGe HBT, the gain of the PNP device is relatively small and the base transit time is relatively long, so most of the current SiGe HBTs use the NPN type. However, on the other hand, under the same base material conditions, the mobility of the majority carrier (electron) in the base region of the PNP transistor is higher, resulting in the sheet resistance of the PNP intrinsic base region being much smaller than that of the NPN type, thereby reducing the charge and discharge time of the emitter junction capacitance and increasing the switching speed of the device. Therefore, as long as the base transit time is further reduced and the current gain of the device is increased, the PNP SiGe HBT will have obvious advantages and application potential in the switching circuit. In addition, if the collector junction of a conventional SiGe HBT is replaced with a Schottky junction, the operating speed of the device can be further improved, because the Schottky contact has the following two obvious main advantages: (1) the collector resistance is 0; (2) because there is no collector junction space charge region, the collector junction transit time can be 0, and the charge storage time is also 0, which can further increase the cutoff frequency.

[0005] The inventors of the present invention have found that, compared with the above two advantages (1) and (2), more importantly, for the carriers transported in the collector junction, the use of the Schottky collector junction can effectively avoid the conversion process of the carriers from the narrow bandgap base region to the wide bandgap collector region. This is because the collector junction valence band discontinuity ΔE of the conventional PNP type Si / SiGe / Si HBT structure is V The large size, together with the carrier velocity overshoot effect, is not conducive to further improving the device performance. At this time, the hole concentration accumulated in the collector junction increases by exp(qΔE V / kT)(q is the electron charge, k is the Boltzmann constant, and T is the temperature), which reduces the collector current and increases the collector junction transit time. If a Schottky barrier is used, the above unfavorable factors can be effectively avoided.

[0006] The inventor of the present invention has further discovered through research that in order to achieve the purpose of reducing the transit time of the base region of the PNP type SiGe HBT, in addition to the conventional means of reducing the thickness of the SiGe base region, the advantages of "strain engineering" can also be combined. At present, "strain engineering" is mainly used in the process of high-speed MOSFET, especially in the strain process below 90 nanometers, uniaxial strain is a commonly used technical means. Therefore, if the uniaxial strain technology can be introduced into the PNP type SiGe HBT, through simple process steps, stress can be applied to the base region of the PNP type SiGe HBT, the longitudinal mobility of the minority carriers (holes) in the base region can be reduced, and the transit time of the base region can be reduced to increase the cutoff frequency of the device; at the same time, the compatibility with the conventional silicon-based CMOS process is also taken into account, which is convenient for large-scale commercial manufacturing. Summary of the invention

[0007] Aiming at the technical problems that the mobility of holes in the existing PNP type SiGe HBT device is smaller than that of electrons, the gain of the device is relatively small, the base region transit time is relatively long, and the device switching speed and cutoff frequency are not high, the present invention provides a mesa structure PNP type Schottky collector SOI SiGe HBT structure.

[0008] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0009] A mesa structure PNP type Schottky collector region SOI SiGe HBT structure comprises an SOI substrate, wherein the SOI substrate comprises a single crystal silicon substrate and a buried oxide layer stacked on the surface of the single crystal silicon substrate, a P-type heavily doped single crystal silicon layer is formed on the surface of the buried oxide layer, the thickness of the P-type heavily doped single crystal silicon layer is much greater than the depletion thickness of the layer caused by the bias of the SOI substrate, a metal silicide thin layer is formed on the surface of the P-type heavily doped single crystal silicon layer, and an N-type heavily doped Si 1-x Ge x The base layer, the N-type heavily doped Si 1-x Ge x A P-type doped single crystal silicon emitter cap layer is formed on the surface of the base layer, a P-type heavily doped polysilicon emitter layer is formed on the surface of the P-type doped single crystal silicon emitter cap layer, an emitter electrode and left and right base electrode contact mesas are formed by etching the P-type heavily doped polysilicon emitter layer to the P-type doped single crystal silicon emitter cap layer, left and right collector electrode contact mesas are formed by etching the P-type heavily doped polysilicon emitter layer to the metal silicide thin layer, the entire surface of the mesa structure is covered with an oxide film layer, the oxide film layers corresponding to the base, collector and middle emitter positions are etched to form corresponding electrode contact windows, and the N-type heavily doped Si under the base window 1-x Ge x The base layer is etched to form a base electrode contact area, a corresponding metal electrode is formed on the electrode contact window, and N-type heavily doped Si is deposited in the base electrode contact area. 1-y Ge y , and 0 <y<x<1。

[0010] Furthermore, the buried oxide layer has a thickness of 0.5 μm.

[0011] Furthermore, the metal silicide thin layer is CoSi2 with a thickness of 5 nm.

[0012] Furthermore, the N-type heavily doped Si 1-x Ge x The thickness of the base layer is 20-30nm.

[0013] Furthermore, the thickness of the P-type doped single-crystal silicon emitter cap layer is 10 nm, and the thickness of the P-type heavily doped polycrystalline silicon emitter layer is 0.5 μm.

[0014] Furthermore, the oxide film layer is a SiO2 oxide layer with a thickness of 100 nm.

[0015] The present invention also provides a method for preparing the aforementioned mesa structure PNP type Schottky collector region SOI SiGe HBT structure, the method comprising the following steps:

[0016] S1. Prepare an SOI substrate, which includes a single crystal silicon substrate and a buried oxide layer stacked on the surface of the single crystal silicon substrate. Deposit a P-type heavily doped single crystal silicon layer on the surface of the buried oxide layer, with a doping concentration of 2×10 19 cm -3 , and the thickness of the P-type heavily doped single crystal silicon layer is much greater than the depletion thickness of the layer caused by the bias of the SOI substrate, and then the surface of the P-type heavily doped single crystal silicon layer is cleaned and chemically mechanically polished;

[0017] S2, growing a 5 nm thick metal layer on the surface of the P-type heavily doped single crystal silicon layer by physical vapor deposition, and then performing a rapid thermal annealing process to oxidize the metal and the underlying single crystal silicon surface to form a thin metal silicide layer as a collector region;

[0018] S3, using molecular beam epitaxy technology to deposit a thin layer of N-type heavily doped Si on the surface of the metal silicide thin layer 1-x Ge x The base layer has a doping concentration of 1×10 19 cm -3 ; Then in N-type heavily doped Si 1-x Ge x A P-type doped single crystal silicon emitter cap layer is grown on the surface of the base layer, with a doping concentration of 5×10 17 cm -3 Finally, a layer of P-type heavily doped polysilicon emitter layer with a typical thickness of 0.5 μm is deposited on the surface of the P-type doped single crystal silicon emitter cap layer, and the doping concentration is 2×10 19 cm -3 ;

[0019] S4, according to the preset emitter width of the device, the emitter and base regions are etched from the P-type heavily doped polysilicon emitter region layer to the P-type doped single crystal silicon emitter region cap layer, and then the collector region is etched from the P-type heavily doped polysilicon emitter region layer to the metal silicide thin layer to form a mesa structure;

[0020] S5. On the mesa structure after the entire etching is completed, an oxide thin film layer covering the entire mesa is formed by dry oxidation. The electrode contact windows for the emitter, base, and collector are determined. Then, the oxide thin film layer in the emitter region, base region, and collector region windows, as well as the N-type heavily doped Si under the base region window, are etched away. 1-x Ge x The base region, and then the etched Si 1-x Ge x region is deposited with N-type heavily doped Si 1-y Ge y , and 0 < y < x < 1. Finally, metal is deposited on the electrode contact windows of the emitter region, base region, and collector region as the emitter, base, and collector.至此器件制作完成。

[0021] Furthermore, in step S2, the metal grown on the surface of the P-type heavily doped single-crystalline silicon layer is Co, and Co is oxidized with the underlying single-crystalline silicon surface to form CoSi2.

[0022] Furthermore, in step S5, the oxide thin film layer is a 10-nm-thick SiO2 oxide layer.

[0023] Furthermore, in step S5, the value of y is 0.1 and the value of x is 0.3.

[0024] Compared with the prior art, the mesa structure PNP-type Schottky collector region SOI SiGe HBT structure and its preparation method provided by the present invention have the following technical advantages:

[0025] 1. Utilize an extremely thin metal silicide thin layer such as CoSi2 to form a Schottky contact between the single-crystalline silicon in the base region, which not only ensures excellent contact interface characteristics but also can improve the switching conversion speed and cut-off frequency of the device. At the same time, it is compatible with the conventional silicon-based process, and the process is relatively simple.

[0026] 2. In the Si 1-x Ge x base region, "embedded" growth is used to form Si 1-y Ge y base contact regions on both sides (note: form the base metal electrode in contact with the metal). Under the condition of 0 < y < x < 1, the Ge component content values of x and y can be flexibly designed, thus improving the device design freedom. Due to lattice mismatch, the Si 1-y Ge y on both sides exert a transverse uniaxial tensile stress and a longitudinal compressive stress on the middle Si 1-x Ge x base region. Among them, the longitudinal compressive stress can effectively improve the mobility of minority carriers (holes) in the base region and the base transit time, and improve the cut-off frequency of the device.

[0027] 3. Use a very thin P-type doped single crystal silicon emitter cap layer and a very thick P-type heavily doped polysilicon emitter layer as a "combined emitter" structure. At the same time, according to the principle of elastic mechanics, the lateral uniaxial tensile stress of the base region can be "transmitted" to the P-type doped single crystal silicon emitter cap layer above, making it a strained silicon layer with compressive strain, that is, the P-type doped single crystal silicon emitter cap layer is also subjected to tensile strain Si 1-x Ge x The influence of the base region forms uniaxial compressive strained silicon. According to the theory of semiconductor device physics, the compressive strained silicon cap layer can further improve the injection efficiency of the emitter, increase the cutoff frequency and DC amplification factor (gain) of the device;

[0028] 4. The introduction of mature SOI substrate technology can further reduce parasitic capacitance effects, reduce device power consumption, avoid latch-up effects, etc., improve the overall performance of the device, and facilitate process integration with current small-size, low-power SOI CMOS devices, which is in line with the technical route of proportional device reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of a mesa-structured PNP-type Schottky collector region SOI SiGe HBT provided by the present invention.

[0030] Figure 2a to 2e It is a schematic diagram of the cross-sectional structure of each process stage in the method for preparing the mesa structure PNP type Schottky collector region SOI SiGe HBT structure provided by the present invention. DETAILED DESCRIPTION

[0031] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below with reference to specific diagrams.

[0032] In the description of the present invention, it should be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0033] Please refer to Figure 1As shown, the present invention provides a mesa structure PNP type Schottky collector region SOI SiGe HBT structure, including an SOI substrate, the SOI substrate including a single crystal silicon substrate and a buried oxide layer (BOX) stacked on the surface of the single crystal silicon substrate, the buried oxide layer is specifically a SiO2 oxide layer formed by oxidation on the surface of the single crystal silicon substrate, a P-type heavily doped single crystal silicon layer is formed on the surface of the buried oxide layer, the thickness of the P-type heavily doped single crystal silicon layer is much greater than the depletion thickness of the layer caused by the bias of the SOI substrate, so as to ensure that the resistance of the collector region does not become too large due to the influence of the depletion region width, a metal silicide thin layer is formed on the surface of the P-type heavily doped single crystal silicon layer, the P-type heavily doped single crystal silicon layer and the metal silicide thin layer thereon constitute a "combined collector" structure, and an N-type heavily doped Si 1-x Ge x The base layer, the N-type heavily doped Si 1-x Ge x A P-type doped single crystal silicon emitter cap layer is formed on the surface of the base layer, and a P-type heavily doped polysilicon emitter layer is formed on the surface of the P-type doped single crystal silicon emitter cap layer. The P-type heavily doped polysilicon emitter layer and the P-type doped single crystal silicon emitter cap layer constitute a "combined emitter" structure. The P-type heavily doped polysilicon emitter layer to the P-type doped single crystal silicon emitter cap layer are etched to form an emitter electrode and left and right base electrode contact mesas, wherein the emitter electrode contact mesas is located in the middle, and the base electrode contact mesas are located on the left and right sides of the emitter electrode contact mesas. On the side, the P-type heavily doped polysilicon emitter layer is etched to the metal silicide thin layer to form left and right collector electrode contact mesas, specifically the left collector electrode contact mesas is located on the left side of the left base electrode contact mesas, and the right collector electrode contact mesas is located on the right side of the right base electrode contact mesas, the entire surface of the mesa structure is covered with an oxide film layer, and the oxide film layer corresponding to the base region, the collector region and the middle emitter region is etched to form corresponding electrode contact windows, namely, base window, collector window and emitter window, and the N-type heavily doped Si under the base window 1-x Ge x The base layer is etched to form a base electrode contact area, and the corresponding metal electrodes, namely the base, collector and emitter, are formed on the electrode contact window. N-type heavily doped Si is deposited in the base electrode contact area. 1-y Ge y , that is, in N-type heavily doped Si 1-x Ge x The left and right sides of the base layer are N-type heavily doped Si 1-y Ge y , where x and y are the molar contents of Ge (germanium), and 0 <y<x<1。

[0034] As a specific embodiment, the thickness of the buried oxide layer should not be too thick, and a typical thickness value is 0.5 μm.

[0035] As a specific embodiment, the interface morphology and interface state at the interface where the metal silicide thin layer contacts the single crystal silicon in the P-type heavily doped single crystal silicon layer below it have a great influence on the device characteristics. According to the current conventional silicon process, a very thin layer (usually less than 10 nanometers) of CoSi2 with good interface morphology and interface state can be grown on the single crystal silicon material, and the barrier height of CoSi2 contacting the P-type single crystal silicon is about 0.7eV, so CoSi2 is the preferred metal silicide material for forming the collector Schottky barrier. As a preferred embodiment, the thickness of the metal silicide thin layer CoSi2 is 5nm.

[0036] As a specific embodiment, the N-type heavily doped Si 1-x Ge x The thickness of the base layer is 20-30nm. Therefore, under the condition of ensuring that the base SiGe layer is not relaxed, reducing the base thickness as much as possible is beneficial to reducing the base transit time, but it cannot be too small, otherwise it will increase the block resistance of the base.

[0037] As a specific embodiment, the thickness of the P-type doped single-crystal silicon emitter cap layer is 10nm, and the thickness of the P-type heavily doped polycrystalline silicon emitter layer is 0.5μm, thereby the polycrystalline silicon and single-crystal silicon form a "combined emitter" structure. At this time, the single-crystal silicon layer is strained, and the stress changes the energy band structure of the single-crystal silicon layer. Therefore, from a physical analysis, the DC current gain of the device can be improved.

[0038] As a specific embodiment, the oxide film layer is a 100 nm thick SiO2 oxide layer, which is helpful to reduce the self-heating effect of the device.

[0039] The present invention also provides a method for preparing the aforementioned mesa structure PNP type Schottky collector region SOI SiGe HBT structure, the method comprising the following steps:

[0040] S1. Prepare an SOI substrate. The SOI substrate includes a single crystal silicon substrate and a buried oxide layer (BOX) stacked on the surface of the single crystal silicon substrate. The buried oxide layer is specifically a SiO2 oxide layer formed by oxidation on the surface of the single crystal silicon substrate. The thickness of the SiO2 oxide layer should not be too thick, and the typical thickness is 0.5 μm. Then, a P-type heavily doped single crystal silicon layer is deposited on the surface of the buried oxide layer, and the doping concentration is 2×10 19 cm -3, and the thickness of the P-type heavily doped single crystal silicon layer is much greater than the depletion thickness t of the layer caused by the SOI substrate bias. The surface of the P-type heavily doped single crystal silicon layer is then cleaned and chemically mechanically polished (CMP) to facilitate the formation of metal silicide on the P-type heavily doped single crystal silicon layer. For specific structures, please refer to Figure 2a Specifically, under the action of the substrate voltage, the SOI substrate forms a back-to-back MOS capacitor structure. According to the physics of semiconductor devices, the depletion thickness t can be solved by the following quadratic equation:

[0041]

[0042] Where q is the electron charge, N Si is the doping concentration of the P-type heavily doped single crystal silicon layer above the buried oxide layer, ε Si and ε OX are the dielectric constants of the single crystal silicon and buried oxide layer in the P-type heavily doped single crystal silicon layer, t OX is the thickness of the buried oxide layer, V S 、V C and V MS They are substrate voltage, collector voltage and work function difference of single crystal silicon regions on both sides of buried oxide layer.

[0043] S2. A 5 nm thick metal layer is grown on the surface of the P-type heavily doped single crystal silicon layer by using the existing physical vapor deposition (PVD) method, and then a rapid thermal annealing (RTA) treatment is performed to oxidize the metal and the single crystal silicon surface below to form a thin metal silicide layer as a collector region. As a specific implementation method, the metal grown on the surface of the P-type heavily doped single crystal silicon layer is Co, and Co and the single crystal silicon surface below are oxidized to become CoSi2, and CoSi2 is used as the collector region. For the specific structure, please refer to Figure 2b shown.

[0044] S3, using molecular beam epitaxy (MBE) technology to deposit a thin layer of N-type heavily doped Si (e.g., 30 nm thick) on the surface of a metal silicide thin layer such as CoSi2. 1-x Ge x The base layer has a doping concentration of 1×10 19 cm -3 , the Ge component x is preferably 0.3; then the N-type heavily doped Si 1-x Ge x A 10nm thick P-type doped single crystal silicon emitter cap layer is grown on the surface of the base layer, with a doping concentration of 5×10 17 cm -3 Finally, a layer of P-type heavily doped polysilicon emitter layer with a typical thickness of 0.5 μm is deposited on the surface of the P-type doped single crystal silicon emitter cap layer, and the doping concentration is 2×10 19 cm -3, for the specific structure, please refer to Figure 2c as shown.

[0045] S4. According to the preset emitter width of the device, etch the emitter and base regions from the P-type heavily doped polysilicon emitter layer to the P-type doped single-crystalline silicon emitter cap layer. The emitter region is located in the middle of the base region, that is, the base region is located on both sides of the emitter region. Then, etch the collector region from the P-type heavily doped polysilicon emitter layer to the metal silicide thin layer to form a mesa structure. The collector region is located on both sides of the base region. For the specific structure, please refer to Figure 2d as shown.

[0046] S5. On the entire etched mesa structure, form an oxide thin film layer covering the entire mesa through dry oxidation. For example, a 10-nm-thick SiO2 oxide layer can be covered on the entire mesa as the oxide thin film layer. Determine the electrode contact windows for the emitter, base, and collector. Then, etch off the oxide thin film layer in the emitter region, base region, and collector region windows, and the N-type heavily doped Si 1-x Ge x base region under the base region window. Then, deposit and grow N-type heavily doped Si 1-x Ge x in the etched Si 1- y Ge y , with a doping concentration of 2×10 19 cm -3 , and 0 < y < x < 1. Finally, deposit metal on the electrode contact windows of the emitter region, base region, and collector region as the emitter, base, and collector.至此, the device fabrication is completed. For the specific structure, please refer to Figure 2e as shown.

[0047] As a specific embodiment, in step S5, the Ge component y in N-type heavily doped Si 1-y Ge y takes a value of 0.1, and the Ge component x in the N-type heavily doped Si 1-x Ge x base region layer takes a value of 0.3.

[0048] Compared with the prior art, the mesa structure PNP-type Schottky collector region SOI SiGe HBT structure and its preparation method provided by the present invention have the following technical advantages:

[0049] 1. Utilize an extremely thin metal silicide thin layer such as CoSi2 to form a Schottky contact of Si / CoSi2 with the single-crystalline silicon in the base region, which not only ensures excellent contact interface characteristics, but also can improve the switching conversion speed and cut-off frequency of the device. At the same time, it is compatible with the conventional silicon-based process, and the process is relatively simple;

[0050] 2. In Si 1-xGe x The base regions on both sides are formed into Si 1-y Ge y base contact regions in the form of "embedded" growth (note: forming base metal electrodes in contact with metal). Under the condition of 0 < y < x < 1, the Ge component content values of x and y can be flexibly designed, thus improving the device design freedom; due to lattice mismatch, the Si 1-y Ge y on both sides generates a transverse uniaxial tensile stress effect and a longitudinal compressive stress effect on the middle Si 1-x Ge x base region. Among them, the longitudinal compressive stress can effectively improve the mobility of minority carriers (holes) in the base region and the base transit time, and improve the cut-off frequency of the device;

[0051] 3. Use a very thin P-type doped single-crystalline silicon emitter cap layer and a very thick P-type heavily doped polycrystalline silicon emitter layer as the "combined emitter" structure. At the same time, according to the principle of elasticity, the transverse uniaxial tensile stress in the base region can be "conducted" into the above P-type doped single-crystalline silicon emitter cap layer, making it a strained silicon layer with compressive strain, that is, the P-type doped single-crystalline silicon emitter cap layer is also affected by the tensile strain Si 1-x Ge x base region and forms uniaxial compressive strained silicon. According to the theory of semiconductor device physics, the compressive strained silicon cap layer can further improve the injection efficiency of the emitter, and improve the cut-off frequency and DC amplification factor (gain) of the device;

[0052] 4. Introduce the mature SOI substrate technology, which further plays roles such as reducing the parasitic capacitance effect, lowering the device power consumption, avoiding the latch-up effect, etc., improving the overall performance of the device, facilitating the process integration with the current small-size low-power SOI CMOS devices, and conforming to the technical route of device scaling.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not restrictive. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. Mesa structure PNP type Schottky collector SOI SiGe HBT structure, characterized by: The SOI substrate includes a single crystal silicon substrate and a buried oxide layer stacked on the surface of the single crystal silicon substrate, wherein the surface of the buried oxide layer is formed with a doping concentration of 2×10 19 cm -3 The thickness of the P-type heavily doped single crystal silicon layer is much greater than the depletion thickness of the P-type heavily doped single crystal silicon layer caused by the SOI substrate bias, thereby ensuring that the resistance of the collector region does not become too large due to the influence of the depletion region width, and a metal silicide thin layer is formed on the surface of the P-type heavily doped single crystal silicon layer, and a doping concentration of 1×10 19 cm -3 N-type heavily doped Si 1-x Ge x The base layer, the N-type heavily doped Si 1-x Ge x A P-type doped single crystal silicon emitter cap layer is formed on the surface of the base layer, and a doping concentration of 2×10 19 cm -3 The P-type heavily doped polysilicon emitter layer is etched to form an emitter electrode and left and right base electrode contact mesas from the P-type heavily doped polysilicon emitter layer to the P-type doped monocrystalline silicon emitter cap layer, and left and right collector electrode contact mesas are formed from the P-type heavily doped polysilicon emitter layer to the metal silicide thin layer, and the entire surface of the mesa structure is covered with an oxide film layer, and the oxide film layers corresponding to the base region, the collector region and the middle emitter position are etched to form corresponding electrode contact windows, and the N-type heavily doped Si under the base window 1-x Ge x The base layer is etched to form a base electrode contact area, a corresponding metal electrode is formed on the electrode contact window, and a doping concentration of 2×10 19 cm -3 N-type heavily doped Si 1-y Ge y , and 0 <y<x<1。 2. The mesa structure PNP type Schottky collector region SOI SiGe HBT structure according to claim 1, characterized in that: The thickness of the buried oxide layer is 0.5 μm.

3. The mesa structure PNP type Schottky collector region SOI SiGe HBT structure according to claim 1, characterized in that: The metal silicide thin layer is CoSi2 with a thickness of 5 nm.

4. The mesa structure PNP type Schottky collector region SOI SiGe HBT structure according to claim 1, characterized in that: The N-type heavily doped Si 1-x Ge x The thickness of the base layer is 20-30nm.

5. The mesa structure PNP type Schottky collector region SOI SiGe HBT structure according to claim 1, characterized in that: The thickness of the P-type doped single-crystal silicon emitter cap layer is 10 nm, and the thickness of the P-type heavily doped polycrystalline silicon emitter layer is 0.5 μm.

6. The mesa structure PNP type Schottky collector region SOI SiGe HBT structure according to claim 1, characterized in that: The oxide film layer is a SiO2 oxide layer with a thickness of 100 nm.

7. A method for preparing a mesa structure PNP type Schottky collector region SOI SiGe HBT structure according to any one of claims 1 to 6, characterized in that: The method comprises the following steps: S1. Prepare an SOI substrate, which includes a single crystal silicon substrate and a buried oxide layer stacked on the surface of the single crystal silicon substrate. Deposit a P-type heavily doped single crystal silicon layer on the surface of the buried oxide layer, with a doping concentration of 2×10 19 cm -3 , and the thickness of the P-type heavily doped single crystal silicon layer is much greater than the depletion thickness of the P-type heavily doped single crystal silicon layer caused by the SOI substrate bias, so as to ensure that the resistance of the collector region does not become too large due to the influence of the depletion region width, and then the surface of the P-type heavily doped single crystal silicon layer is cleaned and chemically mechanically polished; S2, growing a 5 nm thick metal layer on the surface of the P-type heavily doped single crystal silicon layer by physical vapor deposition, and then performing a rapid thermal annealing process to silicide the metal and the underlying single crystal silicon surface to form a thin metal silicide layer as a collector region; S3, using molecular beam epitaxy technology to deposit a thin layer of N-type heavily doped Si on the surface of the metal silicide thin layer 1-x Ge x The base layer has a doping concentration of 1×10 19 cm -3 ; Then in N-type heavily doped Si 1-x Ge x A P-type doped single crystal silicon emitter cap layer is grown on the surface of the base layer, with a doping concentration of 5×10 17 cm -3 Finally, a 0.5 μm thick P-type heavily doped polysilicon emitter layer is deposited on the surface of the P-type doped single crystal silicon emitter cap layer, with a doping concentration of 2×10 19 cm -3 ; S4, according to the preset emitter width of the device, the emitter and base regions are etched from the P-type heavily doped polysilicon emitter region layer to the P-type doped single crystal silicon emitter region cap layer, and then the collector region is etched from the P-type heavily doped polysilicon emitter region layer to the metal silicide thin layer to form a mesa structure; S5. On the mesa structure after the entire etching is completed, an oxide thin film layer covering the entire mesa is formed by dry oxidation. The electrode contact windows for the emitter, base, and collector are determined, and then the oxide thin film layer in the emitter region, base region, and collector region windows, as well as the N-type heavily doped Si under the base region window, are etched away. 1-x Ge x The base region, and then the etched Si 1-x Ge x region is deposited with N-type heavily doped Si 1-y Ge y , with a doping concentration of 2×10 19 cm -3 , and 0 < y < x < 1. Finally, metal is deposited on the electrode contact windows of the emitter region, base region, and collector region as the emitter, base, and collector, and thus the device fabrication is completed.

8. The method for preparing a mesa structure PNP type Schottky collector region SOI SiGe HBT structure according to claim 7, characterized in that: In the step S2, the metal grown on the surface of the P-type heavily doped single crystal silicon layer is Co, and Co is silicidized with the single crystal silicon surface below to form CoSi2.

9. The method for preparing a mesa structure PNP type Schottky collector region SOI SiGe HBT structure according to claim 7, characterized in that: In the step S5, the oxide film layer is a SiO2 oxide layer with a thickness of 10 nm.

10. The method for preparing a mesa structure PNP type Schottky collector region SOI SiGe HBT structure according to claim 7, characterized in that: In step S5, the value of y is 0.1, and the value of x is 0.3.

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