Floating-point addition

Abstract

The present application discloses floating-point addition. A floating-point addition circuit is provided for adding a first floating-point operand and a second floating-point operand, each of the first floating-point operand and the second floating-point operand including a significand and an exponent. An alignment shift circuit shifts the smaller operand significand based on the exponent difference to align with the larger operand significand. An increment circuit generates alternative versions of the larger operand significand, each version based on a different rounding increment applied to the larger operand significand. The addition circuit generates multiple candidate sum values, each candidate sum value representing the sum of the shifted smaller operand significand and one of the corresponding alternative versions of the larger operand significand. One of the candidate sum values ​​is selected as the rounded result of the addition of the first floating-point operand and the second floating-point operand. This allows for faster execution of the floating-point addition because the delay of the rounding increment can be hidden in the shadow of the alignment shift delay.

Description

Technical Field

[0001] The present technology relates to the field of data processing, and more specifically, to a floating-point addition circuit. Background Art

[0002] Data processing devices can provide support for processing numbers represented in floating-point notation. In floating-point notation, a number is represented by a significand I.F, an exponent E, and a sign bit S. The sign bit S indicates whether the floating-point number is positive or negative. The significand I.F indicates the number of digits in the floating-point number. The exponent E indicates the position of the base point (also known as the binary point) relative to the significand. Therefore, by changing the value of the exponent, the base point can fluctuate within the significand, allowing floating-point notation to represent a wider range of numbers for a predetermined number of bits than fixed-point notation, in which the base point has a fixed position within the significand. However, using floating-point notation can increase the complexity of performing addition because, for example, when adding two floating-point numbers with different exponents, the significands of the floating-point numbers need to be aligned based on the difference between the exponents before the addition. Furthermore, because some bits are used to store the exponent, the additional range of floating-point representation can be achieved at the expense of reduced precision. Sometimes, a floating-point operation may generate a result with more significands than the number of bits used for the significand. If this occurs, the result may be rounded to a value that can be represented using the available significands. Both alignment and rounding may introduce additional latency when performing the addition. Summary of the Invention

[0003] At least some examples provide floating-point addition circuitry for adding a first floating-point operand and a second floating-point operand, the first floating-point operand and the second floating-point operand each including a significand and an exponent; the floating-point addition circuitry comprising:

[0004] an alignment shift circuit configured to shift a smaller operand significand based on an exponent difference representing a difference between exponents of a first floating-point operand and a second floating-point operand to align the smaller operand significand with a larger operand significand, wherein the smaller operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the smaller exponent and the larger operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the larger exponent;

[0005] an increment circuit for generating a plurality of alternative versions of the larger operand's significand, wherein each alternative version of the larger operand's significand is based on a different rounding increment applied to the larger operand's significand;

[0006] a plurality of summing circuits for generating a plurality of candidate sum values, wherein each candidate sum value represents a sum of a respective one of a plurality of alternative versions of the shifted smaller operand significant bits generated by the alignment shift circuit and the larger operand significant bits generated by the increment circuit; and

[0007] A selection circuit is configured to select one of a plurality of candidate sum values ​​generated by a plurality of addition circuits, wherein the selected sum value represents a rounded result of adding a first floating-point operand and a second floating-point operand.

[0008] At least some examples provide a floating-point addition circuit for adding a first floating-point operand and a second floating-point operand, wherein the first floating-point operand and the second floating-point operand each include a significand and an exponent; the floating-point addition circuit comprising:

[0009] means for shifting a smaller operand significand to align the smaller operand significand with a larger operand significand based on an exponent difference representing a difference between exponents of a first floating-point operand and a second floating-point operand, wherein the smaller operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the smaller exponent and the larger operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the larger exponent;

[0010] means for generating a plurality of alternative versions of the larger operand's significand, wherein each alternative version of the larger operand's significand is based on a different rounding increment applied to the larger operand's significand;

[0011] a plurality of means for generating a plurality of candidate sum values, wherein each candidate sum value represents a sum of a respective one of a plurality of alternative versions of the shifted smaller operand significant bits generated by the alignment shift circuitry and the larger operand significant bits generated by the increment circuitry; and

[0012] Means for selecting a candidate sum value from a plurality of candidate sum values ​​generated by the plurality of adding circuits, wherein the selected sum value represents a rounded result of adding the first floating point operand and the second floating point operand.

[0013] At least some examples provide a method for adding a first floating-point operand and a second floating-point operand, the first floating-point operand and the second floating-point operand including a significand and an exponent; the method comprising:

[0014] shifting a smaller operand significand to align the smaller operand significand with a larger operand significand based on an exponent difference representing a difference between exponents of the first floating-point operand and the second floating-point operand, wherein the smaller operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the smaller exponent and the larger operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the larger exponent;

[0015] generating a plurality of alternative versions of the larger operand's significand, wherein each alternative version of the larger operand's significand is based on a different rounding increment applied to the larger operand's significand;

[0016] performing a plurality of additions to generate a plurality of candidate sum values, wherein each candidate sum value represents a sum of a respective one of a plurality of alternative versions of the shifted smaller operand significant bits generated by the alignment shift circuitry and the larger operand significant bits generated by the increment circuitry; and

[0017] Selecting a candidate sum value from among a plurality of candidate sum values ​​generated by the plurality of adding circuits, wherein the selected sum value represents a rounded result of adding the first floating point operand and the second floating point operand. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other aspects, features, and advantages of the present technology will become apparent from the following description of examples, which should be read in conjunction with the following drawings.

[0019] Figure 1 An example of a data processing apparatus is schematically shown;

[0020] Figure 2 A portion of a floating point addition unit is shown;

[0021] Figure 3 The far path circuitry of the floating point adder unit is shown in more detail;

[0022] Figure 4 showing portions of the far path circuit logic in greater detail; and

[0023] Figure 5 is a flow chart illustrating a method for summing for far path processing. DETAILED DESCRIPTION

[0024] A floating-point addition circuit is provided for adding a first floating-point operand and a second floating-point operand, each of the first floating-point operand and the second floating-point operand including a significand and an exponent. The floating-point addition circuit includes an alignment shift circuit for shifting a smaller operand significand (the significand of the first floating-point operand and the second floating-point operand having the smaller exponent) by a certain number of bit positions to align the smaller operand significand with the larger operand significand (the significand of the first floating-point operand and the second floating-point operand having the larger exponent). The number of bits used for the alignment shift may depend on an exponent difference (the difference between the exponents of the first floating-point operand and the second floating-point operand).

[0025] In one method for processing floating-point addition, after the operands are aligned by applying a shift, the shifted significant bits of the smaller operand are added to the significant bits of the larger operand to generate a summed result. Rounding is then applied by first determining whether a round increment is required based on the bits shifted out of the significant bits of the smaller operand by the shifter and the least significant bit of the summed result, and then adding the round increment to the summed result if a round increment is determined to be required. Thus, in this method, the alignment shift of the significant bits of the smaller operand, the addition of the significant bits of the larger operand and the aligned significant bits of the smaller operand, and the addition of the round increment are all performed sequentially.

[0026] However, there is a growing desire to improve performance by enabling processors to operate at higher clock frequencies. As clock frequencies increase, the challenge of fitting all the work required to perform a floating-point addition into a single clock cycle increases. Generally, circuit designers have the choice of reducing the clock frequency, in which case there will be a performance hit as other processing operations with less stringent timing constraints will be slowed down, or performing the floating-point addition over multiple clock cycles, which may reduce the performance of the floating-point addition, which can have a significant impact on performance as floating-point additions are common in certain software applications. In practice, a typical floating-point addition unit will use the second approach and perform the floating-point addition across multiple clock cycles, allowing the use of a higher clock frequency to avoid delaying other operations that require less circuit logic depth.

[0027] The inventors have recognized that alignment shifting for shifting the smaller operand significant bits is relatively slow, and that the larger operand significant bits may not require a significant amount of processing when performing the shift. Furthermore, the inventors have recognized that it is not necessary to wait until the final sum of the larger operand significant bits and the shifted smaller operand significant bits is available before applying the rounding increment. Instead, the rounding increment may be applied to the larger operand significant bits before the larger operand significant bits are added to the smaller operand significant bits, so that the delay associated with adding the rounding increment may be hidden in the shadow of the delay associated with the alignment shifting of the smaller operand significant bits.

[0028] This approach may be considered counterintuitive because it may not be known whether a rounding increment is needed until the shifted smaller operand significand and the sum of the larger operand significand and the shifted smaller operand significand are available. However, this can be addressed by generating two or more alternative versions of the larger operand significand, each based on a different rounding increment; and then adding each of the corresponding versions of the larger operand significand to the shifted smaller operand significand to produce multiple candidate sum values. Selection circuitry can then select between the candidate sum values ​​to determine which value should be used as the final result representing the rounded result of adding the first floating-point operand to the second floating-point operand.

[0029] Therefore, the floating-point addition circuit has an incrementing circuitry that is provided for generating two or more alternative versions of the larger operand significant digit, each version being based on a different rounding increment applied to the larger operand significant digit. Two or more addition circuits are provided to generate two or more candidate sum values. Each candidate sum value represents the sum of the shifted smaller operand significant digit generated by the alignment shift circuit and a corresponding version of the alternative version of the larger operand significant digit generated by the incrementing circuit. A selection circuit selects one of the candidate sum values ​​generated by the addition circuit to provide a rounding result for adding the first floating-point operand and the second floating-point operand.

[0030] Thus, with this approach, rounded results can be obtained much faster, making it possible to perform floating-point additions involving significand alignment and rounding in a single clock cycle (even at relatively high clock frequencies), which might not otherwise be practical. This can have a significant impact on performance.

[0031] The increment circuit can perform at least one addition to generate an alternative version of the larger operand's significant digit. Each addition can add a corresponding rounded increment to the larger operand's significant digit. The increment circuit can perform (one or more) incremental additions in parallel with at least a portion of the shifting of the smaller operand's significant digits performed by the alignment shift circuit. Thus, this avoids the delay of rounding the addition after the addition circuit generates the aligned significant digit sum, thereby improving performance.

[0032] In some examples, alternative versions of the larger operand significand may include: a first version with a round increment based on 0, and a second version with a round increment based on 1. These versions may correspond to situations where a round increment is not required and where a round increment is required, respectively.

[0033] In practice, however, the sum of the aligned smaller operand significant bits and the larger operand significant bits may also result in overflow, in which case the normalization of the result may result in the most significant bit being in a higher position than when there is no overflow, in which case a rounding increment needs to be applied one bit higher than when there is no overflow. In order to avoid the need to perform a shift or additional addition after the corresponding addition circuit calculates the sum of the smaller operand significant bits and the larger operand significant bits, a third version of the larger operand significant bits can be generated, the rounding increment of the third version being 2, thereby effectively representing the addition of the rounding increment to a bit position one bit higher than when there is no overflow. Therefore, each alternative version of the larger operand significant bits can include: a first version based on a rounding increment of 0, a second version based on a rounding increment of 1, and a third version based on a rounding increment of 2. By calculating the sum of each version of the larger operand significant bits and the smaller operand significant bits, each possible rounding result value that may be required has been generated by multiple addition circuits, so that the selection circuit can simply select one of these values ​​without the need for additional addition to round.

[0034] Therefore, since the first version of the larger operand's significand is based on a rounded increment of 0, it can be understood that the first version is exactly the same as the input value of the larger operand's significand. Therefore, no increment circuitry is required to perform addition to generate the first version (the larger operand's significand can be passed directly to the corresponding addition circuitry). However, the increment circuitry performs addition to generate the second or third versions. The delay of adding the rounded increment is generated in parallel with the alignment shift delay, thereby improving performance.

[0035] The selection circuitry may select between candidate sum values ​​based on a rounding status flag that may provide information about the value of the bits shifted out of the smaller operand significant bits in the alignment shift and / or the least significant bits of the summed result. For a typical floating-point adder, the rounding status flag is typically determined based on the bits shifted out by the shifter after performing the alignment shift on the smaller operand significant bits.

[0036] However, in the method discussed below, the rounding state determination circuitry can determine a subset of the rounding state flags based on an unshifted version of the smaller operand's significant bits. This means that at least a portion of the determination of the subset of rounding state flags can be performed in parallel with at least a portion of the shifting of the smaller operand's significant bits performed by the alignment shift circuitry, which improves performance by reducing the overall latency of the addition operation. For example, the rounding state determination circuitry can determine at least one mask based on the difference between the exponents of the first floating-point operand and the second floating-point operand. The rounding state determination circuitry can apply the at least one mask to the unshifted version of the smaller operand's significant bits to determine the subset of rounding state flags.

[0037] In particular, the subset of rounding state flags that can be determined using such a mask can include at least one guard flag and at least one sticky flag. The guard flag can represent the bit value of the least significant bit that is shifted out of the smaller operand's significant bit when performing an aligned shift (i.e., the bit that is one bit to the right of the bit that becomes the least significant bit of the smaller operand's significant bit of the shifter).

[0038] The rounding status flags may also include at least one least significant bit flag that is determined based on the addition performed by one of the adding circuits. The least significant bit flag may correspond to

[0039] The value of the least significant bit in the sum obtained by adding the larger operand significand and the shifted smaller operand significand (according to the first version of the larger operand significand with zero-based rounding increments). Although the least significant bit flag cannot be determined by masking, it is usually still available early in the addition of the adding circuit because the adding circuit tends to calculate the lower bits earlier than the more significant bits, so this can provide sufficient time to control the rounding selection between candidate sum values ​​based on the least significant bit flag. In addition, the protection flag to be used in the case of overflow can also be determined based on the addition performed by one of the adding circuits, because it may be equal to the least significant bit flag in the non-overflow case.

[0040] As described above, the addition performed based on the larger operand significant bits and the shifted smaller operand significant bits may result in overflow. Therefore, the selection circuitry may select between candidate sum values ​​based not only on the rounding status flag, but also on an overflow indication indicating whether the addition of the aligned significant bits of the first floating-point operand and the second floating-point operand results in overflow. For example, if overflow occurs and a round increment is required, the selection circuitry may select the third version of the candidate sum value based on the larger operand significant bits, while if overflow does not occur and a round increment is required, the selection circuitry may select the second version of the candidate sum value based on the larger operand significant bits.

[0041] Whether rounding increment is needed can be determined separately for overflow and non-overflow situations. To help achieve this, a rounding state determination circuit can determine, together with at least one of the addition circuits, a non-overflow rounding state flag set assuming no overflow, and an overflow rounding state flag set assuming overflow. Before determining that the result of an overflow has been available, both the non-overflow rounding state flag set and the overflow rounding state flag set can be determined. Similarly, this helps improve performance because, typically, determining whether an overflow has occurred requires waiting until the most significant bit of the addition performed by the addition circuit is available, which can be relatively slow. Therefore, waiting to learn whether an overflow has occurred before calculating the relevant rounding state flags can result in significant delays. By determining separate rounding state flag sets for the overflow and non-overflow situations, it is possible to select between candidate sum values ​​earlier than would otherwise be possible. The overflow / non-overflow protection and sticky flags can be calculated by masking (as described above), and the overflow / non-overflow least significant bit flag can be calculated as the lowest two bits of the result of the addition of the larger operand significant bits (first version) and the shifted smaller operand significant bits.

[0042] The selection between candidate sum values ​​can be divided into several stages, performing three separate selections. A first rounding selection circuit can select one of a first candidate sum value and a second candidate sum value based on a set of non-overflow rounding status flags generated assuming no overflow. A second rounding selection circuit can select between the first candidate sum value and a third candidate sum value based on a set of overflow rounding status flags determined assuming overflow. The first, second, and third candidate sum values ​​can be sum values ​​based on the first, second, and third versions of the larger operand's significant bits, with rounding increments of 0, 1, or 2, respectively. The first and second rounding selection circuits can operate in parallel with each other and with a portion of the overflow indication determination itself. Subsequently, when an overflow indication is available, the overflow selection circuit selects between the outputs of the first and second rounding selection circuits based on the overflow indication, and the output selected by the overflow selection circuit can be used as the rounded result for adding the first and second floating-point operands. This approach improves performance compared to performing a three-way selection because the rounding selection is known before the overflow selection. The combined round and overflow multiplexer selection logic will incur delays due to the control logic (the selection is based on the round and overflow logic functions, and the selection logic is slower than the slowest of the round and overflow inputs) and the large 3-way multiplexer.

[0043] As described above, the alignment shift used to align the smaller operand's significand with the larger operand's significand can be a relatively slow part of the floating-point addition process. To improve the performance of the alignment shift, the alignment shift circuitry can begin shifting the significands of the first and second floating-point operands before the result of determining which of the first and second floating-point operands has the smaller exponent is available. For example, the exponent difference can be determined by subtracting one exponent from the other, and since subtraction can typically be performed using a carry-propagation adder, the low-order bits of the exponent difference can be available before the high-order bits, as the calculation of the high-order bits must wait until the carry from the low-order bits propagates to the high-order bits. Which operand has the smaller exponent can be determined based on the most significant bit of the exponent difference, and thus, can only be determined after the lower portion of the exponent difference has been determined. Therefore, to improve performance, the shifting of each floating-point significand can be started based on the lower portion of the exponent difference, without knowing which operand actually needs to be shifted. Once it is known which operand has the smaller exponent, the corresponding partially shifted significand can be selected for further shifting.

[0044] Therefore, the alignment shift circuit may include: a first shift circuit for shifting the significand of the first floating-point operand based on a low-order portion of a first exponent difference to generate a first shift value, wherein the first exponent difference corresponds to a result of subtracting the exponent of the first floating-point operand from the exponent of the second floating-point operand; a second shift circuit for shifting the significand of the second floating-point operand based on a low-order portion of a second exponent difference to generate a second shift value, wherein the second exponent difference corresponds to a result of subtracting the exponent of the second floating-point operand from the exponent of the first floating-point operand; a significand selection circuit for selecting the first shift value when the first floating-point operand has a smaller exponent and selecting the second shift value when the second floating-point operand has a smaller exponent; and a third shift circuit for shifting one of the first shift value and the second shift value selected by the significand selection circuit based on a high-order portion of a corresponding one of the first exponent difference and the second exponent difference.

[0045] Thus, in this way, the delays of the first and second shift circuits can occur in parallel with determining which of the first and second floating-point operands has the smaller exponent, meaning that the delays beyond the point in time when it has been determined which operand has the smaller exponent are lower. In this way, the third shift circuit can perform the shift in parallel with the increment circuit generating an alternate version of the larger operand's significand.

[0046] The data processing device may include the floating-point addition circuit discussed above. The floating-point addition circuit discussed above may not be the only processing path provided for adding floating-point operands. The floating-point addition circuit discussed above can be used for far-path floating-point addition (addition of similar-sign operands, subtraction of non-similar-sign operands, addition of non-similar-sign operands with exponent difference greater than 1, or subtraction of similar-sign operands with exponent difference greater than 1). A separate near-path addition circuit can be provided to process the addition of non-similar-sign operands with exponent difference of 0 or 1 or the subtraction of similar-sign operands with exponent difference of 0 or 1. For the near-path addition circuit, multi-bit alignment shift is not required, but standardized shift may be required to process the leading zero in the result, and the result may be a subnormal value. Therefore, the floating-point addition circuit comprising the above-mentioned alignment shift circuit, increment circuit, addition circuit and selection circuit can be used for the far-path processing circuit of the floating-point addition unit in the data processing device.

[0047] Floating-point representation

[0048] Floating point (FP) is an efficient way to approximate real-world numbers using a small number of bits. The IEEE 754-2008 FP standard proposes several different formats for FP numbers, and ARM focuses on binary64 (also known as double precision, or DP), binary32 (also known as single precision, or SP), and binary16 (also known as half precision, or HP). The numbers 64, 32, and 16 refer to the number of bits required for each format.

[0049] FP numbers are very similar to the "scientific notation" taught in science class, where we write -2.0×10 6 , not -2,000,000. The parts of this number are: the sign (negative in this case), the significand (2.0), the base of the exponent (10), and the exponent (6). All of these parts have analogs in FP numbers, but there are differences, the most important of which is that the components are stored in binary, and the base of the exponent is always 2.

[0050] More precisely, an FP number consists of a sign bit, some biased exponent bits, and some fraction bits. Some FP formats of interest provide the following bits:

[0051] Format symbol index Decimals Exponential bias DP[63:0] 63 62:52 (11th place) 51:0 (52 bits) 1023 SP[31:0] 31 30:23 (8 digits) 22:0 (23rd place) 127 HP[15:0] 15 14:10 (5 people) 9:0 (10 digits) 15

[0052] The sign of a negative number is 1, and the sign of a positive number is 0. Every number, including zero, has a sign.

[0053] The exponent is biased, meaning the true exponent is different from the exponent stored in the number. For example, the biased SP exponent is 8 bits long and ranges from 0 to 255. While exponents 0 and 255 are special cases, all other exponents have a bias of 127, meaning the true exponent is 127 less than the biased exponent. The smallest biased exponent is 1, corresponding to a true exponent of -126. The largest biased exponent is 254, corresponding to a true exponent of 127. HP and DP exponents work the same way, with biases as shown in the table above.

[0054] The SP exponent 255 (or DP exponent 2047 or HP exponent 31) is reserved for infinity and a special symbol called NaN (Not a Number). The fraction of an infinity (which can be positive or negative) is zero. Any number with an exponent of 255 and a non-zero fraction is a NaN. Infinity provides a saturation value, so it effectively means something like "this calculation produced a number larger than we can represent in this format." NaN is returned for operations that are not mathematically defined on real numbers, such as division by zero or taking the square root of a negative number.

[0055] In either format, exponent zero is reserved for subnormal numbers and zero. Normal numbers represent values: -1 符号 ×1.Decimal×2 e , where e is the true exponent calculated from the biased exponent. The term "1.decimal" is called the significand, and 1 is not stored as part of the FP number, but is inferred from the exponent. All exponents except 0 and the largest exponent represent the significand of the form "1.decimal". An exponent of 0 represents a significand of the form "0.decimal" and a true exponent equal to 1 - bias for the given format. Such numbers are called subnormals (historically, these numbers were called anomalous, but modern usage prefers the term subnormal). A number with both exponent and decimal equal to zero is zero.

[0056] The following table shows some example numbers in HP format. The entries are in binary format, with the "_" character added to improve readability. Note that the subnormal entries (row 4 of the table, whose exponent is zero) generate a different significand than the normal entries in the previous row.

[0057] symbol 5-digit index 10 decimal places 11 significant digits Bit 0 01111 00_0000_0000 100_0000_0000 <![CDATA[1.0×2 0 ]]> 1 01110 10_0000_0000 110_0000_0000 <![CDATA[-1.1×2 -1 ]]> 0 00001 10_0000_0000 110_0000_0000 <![CDATA[1.1×2 -14 ]]> 0 00000 10_0000_0000 010_0000_0000 <![CDATA[0.1×2 -14 ]]> 1 11111 00_0000_0000 -Infinity 0 11111 00_1111_0011 NaN

[0058] Much of the complexity of FP implementations is due to subnormals, so they are typically handled by microcode or software. Handling subnormal processing circuitry in hardware can speed up these operations by 10 to 100 times compared to software or microcode implementations.

[0059] Integer, fixed-point, floating-point

[0060] The FP way of handling signs is called signed magnitude, and it differs from the way integers are normally stored in computers (two's complement). In signed-value representation, the positive and negative versions of the same number differ only in the sign bit. A 4-bit signed-value integer (consisting of a sign bit and 3 significand bytes) represents addition and subtraction of one as:

[0061] +1=0001

[0062] -1=1001

[0063] In two's complement representation, an n-bit integer i is represented by the binary n+1-bit value 2 n +i represents the low-order n bits, so the 4-bit two's complement integer will be added or subtracted as:

[0064] +1=0001

[0065] -1=1111

[0066] The two's complement format is practically universal for signed integers because it simplifies computer arithmetic.

[0067] A fixed-point number looks exactly like an integer, but it actually represents a value with a certain number of fractional bits. Sensor data is often in fixed-point format, and a large amount of fixed-point software was written before the widespread adoption of FP. Working with fixed-point numbers is cumbersome because programmers must keep track of the "binary point," the separator between the integer and fractional parts of a number, and must constantly shift the number to keep the bits in the correct position. FP numbers don't present this difficulty, so it's desirable to be able to convert between fixed-point and FP numbers. This conversion means you can still use fixed-point software and data, but you're not limited to fixed-point when writing new software.

[0068] Rounding of FP numbers

[0069] The IEEE-754 standard requires that most FP operations be computed as if they were performed with unlimited range and precision and then rounded to fit within an FP number. If a calculation fits an FP number exactly, that value is always returned, but often the calculation produces a value that lies between two consecutive floating-point numbers. Rounding is the process of selecting which of two consecutive numbers should be returned.

[0070] There are several ways of rounding, called rounding modes; the six such rounding modes are as follows:

[0071] model definition RNE Round to the nearest even value Take the closest value, or if two values ​​are equally close, take the even value RNA Round to the nearest value Take the closest value, or if two values ​​are equally close, take the value farthest from zero RZ Round towards zero Take the value closest to zero RP Round toward positive infinity Take the value closest to positive infinity RM Round towards negative infinity Take the value closest to negative infinity RX Round towards odd Take odd values

[0072] This definition doesn't tell us how to do this in any practical way. A common implementation is to do the operation, find the truncated value (i.e., the value that fits in FP format) and all the remaining bits, and then adjust the truncated value if some condition is met. All calculations are based on:

[0073] L (Lowest) least significant bit of the truncated value

[0074] G (Guard) The next most significant bit (that is, the first bit not included in the truncation)

[0075] S (sticky) is the logical OR of all remaining bits that were not part of the truncation.

[0076] Given these three values ​​and the truncation value, we can calculate the correctly rounded value according to the following table (Table 1):

[0077] Table 1

[0078] For example, consider multiplying two 4-bit significands and then rounding to 4 significands.

[0079] sig1 = 1011 (decimal 11)

[0080] sig2 = 0111 (decimal 7)

[0081] Multiply the benefits

[0082] sig1×sig2=1001_101 (decimal 77)

[0083] L Gss

[0084] model Change to cutoff value RNE If (L&G)|(G&S), then increment RNA If G, then increase RZ none RP If it is a positive number &(G|S), it will be incremented RM If it is a negative number &(G|S), it will be incremented RX If G|S, then set L

[0085] The least significant bit of the truncated 4-bit result is labeled L, the next bit is G, and S is the logical OR of the remaining bits labeled s (i.e., S=0|1=1). To round, we adjust our 4-bit result (1001) according to the rounding mode and calculation in the table above. So, for example, in RNA rounding, G is set, so we return 1001+1=1010. For RX rounding, G|S is true, so we set L to 1 (it was already 1, so there is no change in this case) and return 1001.

[0086] Example

[0087] Figure 1An example of a data processing device 2 is schematically shown. The data processing device has a processing pipeline 4 comprising a plurality of pipeline stages. In this example, the pipeline stages include a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetched program instructions to generate micro-operations to be processed by the rest of the pipeline; an issue stage 12 for checking whether operands required for a micro-operation are available in a register file 14 and issuing the micro-operation for execution if the operands required for a given micro-operation are available; an execute stage 16 for performing the data processing operation corresponding to the micro-operation, generating a result value by processing the operands read from the register file 14; and a writeback stage 18 for writing the processing result to the register file 14. It should be understood that this is merely one example of a possible pipeline architecture, and other systems may have additional stages or stages in a different configuration. For example, in an out-of-order processor, an additional register renaming stage may be included to map architectural registers specified by program instructions or micro-operations to physical register descriptors identifying physical registers in the register file 14.

[0088] The execution stage 16 includes multiple processing units for performing different categories of processing operations. For example, the execution units may include a scalar arithmetic / logic unit (ALU) 20 for performing arithmetic or logical operations on scalar operands read from a scalar register file 21; a floating point unit 22 for performing operations on floating point values; a branch unit 24 for evaluating the results of branch operations and adjusting the program counter representing the current execution point accordingly; and a load / store unit 28 for performing load / store operations to access data in the memory system 8, 30, 32, 34. In this example, the memory system includes a level 1 data cache 30, a level 1 instruction cache 8, a shared level 2 cache 32, and a main system memory 34. It will be understood that this is only one example of a possible memory hierarchy and that other arrangements of caches may be provided. The particular type of processing units 20 to 28 shown in the execution stage 16 is only one example, and other implementations may have different sets of processing units, or may include multiple instances of the same type of processing unit so that multiple micro-operations of the same type can be processed in parallel. It will be understood that Figure 1 This is only a simplified representation of some components of a possible processor pipeline architecture, and the processor may include many other elements that are not shown for the sake of brevity, such as branch prediction mechanisms or address translation or memory management mechanisms.

[0089] One operation supported by the floating point unit 22 may be the addition of two operands opa and opb, where opb and opb are expressed as floating point numbers. Figure 2The floating-point adder 40 shown may include near-path processing circuitry 42 and far-path processing circuitry 44, as well as a multiplexer or selector 46 for selecting between the outputs of near-path processing circuitry 42 and far-path processing circuitry 44. The floating-point addition unit can handle both addition and subtraction operations. For addition operations, if the two floating-point operands opa and opb have the same sign (both positive or both negative), it is a valid addition; if the two operands have different signs (one positive and the other negative), it is a valid subtraction. For subtraction operations, if the two operands have different signs, it is effectively an addition; if the two operands have the same sign, it is effectively a subtraction. The selection of the far-path adder or the near-path adder depends on the relative signs of the two operands and whether the instruction being executed is an addition or subtraction instruction. Hereinafter, terms such as signed addition (LSA) refer to valid addition operations, i.e., addition operations where the two operands have the same sign or subtraction operations where the two operands have different signs. The term Unlikely Signed Addition (USA) refers to a valid subtraction, that is, an addition operation where the two operands have different signs or a subtraction operation where the two operands have the same sign.

[0090] Near-path adder 42 has specific logic for handling USA (where the exponents of the two operands are the same or differ by only 1). Far-path adder 44 is used for LSA (regardless of the size of the exponent difference) and USA with an exponent difference greater than 1. Therefore, multiplexer 46 selects the near / far path output based on a comparison of the signs of opa and opb, a comparison of the exponents of opa and opb, and whether an addition or subtraction operation is requested.

[0091] The near-path logic 42 may include a leading zero counter to handle the possibility that the result has multiple leading zeros, where these leading zeros need to be eliminated by shifting to generate a normalized floating-point value with a valid digit of 1.F. In addition, the near-path circuit logic 42 may have circuitry for handling subnormal outputs. In the far-path adder 44, such leading zero counting and subnormal handling may not be required. Any known method may be used for the near-path adder 42. However, one design that can be used for the near-path adder 42 is the design described in U.S. patent application Ser. No. 15 / 793,063, filed by the same applicant and inventor as the present application. The contents of U.S. Ser. No. 15 / 793,063 are incorporated herein by reference in their entirety.

[0092] The design of the far path summing circuit 44 will be discussed in more detail below. Far path operations generally require alignment because we can only add or subtract bits that represent the same power of 2. So if we want to calculate:

[0093] 1.100×2 6 –1.100×2 4 ,

[0094] We first have to align the smaller operand with the larger operand. We do this by converting the problem into an equivalent problem by right-shifting the significand of the smaller operand (and increasing the exponent) until the two exponents are equal:

[0095] 1.100×2 6 –0.011×2 6

[0096] We then complete the addition or subtraction of the significands, perform a mathematically simple (to zero or one) normalization, and round the result. Typically, the far-path adder first aligns the significands, adds the aligned smaller operand significand to the larger operand significand, performs normalization if overflow occurs, and rounds the result by applying a rounding increment. However, packing all of this work into a single clock cycle is very difficult at the clock frequencies supported by modern processors, so in practice, most far-path adders require multiple cycles to complete this operation.

[0097] Figure 3 An example of a portion of the far path addition circuit 44 is shown. In this technique, the far path addition of opa, opb can be performed faster by performing the addition for applying the round increment in parallel with the alignment shift of the smaller operand's significant bits, generating several candidate sum values ​​based on each possible round increment that can be applied (including accounting for overflow), and then selecting between the candidate sum values ​​based on a rounding status flag determined based on the smaller operand's significant bits and the sum result.

[0098] Therefore, if Figure 3 As shown, the far path adder 44 may include an alignment shift circuit 50 , an increment circuit 52 , a plurality of adder circuits 54 , a selection circuit 56 , and a rounding state determination circuit 58 .

[0099] The alignment shift circuit 50 shifts the significand of the operand opa, opb, having the smaller exponent by a number of bit positions (determined based on the difference in the exponents of the two operands) to align the smaller operand significand with the larger operand significand. The label "sigs" is used to indicate the smaller operand significand (i.e., sigs is the significand of the operand opa, opb with the smaller exponent). The label "sigl" is used to refer to the larger operand significand (i.e., the significand of the operand opa, opb with the larger exponent).

[0100] In parallel with the alignment shift performed by the alignment shift circuit 50 to generate the shifted smaller operand significand (shifted sigs), the increment circuit 52 applies different rounding increments of 0, 1, and 2 to the larger operand significand sigl to generate multiple alternative versions 60 of sigl, which are provided to respective adder circuits 54. Each adder circuit 54 adds the shifted sigs to a corresponding one of the alternative versions 60 of sigl to generate a corresponding candidate sum value 62. Thus, three candidate sum values ​​62 are generated, one corresponding to sigl+sigs, one corresponding to sigl+sigs+1, and one corresponding to sigl+sigs+2.

[0101] The selection circuit 56 selects between the three candidate sum values ​​62 based on the following conditions:

[0102] (i) a subset of the rounding state information (the guard flags and the sticky flags (G, S) in the overflow / non-overflow case) determined by the rounding state determination circuit 58 using the unshifted smaller operand significand bits;

[0103] (ii) another subset of rounding status information (the least (L) flag for overflow / non-overflow cases) generated by one of the adder circuits 54, which adds sigs to the first version of sigl based on the round increment of 0; and

[0104] (iii) An overflow indication 63 which indicates whether or not there is an overflow in the addition of sigl and sigs.

[0105] The determination of the G, S flags by the rounding state determination circuit 58 may be performed in parallel with the alignment shift 50 based on masking the unshifted version of sigs, without waiting for the result of the shift.

[0106] Thus, by speculatively generating multiple alternative versions of the larger operand significand based on all round increments that may be needed, and generating multiple candidate sums of the corresponding alternative versions of the larger operand significand with the shifted smaller operand significand, this allows the latency associated with the rounded increment addition to be hidden in the shadow of the aligned shift to speed up the operation and make the far path addition logic more realistically fit into a single cycle. This enables the processor as a whole to operate at a higher clock frequency without having to split the floating point addition into multiple cycles.

[0107] like Figure 3As shown, the far-path adder 44 may also include circuit logic 66 for calculating the sign S and exponent E of the result value corresponding to the addition of opa and opb. For LSA, in the absence of overflow, the result exponent E can simply be equal to the exponent of the larger of the two operands, opa and opb. If overflow occurs, the result exponent E is equal to the exponent of the larger operand plus one. For USA, the non-overflow exponent is the exponent of the larger operand minus 1, while the overflow exponent is the exponent of the larger operand. In the case of sign-like addition, the result sign is equal to the signs of the two input operands. In the case of non-sign-like addition, the result sign is equal to the sign of the operand with the larger exponent. Therefore, the logic depth of the sign / exponent calculation logic 66 can be much shorter than the significand calculation logic. In practice, at a given clock frequency, the generation of the significand is more complex in terms of meeting circuit timing, so the remaining description focuses on the generation of the significand. Any known technique can be used to calculate the sign and exponent of the result.

[0108] Figure 4 The significant bit generation logic within the far path adder 44 is shown in more detail. In this example, the inputs to the far path adder 44 are two 64-bit double precision (DP) FP numbers: opa[63:0] and opb[63:0], which include the signs signa and signb, the exponents expa[10:0] and expb[10:0], and the fractions fraca[51:0] and fracb[51:0]. The significant bits siga[52:0] and sigb[52:0] are constructed by adding bits in front of the bits corresponding to whether the relevant exponent is zero (0) or non-zero (1).

[0109] The alignment shift circuit 50 shifts the significand of the smaller number to the right to align it with the significand of the larger number. The alignment shift is given by the corresponding exponent difference, so if, for example, expa > expb, then we shift sigb to the right by expa - expb bit positions. The fact that biased exponents 0 and 1 actually represent the same exponent is a complication (a biased exponent 0 represents a subnormal value when the fraction is non-zero), so if the exponent is 0, we substitute an exponent 1 when computing the exponent difference.

[0110] We begin the aligned shift without knowing which number has the larger exponent, so we actually perform two subtractions using adder 70: expa-expb and expb-expa. The low-order bits of these subtractions are available earlier than the high-order bits, so as soon as the low-order portions of expa-expb and expb-expa are available, first shift circuit 72 begins shifting sigb (by expb-expa bit positions) and second shift circuit 74 begins shifting sigb (by expa-expb bit positions), so that we obtain the partially shifted result when we know which exponent is larger. There is no need to track the guard and sticky bits that are shifted out of the significand, and the shifted-out bits are simply discarded because we will have earlier information about the shifted-out bits by applying a mask to the smaller operand before shifting it using rounding state determination circuit 58. We also avoid a correction shift for a zero exponent because we have replaced exponent = 0 with exponent = 1.

[0111] Once it is determined which of expa and expb is larger, selection circuit 76 within aligned shift unit 50 selects the output of first shift circuit 72 (partially shifted siga) if operand opa has the smaller exponent, and selects the output of second shift circuit 74 (partially shifted sigb) if operand opb has the smaller exponent. The one of siga and sigb corresponding to the smaller exponent becomes the smaller operand significant bit sigs, and the other becomes the larger operand sigl. Then, third shift circuit 78 performs an aligned shift of the smaller operand significant bit sig based on the high-order portion of the corresponding first / second exponent difference. That is, if sigs multiplexer 76 selects to partially shift siga, third shift circuit 78 shifts sigs based on the high-order bits of expb-expa, whereas if sigs multiplexer 76 selects to partially shift sigb, third shift circuit 78 shifts sigs based on the high-order bits of expa-expb.

[0112] At the same time, multiplexer 79 selects the larger operand significand sigl once it determines which operand has the larger exponent. Note that unlike sigs multiplexer 76, sigl multiplexer 79 selects the unshifted version of sigl rather than the partially shifted version of sigl generated by first shift circuit 72 / second shift circuit 74.

[0113] Left shifters 80 and 81 are provided in the signal paths that convey sig1 and the shifted sigs to the increment circuit 52 and adder circuit 54, respectively. These left shifters apply a 1-bit left shift when performing USA, but not when performing LSA. This is done to ensure that significand overflow occurs at the same location regardless of whether LSA or USA is being performed, which simplifies overflow detection and handling of overflow rounding. Furthermore, if USA is being performed, the left shifter 81 in the sigs path inverts sigs (while it does not invert sigs in the case of LSA). This is because floating-point significands are represented as sign-magnitude rather than two's complement, so to provide USA, the smaller operand must be negated, which is accomplished by inverting all bits and adding 1. The addition of 1 is handled by controlling the carry input of each adder circuit 54 based on whether LSA or USA is being performed and based on the guard / sticky flag. The carry out of adder circuit 54 is zero for LSA, zero for USA with any bit set in either the protect flag or the sticky flag, and one for USA with both the protect and sticky bits set to 0. This is because we need to add 1 to the two's complement USA, but the added 1 is added at the end of the shifted-out bits, so the added 1 reaches the 54-bit adder only if the shifted-out bits of the non-inverted version of sigs are all zeros (i.e., if the shifted-out bits of the inverted version are all 1s).

[0114] Thus, the output of the left shifter (either shifted by 1 bit or not shifted, depending on whether USA or LSA is being performed) is provided to increment circuit 52 and adder circuit 54, respectively.

[0115] At the same time, in parallel with the aligned shifting and selection of the significand based on which exponent is larger, the rounding state determination circuit 58 determines the guard flag g and the sticky flag s for use in determining whether round increments are applied. Multiplexer 83 selects the unshifted version of sigs based on the determination of which of expa and expb is smaller.

[0116] The mask generation circuit 84 constructs a mask to be applied to the unshifted version of sigs by first constructing an exponent difference sticky mask ediff_smask[54:0] having a certain number of zeros followed by d trailing ones, where d is the exponent difference expl–exps (where expl is the larger of expa and expb and exps is the smaller of expa and expb). The mask ediff_smask[54:0] has a 1 corresponding to each bit of the mask that will eventually be shifted out of the smaller operand.

[0117] It is desirable to avoid the need for a shifter to generate the mask ediff_smask[54:0], as this would result in a delay equivalent to the shift of sigs, which would negate the advantage of computing the guard / sticky flags by masking in the first place. For DP floating point, the exponent difference is an 11-bit value d containing bits d10-d0, and one method of generating the mask (where the lower d bits are set to 1 and all other bits are set to 0) uses a combination of AND (&) and OR (|) gates designed according to the following logic (Emask[i] is an abbreviation for bit i of ediff_smask[54:0]):

[0118]

[0119]

[0120] Therefore, the exponent difference mask is generated using combinational logic rather than shifters, which can be generated faster.

[0121] A slight complication is that the significand for the effective subtraction (non-signed addition, or USA) is left-shifted by 1 bit position using shifters 80, 81 as described above, so the significand overflow occurs at the same position as the effective addition (signed addition, or LSA). This left shift is compensated by a 1-bit right shift of ediff_smask for USA, so that even when an artificial 1-bit left shift is applied to the significand, the correct guard bit can still be selected. The most significant "1" bit in the exponent difference mask ediff_smask indicates the position of the guard bit, which we find using gmask:

[0122] gmask0[53:0]=ediff_smask[53:0]^ediff_smask[54:1];

[0123] gmask[52:0]=({53{~usa_v1}}&f_gmask0[52:0])

[0124] |({53{usa_v1}}&f_gmask0[53:1]);

[0125] Creating an XOR (^) of gmask0 locates the first non-zero bit, and gmask-mux selects between the LSA (unshifted) and USA (1-bit right-shifted) versions.

[0126] The remaining '1' bits in the exponent difference mask represent the bit positions of the bits shifted out to form the sticky flag, so the sticky mask is formed by right-shifting ediff_smask by one additional position and then selecting between the USA and LSA versions again.

[0127] smask[52:0]=({53{~usa_v1}}&ediff_smask[53:1])

[0128] |({53{usa_v1}}&ediff_smask[54:2]);

[0129] So, given the sticky bit s (the sticky rounding state flag), we perform a reduction operation by applying the mask to the unshifted less significant bits sigs[52:0] and seeing if any bits are set using a reduce-or (not a bitwise-or, where the result of a reduce-or corresponds to each individual bit in the same binary value being ORed together, e.g., (bit3|(bit2|(bit1|bit0), etc.):

[0130] assign s=|(sigs_unshifted[52:0]&smask[52:0]);

[0131] When computing the final sticky bit, we don't have to worry about whether the operation is LSA or USA, because for USA, the bits shifted out are invalidated. This means that all shifted-out bits that were zero will remain zero (because -0=0), and shifted-out bits that have a 1 set will remain non-zero (because -nonzero is still non-zero).

[0132] Protecting the bits is a bit more complicated.

[0133] raw_g=|(sigs_unshifted[52:0]&gmask[52:0]);

[0134] For LSA, f_raw_g is the guard bit. However, USA inverts this guard bit, and inverts it again if there is a carry from the low-order bit. We only get this carry if s is zero, so g is given by:

[0135] g_cin=~s&usa;

[0136] g = (raw_g^usa)^g_cin;

[0137] The high-order bits of LSA or USA can carry out, which is called a significant overflow. This causes g and s to appear one bit to the left of the non-significant overflow position. This is explained by the bit addition logic

[0138] ovfl_s=raw_g|s;

[0139] The value ovfl_g (the protection flag in case of overflow) is exactly the same as bit 0 of the unrounded sum (sigs+sigl), and since this value is generated much earlier than the rest of the sum, we do not need to pre-compute ovfl_g using the rounding determination circuit 58. Instead, ovfl_g will be available from the adder circuit 54, which adds sigs and sigl.

[0140] Given the unrounded ovfl_l and l for the two low-order bits, we can calculate the rounding exactly using the usual method (as shown in Table 1 above).

[0141] The next issue is the rounding increment, which can occur in either the non-overflow case (sum + 1) or the overflow case (sum + 2). Given the goal of fitting the logic depth into a single clock cycle, and the relatively high frequency, there is no time to generate this additional increment after the adder circuit 54 generates the sum, or even for a 3:2 CSA before the final adder(s), so how do we get this increment?

[0142] The answer is that it should be noted that while the smaller operand is being shifted, the larger operand essentially does nothing (not nothing at all, as described above, there is a one-bit left shift for USA at shifter 80, but that is done very early). We can use a longer shift time for the smaller operand to increment the larger operand in two places, so that we end up with three larger operands: sig1, sig1+1, and sig1+2. These incremented values ​​align perfectly with the rounded positions of the final sum. Therefore, increment circuit 52 includes two adders, one for determining sig1+1 and the other for determining sig1+2. The results, along with the incremented versions of sig1, are passed to adder circuit 54 as three alternate versions of sig1.

[0143] Three adder circuits 54 calculate the three final sums:

[0144] (1) sigl + shifted sigs

[0145] (2) sigl+1+shifted sigs

[0146] (3) sigl+2+shifted sigs

[0147] One of these values ​​is the correctly rounded far path sum, and the selection circuit 56 uses the pre-computed rounding information (l, g, s, ovfl_l, ovfl_g, ovfl_s) and the overflow indication 63 to select the correct answer. Of these rounding status flags, g, s, and ovfl_s have been calculated by the rounding status determination circuit 58 using the mask as described above. The non-overflow least significant bit flag (l) and the overflow protection flag (ovfl_g) are both equal to the least significant bit of the summation of sigl + shifted sigs performed by one of the adder circuits 54, and the overflow least significant bit flag (l) is equal to the second least significant bit of the summation of sigl + shifted sigs.

[0148] In fact, the rounding information is available before we know whether a significand overflow has occurred, so the selection circuit actually includes three multiplexers: a first multiplexer 90 and a second multiplexer 91 (round selection circuit) first select the non-incremented value and the incremented value for the non-overflow and overflow cases, respectively. Thus, if the non-overflow set of the rounding status flags (l, g, s) indicates that an increment is not required according to Table 1 above based on the selected rounding mode, the first round selection circuit 90 selects the first candidate sum value sigl + shifted sigs, and if an increment is required according to l, g, s for the currently selected rounding mode, the second candidate sum value sigl+1 + shifted sigs is selected. If the overflow set of the rounding status flags (ovfl_l, ovfl_g, ovfl_s) for the currently selected rounding mode indicates that a round increment is not required according to the logic shown in Table 1, the second round selection circuit selects the first candidate sum value sigl + shifted sigs. If the overflow set of the rounding status flags indicates that a round increment is required for the selected rounding mode, the third candidate sum value sigl+2 + shifted sigs is selected. The selected rounding mode can be indicated in a control register or in a parameter specified by the instruction that causes the processor to perform the floating-point addition. A third multiplexer (overflow selection circuit) 92 then selects between the outputs of the first multiplexer 90 and the second multiplexer 91 based on the overflow indication 63. Therefore, if the overflow indication 63 indicates that an overflow has occurred, the output of the second multiplexer 91 is used as the final result, while if no overflow has occurred, the output of the first multiplexer 90 is selected as the final result. If the rounding status flag indicates that an increment is not required, the overflow indication 63 is equal to sigl + the upper bit of the shifted sum of sigs; if the rounding status flag indicates that an increment is required, the overflow indication 63 is equal to sigl + the upper bit of the shifted sum of sigs.

[0149] Figure 5 It shows the use of Figure 4Flowchart of a method for processing the floating-point addition of operands opa and opb in the far path using circuit logic. At step 100, the alignment shift circuitry begins shifting the significands of operands opa and opb based on the low-order portions of the respective exponent differences (expb–expa, expa–expb). Simultaneously, at step 102, a determination is made as to which of the exponents, expa and expb, is smaller. Once the operand with the smaller exponent has been determined, then at step 104, multiplexer 76 of alignment shift circuitry 50 selects a partially shifted version of the significand sigs of the smaller operand. Furthermore, at step 106, multiplexer 79 selects the significand sig1 of the larger operand. Furthermore, at step 108, rounding state determination circuitry 58 begins generating a rounding mask based on the exponent difference exp–exps, where expl is the larger exponent of expa and expb, and exps is the smaller exponent.

[0150] At step 110 , the alignment shift circuit 50 continues to shift the smaller operand significand sigs based on the upper bits of the exponent difference expl−exps, and, at step 112 , if the operation is a non-signed addition, the shifter 81 applies an additional 1-bit left shift, and the shifted smaller operand significand is also inverted to process the 2's complement of the smaller operand significand.

[0151] Similarly, at step 114, if the operation is USA, a 1-bit left shift is applied to the larger operand significand sigl (for LSA, no shift is performed on sigl). At step 116, the increment circuit 52 generates alternative versions of the larger operand significand sigl corresponding to different rounding increments of 0, 1, and 2, respectively. The larger operand significand sigl is simply passed through unchanged to generate the first alternative version sigl, while the second and third alternative versions, based on rounding increments of 1 and 2, respectively, are generated by the carry-propagation adder 53 of the increment circuit 52.

[0152] At step 118, each of the adding circuits 54 adds one of the alternate versions of the larger operand significant bits sigl generated at step 116 to the shifted smaller operand sig generated by the alignment shift circuit 50 and the shifter 81. The carry out of each adder circuit 54 is determined to be 0 for either LSA or USA, and is determined to be 1 for USA where both the guard bit and the sticky bit are 0. The additions performed by each adder circuit 54 generate a plurality of candidate sum values ​​62, where each candidate sum value 62 represents a possible rounded sum result that can be selected based on the rounding state and the presence or absence of overflow.

[0153] At the same time, in parallel with the incrementing and shifting of the smaller operand significant bits, at step 120, the rounding state determination circuit 58 uses the mask generated at step 108 to calculate the corresponding overflow and non-overflow sets of sticky flags and the non-overflow protection flag using the mask logic discussed above. The adder circuit 54, which adds the non-incremented larger operand significant bit sigl to the shifted smaller operand sigl, also provides overflowed and non-overflowed versions of the least significant bit flag, and an overflowed version of the protection flag that is equal to the non-overflow least significant bit flag.

[0154] At step 122, the overflow rounding state flag set and the non-overflow rounding state flag set are used for two separate selections of whether to apply the rounding tool, one for the overflow case and the other for the non-overflow case. At step 124, the rounded non-overflow result is selected, and if the current rounding mode and state flags for the non-overflow case indicate that the increment should not be applied, a first candidate sum value corresponding to a round increment of 0 is used; or if the increment is to be applied in the non-overflow case, a second candidate sum value corresponding to a round increment of 1 is selected. Similarly, based on the overflow rounding state flag set and the current rounding mode, it is determined whether an increment is required for the overflow case. If an increment is not required, an alternative candidate sum value based on the larger operand significant bit SIG1 (round increment of 0) is used, and if a round increment is required for the overflow case, an alternative SIG1 version of the candidate sum corresponding to a round increment of 2 is selected.

[0155] In parallel with the selections at steps 122 and 124, at step 126, a determination is made as to whether an overflow occurs based on the addition by the adder circuit 54. Once the overflow indication 63 is prepared, at step 128, the overflow selection circuit determines which of the rounded non-overflow and overflow results obtained at step 124 should be selected as the final normalized and rounded result of the far path addition of operands opa, opb.

[0156] Therefore, it can be seen that much of the rounding process (including the addition by the increment circuit 52 and the calculation of the rounding status flag by the rounding status determination circuit 58) can be performed in parallel with the shifting of the smaller operand significant bit sig by the alignment shift circuit 50, which enables the far path addition to be packed into a single clock cycle even at a relatively high clock frequency. This significantly improves performance.

[0157] Example

[0158] An example of floating-point addition using this technique is shown below. In this example, we use a strange hybrid representation that includes a binary significand and a decimal exponent. No machine can do this, but it gives a clear interpretation.

[0159] Far path operations usually require alignment because we can only add or subtract bits that represent the same power of two. So if we want to calculate

[0160] opa–opb=1.1×2 6 –1.01×2 -15

[0161] We first have to align the smaller operand with the larger operand. We convert this problem into an equivalent problem by right-shifting the significand of the smaller operand (and implicitly increasing the exponent) until the two exponents are equal:

[0162] 1.1×2 6 –0.00000000000000101×2 6

[0163] When we start the operation, we don't know which exponent is greater, so we make two exponent differences: 6 - (-15) = 21 (binary 010101) and -15 - 6 = -21 (binary 101011). The low-order bits of the subtraction are available earlier than the high-order bits, so we start by shifting the significand with two different right shifts:

[0164] Assuming siga is larger, we start shifting sigb to the right by 010101

[0165] 1.01->0.101 (for low-order shift bits, shift one bit)

[0166] ->0.101 (do not shift two bits because the next shift bit is zero)

[0167] ->0.0000101 (shift four bits)

[0168] ->0.0000101 (do not shift eight bits)

[0169] Assuming sigb is larger, we start moving siga to the right to 101011

[0170] 1.1->0.11 (for low-order shift bits, shift one bit)

[0171] ->0.0011 (shift two bits)

[0172] ->0.0011 (do not shift four digits)

[0173] ->0.000000000011 (shift eight bits)

[0174] After multiple shifts like this, we know which exponential difference is positive, so we know that sigb is smaller, and we complete the shift where sigs = sigb.

[0175] ->0.00000000000000000000101 (shifted 16 bits)

[0176] ->0.00000000000000000000101 (do not shift 32 bits)

[0177] sigl is exactly the unshifted siga=1.1

[0178] When we add or subtract sig1 from sigs, there may be a carry from the most significant bit, which is called a significand overflow. Keeping this carry in a predetermined location simplifies processing, which we do by shifting sig1 and sigs left by 1 for unsigned addition (USA, also known as significand subtraction). USA also requires the inversion of sigs (the definition of 2's complement subtraction is sig1 + ~ sigs + 1).

[0179] The shifted sigs (expanded to 53 binary bits) is

[0180] 0_0000_0000_0000_0000_0000_1010_0000_0000_0000_0000_0000_0000_0000

[0181] The inverted and USA-1 bit left shifted signal (54 bits binary) is

[0182] 11_1111_1111_1111_1111_1110_1011_1111_1111_1111_1111_1111_1111_1111

[0183] When we shift sigs, we use the unshifted sigs to calculate the rounding information. We make a mask ediff_smask[54:0] based on the exponent difference d=expl-exps (d=21 in this example). The details of the mask construction are shown in the figure above. The mask consists of 34 zeros and 21 ones. We use logical XOR to operate on this mask.

[0184] Assign gmask0[53:0]=ediff_smask[53:0]^ediff_smask[54:1];

[0185] The mask is 33 zeros followed by a single, followed by 120 zeros. This mask is used to identify the guard bit g. Because we performed a 1-bit left shift on sigs for USA, the mask must also be left shifted 1 bit for USA (this means we can find the correct g for both USA and LSA by applying the mask to the unshifted sigs).

[0186] Assign gmask[52:0]=({53{~usa}}&gmask0[52:0])

[0187] |({53{usa}}&gmask0[53:1]);

[0188] We now use the mask to locate g in the unshifted sigs

[0189] raw_g=|(sigs_unshifted[52:0]&gmask[52:0]);

[0190] In our example, raw_g is zero. We use a similar masking technique to calculate the sticky flag(s)

[0191] Assignment smask[52:0]=({53{~usa}}&ediff_smask[53:1])

[0192] |({53{usa}}&ediff_smask[54:2]);

[0193] Assign s = |(sigs_unshifted[52:0]&smask[52:0]);

[0194] In our example, s is also zero.

[0195] So far, we have only calculated raw_g, which is the guard bit before it can be changed due to the USA logic. Recall that USA inverts sigs and adds 1, so the real guard bit requires more calculations:

[0196] Assign value n g_cin=~s&usa; / / Carry to the guard bit

[0197] Assignment g=(raw_g^usa)^g_cin;

[0198] We do not attempt to precompute l (the least significant bit of sigs – sigs) because it is available early in the adder. Given l, g, s, we can now compute the rounding. In this example, g = s = 0, so there is no rounding increment.

[0199] Very similar logic is used to calculate lo, go, so (significand overflow versions of l, g, s). Again, go = so = 0, so in the case of significand overflow, the result has no rounding increment.

[0200] The rounding choices for the non-overflow case of subtraction are (sig1–sigs) and (sig1–sigs+1).

[0201] We note that sigl–sigs+1=(sigl+1)–sigs

[0202] Since there is almost no logic on the SIGL path, we fill this gap by computing SIGL+1.

[0203] Similarly, the rounding options for subtraction overflow are (sigl–sigs) and (sigl–sigs+2).

[0204] sigl–sigs+2=(sigl+2)–sigs, so we also calculate sigl+2.

[0205] We then compute 3 different sums:

[0206] (1) SIGL–SIGS

[0207] (2)(signal+1)–signal

[0208] (3)(Signal+2)–Signal

[0209] Rounding multiplexer selection:

[0210] (Non-significant overflow) between (1) and (2)

[0211] (Valid bit overflow) between (1) and (3)

[0212] In our examples, we always choose the uncorrected value (1) since g=s=go=so=0.

[0213] Finally, we choose between overflow and non-overflow cases. An overflow case occurs if bit 53 of sigs is set, or if bit 53 of the rounded increment sum (sigs+1)–sigs is set. Our final sum (opl+~ops+1) is

[0214] 11_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000

[0215] 11_1111_1111_1111_1111_1110_1011_1111_1111_1111_1111_1111_1111_1111 1

[0217] It gives

[0218] 10_1111_1111_1111_1111_1110_1100_0000_0000_0000_0000_0000_0000

[0219] Bit 53 is set, so we select the overflow result (bits 53:1).

[0220] In this application, the phrase "configured to..." is used to indicate that the components of a device are configured to perform a defined operation. In this context, "configuration" refers to the interconnected arrangement or manner of hardware or software. For example, a device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that the device components need to be modified in any way to provide the defined operation.

[0221] Although illustrative embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be made thereto by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims.

Claims

1. A floating-point addition circuit for adding a first floating-point operand and a second floating-point operand, wherein the first floating-point operand and the second floating-point operand each include a significand and an exponent, the floating-point addition circuit comprising: an alignment shift circuit configured to shift a smaller operand significant bit based on an exponent difference to align the smaller operand significant bit with a larger operand significant bit, the exponent difference representing a difference between exponents of the first floating-point operand and the second floating-point operand, wherein the smaller operand significant bit is the significant bit of the one of the first floating-point operand and the second floating-point operand having the smaller exponent and the larger operand significant bit is the significant bit of the one of the first floating-point operand and the second floating-point operand having the larger exponent; increment circuitry for generating a plurality of alternative versions of the larger operand significand, each alternative version of the larger operand significand being based on a different rounding increment applied to the larger operand significand; a plurality of summing circuits configured to generate a plurality of candidate sum values, each candidate sum value representing a sum of: the shifted smaller operand significand generated by the alignment shift circuit and a respective one of the plurality of alternative versions of the larger operand significand generated by the increment circuit; a selection circuit configured to select one of the plurality of candidate sum values ​​generated by the plurality of adding circuits based on a plurality of rounding status flags, the selected sum value representing a rounded result of adding the first floating-point operand and the second floating-point operand; and Round state determination circuitry is configured to determine a subset of the plurality of round state flags based on an unshifted version of the smaller operand significand.

2. The floating-point addition circuit according to claim 1, wherein: The increment circuit is configured to perform at least one addition, each addition adding a corresponding rounded increment to the larger operand significand; The increment circuit is configured to perform the at least one addition in parallel with at least a portion of the shifting of the smaller operand's significant bits performed by the alignment shift circuit.

3. The floating-point addition circuit according to any one of claims 1 and 2, wherein: The plurality of alternative versions of the larger operand significand include: The first version, the rounding increment for the first version is 0; a second version, for which the rounding increment is 1; and The third version, for which the rounding increment is 2.

4. The floating-point addition circuit according to any one of claims 1 and 2, wherein: The rounding state determination circuitry is configured to perform at least a portion of the determination of the subset of the plurality of rounding state flags in parallel with at least a portion of the shifting of the smaller operand significant bits performed by the alignment shift circuitry.

5. The floating-point addition circuit according to any one of claims 1 and 2, wherein: The round state determination circuitry is configured to determine at least one mask based on the exponent difference and to determine the subset of the plurality of round state flags based on masking the unshifted version of the smaller operand significand using the at least one mask.

6. The floating-point addition circuit according to any one of claims 1 and 2, wherein: The subset of the plurality of rounding status flags includes at least one guard flag and at least one sticky flag.

7. The floating-point addition circuit according to claim 6, wherein: The plurality of rounding status flags further include at least one least significant bit flag that is determined based on an addition performed by one of the plurality of adding circuits.

8. The floating-point addition circuit according to any one of claims 1 and 2, wherein: The selection circuit is configured to select the one of the candidate sum values ​​based on a plurality of rounding status flags and based on an overflow indication indicating whether addition of the aligned significant bits of the first floating point operand and the second floating point operand results in an overflow.

9. The floating point addition circuit of claim 8 , comprising a rounding state determination circuit, wherein: At least one of the plurality of adding circuits and the rounding state determination circuit are configured to determine a non-overflow rounding state flag set assuming no overflow and an overflow rounding state flag set assuming overflow before a result of determining whether overflow occurs is available.

10. The floating-point addition circuit according to any one of claims 1 and 2, wherein: The alignment shift circuit is configured to begin shifting the significands of both the first floating point operand and the second floating point operand prior to determining which of the first floating point operand and the second floating point operand has a smaller exponent.

11. A floating-point addition circuit for adding a first floating-point operand and a second floating-point operand, wherein the first floating-point operand and the second floating-point operand each include a significand and an exponent, the floating-point addition circuit comprising: an alignment shift circuit configured to shift a smaller operand significant bit based on an exponent difference to align the smaller operand significant bit with a larger operand significant bit, the exponent difference representing a difference between exponents of the first floating-point operand and the second floating-point operand, wherein the smaller operand significant bit is the significant bit of the one of the first floating-point operand and the second floating-point operand having the smaller exponent and the larger operand significant bit is the significant bit of the one of the first floating-point operand and the second floating-point operand having the larger exponent; increment circuitry for generating a plurality of alternative versions of the larger operand significand, each alternative version of the larger operand significand being based on a different rounding increment applied to the larger operand significand; a plurality of adding circuits for generating a plurality of candidate sum values, each candidate sum value representing a sum of: the shifted smaller operand significant bits generated by the alignment shift circuit and a respective one of the plurality of alternative versions of the larger operand significant bits generated by the increment circuit; and a selection circuit configured to select one of the plurality of candidate sum values ​​generated by the plurality of adding circuits, the selected sum value representing a rounded result of adding the first floating-point operand and the second floating-point operand; wherein: The selection circuit is configured to select the one of the candidate sum values ​​based on a plurality of rounding status flags and based on an overflow indication, the overflow indication indicating whether addition of the aligned significant bits of the first floating-point operand and the second floating-point operand results in an overflow, and the selection circuit comprises: a first round selection circuit configured to select between a first candidate sum value and a second candidate sum value based on a non-overflow rounding state flag determined assuming that no overflow exists; a second round selection circuit configured to select between the first candidate sum value and a third candidate sum value based on an overflow rounding status flag determined when an overflow is assumed; and Overflow selection circuitry is configured to select between outputs of the first round selection circuitry and the second round selection circuitry based on the overflow indication to provide a selected sum value representing the rounded result of adding the first floating point operand and the second floating point operand.

12. The floating-point addition circuit according to claim 11, wherein: The first round selection circuitry and the second round selection circuitry are configured to determine which candidate sum value to select in parallel with at least a portion of determining the overflow indication.

13. The floating-point addition circuit according to claim 11, wherein: The first candidate sum value is based on a first version of the larger operand's significand, the rounding increment for the first version being 0; the second candidate sum value being based on a second version of the larger operand's significand, the rounding increment for the second version being 1; The third candidate sum value is based on a third version of the larger operand significand, with a rounding increment of 2 for the third version.

14. A floating-point addition circuit for adding a first floating-point operand and a second floating-point operand, wherein the first floating-point operand and the second floating-point operand each include a significand and an exponent, the floating-point addition circuit comprising: an alignment shift circuit configured to shift a smaller operand significant bit based on an exponent difference to align the smaller operand significant bit with a larger operand significant bit, the exponent difference representing a difference between exponents of the first floating-point operand and the second floating-point operand, wherein the smaller operand significant bit is the significant bit of the one of the first floating-point operand and the second floating-point operand having the smaller exponent and the larger operand significant bit is the significant bit of the one of the first floating-point operand and the second floating-point operand having the larger exponent; increment circuitry for generating a plurality of alternative versions of the larger operand significand, each alternative version of the larger operand significand being based on a different rounding increment applied to the larger operand significand; a plurality of adding circuits for generating a plurality of candidate sum values, each candidate sum value representing a sum of: the shifted smaller operand significant bits generated by the alignment shift circuit and a respective one of the plurality of alternative versions of the larger operand significant bits generated by the increment circuit; and a selection circuit configured to select one of the plurality of candidate sum values ​​generated by the plurality of adding circuits, the selected sum value representing a rounded result of adding the first floating-point operand and the second floating-point operand; Wherein, the alignment shift circuit includes: a first shift circuit configured to generate a first shift value by shifting a significant bit of the first floating-point operand based on a low-order portion of a first exponent difference corresponding to a result of subtracting an exponent of the first floating-point operand from an exponent of the second floating-point operand; a second shift circuit configured to generate a second shift value by shifting a significant bit of the second floating-point operand based on a low-order portion of a second exponent difference, wherein the second exponent difference corresponds to a result of subtracting the exponent of the second floating-point operand from the exponent of the first floating-point operand; a significant bit selection circuit configured to select the first shift value when the first floating-point operand has a smaller exponent and to select the second shift value when the second floating-point operand has a smaller exponent; and a third shift circuit configured to shift the first shift value or the second shift value selected by the valid bit selection circuit, the shift being based on a high-order portion of a corresponding exponent difference of the first exponent difference or the second exponent difference.

15. The floating-point addition circuit according to claim 14, wherein: The third shift circuit is configured to perform a shift in parallel with the generation of the plurality of alternative versions of the larger operand significands by the increment circuit.

16. A data processing apparatus comprising a floating-point addition circuit according to any one of the preceding claims.

17. A floating-point addition circuit for adding a first floating-point operand and a second floating-point operand, wherein the first floating-point operand and the second floating-point operand each include a significand and an exponent; The floating-point addition circuit comprises: means for shifting, shifting a smaller operand significand based on an exponent difference to align the smaller operand significand with a larger operand significand, the exponent difference representing a difference between exponents of the first floating-point operand and the second floating-point operand, wherein the smaller operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the smaller exponent and the larger operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the larger exponent; means for generating, for generating a plurality of alternative versions of the larger operand significand, each alternative version of the larger operand significand being based on a different rounding increment applied to the larger operand significand; a plurality of means for adding for generating a plurality of candidate sum values, each candidate sum value representing a sum of: the shifted smaller operand significant bit generated by the means for shifting and a corresponding one of the plurality of alternative versions of the larger operand significant bit generated by the means for generating; means for selecting, for selecting one of the plurality of candidate sum values ​​generated by the plurality of means for adding based on a plurality of rounding status flags, the selected sum value representing a rounded result of adding the first floating-point operand and the second floating-point operand; and Means for determining a subset of the plurality of rounding status flags based on an unshifted version of the smaller operand significand.

18. A method for adding a first floating-point operand and a second floating-point operand, the first floating-point operand and the second floating-point operand each comprising a significand and an exponent; the method comprising: shifting a smaller operand significand based on an exponent difference to align the smaller operand significand with a larger operand significand, the exponent difference representing a difference between exponents of the first floating-point operand and the second floating-point operand, wherein the smaller operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the smaller exponent and the larger operand significand is the significand of the one of the first floating-point operand and the second floating-point operand having the larger exponent; generating a plurality of alternative versions of the larger operand significand, each alternative version of the larger operand significand being based on a different rounding increment applied to the larger operand significand; performing a plurality of additions to generate a plurality of candidate sum values, each candidate sum value representing a sum of: the shifted smaller operand significant bits generated by the shifting, and a corresponding one of the plurality of alternative versions of the larger operand significant bits; selecting one of the plurality of candidate sum values ​​generated by the plurality of additions based on a plurality of rounding status flags, the selected sum value representing a rounded result of adding the first floating-point operand and the second floating-point operand; and A subset of the plurality of rounding status flags is determined based on an unshifted version of the smaller operand significand.

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