A high-resolution in-situ fluid turbulence heating chip for transmission electron microscopy

Abstract

The invention relates to a transmission electron microscope high-resolution in-situ fluid turbulence heating chip, which has the structure that an upper chip and a lower chip are combined through a metal bonding layer to form a self-sealed ultrathin chamber; the upper chip has two sample injection ports and an upper central window; the lower chip is provided with a fluid inlet, a fluid outlet, a fluid flow channel, a lower central window, a micro-turbulence column array, a heating layer and an insulating layer; the heating layer has four contact electrodes and a spiral ring heating wire; the fluid inlet and the fluid outlet are symmetrically arranged about the central window, with the lower central window being the center and in the central area of ​​the spiral ring heating wire; the lower central window is located at the center of the heating layer; the micro-turbulence column array is arranged on the lower central window, and the chip has the advantages of rapid temperature rise and fall, high resolution, precise temperature control, controllable fluid flow direction and low sample drift rate.

Description

Technical Field

[0001] The invention relates to the field of fluid chips, and in particular to a transmission electron microscope high-resolution in-situ fluid turbulence heating chip. Background Art

[0002] In situ transmission electron microscopy (TEM) is a powerful and indispensable tool for characterizing materials, providing critical structural and chemical information. In recent years, electron microscopy has made significant progress, making atomic-scale imaging a routine process. Fluid TEM has the unique advantage of being able to directly observe the transformation dynamics of materials in fluids with high spatiotemporal resolution. For example, it is possible to track the growth trajectory of individual nanoparticles, the electrochemical deposition and lithiation of electrode materials, and the imaging of biomaterials in liquid water. Fluid TEM can not only be used to observe the behavior of nanomaterials in fluid environments in situ, but also integrate heating and freezing elements on fluid TEM chips and fluid rods for functional testing of nanomaterials, greatly broadening the research scope of transmission electron microscopy.

[0003] With the continuous development of nanotechnology, researchers have tried to combine nanomaterials with fluid transmission to study a new generation of efficient heat transfer technology, and studies have shown that evenly distributing nanoparticles in heat transfer fluids can significantly improve their thermal conductivity. However, due to the large difference between fluid motion behavior at the nanoscale and macroscopic motion behavior, in-situ research on the motion behavior of nanofluids is still very lacking, and the thermal conductivity mechanism of nanofluids is still unclear. Using in-situ turbulent heating TEM technology, researchers can track the dynamic changes of nanofluid structure, dynamic distribution of nanoparticles and other changes in real time to deepen people's understanding of nanofluids, which has guiding significance for the engineering application of nanofluids. Summary of the invention

[0004] The present invention aims to provide a transmission electron microscope high-resolution in-situ fluid turbulence heating chip with rapid temperature rise and fall, high resolution, controllable fluid flow direction, precise temperature control and low sample drift rate.

[0005] The specific plan is as follows:

[0006] A transmission electron microscope high-resolution in-situ fluid turbulence heating chip comprises an upper substrate and a lower substrate, wherein the upper substrate has a first insulating layer on the front and back sides thereof, and the lower substrate has a second insulating layer on the front and back sides thereof, and the front side of the upper substrate is bonded and fixed to the front side of the lower substrate through an annular metal bonding layer, and is self-sealed to form an ultra-thin chamber.

[0007] The upper substrate is provided with two injection ports and an upper central window, the upper central window is located at the center of the heating area, and the two injection ports are symmetrically arranged about the upper central window;

[0008] The lower substrate is provided with a fluid inlet, a fluid outlet, a fluid flow channel, a lower central window, a micro-turbulator column array, a heating layer and a third insulating layer; wherein the fluid inlet and the fluid outlet are connected in a straight line through the fluid flow channel; the width of the fluid flow channel increases at the lower central window and includes the entire heating area; the lower central window is located between the fluid inlet and the fluid outlet; the micro-turbulator column array is a rectangular column array, which is arranged along the longer side of the lower central window and is located in the lower central window, and the arrangement direction of the micro-turbulator column array is consistent with the fluid flow direction; the spiral ring heating wire at the center of the heating layer is placed on the second insulating layer on the front side of the lower substrate, and is roughly symmetrically distributed around the center of the lower central window, with gaps between the heating wires and not connected to each other; the heating layer also has four contact electrodes extending to the edge of the lower substrate and exposed; the third insulating layer covers the entire heating layer area except the four contact electrodes;

[0009] The upper and lower central windows on the upper and lower substrates are aligned, and the long sides of the upper and lower central windows are consistent with the direction of the fluid flow channel.

[0010] Furthermore, the lower substrate also has an isolation section and a support section, the isolation section is arranged outside the heating area in an annular manner, and has the carrier film of the insulating layer on the front surface of the lower substrate as its base; the annular isolation section is divided into a plurality of isolation section units, a support section is provided between two adjacent isolation section units, and the substrate body in the area below the support section is respectively connected to the two adjacent isolation section units;

[0011] Preferably, the isolation segment is divided into four isolation segment units arranged in a rectangular shape, and the support segments are distributed on the four corners of the isolation segment in a direction consistent with the diagonal line;

[0012] Preferably, the length of the isolation section is 0.3 mm-0.6 mm;

[0013] Optionally, the support segment width is 15um-30um.

[0014] Furthermore, the upper center window and the lower center window are both rectangular center windows;

[0015] Preferably, the size of the upper center window or the lower center window is 5um*5um-100um*100um; more preferably, the size of the upper center window or the lower center window is 10um*50um.

[0016] Furthermore, the size of the fluid inlet and the fluid outlet is 200um*200um-800um*800um;

[0017] Optionally, the width of the cross section of the fluid channel at the fluid inlet and fluid outlet is 10um-200um, the width of the cross section at the heating area is 250um-550um, and the height is 50nm-1000nm. 5. The transmission electron microscope high-resolution in-situ fluid turbulence heating chip according to claim 1, characterized in that: the size of the lower substrate is 2mm*2mm-10mm*10mm; preferably, the outer size of the lower substrate is 4mm*8mm;

[0018] Optionally, the thickness of the metal bonding layer is 50 nm-2000 nm; the material of the metal bonding layer is a low melting point metal; preferably, the material of the metal bonding layer is In, Sn or Al.

[0019] Furthermore, the insulating layer is silicon nitride or silicon oxide, and has a thickness of 5nm-200nm;

[0020] Optionally, the thickness of the upper substrate or the lower substrate is 50um-500um.

[0021] Furthermore, each micro-turbulator column in the micro-turbulator column array is a cylinder with a diameter of 1 um-20 um.

[0022] Furthermore, the outer diameter of the spiral annular heating wire of the heating layer is 0.2mm-0.5mm, and the thickness is 50nm-500nm;

[0023] Optionally, the spiral ring heating wire is made of metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium, or an alloy composed of at least two of the above metals or non-metallic molybdenum carbide.

[0024] Furthermore, the preparation method of the upper substrate is:

[0025] S101. Prepare a Si(100) wafer A having a silicon nitride or silicon oxide insulating layer on both sides;

[0026] Preferably, the thickness of silicon nitride or silicon oxide is 20nm-200nm;

[0027] S102. Using a photolithography process, the upper center window and the injection port pattern are transferred from the photolithography mask to the back side of wafer A, and then developed in a positive photoresist developer to obtain wafer A-1;

[0028] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0029] More preferably, the exposure time is 15 s;

[0030] S103. Using a reactive ion etching process, an upper center window and a sample injection port are etched on the insulating layer on the back of the wafer A-1, and then the back of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2;

[0031] S104. Using an ultraviolet laser direct writing process, the small hole pattern of the upper center window is transferred to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-3;

[0032] Preferably, the development time is 50s;

[0033] S105. Using a reactive ion etching process, the insulating layer at the small hole on the front side of the wafer A-3 is etched to a thickness of 10nm-15nm, and then the front side of the wafer A-3 is successively immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4;

[0034] Preferably, the pore size is 0.5um-5um;

[0035] S106. Place the wafer A-4 with its back side facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side of the upper center window, take out the wafer A-4 and rinse it with a large amount of deionized water to obtain a wafer A-5;

[0036] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., and the etching time is 1.5h-4h;

[0037] More preferably, the etching time is 2h;

[0038] S107. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6;

[0039] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0040] More preferably, the exposure time is 15 s;

[0041] S108. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7;

[0042] Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50nm-2000nm;

[0043] More preferably, the metal is In, Sn or Al;

[0044] S109. Laser scribe the wafer A-7, and the resulting independent chips are the upper substrates.

[0045] Furthermore, the preparation method of the lower substrate is:

[0046] S201. Prepare a Si(100) wafer B having a silicon nitride or silicon oxide insulating layer on both sides;

[0047] Preferably, the thickness of silicon nitride or silicon oxide is 5nm-200nm;

[0048] S202. Using a photolithography process, the fluid inlet and outlet and lower center window patterns are transferred from the mask to the back side of wafer B, then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain wafer B-1;

[0049] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s;

[0050] More preferably, the exposure time is 20 s;

[0051] S203. Using a reactive ion etching process, the insulating layer at the lower center window, the fluid inlet, and the fluid outlet of the silicon nitride layer on the back of the wafer B-1 is etched away, and then the back of the wafer is placed in acetone and immersed, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-2;

[0052] S204. Place the back side of wafer B-2 facing upward into a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, take out wafer B-2, rinse with a large amount of deionized water, and blow dry to obtain wafer B-3;

[0053] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70° C.-90° C., and the etching time is 1.5 h-4 h;

[0054] More preferably, the etching temperature is 80° C. and the etching time is 2 h;

[0055] S205. Using a photolithography process, the isolation segment and the isolation segment support segment pattern are transferred from the photolithography mask to the back of the wafer B-3, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-4;

[0056] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist of the photolithography process is AZ5214E; the development time is 65s;

[0057] More preferably, the exposure time is 20 s;

[0058] S206. Using a reactive ion etching process, the insulating layer at the back isolation section and the isolation section support section of the wafer B-4 is etched away, and then the back side of the wafer is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-5;

[0059] S207. Place the back side of wafer B-5 facing upward in a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, remove the wafer, rinse it with a large amount of deionized water, and blow it dry to obtain wafer B-6;

[0060] Preferably, the potassium hydroxide solution is a potassium hydroxide solution with a mass percentage concentration of 20%; the etching temperature is 70° C.-90° C., and the etching time is 1 h-3 h;

[0061] More preferably, the etching temperature is 80°C and the etching time is 2h;

[0062] S208. Using a photolithography process, the heating wire pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-7;

[0063] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet lithography machine, the photoresist used in the photolithography process is AZ5214E; the development time is 50s;

[0064] More preferably, the exposure time is 15 s;

[0065] S209. Using an electron beam evaporation process, a layer of metal heating wire is evaporated on the front side of the wafer B-7, and then the front side of the wafer B-7 is placed in acetone and immersed and peeled, and finally rinsed with deionized water to remove the photoresist, leaving the metal heating wire, to obtain a wafer B-8;

[0066] Preferably, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium, or an alloy composed of at least two of the above metals, or non-metallic molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;

[0067] S210. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of the wafer B-8 as an insulating layer to obtain a wafer B-9;

[0068] Preferably, the thickness of the insulating layer is 30nm-150nm;

[0069] S211. The fluid channel and micro-turbulator array pattern are transferred from the photolithography mask to the front side of the wafer B-9 by photolithography, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-10;

[0070] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet lithography machine, the photoresist used in the photolithography process is AZ5214E, and the development time is 50s;

[0071] More preferably, the exposure time is 15 s;

[0072] S212. A layer of non-precious metal material is deposited on the wafer B-10 by electron beam evaporation, and then the wafer is placed in acetone with the front side facing up and then stripped, and finally rinsed with deionized water to remove the photoresist, leaving the fluid channel and the micro-turbulation column array, to obtain a wafer B-11;

[0073] Preferably, the thickness of the non-precious metal material is 50nm-500nm; the non-precious metal material is Cr, Ti, Al, Zn or Cu; the width of the fluid flow channel is 10um-200um, and the height is 50nm-1um;

[0074] S213. Laser scribe the wafer B-11, and the resulting independent chips are the lower substrates.

[0075] The transmission electron microscope high-resolution in-situ fluid turbulence heating chip provided by the present invention has the following advantages compared with the prior art: the microfluidic channel and micro-turbulence column of the transmission electron microscope high-resolution in-situ fluid turbulence heating chip provided by the present invention can directly observe the fluid motion characteristics at a microscale, study the laws of fluid change behavior at a microscale, reveal the fluid motion mechanism, and deepen the relevant research foundation and application with its unique microscale characteristics. And the micro-turbulence column in the microchannel has a larger surface area, better promotes fluid disturbance, amplifies the fluid behavior at a microscale, and can observe and control a variety of fluid motion states at a microscale. At the same time, the present invention adds temperature control on the basis of fluid turbulence, and realizes functions such as precise temperature control, rapid temperature rise and fall, and designs an isolation section to effectively isolate the temperature heat conduction out of the heating area, so as to realize the accuracy and concentration of the central temperature control area. At the same time, the present invention can also realize high-resolution observation of fluid turbulence, and the fluid flow direction is controllable, the morphology is controllable, and the sample drift rate is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 This is a cross-sectional view of the high-resolution in-situ fluid turbulence heating chip for transmission electron microscopy.

[0077] Figure 2 A top view of the upper substrate is shown.

[0078] Figure 3 A top view of the lower substrate is shown.

[0079] Figure 4 An enlarged view of the heated area and its surroundings is shown.

[0080] Figure 5 An enlarged view of the lower center window is shown. DETAILED DESCRIPTION

[0081] To further illustrate the various embodiments, the present invention provides drawings. These drawings are part of the disclosure of the present invention, which are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, a person of ordinary skill in the art should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0082] The present invention will now be further described with reference to the accompanying drawings and specific implementation methods.

[0083] Example 1

[0084] The present invention provides a method for preparing a transmission electron microscope high-resolution in-situ fluid turbulence heating chip, the preparation method comprising the following steps:

[0085] Substrate production:

[0086] S101. Prepare a Si(100) wafer A having a silicon nitride or silicon oxide insulating layer on both sides, wherein the thickness of the silicon nitride or silicon oxide is 20nm-200nm;

[0087] S102. Using a photolithography process, the upper center window and the injection port pattern are transferred from the photolithography mask to the back side of wafer A, and then developed in a positive photoresist developer to obtain wafer A-1;

[0088] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0089] More preferably, the exposure time is 15 s;

[0090] S103. Using a reactive ion etching process, an upper center window and a sample injection port are etched on the insulating layer on the back of the wafer A-1, and then the back of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2;

[0091] S104. Using an ultraviolet laser direct writing process, the small hole pattern of the upper center window is transferred to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-3;

[0092] Preferably, the development time is 50s;

[0093] S105. Using a reactive ion etching process, the insulating layer at the small hole on the front side of the wafer A-3 is etched to a thickness of 10nm-15nm, and then the front side of the wafer A-3 is successively immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4;

[0094] Preferably, the pore size is 0.5um-5um;

[0095] S106. Place the wafer A-4 with its back side facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side of the upper center window, take out the wafer A-4 and rinse it with a large amount of deionized water to obtain a wafer A-5;

[0096] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., and the etching time is 1.5h-4h;

[0097] More preferably, the etching time is 2h;

[0098] S107. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6;

[0099] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the development time is 50s;

[0100] More preferably, the exposure time is 15 s;

[0101] S108. Using a thermal evaporation coating process, a metal bonding material is evaporated on the wafer A-6 to form a metal bonding layer to obtain a wafer A-7;

[0102] Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50nm-2000nm;

[0103] More preferably, the metal is In, Sn or Al;

[0104] S109. Laser scribe the wafer A-7 into independent chips, which are the upper substrates.

[0105] Lower substrate production:

[0106] S201. Prepare a Si (100) wafer B having a silicon nitride or silicon oxide insulating layer on both sides, the thickness of the silicon nitride or silicon oxide being 5nm-200nm;

[0107] S202. Using a photolithography process, the fluid inlet and outlet and lower center window patterns are transferred from the mask to the back side of wafer B, then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain wafer B-1;

[0108] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s;

[0109] More preferably, the exposure time is 20 s;

[0110] S203. Using a reactive ion etching process, the insulating layer at the lower center window, the fluid inlet, and the fluid outlet of the silicon nitride layer on the back of the wafer B-1 is etched away, and then the back of the wafer is placed in acetone and immersed, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-2;

[0111] S204. Place the back side of wafer B-2 facing upward into a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, take out wafer B-2, rinse with a large amount of deionized water, and blow dry to obtain wafer B-3;

[0112] Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70° C.-90° C., and the etching time is 1.5 h-4 h;

[0113] More preferably, the etching temperature is 80° C. and the etching time is 2 h;

[0114] S205. Using a photolithography process, the isolation segment and the isolation segment support segment pattern are transferred from the photolithography mask to the back of the wafer B-3, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-4;

[0115] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist of the photolithography process is AZ5214E; the development time is 65s;

[0116] More preferably, the exposure time is 20 s;

[0117] S206. Using a reactive ion etching process, the insulating layer at the back isolation section and the isolation section support section of the wafer B-4 is etched away, and then the back side of the wafer is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-5;

[0118] S207. Place the back side of wafer B-5 facing upward in a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, remove the wafer, rinse it with a large amount of deionized water, and blow it dry to obtain wafer B-6;

[0119] Preferably, the potassium hydroxide solution is a potassium hydroxide solution with a mass percentage concentration of 20%; the etching temperature is 70° C.-90° C., and the etching time is 1 h-3 h;

[0120] More preferably, the etching temperature is 80°C and the etching time is 2h;

[0121] S208. Using a photolithography process, the heating wire pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-7;

[0122] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet lithography machine, the photoresist used in the photolithography process is AZ5214E; the development time is 50s;

[0123] More preferably, the exposure time is 15 s;

[0124] S209. Using an electron beam evaporation process, a layer of metal heating wire is evaporated on the front side of wafer B-7, and then the front side of wafer 7 is placed in acetone and immersed in stripping, and finally rinsed with deionized water to remove the photoresist, leaving the metal heating wire, to obtain wafer B-8;

[0125] Preferably, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium, or an alloy composed of at least two of the above metals, or non-metallic molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;

[0126] S210. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of the wafer B-8 as an insulating layer to obtain a wafer B-9;

[0127] Preferably, the thickness of the insulating layer is 30nm-150nm;

[0128] S211. The fluid channel and micro-turbulator array pattern are transferred from the photolithography mask to the front side of the wafer B-9 by photolithography, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-10;

[0129] Preferably, the photolithography process is exposure in the hard contact mode of the ultraviolet lithography machine, the photoresist used in the photolithography process is AZ5214E, and the development time is 50s;

[0130] More preferably, the exposure time is 15 s;

[0131] S212. A layer of non-precious metal material is deposited on the wafer B-10 by electron beam evaporation, and then the wafer is placed in acetone with the front side facing up and then stripped, and finally rinsed with deionized water to remove the photoresist, leaving the fluid channel and the micro-turbulation column array, to obtain a wafer B-11;

[0132] Preferably, the thickness of the non-precious metal material is 50nm-500nm; the non-precious metal material is Cr, Ti, Al, Zn or Cu; the width of the fluid flow channel is 10um-200um, and the height is 50nm-1um;

[0133] S213. Laser-slice the wafer B-11 into independent chips, which are the lower substrates.

[0134] Assembly: Assemble the prepared upper substrate and lower substrate under a microscope, align the upper center window of the upper substrate and the lower center window of the lower substrate, and bond the upper substrate and the lower substrate to make a transmission electron microscope high-resolution in-situ vapor heating chip.

[0135] Example 2

[0136] like Figure 1-Figure 4 As shown, the present invention provides a transmission electron microscope high-resolution in-situ fluid turbulence heating chip, which includes an upper substrate 1 and a lower substrate 2, and the two opposite sides of the upper substrate 1 and the lower substrate 2 are defined as the front side and the back side respectively; wherein, the front side and the back side of the upper substrate 1 are both provided with a first insulating layer 10, and the front side and the back side of the lower substrate 2 are both provided with a second insulating layer 20. In this embodiment, the upper substrate 1 and the lower substrate 2 are both made of silicon substrates, and the first and second insulating layers are silicon nitride or silicon oxide insulating layers.

[0137] The front side of the upper substrate 1 is bonded and fixed to the front side of the lower substrate 2 via an annular metal bonding layer 30 , and is self-sealed to form an ultra-thin chamber 40 , wherein the film thickness of the metal bonding layer 30 is used as the height of the chamber 40 .

[0138] Among them, two injection ports 11 and an upper center window 12 are arranged on the upper substrate 1. The upper center window 12 is located at the center of the heating area, and the two injection ports 11 are symmetrically arranged about the upper center window 12. The two injection ports 11 are connected to the chamber 40, and the upper substrate 1 and the insulating layer on the back are etched away in the area of ​​the upper center window 12, leaving only the insulating layer on the front. In addition, the present invention etches a plurality of blind holes with openings on the front side on the insulating layer of the upper center window 12, so that the window film of the upper center window 12 can be thinner, and the thinner center window film can achieve a higher resolution. Therefore, in order to achieve a higher resolution, the present invention will further design a plurality of small holes in the existing square window, and use a thinner window film in the small holes to achieve a higher resolution. The shape of the small hole is not limited, and is not limited to circular, nearly circular, etc.

[0139] The lower substrate 2 is provided with a fluid inlet 21, a fluid outlet 22, a fluid flow channel 23, a lower central window 24, a micro-turbulator column array 25, a heating layer 26, a third insulating layer 27, an isolation section 28 and a support section 29. The fluid inlet 21 and the fluid outlet 22 are connected in a straight line through the fluid flow channel 23; the width of the fluid flow channel 23 increases at the lower central window 24 and includes the entire heating area; the lower central window 24 is located between the fluid inlet 21 and the fluid outlet 22.

[0140] The micro-turbine column array 25 is a columnar array arranged in a rectangular shape, which is arranged along the longer side of the lower central window 24 and is located in the lower central window 24, and the arrangement direction of the micro-turbine column array 25 is consistent with the flow direction of the fluid. The spiral annular heating wire 261 at the center of the heating layer 26 is placed on the second insulating layer 20 on the front of the lower substrate 2, and is roughly symmetrically distributed with the center of the lower central window 24. The heating wires 261 are spaced apart and are not connected to each other; the heating layer 26 also has four contact electrodes 262 extending to the edge of the lower substrate 2 and exposed, and the four contact electrodes 262 form two pairs, one pair of which is used as a heating electrode and the other pair is used as a monitoring electrode, so that the heating layer is set to two groups of equivalent circuits, and the two groups of equivalent circuits are controlled by separate current source meters and voltage source meters respectively; one group of the two groups of equivalent circuits is responsible for power supply and heat generation, and the other group of circuits is responsible for real-time monitoring of the resistance value of the heating wire after heating, and according to the relationship between resistance (R)-temperature (T) in the design program, the resistance of the test circuit is adjusted in real time through the feedback circuit to reach the set temperature. A third insulating layer 27 is disposed on the heating layer, and the third insulating layer 27 covers the entire heating layer region except for the four contact electrodes 262 .

[0141] The isolation section 28 is arranged outside the heating area in a ring, and the base film of the insulating layer 20 on the front side of the lower substrate 2 is used as the base film, that is, the silicon base film below the isolation section 28 area and the insulating layer on the back side are etched away, leaving only the insulating layer 20 on the front side, and the silicon nitride or silicon oxide acts as a supporting film to isolate the silicon substrate in the heating area from the silicon substrate of the entire chip to block the heat transfer effect, reduce the heat loss in the heating area, avoid the silicon substrate from expanding due to heat, and improve the sample drift phenomenon in the electron microscope test. In order to increase the strength of the isolation section 28, the annular isolation section 28 is divided into multiple isolation section units, and there is a supporting section 29 between two adjacent isolation section units. The silicon base film below the supporting section 29 is not etched away, so that there is a section of silicon base connecting the two adjacent isolation section units, so as to ensure the mechanical strength of the support film of the isolation section 28 and avoid the occurrence of support film rupture. In this embodiment, the isolation section 28 is divided into four isolation section units arranged in a rectangular shape, and the supporting sections 29 are distributed on the four corners of the isolation section.

[0142] In addition, the upper and lower central windows in this embodiment are both rectangular, and the long sides of the two are consistent with the direction of the fluid flow channel. When the upper substrate and the lower substrate are bonded together, the upper central window 12 of the upper substrate 1 and the lower central window 24 of the lower substrate 2 are required to be aligned. If they are skewed, the observation window will be too small and the window may not be found. If they are not aligned, the electron beam will not be able to pass through.

[0143] Although the present invention has been specifically shown and described in conjunction with the preferred embodiments, it should be understood by those skilled in the art that various changes may be made to the present invention in form and details without departing from the spirit and scope of the present invention as defined by the appended claims, all of which are within the scope of protection of the present invention.

Claims

1. A transmission electron microscope high-resolution in-situ fluid turbulence heating chip, comprising an upper substrate and a lower substrate, wherein the upper substrate has a first insulating layer on the front and back sides, and the lower substrate has a second insulating layer on the front and back sides, and the front side of the upper substrate is bonded and fixed to the front side of the lower substrate through an annular metal bonding layer, and is self-sealed to form an ultra-thin chamber, characterized in that: The upper substrate is provided with two injection ports and an upper central window, the upper central window is located at the center of the heating area, and the two injection ports are symmetrically arranged about the upper central window; The lower substrate is provided with a fluid inlet, a fluid outlet, a fluid flow channel, a lower central window, a micro-turbulator column array, a heating layer and a third insulating layer; wherein the fluid inlet and the fluid outlet are connected in a straight line through the fluid flow channel; the width of the fluid flow channel increases at the lower central window and includes the entire heating area; the lower central window is located between the fluid inlet and the fluid outlet; the micro-turbulator column array is a rectangular column array, which is arranged along the longer side of the lower central window and is located in the lower central window, and the arrangement direction of the micro-turbulator column array is consistent with the fluid flow direction, so as to promote fluid disturbance, amplify the fluid behavior at the microscale, and observe and control a variety of fluid motion states at the microscale; the spiral ring heating wire at the center of the heating layer is placed on the second insulating layer on the front side of the lower substrate, and is roughly symmetrically distributed about the center of the lower central window, with gaps between the heating wires and not connected to each other; the heating layer also has four contact electrodes extending to the edge of the lower substrate and exposed; the third insulating layer covers the entire heating layer area except the four contact electrodes; The upper and lower center windows on the upper and lower substrates are aligned, and the long sides of the upper and lower center windows are consistent with the direction of the fluid flow channel; The lower substrate also has an isolation section and a support section. The isolation section is arranged outside the heating area in an annular manner, and has the carrier film of the insulating layer on the front surface of the lower substrate as its base. The annular isolation section is divided into a plurality of isolation section units, and a support section is provided between two adjacent isolation section units. The substrate body in the area below the support section is respectively connected to the two adjacent isolation section units. The outer diameter of the spiral ring heating wire of the heating layer is 0.2mm-0.5mm, and the thickness is 50nm-500nm; the spiral ring heating wire is made of metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium, or an alloy composed of at least two of the above metals or non-metallic molybdenum carbide.

2. The transmission electron microscope high-resolution in-situ fluid turbulence heating chip according to claim 1, characterized in that: The isolation segment is divided into four isolation segment units arranged in a rectangular shape, and the support segments are distributed on the four corners of the isolation segment in the same direction as the diagonal line; or the length of the isolation segment is 0.3mm-0.6mm; the width of the support segment is 15um-30um.

3. The transmission electron microscope high-resolution in-situ fluid turbulence heating chip according to claim 1, characterized in that: The upper center window and the lower center window are both rectangular center windows; the size of the upper center window or the lower center window is 5um*5um-100um*100um; the size of the upper center window or the lower center window is 10um*50um.

4. The transmission electron microscope high-resolution in-situ fluid turbulence heating chip according to claim 1, characterized in that: The dimensions of the fluid inlet and the fluid outlet are 200um*200um-800um*800um; the width of the cross section of the fluid flow channel at the fluid inlet and the fluid outlet is 10um-200um, the width of the cross section at the heating area is 250um-550um, and the height is 50nm-1000nm.

5. The transmission electron microscope high-resolution in-situ fluid turbulence heating chip according to claim 1, characterized in that: The size of the lower substrate is 2mm*2mm-10mm*10mm; the outer size of the lower substrate is 4mm*8mm; the thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal; the material of the metal bonding layer is In, Sn or Al.

6. The transmission electron microscope high-resolution in-situ fluid turbulence heating chip according to claim 1, characterized in that: The insulating layer is silicon nitride or silicon oxide, and has a thickness of 5nm-200nm; the thickness of the upper substrate or the lower substrate is 50um-500um.

7. The transmission electron microscope high-resolution in-situ fluid turbulence heating chip according to claim 1, characterized in that: Each micro-turbulator column in the micro-turbulator column array is a cylinder with a diameter of 1um-20um.

8. The transmission electron microscope high-resolution in-situ fluid turbulence heating chip as claimed in claim 1, characterized in that: The preparation method of the upper substrate is: S101. Prepare a Si(100) wafer A having a silicon nitride or silicon oxide insulating layer on both sides; the thickness of the silicon nitride or silicon oxide is 20nm-200nm; S102. Using a photolithography process, the upper center window and the injection port pattern are transferred from the photolithography mask to the back side of wafer A, and then developed in a positive photoresist developer to obtain wafer A-1; The photolithography process is exposure in the hard contact mode of the UV lithography machine; The developing time is 50s; the exposure time is 15s; S103. Using a reactive ion etching process, an upper center window and a sample injection port are etched on the insulating layer on the back of the wafer A-1, and then the back of the wafer A-1 is immersed in acetone, and finally rinsed with a large amount of deionized water to remove the photoresist to obtain a wafer A-2; S104. Using an ultraviolet laser direct writing process, the small hole pattern of the upper center window is transferred to the front side of the wafer A-2, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-3; the development time is 50s; S105. Using a reactive ion etching process, the thickness of the insulating layer at the small hole on the front side of the wafer A-3 is etched to 10nm-15nm, and then the front side of the wafer A-3 is placed in acetone and immersed, and finally rinsed with acetone to remove the photoresist to obtain a wafer A-4; the aperture size of the small hole is 0.5um-5um; S106. Place the back side of wafer A-4 facing upward into a potassium hydroxide solution for wet etching until only a thin film window is left on the front side of the upper center window, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5; the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80° C., the time is 1.5h-4h; and the etching time is 2h; S107. Using a photolithography process, the bonding layer pattern is transferred from the photolithography mask to the front side of the wafer A-5, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer A-6; The photolithography process is exposure in the hard contact mode of the ultraviolet lithography machine; the development time is 50 seconds; and the exposure time is 15 seconds; S108. Using a thermal evaporation coating process, a metal bonding material is evaporated on wafer A-6 to form a metal bonding layer to obtain wafer A-7; the metal is a low melting point metal; the thickness of the metal bonding layer is 50nm-2000nm; and the metal is In, Sn or Al; S109. Laser scribe the wafer A-7, and the resulting independent chips are the upper substrates.

9. The transmission electron microscope high-resolution in-situ fluid turbulence heating chip as claimed in claim 1, characterized in that: The preparation method of the lower substrate is: S201. Prepare a Si (100) wafer B having a silicon nitride or silicon oxide insulating layer on both sides; the thickness of the silicon nitride or silicon oxide is 5nm-200nm; S202. Using a photolithography process, the fluid inlet and outlet and lower center window patterns are transferred from the mask to the back of wafer B, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain wafer B-1; the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist used in the photolithography process is AZ5214E; the development time is 65s; The exposure time is 20s; S203. Using a reactive ion etching process, the insulating layer at the lower center window, the fluid inlet, and the fluid outlet of the silicon nitride layer on the back of the wafer B-1 is etched away, and then the back of the wafer is placed in acetone and immersed, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-2; S204. Place the back side of wafer B-2 upward into a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely etched, take out wafer B-2, rinse with a large amount of deionized water, and blow dry to obtain wafer B-3; the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70°C-90°C, and the etching time is 1.5h-4h; the etching temperature is further 80°C; and the etching time is 2h; S205. Using a photolithography process, the isolation segment and the isolation segment support segment patterns are transferred from the photolithography mask to the back of the wafer B-3, and then developed in a positive photoresist developer, and then the surface is cleaned with deionized water to obtain a wafer B-4; the photolithography process is exposure in the hard contact mode of the ultraviolet photolithography machine; the photoresist of the photolithography process is AZ5214E; the development time is 65s; and the exposure time is 20s; S206. Using a reactive ion etching process, the insulating layer at the back isolation section and the isolation section support section of the wafer B-4 is etched away, and then the back side of the wafer is immersed in acetone, and finally rinsed with acetone to remove the photoresist to obtain a wafer B-5; S207. Place the back side of wafer B-5 upward in a potassium hydroxide solution for wet etching until the exposed substrate silicon is completely corroded, take out the wafer, rinse it with a large amount of deionized water, and then blow it dry to obtain wafer B-6; the potassium hydroxide solution is a potassium hydroxide solution with a mass percentage concentration of 20%; the etching temperature is 70°C-90°C, and the etching time is 1h-3h; the etching temperature is further 80°C, and the etching time is 2h; S208. Using a photolithography process, the heating wire pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive photoresist developer, and then rinsed and cleaned with deionized water to obtain a wafer B-7; The photolithography process is to expose in the hard contact mode of the ultraviolet lithography machine, and the photoresist used in the photolithography process is AZ5214E; the development time is 50s; and the exposure time is 15s; S209. Using an electron beam evaporation process, a layer of metal heating wire is evaporated on the front side of the wafer B-7, and then the wafer B-7 is placed in acetone with the front side facing upward to be immersed and peeled off, and finally rinsed with deionized water to remove the photoresist, leaving the metal heating wire, and obtaining the wafer B-8; the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium, or an alloy composed of at least two of the above metals, or non-metallic molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm; S210. Using a PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of the wafer B-8 as an insulating layer to obtain a wafer B-9; the thickness of the insulating layer is 30nm-150nm; S211. Transfer the fluid channel and micro-turbulator array pattern from the photolithography mask to the front side of the wafer B-9 by using a photolithography process, then develop it in a positive photoresist developer, and then rinse and clean the surface with deionized water to obtain a wafer B-10; the photolithography process is to expose in the hard contact mode of the ultraviolet photolithography machine, the photoresist used in the photolithography process is AZ5214E, the development time is 50s; the exposure time is 15s; S212. A layer of non-precious metal material is deposited on the wafer B-10 by electron beam evaporation, and then the wafer is placed in acetone with the front side facing up to be immersed and peeled off, and finally rinsed with deionized water to remove the photoresist, leaving the fluid channel and the micro-turbulence column array, to obtain wafer B-11; the thickness of the non-precious metal material is 50nm-500nm; the non-precious metal material is Cr, Ti, Al, Zn or Cu; the width of the fluid flow channel is 10um-200um, and the height is 50nm-1um; S213. Laser scribe the wafer B-11, and the resulting independent chips are the lower substrates.

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