Semiconductor device and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises forming a first and a second gate stack on the first to second well regions of the substrate, respectively, and forming a third gate stack on the third well region and the fourth well region of the substrate; using a photoresist mask, using the first gate stack and the third gate stack as a hard mask, forming a second doping type first source region and a first drain region in the first well region, and forming a second doping type third source region and a third drain region in the third well region and the fourth well region; using the first to the third gate stack as a hard mask, performing general implantation to form a first doping type second source region and a second drain region in the second well region, and when forming the second source region and the second drain region, the second doping type dopant of the first source region and the first drain region, the third source region and the third drain region are compounded with the first doping type dopant. The method omits additional masking and photolithography steps when forming the second source region and the second drain region, does not affect the performance of the semiconductor device, and can reduce the manufacturing cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process can integrate diodes, CMOS tubes, DMOS tubes, LDMOS tubes with various breakdown voltages, triodes, resistors and other devices into the same single chip. BCD devices have low power loss, high system performance and good stability. They are very popular in the fields of automotive electronics, power management, display drivers, etc. and have broad market prospects.

[0003] The traditional BCD process provides MOS tubes, diodes, triodes, resistors and other devices at the same time, which generally requires multiple masking and photolithography steps, and the process is complex and costly.

[0004] Therefore, the present invention needs to provide a semiconductor device and a method for manufacturing the same which can reduce mask and photolithography operations and do not affect the performance of the semiconductor device. Summary of the invention

[0005] In view of this, the present application provides a semiconductor device and a method for manufacturing the same in order to solve the above problems existing in the prior art.

[0006] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a first gate stack on a first well region of a first region of a substrate, the first well region being of a first doping type; forming a second gate stack on a second well region of the first region of the substrate, the second well region being of a second doping type, the first doping type being opposite to the second doping type, and the first well region and the second well region being adjacent to each other; forming a third gate stack on a third well region and a fourth well region of the second region of the substrate, the third well region being of the second doping type, the fourth well region being of the first doping type, the fourth well region being located in the third well region, and the first region and the second region being adjacent to each other; using a photoresist mask and using the first gate stack , using the third gate stack as a hard mask to form a first source region and a first drain region of the second doping type in the first well region, a third drain region of the second doping type in the third well region, and a third source region of the second doping type in the fourth well region; and removing the photoresist mask, performing general implantation to form a second source region and a second drain region of the first doping type in the second well region, wherein, in the step of forming the second source region and the second drain region, dopants of the second doping type in the first source region and the first drain region and in the third source region and the third drain region compound with dopants of the first doping type, and equivalent dopants in the first source region and the first drain region and in the third source region and the third drain region are maintained as the second doping type.

[0007] Preferably, the doping dose of the second doping type dopant forming the first source region and the first drain region and the third source region and the third drain region is higher than the doping dose of the first doping type dopant forming the second source region and the second drain region, so that the first source region and the first drain region and the third source region and the third drain region form an ohmic contact.

[0008] Preferably, after the step of forming the second source region and the second drain region, it also includes: forming an interlayer dielectric layer on the first gate stack, the second gate stack and the third gate stack; forming a plurality of channel holes that penetrate the interlayer dielectric layer and at least reach the first source region and the first drain region, the second source region and the second drain region and the third source region and the third drain region respectively; and filling the plurality of channel holes with a conductive material to form a plurality of conductive channels.

[0009] Preferably, after forming the conductive channel, portions of the first source region and the first drain region exposed by the channel hole and in contact with the conductive channel serve as the first source ohmic contact region and the first drain ohmic contact region, and portions of the third source region and the third drain region exposed by the channel hole and in contact with the conductive channel serve as the third source ohmic contact region and the third drain ohmic contact region.

[0010] Preferably, between the steps of forming the channel hole and the conductive channel, it also includes: using the multiple channel holes as injection channels, injecting dopants of the first doping type, forming a second source ohmic contact region and a second drain ohmic contact region in the second well region, the first source region and the first drain region and the second doping type dopant of the third source region and the third drain region compound the dopant of the first doping type, and the equivalent dopant of the first source region and the first drain region exposed through the channel holes as a part of the first source ohmic contact region and the first drain ohmic contact region is maintained as the second doping type, and the equivalent dopant of the third source region and the third drain region exposed through the channel holes as a part of the third source ohmic contact region and the third drain ohmic contact region is maintained as the second doping type.

[0011] Preferably, it also includes: in the step of forming the second source region and the second drain region, forming a first channel region of the first doping type in the fourth well region, and forming a second channel region of the first doping type in a fifth well region of the first doping type in the second region of the substrate, and the fifth well region is adjacent to the third well region.

[0012] Preferably, the multiple channel holes include channel holes that penetrate the interlayer dielectric layer and reach the first channel region and the second channel region respectively. In the step of forming the second source ohmic contact region and the second drain ohmic contact region, a first channel contact region of a first doping type is formed in the first channel region, and a second channel contact region of the first doping type is formed in the second channel region.

[0013] Preferably, it also includes: in the step of forming the first source region and the first drain region and the third source region and the third drain region, forming a first doping region of the second doping type in the substrate; in the step of forming the second source region and the second drain region, forming a second doping region of the first doping type extending outward in the sixth well region of the first area of ​​the substrate, and forming a fourth doping region of the first doping type in the sixth well region, the second doping region is in contact with the first doping region to form a PN structure, the sixth well region is adjacent to the second well region, the sixth well region is of the first doping type, the dopant of the second doping type in the first doping region is compounded with the dopant of the first doping type, and the equivalent dopant of the first doping region is maintained as the second doping type.

[0014] Preferably, the multiple channel holes include channel holes that penetrate the interlayer dielectric layer and reach the first doping region and the fourth doping region respectively. After forming the conductive channel, the portion of the first doping region exposed by the channel hole and in contact with the conductive channel serves as the first doped contact region. In the step of forming the second source ohmic contact region and the second drain ohmic contact region, a fourth doped contact region is formed in the fourth doping region, a portion of the dopants of the second doping type in the first doping region recombine the dopants of the first doping type, and the equivalent dopant of the first doped contact region in the first doping region is maintained as the second doping type.

[0015] Preferably, it also includes: in the step of forming the second source region and the second drain region, forming a third doping region of the first doping type in a seventh well region of the second doping type in the first region of the substrate to form a body resistor, and the seventh well region is adjacent to the sixth well region in the first region.

[0016] Preferably, the first gate stack, the second gate stack and the third gate stack respectively include a gate conductor and a gate dielectric, the gate dielectric is located between the gate conductor and the substrate, the gate conductor is a polysilicon layer, and the equivalent dopant of the gate conductor in the semiconductor device is the first doping type or the second doping type.

[0017] Preferably, in the process of forming the first gate stack, the second gate stack and the third gate stack, the gate conductor is polysilicon of the second doping type; in the process of forming the second source region and the second drain region, the dopant of the second doping type in the gate conductor is compounded with the dopant of the first doping type; the multiple channel holes include at least one channel hole that penetrates the interlayer dielectric layer to reach the gate conductor, and in the step of forming the second source ohmic contact region and the second drain ohmic contact region, the dopant of the second doping type of the gate conductor is compounded with the dopant of the first doping type, and the equivalent dopant of the gate conductor is maintained as the second doping type.

[0018] Preferably, in the process of forming the first gate stack, the second gate stack and the third gate stack, the gate conductor is polysilicon of the first doping type, and in the process of forming the first source region, the first drain region, the third source region and the third drain region, at least the dopant of the first doping type in the gate conductor in the first gate stack is compounded with the dopant of the second doping type; in the process of forming the second source region and the second drain region, the dopant of the first doping type is injected into the gate conductor; the multiple channel holes include at least one channel hole that penetrates the interlayer dielectric layer to reach the gate conductor, and in the step of forming the second source ohmic contact region and the second drain ohmic contact region, the dopant of the first doping type is injected into the gate conductor, and the equivalent dopant of the gate conductor is maintained as the first doping type.

[0019] Preferably, before the step of forming the first gate stack, the second gate stack and the third gate stack, it also includes: forming the second well region and the seventh well region of the second doping type in the first area of ​​the substrate, and forming the third well region of the second doping type in the second area of ​​the substrate; forming the first well region and the sixth well region of the first doping type in the first area of ​​the substrate, and forming the fourth well region and the fifth well region of the first doping type in the second area of ​​the substrate, wherein the well regions in the first area are arranged in parallel, the third well region and the fifth well region in the second area are adjacent to each other, and the fourth well region is located in the third well region; forming an isolation structure extending downward from the surface of the substrate between adjacent well regions, and the isolation structure serves as a part of the hard mask in the steps of forming the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region.

[0020] Preferably, the process of forming the well region of the first doping type includes: using a first photoresist mask to form an active region in a first area and a second area on the substrate; removing the first photoresist mask, using a second photoresist mask to block at least a portion of the substrate where the well region of the second doping type is formed, forming a first well region and a sixth well region of the first doping type in the first area of ​​the substrate, and forming a fourth well region and a fifth well region of the first doping type in the second area of ​​the substrate; using the second photoresist mask to block, and using the active area as a hard mask to form a compensation region of the first doping type on a portion of the surface of the well region of the first doping type, and then removing the second photoresist mask, wherein, in the process of forming the isolation structure, the active area is used as part of the hard mask, and then the active area is removed.

[0021] Preferably, the process of forming the well region of the second doping type and the well region of the first doping type includes: using a first photoresist mask to form an active region in the first area and the second area on the substrate; removing the first photoresist mask, using a third photoresist mask to block, so as to form the second well region and the seventh well region of the second doping type in the first area of ​​the substrate, and the third well region of the second doping type in the second area of ​​the substrate, and then removing the third photoresist mask; using a second photoresist mask to block at least the portion of the substrate where the well region of the second doping type is formed, forming a first well region and a sixth well region of the first doping type in the first area of ​​the substrate, and forming a fourth well region and a fifth well region of the first doping type in the second area of ​​the substrate; using the second photoresist mask to block, and using the active area as a hard mask to form a compensation region of the first doping type on a portion of the surface of the well region of the first doping type, and then removing the second photoresist mask, wherein, in the process of forming the isolation structure, the active area is used as part of the hard mask, and then the active area is removed.

[0022] Preferably, the implantation energy of the dopant of the first doping type forming the well region of the first doping type enables the dopant to penetrate the active region.

[0023] Preferably, the implantation energy of the dopant of the first doping type implanted when forming the compensation region is such that the dopant cannot penetrate the active region.

[0024] Preferably, the method further comprises: in the step of forming the isolation structure, forming a field oxygen region extending downward on a surface in the third well region, a surface in the fourth well region, and a surface in the sixth well region.

[0025] Preferably, it also includes: in the step of forming the first gate stack, the second gate stack and the third gate stack, forming a fourth gate stack on the field oxide region to serve as a field plate, and the third gate stack includes at least a portion located on the field oxide region as a field plate.

[0026] Preferably, the isolation structure includes at least one of a field oxide region and a trench isolation.

[0027] Preferably, the first doping type is P type, and the second doping type is N type.

[0028] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a first well region of a first doping type and a second well region of a second doping type located in a first region of the substrate, a third well region of a second doping type and a fourth well region of a first doping type located in a second region of the substrate, the first doping type being opposite to the second doping type, the first region being adjacent to the second region, the first well region being adjacent to the second well region, and the fourth well region being located in the third well region; a first gate stack located on the first well region, a second gate stack located on the second well region, and a third gate stack located on the third well region and the fourth well region; a first source region and a first drain region of a second doping type located in the first well region, a second source region and a second drain region of a first doping type located in the second well region, and a third source region and a third drain region of a second doping type located in the third well region and the fourth well region, wherein dopants of the second doping type in the first source region and the first drain region are compounded with dopants of the first doping type in the second source region and the second drain region, and dopants of the second doping type in the third source region and the third drain region are compounded with dopants of the first doping type in the second source region and the second drain region.

[0029] Preferably, the second drain region and the second source region have the same doping dose.

[0030] Preferably, it also includes: an interlayer dielectric layer, located above the first gate stack, the second gate stack, and the third gate stack; a plurality of channel holes, penetrating the interlayer dielectric layer and reaching at least the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region respectively; and a plurality of conductive channels, formed by filling the plurality of channel holes with conductive materials.

[0031] Preferably, the portions of the first source region and the first drain region in contact with the conductive channel serve as the first source ohmic contact region and the first drain ohmic contact region, the portions of the second source region and the second drain region in contact with the conductive channel serve as the second source ohmic contact region and the second drain ohmic contact region, and the portions of the third source region and the third drain region in contact with the conductive channel serve as the third source ohmic contact region and the third drain ohmic contact region.

[0032] Preferably, it also includes: a fifth well region of the first doping type located in the second area of ​​the substrate, the fifth well region and the third well region being adjacent to each other; a first channel region of the first doping type located in the fourth well region, and a second channel region of the first doping type located in the fifth well region, the doping doses in the first channel region and the second channel region being the same as the doping doses in the second source region and the second drain region.

[0033] Preferably, the plurality of channel holes include channel holes penetrating the interlayer dielectric layer and reaching the first channel region and the second channel region respectively, the first channel region includes a first channel contact region, and the second channel region includes a second channel contact region.

[0034] Preferably, it also includes: a sixth well region of the first doping type located in the first area of ​​the substrate, the sixth well region being adjacent to the second well region; a first doping region of the second doping type located in the substrate; and a second doping region of the first doping type extending outwardly from the sixth well region, the first doping region being in contact with the second doping region to form a PN structure, the second doping type dopant of the first doping region being compounded with the first doping type dopant in the second source region and the second drain region, and the doping dose in the second doping region being the same as the doping dose in the second source region and the second drain region.

[0035] Preferably, it also includes: a fourth doping region of the first doping type located in the sixth well region, the multiple channel holes include channel holes that penetrate the interlayer dielectric layer and reach the first doping region and the fourth doping region respectively, the fourth doping region includes a fourth doped contact region, the first doping region includes a first doped contact region, and the doping dose in the fourth doping region is the same as the doping dose in the second source region and the second drain region.

[0036] Preferably, it also includes: a seventh well region of the second doping type located in the first area of ​​the substrate, the seventh well region being arranged parallel to the well region in the first area; and a third doping region of the first doping type formed in the seventh well region to form a body resistor, the doping dose in the third doping region being the same as the doping dose in the second source region and the second drain region.

[0037] Preferably, the first gate stack and the second gate stack respectively include a gate conductor and a gate dielectric, the gate dielectric is located between the gate conductor and the substrate, the equivalent dopant of the gate conductor is a first doping type or a second doping type, and the multiple channel holes include at least one channel hole that penetrates the interlayer dielectric layer to reach the gate conductor.

[0038] Preferably, it further comprises: an isolation structure, which is located between adjacent well regions and extends downward from the surface of the substrate.

[0039] Preferably, the method further comprises: a compensation region of the first doping type located on a partial surface of the well region of the first doping type.

[0040] Preferably, the isolation structure includes at least one of a field oxide region and a trench isolation.

[0041] Preferably, it also includes: a field oxide region located on the surface of the third well region and extending downward; a fourth gate stack located on the field oxide region and serving as a field plate, and the third gate stack includes at least a portion located on the field oxide region and serving as a field plate.

[0042] Preferably, the first doping type is P type, and the second doping type is N type.

[0043] Preferably, the semiconductor device is a BCD device.

[0044] Preferably, the semiconductor device at least includes a CMOS device and at least one of a diode, a resistor, a capacitor, a low-voltage lateral transistor, a low-voltage vertical transistor, and a high-voltage semiconductor device.

[0045] Preferably, the high-voltage semiconductor device includes but is not limited to: a high-voltage JFET device, a gate-oxide high-voltage MOS device, and a field-oxide high-voltage MOS device.

[0046] The semiconductor device and the manufacturing method thereof provided by the present invention form a first semiconductor device structure and a second semiconductor device structure in a first region of a substrate, and form a fifth semiconductor device structure in a second region of the substrate. After forming the first source region and the first drain region in the first semiconductor device structure and the third source region and the third drain region in the fifth semiconductor device structure and removing the photoresist mask, a dopant of the first doping type is injected into the substrate to form the second source region and the second drain region in the second semiconductor device. The dopant of the second doping type in the first source region and the first drain region and the third source region and the third drain region is compounded with the dopant of the first doping type injected into the second source region and the second drain region in the second semiconductor device structure in this step, and the equivalent dopant of the first source region and the first drain region and the third source region and the third drain region is maintained as the second doping type. Therefore, when forming the second source region and the second drain region in the second semiconductor device structure, it is not necessary to use an additional mask to shield the first semiconductor device structure and the fifth semiconductor device structure. Compared with conventional practices, the number of photolithography times is reduced, which not only reduces the manufacturing cost, but also the performance of the semiconductor device manufactured by the above method can be guaranteed.

[0047] Preferably, in the present invention, when forming the second source ohmic contact region and the second drain ohmic contact region and the channel contact region, a channel hole penetrating the interlayer dielectric layer and reaching the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region is used as an injection channel to inject a dopant of the first doping type to form the second source ohmic contact region and the second drain ohmic contact region. Further, the dopant of the second doping type in the first source region and the first drain region and the third source region and the third drain region is compounded with the dopant of the first doping type injected into the second source region and the second drain region in the second semiconductor device structure in this step, and the equivalent dopant of at least a portion of the first source region and the first drain region is maintained as the second doping type to serve as the first source ohmic contact region and the first drain ohmic contact region, and the equivalent dopant of at least a portion of the third source region and the third drain region is maintained as the second doping type to serve as the third source ohmic contact region and the third drain ohmic contact region. Therefore, when forming the second source ohmic contact region and the second drain ohmic contact region in the second semiconductor device structure, there is no need to use an additional mask to cover the first semiconductor device structure and the fifth semiconductor device structure and form the second source ohmic contact region and the second drain ohmic contact region through a photolithography step. Compared with conventional practices, the number of photolithography times is reduced and the manufacturing cost is reduced.

[0048] Preferably, the present invention forms an isolation structure between adjacent well regions, and before forming a field oxygen region as an isolation structure, an active region is formed before forming a well region of the first doping type, and then a compensation region of the first doping type is formed on a partial surface of the well region of the first doping type using the active region as a hard mask to compensate for the loss of dopants in the well region of the first doping type due to the formation of the field oxygen region. At the same time, when forming the compensation region, the active region is first formed before forming the well region of the first doping type, and then after forming the well region of the first doping type, the compensation region is continuously formed without removing the photoresist mask used to shield the well region of the second doping type, and the well region of the first doping type is formed by high-energy implantation and the compensation region is formed on at least a partial surface of the well region of the first doping type by low-energy implantation through one photolithography, without using an additional mask to shield the well region of the second doping type and forming the compensation region through the photolithography step, and compared with conventional practices, the number of photolithography times is reduced, the process steps are simplified, and the manufacturing cost is reduced.

[0049] Preferably, in the step of forming the second source region and the second drain region, the present invention can simultaneously form a body resistor with high resistivity to achieve a large voltage drop, that is, when forming the resistor, no additional mask and photolithography operation are required to form a resistor with a high resistance value, thereby reducing the manufacturing cost. And at the same time, in the step of forming the second source region and the second drain region, a second doping region of the first doping type in contact with the first doping region of the second doping type is formed to form a PN structure of a diode device structure, that is, a diode with comparable voltage resistance to the existing one can be manufactured under the current simple process of reducing photolithography, such as a diode in a specific area of ​​a voltage-stabilizing diode or a triode. Therefore, no additional mask and photolithography steps are required to form the PN structure, thereby reducing the manufacturing cost. Further, when forming the PN structure, a part of the dopant of the second doping type in the first doping region is compounded with the dopant of the first doping type, and the equivalent dopant of the first doping region is maintained as the second doping type. Therefore, when forming the PN structure of the diode, no additional mask and photolithography steps are required, and compared with conventional practices, the number of photolithography steps is reduced, thereby reducing the manufacturing cost.

[0050] Preferably, when the gate conductor in the semiconductor device of the present invention is a polysilicon layer of the second doping type, the equivalent dopant of the final gate conductor in the semiconductor device is maintained as the second doping type. When the gate conductor in the semiconductor device is formed as a polysilicon layer of the first doping type, the equivalent dopant of the final gate conductor in the semiconductor device is maintained as the first doping type. That is, the polysilicon in the gate conductor is simultaneously injected with dopants during the process of forming the source and drain regions, and the dopant dosage is the same as the doping dosage when the source and drain regions are formed, and the dopant is compounded by a part of the initial dopant in the gate conductor to maintain the initial doping type.

[0051] Preferably, the semiconductor device in the present invention includes a BCD device, a Bi-CMOS device, or a CMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings.

[0053] Figure 1 A schematic structural diagram of a semiconductor device according to an embodiment of the present invention is shown.

[0054] Figure 2 The flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0055] FIG. 3A to FIG. 3H The schematic diagram shows the structure of each specific step in the semiconductor device manufacturing process.

[0056] Figure 4 A schematic diagram of a process for forming first to seventh well regions in another embodiment of the present invention is shown.

[0057] FIG. 5A to FIG. 5E A structural schematic diagram of each specific step in the process of forming the first to seventh well regions is shown. DETAILED DESCRIPTION

[0058] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0059] Many specific details of the present application are described below to provide a clearer understanding of the present application. However, as those skilled in the art will appreciate, the present application may be implemented without following these specific details.

[0060] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly above the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0061] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0062] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the semiconductor device, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0063] Figure 1 A schematic structural diagram of a semiconductor device according to an embodiment of the present invention is shown.

[0064] like Figure 1 As shown, the semiconductor device includes a substrate 100, a first semiconductor device 101, a second semiconductor device 102, a third semiconductor device 103, a fourth semiconductor device 104, and a fifth semiconductor device 105 located in the second region of the substrate and arranged adjacently in the lateral direction, and an isolation structure extending downward from the surface of the substrate 100 is provided between adjacent devices. The first region and the second region in the substrate 100 are adjacent to each other, the first region is a low-voltage device region, and the second region is a high-voltage device region.

[0065] In this embodiment, in the first region, the first semiconductor device is a low-voltage NMOS device 101, the second semiconductor device is a low-voltage PMOS device 102, the third semiconductor device is a diode 103, and the fourth semiconductor device is a resistor 104, and adjacent devices are isolated by a field oxygen region 200 located on the surface of the substrate 100 and extending downward. In other embodiments, other low-voltage devices such as lateral triodes, vertical triodes, capacitors, etc. can also be integrated in the first region, and devices such as diodes and resistors can also be removed according to actual needs. In addition, in other embodiments, the high-voltage devices in the second region can also be removed, and only the low-voltage devices in the first region are made. And the high-voltage semiconductor devices in the second region include but are not limited to: high-voltage JFET devices, gate oxygen high-voltage MOS devices, and field oxygen high-voltage MOS devices. In other embodiments, adjacent devices are isolated by a groove located on the surface of the substrate 100 and extending downward, and the depth of the groove is set based on the depth of the well region of each of the two adjacent devices to achieve isolation.

[0066] The low voltage NMOS device 101 includes a P-type low voltage first well region 110 located in the first region of the substrate, a first gate stack located above the first well region 110, an N-type first source region 711 and a first drain region 712 located on both sides of the first gate stack and in the first well region 110, and an interlayer dielectric layer 810 located above the first gate stack. The first gate stack includes a gate conductor 320 located in the first region, a gate dielectric 310 located between the gate conductor 320 in the first region and the first well region 110, and a gate spacer 330 located at the sidewalls of the gate conductor 320 and the gate dielectric 310 at both ends in the first region, and the gate conductor 320 is polysilicon. The low voltage NMOS device 101 also includes a conductive channel 820 that penetrates the interlayer dielectric layer 810 and is electrically connected to the gate conductor 320, the first source region 711, and the first drain region 712, respectively, and a passivation layer 900 located on the surface of the interlayer dielectric layer 810 and the conductive channel 820 in the low voltage NMOS device 101. Among them, the partial area of ​​the first source region 711 that contacts the conductive channel 820 is used as the first source ohmic contact area, and the partial area of ​​the first drain region 712 that contacts the conductive channel 820 is used as the first drain ohmic contact area, and the first source ohmic contact area and the first drain ohmic contact area are N-type doped. In other embodiments, at least a portion of the surface of the first well region 110 located below the field oxygen region 200 is used as a P-type compensation area to enhance the isolation effect.

[0067] The low voltage PMOS device 102 includes an N-type high voltage second well region 120 located in the first region of the substrate, a second gate stack located above the second well region 120, a P-type second source region 721 and a second drain region 722 located on both sides of the second gate stack and in the second well region 120, and an interlayer dielectric layer 810 located above the second gate stack. The second gate stack includes a gate conductor 320 located in the first region, a gate dielectric 310 located between the gate conductor 320 in the first region and the second well region 120, and a gate sidewall 330 located at the sidewalls of the gate conductor 320 and the gate dielectric 310 at both ends in the first region, and the gate conductor 320 is polysilicon. The low voltage PMOS device 102 also includes a conductive channel 820 that penetrates the interlayer dielectric layer 810 and is electrically connected to the gate conductor 320, the second source region 721, and the second drain region 722, respectively, and a passivation layer 900 located on the surface of the interlayer dielectric layer 810 and the conductive channel 820 in the low voltage PMOS device 102. Among them, the partial area of ​​the second source region 721 that contacts the conductive channel 820 serves as the second source ohmic contact area, and the partial area of ​​the second drain region 722 that contacts the conductive channel 820 serves as the second drain ohmic contact area. The second source ohmic contact area and the second drain ohmic contact area are P-type.

[0068] The diode 103 includes a P-type low-voltage sixth well region 130 located in the first region of the substrate, a P-type second doping region 732 located at least partially in the sixth well region 130, an N-type first doping region 731 in lateral contact with the second doping region 732, a P-type fourth doping region 733 located in the sixth well region 130 and isolated from the second doping region 732, and an interlayer dielectric layer 810 located above the substrate. The P-type second doping region 732 contacts the N-type first doping region 731 to form a PN structure. The diode 103 also includes a conductive channel 820 that penetrates the interlayer dielectric layer 810 and is electrically connected to the first doping region 731 and the fourth doping region 733, respectively, and a passivation layer 900 located on the interlayer dielectric layer 810 of the diode 103 and the surface of the conductive channel 820. Among them, the partial area of ​​the first doped region 731 that contacts the conductive channel 820 is used as the first doped contact area, and the partial area of ​​the fourth doped region 733 that contacts the conductive channel 820 is used as the fourth doped contact area, the first doped contact area is N-type, and the fourth doped contact area is P-type. In other embodiments, at least a portion of the surface of the sixth well region 130 located below the field oxygen region 200 is used as a P-type compensation area to enhance the isolation effect.

[0069] The resistor 104 includes an N-type high voltage seventh well region 140 in the first region of the substrate, a P-type third doped region 741 in the seventh well region 140 , and an interlayer dielectric layer 810 above the substrate. The resistor 104 also includes a passivation layer 900 on the surface of the interlayer dielectric layer 810 .

[0070] The fifth semiconductor device of the high-voltage device arranged in the second region adjacent to the semiconductor device in the first region in the lateral direction is a high-voltage LDMOS device 105, and the high-voltage LDMOS device 105 is adjacent to the resistor 104, and the two are isolated by a field oxygen region 200 located on the surface of the substrate 100 and extending downward. In other embodiments, for example, high-voltage JFET devices, gate-oxide high-voltage MOS devices, field-oxide high-voltage MOS devices, etc. may also be integrated in the second region. In other embodiments, adjacent devices are isolated by a trench located on the surface of the substrate 100 and extending downward, and the depth of the trench is set based on the depth of the well region of the two adjacent devices to achieve isolation.

[0071] The high-voltage LDMOS device 105 includes an N-type high-voltage third well region 150 and a P-type low-voltage fifth well region 170 located adjacent to each other in the second region of the substrate, a P-type low-voltage fourth well region 160 located in the third well region 150, the fourth well region 160 is located at a first boundary of the third well region 150 and close to the fifth well region 170 located in the second region of the substrate, a field oxide region 200 extending downward along the surface of the substrate 100 and located between the adjacent third well region 150 and the fifth well region 170, and a P-type low-voltage fourth well region 160 located in the third well region 150. The third drain region 751 of N type at the second boundary of the triple well region 150, the fourth gate stack as a field plate located above the field oxide region 200, and the third gate stack extending along the surface of the field oxide region 200 to the third well region 150 and the fourth well region 160, the third source region 752 of N type and the first channel region 753 of P type located in the fourth well region 160, the second channel region 754 of P type located in the fifth well region 170, and the interlayer dielectric layer 810 located above the substrate 100 in the area where the high-voltage LDMOS device 105 is located. The fourth gate stack includes a gate conductor 320 located on the field oxide region 200, a gate dielectric 310 located between the gate conductor 320 and the field oxide region 200, and a gate spacer 330 located at the sidewalls of both ends of the gate conductor 320 and the gate dielectric 310, and the gate conductor 320 is polysilicon. The third gate stack includes a gate conductor 320 located above the field oxide region 200 and extending along the field oxide region 200 to the third well region 150 and the fourth well region 160, a gate dielectric 310 located on the third well region 150, the fourth well region 160 and the field oxide region 200, and the gate dielectric 310 is located below the gate conductor 320, and a gate spacer 330 located at the sidewalls of the gate conductor 320 and the gate dielectric 310 at both ends, and the gate conductor 320 is polysilicon. The fourth gate stack and the part of the third gate stack located on the field oxide region 200 are used as field plates to optimize the electric field on the device surface, and the part of the third gate stack located in the well region forms a device channel. The high-voltage LDMOS device 105 further includes a conductive channel 820 that penetrates the interlayer dielectric layer 810 and is electrically connected to the third drain region 751, the third source region 752, the first channel region 753, the second channel region 754, and the fourth gate stack, and a conductive channel (not shown in the figure) that is electrically connected to the third gate stack, and a passivation layer 900 located on the surface of the interlayer dielectric layer 810 and the conductive channel 820 in the high-voltage LDMOS device 105. Among them, the partial area of ​​the third source region 752 that contacts the conductive channel 820 serves as the third source ohmic contact area, and the partial area of ​​the third drain region 751 that contacts the conductive channel 820 serves as the third drain ohmic contact area, and the third source ohmic contact area and the third drain ohmic contact area are N-type. The partial area of ​​the first channel region 753 that contacts the conductive channel 820 serves as the first channel contact area, and the first channel contact area is P-type.A portion of the second channel region 754 that contacts the conductive channel 820 serves as a second channel contact region, and the second channel contact region is of P type.

[0072] In this embodiment, the doping type of the gate conductor 320 can be P-type or N-type.

[0073] Figure 2 A schematic diagram showing a process flow of a semiconductor structure manufacturing method according to an embodiment of the present invention is shown. FIG. 3A to FIG. 3H The schematic diagram shows the structure of each specific step in the semiconductor device manufacturing process.

[0074] In this embodiment, Figure 1 The manufacturing steps of the semiconductor device provided in are used as an example for explanation.

[0075] like Figure 2 As shown, Figure 1 The method for manufacturing a semiconductor device provided comprises the following steps:

[0076] In step S10, at least one well region of the second doping type is formed in the first region and the second region of the substrate respectively. Figure 3A As shown, two N-type high-voltage second well regions 120 and a seventh well region 140 are formed in parallel in the first region 111 of the substrate 100, and an N-type high-voltage third well region 150 is formed in the second region 112 adjacent to the first region 111. The first region 111 is a low-voltage device region, and the second region 112 is a high-voltage device region, and the formed multiple N-type well regions are distributed in parallel.

[0077] In step S20, at least one well region of the first doping type is formed in the first region and the second region of the substrate respectively. Figure 3B As shown, in Figure 3A In terms of structure, a P-type low-voltage first well region 110 and a sixth well region 130 arranged in parallel are formed in the first region 111 of the substrate 100, and a P-type low-voltage fifth well region 170 arranged in parallel with the third well region 150 and a P-type low-voltage fourth well region 160 located in the third well region 150 near the first boundary are formed in the second region 112 of the substrate.

[0078] In step S30, an isolation structure extending downward from the substrate surface is formed between adjacent well regions and in the well regions. Figure 3CAs shown, a field oxide region 200 extending downward from the upper surface of the substrate 100 is formed between adjacent well regions by local oxidation of silicon (LOCOS) isolation or chemical vapor deposition (CVD) and other methods to achieve isolation of adjacent well regions. Further, an oxide layer is grown using the active region as a hard mask to form the field oxide region 200. In other embodiments, a trench is formed between adjacent well regions as an isolation structure to achieve isolation, wherein the depth of the trench is, for example, related to the depth of the adjacent well region or doping region. The active region is then removed.

[0079] In step S40, gate stacks and field plates are formed on corresponding well regions. Figure 3DAs shown, a first gate stack and a second gate stack are formed above the first well region 110 and the second well region 120, respectively, a fourth gate stack as a field plate is formed above the field oxygen region 200 on the third well region 150, and a third gate stack is formed above the field oxygen region 200 on the third well region 150 and extends to the third well region 150 and part of the fourth well region 160, the portion of the third gate stack located above the field oxygen region 200 is used as a field plate, and the portion of the third gate stack located above the third well region and the fourth well region is used to form a device channel. Further, the impurities and the oxide layer formed by the substrate 100 exposed to the air are cleaned, and the substrate 100 is placed in an oxidation furnace to grow and form a silicon dioxide layer. After that, the substrate 100 is placed in a low-pressure CVD device with silane, and the silane is decomposed to deposit a layer of polysilicon on the surface of the gate dielectric 310. The polysilicon is imprinted in the photolithography area using deep ultraviolet lithography technology. Afterwards, a silicon dioxide layer is deposited, and the deposited silicon dioxide is etched using an anisotropic plasma etcher to obtain a first gate stack including a gate dielectric 310 and a gate conductor 320 located above the first well region 110, a second gate stack including a gate dielectric 310 and a gate conductor 320 located above the second well region 120, a fourth gate stack including a gate dielectric 310 and a gate conductor 320 located on the field oxide region on the third well region 150, and a third gate stack including a gate dielectric 310 and a gate conductor 320 located on the fourth well region 160, the third well region 150, and a partial surface of the field oxide region. Afterwards, gate spacers 330 are formed at the sidewalls of both ends of the first to fourth gate stacks, respectively. The polysilicon of the gate conductor 320 may be P-type doped or N-type doped. In other embodiments, the polysilicon of the gate conductor is doped with the second doping type during the process of forming the first source region and the first drain region and the third source region and the third drain region, and in this embodiment, the equivalent doping type of the gate conductor in the semiconductor device is consistent with the initial doping type of the gate conductor. In other embodiments, the polysilicon of the gate conductor may be doped with the first doping type during the process of forming the second source region and the second drain region, so that the equivalent doping type of the gate conductor in the semiconductor device is consistent with the initial doping type of the gate conductor.

[0080] In step S50, a first source region and a first drain region of a second doping type, a first doping region, a third source region, and a third drain region are formed in the first well region, the substrate, and the third well region. Figure 3EAs shown, a photoresist mask is used to shield the second well region 120, the sixth well region 130, the seventh well region 140, the fifth well region 170 and part of the fourth well region 160 in the substrate 100, and the first gate stack, the third gate stack, the fourth gate stack and the field oxygen region 200 are used as hard masks to implant a dopant of the second doping type to form a first source region 711 and a first drain region 712 of the second doping type in the first well region 110, a third source region 752 and a third drain region 751 of the second doping type in the third well region 150 and the fourth well region 160, and a first doping region 731 of the second doping type is formed in the region near the sixth well region 130 in the substrate 100. The implantation energy, doping amount and implantation angle of the dopant to form the second doping type doping region can also be selected according to the requirements of the semiconductor device for voltage resistance, size, current, etc. The photoresist mask is then removed.

[0081] In step S60, a second source region and a second drain region of the first doping type, second to fourth doping regions, a second channel region, and a first channel region are formed in the second well region and the fourth to seventh well regions, respectively. Figure 3FAs shown, the field oxygen region 200 is used as a hard mask, and a first doping type dopant is implanted by blanket implantation to form a first doping type second source region 721 and a first drain region 722 in the second well region 120, respectively, a first doping type first channel region 753 and a second channel region 754 are formed in the fourth well region 160 and the fifth well region 170, respectively, a first doping type second doping region 732 is formed in the sixth well region 130 extending outward to contact the first doping region 731 to form a PN structure in the diode 103, a first doping type fourth doping region 733 is formed in the sixth well region 130, and a first doping type third doping region 741 is formed in the seventh well region 140 to form a body resistance structure in the resistor 104, and the resistance range of the resistor 104 is 300 to 2000Ω. The doping dose of the N-type dopant injected in step S50 is higher than the doping dose of the first doping type dopant, so that the first source region and the first drain region, as well as the third source region and the third drain region form ohmic contacts. Further, in step S60, the dopant of the first doping type injected into the first source region 711 and the first drain region 712 in the first well region 110 is combined with part of the dopant of the second doping type in the first source region 711 and the first drain region 712, and the equivalent dopant of the first source region 711 and the first drain region 712 obtained in this step is maintained as the second doping type, that is, the dopant of the second doping type in the first source region 711 and the first drain region 712 includes the dopant of the first doping type. In step S60, the dopant of the first doping type injected into the third drain region 751 in the third well region 150 and the third source region 752 in the fourth well region 160 is recombined with part of the dopant of the second doping type in the third source region 752 and the third drain region 751, and the equivalent dopant of the third source region 752 and the third drain region 751 obtained in this step is maintained as the second doping type, that is, the dopant of the second doping type in the third source region 752 and the third drain region 751 includes the dopant of the first doping type. In step S60, the dopant of the first doping type injected into the first doping region 731 in the substrate 100 is recombined with part of the dopant of the second doping type in the first doping region 731, and the equivalent dopant of the first doping region 731 obtained in this step is maintained as the second doping type. Therefore, the manufacturing method does not affect the performance of the semiconductor device, so it is not necessary to use a photoresist mask to block to form the doping region of the first doping type in this step.

[0082] In step S70, a plurality of channel holes penetrating the interlayer dielectric layer are formed above the gate stack and the field plate region. Figure 3G As shown, in Figure 3FAn interlayer dielectric layer 810 is deposited above the structure shown, and a channel hole 811 is formed through the interlayer dielectric layer 810 to reach the first source region 711, the first drain region 712, the gate conductor 320 of the first gate stack, the second source region 721, the second drain region 722, the gate conductor 320 of the second gate stack, the first doped region 731, the fourth doped region 733, the third drain region 751, the third source region 752, the first channel region 753, the second channel region 754, and the gate conductor 320 of the fourth gate stack. The channel hole connecting the resistor 104 to the third doped region 741 and the outside and the channel hole connecting the gate conductor 320 in the third gate stack and the outside are not shown in the figure. In other embodiments, in this step, only the interlayer dielectric layer 810 is first penetrated to form the channel hole 811 reaching the first source region 711, the first drain region 712, the second source region 721, the second drain region 722, the first doped region 731, the fourth doped region 733, the third drain region 751, the third source region 752, the first channel region 753, and the second channel region 754. After the ohmic contact of the first doping type is formed in the above-mentioned doped regions, the channel hole 811 is further formed to penetrate the interlayer dielectric layer 810 and reach the gate conductor 320 of the first gate stack, the gate conductor 320 of the second gate stack, and the gate conductor 320 in the fourth gate stack.

[0083] In step S80, the channel hole is used as an injection channel to form a second source ohmic contact region, a second drain ohmic contact region, a fourth doped contact region, a first channel contact region, a second channel contact region, and fill the channel hole to form a conductive channel. Figure 3HAs shown, the interlayer dielectric layer 810 is used as a hard mask and the channel hole 811 is used as an injection channel to inject the first doping type dopant, so as to form the first doping type second source ohmic contact region, the second drain ohmic contact region, the fourth doping contact region, the first channel contact region, and the second channel contact region in the second source region 721, the second drain region 722, the fourth doping region 733, the first channel region 753, and the second channel region 754, respectively. Further, in the step of forming the above-mentioned first doping type ohmic contact, the first doping type dopant injected into the first source region 711 and the first drain region 712 is combined with part of the second doping type equivalent dopant in the first source region 711 and the first drain region 712, so that the partial regions in the first source region and the first drain region that are respectively in contact with the channel hole 811 are used as the first source ohmic contact region and the first drain ohmic contact region, and the equivalent dopant in the first source ohmic contact region and the first drain ohmic contact region is maintained as the second doping type. In the step of forming the ohmic contact of the first doping type, the first doping type dopant injected into the third source region 752 and the third drain region 751 is combined with part of the equivalent dopant of the second doping type in the third source region 752 and the third drain region 751, so that the partial regions in the third source region and the third drain region that are in contact with the channel hole 811 are used as the third source ohmic contact region and the third drain ohmic contact region, and the equivalent dopant of the third source ohmic contact region and the third drain ohmic contact region is maintained as the second doping type. In the step of forming the ohmic contact region of the first doping type, the equivalent dopant of the second doping type in the first doping region 731 is combined with the first doping type dopant in the first doping region 731, so that the partial region in the first doping region 731 that is in contact with the channel hole 811 is used as the first doped ohmic contact region, and the equivalent dopant of the first doped ohmic contact region is maintained as the second doping type. The doping dose of the ions injected this time is lower than the doping dose of the second doping type dopant injected when forming the N-type doping region. Wherein, when the gate conductor 320 in the semiconductor device is formed as a polysilicon layer of the second doping type in the process of forming the gate stack, the equivalent dopant of the final gate conductor in the semiconductor device is maintained as the second doping type. In other embodiments, when the gate conductor 320 in the semiconductor device is formed as a polysilicon layer of the first doping type in the process of forming the gate stack, the equivalent dopant of the final gate conductor in the semiconductor device is maintained as the first doping type. Wherein, the polysilicon in the gate conductor is simultaneously injected with dopants in the process of forming the source and drain regions, and the doping dose is the same as the doping dose when forming the source and drain regions, and the dopant is compounded by the initial dopant in the gate conductor 320 to maintain the initial doping type. Next, the channel hole is filled to form a conductive channel.A conductive channel 820 is formed in the channel hole 811 using a conductive material so that the first source region 711, the first drain region 712, the gate conductor 320 of the first gate stack, the second source region 721, the second drain region 722, the gate conductor 320 of the second gate stack, the first doping region 731, the fourth doping region 733, the third drain region 751, the third source region 752, the first channel region 753, and the second channel region 754 are connected to the outside through the conductive channel 820. Then, a low voltage NMOS device 101, a low voltage PMOS device 102, a diode 103, and a resistor 104 are formed adjacent to each other in the first region 111 of the substrate 100, and a high voltage LDMOS device 105 is formed in the second region 112 of the substrate 100, and the first region 111 is adjacent to the second region 112.

[0084] In step S90, a passivation layer is formed. Figure 2 As shown, in Figure 3H A passivation layer 900 is formed by photolithography and deposited on the structure shown. The passivation layer 900 is, for example, at least one of silicon nitride and silicon dioxide.

[0085] Figure 4 A schematic diagram showing a process of forming the first to seventh well regions in another embodiment of the present invention is shown. FIG. 5A to FIG. 5E A structural schematic diagram of each specific step in the process of forming the first to seventh well regions is shown.

[0086] In this embodiment, on the basis of the above-mentioned embodiment, a compensation region of the first doping type is formed on at least a portion of the surface of the well region of the first doping type, so that an isolation structure formed later on the surface of the well region of the first doping type and extending downward contacts the compensation region, so that the doping of the well region of the first doping type is compensated when the isolation structure is formed. In the following embodiment, the compensation region is formed on at least a portion of the surface of the well region of the first doping type without additional masking and photolithography steps, thereby enhancing the isolation effect of the isolation structure.

[0087] like Figure 4 , FIG. 5A to FIG. 5E As shown, the process of forming the first to seventh well regions in this embodiment includes the following steps:

[0088] Step S121: forming a second well region and a seventh well region of a second doping type in the first region of the substrate, and forming a third well region of a second doping type in the second region. Figure 5AAs shown, a first oxide layer is formed on a P-type substrate 100, for example, a silicon dioxide layer is generated by a thermal oxidation method; a third photoresist mask 330 is used to etch the first oxide layer and locate the position of the well region of the second doping type in the substrate 100, the photoresist is removed, and then high-energy N-type ion implantation is performed. After annealing, the first oxide layer is removed, and then the second well region 120 and the seventh well region 140 of N-type high voltage are formed in the first region 111 of the substrate 100, and the third well region 150 of N-type high voltage is formed in the second region 112 of the substrate 100. At the same time, the removed part of the first oxide layer forms a step difference, which can be used for subsequent photolithography alignment, eliminating the conventional alignment photolithography step. The third photoresist mask 330 is then removed.

[0089] Step S122: forming an oxide layer on the substrate and forming a nitride layer on the oxide layer. Figure 5B As shown, an oxide layer 201 and a nitride layer 202 are sequentially deposited on the surface of the substrate 100 . The oxide layer 201 is, for example, a silicon dioxide layer, and the nitride layer 202 is, for example, a silicon nitride layer.

[0090] Step S123: forming active regions in the first region and the second region of the substrate. Figure 5C As shown, the first photoresist mask 310 is used to photolithographically etch the oxide layer 201 and the nitride layer 202 to form active areas in the first area 111 and the second area 113 of the substrate 100. The active areas after photolithography are used as hard masks for forming compensation areas and isolation structures. The first photoresist mask is then removed.

[0091] Step S124: using a photoresist mask to at least cover the well region of the second doping type on the substrate, so as to form a first well region and a sixth well region of the first doping type in the first region, and to form a fourth well region and a fifth well region of the first doping type in the second region. Figure 5D As shown, a second photoresist mask 320 is used to at least block the second well region 120 and the seventh well region 140 of the second doping type in the first area 111 of the substrate 100, and part of the third well region 150 of the second doping type in the second area 112, and high-energy implantation is performed to form a first well region 110 and a sixth well region 130 of the first doping type in the first area 111 of the substrate 100, and a fourth well region 160 and a fifth well region 170 of the first doping type in the second area 112 of the substrate 100, wherein the implantation energy of the dopant of the first doping type implanted by the high-energy implantation enables the dopant to penetrate the active area.

[0092] Step S125: using a photoresist mask and the active region as a hard mask, forming a compensation region of the first doping type on at least a portion of the surface of the well region of the first doping type. Figure 5EAs shown, further, without removing the second photoresist mask 320, the active area is used as a hard mask to form a compensation area of ​​the first doping type in the well area of ​​the first doping type at least below the field oxygen area, and the injection energy of the dopant of the first doping type in the compensation area makes it impossible for the dopant to penetrate the active area. Then, the second photoresist mask is removed. Then, when forming the isolation structure, the following method is used: Figure 5E The active area shown in the structure is used as a hard mask to form an isolation structure 200, and then the active area is removed, and subsequent steps are completed according to the above-mentioned semiconductor device manufacturing method to form a semiconductor device.

[0093] In other embodiments, in the process of forming the first to seventh well regions, the active region can be first formed on the substrate using a first photoresist mask, and then a third photoresist mask is used to block and high-energy implantation is performed to form a well region of the second doping type, and then a second photoresist mask is used and high-energy implantation is performed to form a well region of the first doping type, and then the second photoresist mask is used to block and the active region is used as a hard mask to form a compensation region of the first doping type on at least a portion of the surface of the well region of the first doping type. The above-mentioned single photolithography step is the same as the single step process for forming the first to seventh well regions provided above. Preferably, in the process of high-energy implantation of the well region of the first doping type and the well region of the second doping type, multiple high-energy implantations can be performed to form them.

[0094] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0095] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the disclosure to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first gate stack on a first well region of a first region of a substrate, wherein the first well region is of a first doping type; forming a second gate stack on a second well region of the first region of the substrate, wherein the second well region is of a second doping type, the first doping type is opposite to the second doping type, and the first well region and the second well region are adjacent to each other; forming a third gate stack on a third well region and a fourth well region of a second region of the substrate, wherein the third well region is of the second doping type, the fourth well region is of the first doping type, the fourth well region is located in the third well region, and the first region and the second region are adjacent to each other; Using a photoresist mask and using the first gate stack and the third gate stack as hard masks, respectively forming a first source region and a first drain region of a second doping type in the first well region, forming a third drain region of a second doping type in the third well region, and forming a third source region of a second doping type in the fourth well region; as well as The photoresist mask is removed, and general implantation is performed, wherein a second source region and a second drain region of the first doping type are formed in the second well region, In the step of forming the second source region and the second drain region, the dopants of the second doping type in the first source region and the first drain region and in the third source region and the third drain region recombine the dopants of the first doping type, and the equivalent dopants in the first source region and the first drain region and the third source region and the third drain region are maintained as the second doping type.

2. The manufacturing method according to claim 1, wherein: The doping dose of the second doping type dopant forming the first source region and the first drain region and the third source region and the third drain region is higher than the doping dose of the first doping type dopant forming the second source region and the second drain region, so that the first source region and the first drain region and the third source region and the third drain region form an ohmic contact.

3. The manufacturing method according to claim 1, wherein: After the step of forming the second source region and the second drain region, the method further comprises: forming an interlayer dielectric layer on the first gate stack, the second gate stack and the third gate stack; forming a plurality of channel holes penetrating the interlayer dielectric layer and reaching at least the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region respectively; and The plurality of via holes are filled with a conductive material to form a plurality of conductive vias.

4. The manufacturing method according to claim 3, wherein: After forming the conductive channel, portions of the first source region and the first drain region exposed by the channel hole and in contact with the conductive channel serve as the first source ohmic contact region and the first drain ohmic contact region, and portions of the third source region and the third drain region exposed by the channel hole and in contact with the conductive channel serve as the third source ohmic contact region and the third drain ohmic contact region.

5. The manufacturing method according to claim 4, wherein: Between the steps of forming the channel hole and the conductive channel, the step further includes: The plurality of channel holes are used as injection channels to inject a dopant of a first doping type to form a second source ohmic contact region and a second drain ohmic contact region in the second well region, The first source region and the first drain region combine the dopants of the first doping type with the dopants of the second doping type of the third source region and the third drain region, and the equivalent dopants of the first source region and the first drain region exposed through the channel hole as a portion of the first source ohmic contact region and the first drain ohmic contact region are maintained as the second doping type, and the equivalent dopants of the third source region and the third drain region exposed through the channel hole as a portion of the third source ohmic contact region and the third drain ohmic contact region are maintained as the second doping type.

6. The manufacturing method according to claim 5, wherein: Also includes: In the step of forming the second source region and the second drain region, a first channel region of the first doping type is formed in the fourth well region, and a second channel region of the first doping type is formed in the fifth well region of the first doping type in the second region of the substrate, and the fifth well region is adjacent to the third well region.

7. The manufacturing method according to claim 6, wherein: The plurality of channel holes include channel holes penetrating the interlayer dielectric layer and reaching the first channel region and the second channel region respectively. In the step of forming the second source ohmic contact region and the second drain ohmic contact region, a first channel contact region of a first doping type is formed in the first channel region, and a second channel contact region of a first doping type is formed in the second channel region.

8. The manufacturing method according to claim 5, wherein: Also includes: In the step of forming the first source region and the first drain region and the third source region and the third drain region, a first doping region of a second doping type is formed in the substrate; In the step of forming the second source region and the second drain region, a second doping region of the first doping type extending outward is formed in the sixth well region of the first region of the substrate, and a fourth doping region of the first doping type is formed in the sixth well region, the second doping region is in contact with the first doping region to form a PN structure, the sixth well region is adjacent to the second well region, and the sixth well region is of the first doping type, The dopant of the second doping type in the first doping region combines with the dopant of the first doping type, and the equivalent dopant of the first doping region remains the second doping type.

9. The manufacturing method according to claim 8, wherein: The plurality of channel holes include channel holes that penetrate the interlayer dielectric layer and reach the first doping region and the fourth doping region respectively. After forming the conductive channel, the portion of the first doped region exposed by the channel hole and in contact with the conductive channel serves as a first doped contact region. In the step of forming the second source ohmic contact region and the second drain ohmic contact region, a fourth doped contact region is formed in the fourth doped region, A portion of the dopants of the second doping type in the first doping region recombine with the dopants of the first doping type, and an equivalent dopant of the first doped contact region in the first doping region remains at the second doping type.

10. The manufacturing method according to claim 5, wherein: Also includes: In the step of forming the second source region and the second drain region, a third doping region of the first doping type is formed in a seventh well region of the second doping type in the first region of the substrate to form a body resistor, and the seventh well region is adjacent to the sixth well region in the first region.

11. The manufacturing method according to claim 5, wherein: The first gate stack, the second gate stack and the third gate stack respectively include a gate conductor and a gate dielectric, the gate dielectric is located between the gate conductor and the substrate, the gate conductor is a polysilicon layer, and the equivalent dopant of the gate conductor in the semiconductor device is a first doping type or a second doping type.

12. The manufacturing method according to claim 11, wherein: In the process of forming the first gate stack, the second gate stack, and the third gate stack, the gate conductor is polysilicon of the second doping type; In the process of forming the second source region and the second drain region, the second doping type dopant in the gate conductor is combined with the first doping type dopant; The plurality of channel holes include at least one channel hole penetrating through the interlayer dielectric layer to reach the gate conductor, In the step of forming the second source ohmic contact region and the second drain ohmic contact region, the second doping type dopant of the gate conductor recombine the first doping type dopant, and the equivalent dopant of the gate conductor is maintained as the second doping type.

13. The manufacturing method according to claim 11, wherein: In the process of forming the first gate stack, the second gate stack, and the third gate stack, the gate conductor is polysilicon of the first doping type, In the process of forming the first source region, the first drain region, the third source region, and the third drain region, at least the dopant of the first doping type in the gate conductor in the first gate stack is combined with the dopant of the second doping type; In the process of forming the second source region and the second drain region, the dopant of the first doping type is implanted into the gate conductor; The plurality of channel holes include at least one channel hole penetrating through the interlayer dielectric layer to reach the gate conductor, In the step of forming the second source ohmic contact region and the second drain ohmic contact region, the dopant of the first doping type is implanted into the gate conductor, The equivalent dopant of the gate conductor is maintained at the first doping type.

14. The manufacturing method according to claim 1, wherein: Before forming the first gate stack, the second gate stack and the third gate stack, the method further includes: forming the second well region and the seventh well region of the second doping type in the first region of the substrate, and forming the third well region of the second doping type in the second region of the substrate; The first well region and the sixth well region of the first doping type are formed in the first region of the substrate, and the fourth well region and the fifth well region of the first doping type are formed in the second region of the substrate, wherein the well regions in the first region are arranged in parallel, the third well region and the fifth well region in the second region are adjacent to each other, and the fourth well region is located in the third well region; An isolation structure extending downward from the substrate surface is formed between adjacent well regions. The isolation structure serves as a part of the hard mask in the step of forming the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region.

15. The manufacturing method according to claim 14, wherein: The process of forming the well region of the first doping type includes: Using a first photoresist mask, forming an active region in a first region and a second region on the substrate; Removing the first photoresist mask, using a second photoresist mask to cover at least a portion of the substrate where the well region of the second doping type is formed, forming a first well region and a sixth well region of the first doping type in the first region of the substrate, and forming a fourth well region and a fifth well region of the first doping type in the second region of the substrate; The second photoresist mask is used for shielding, and the active area is used as a hard mask to form a compensation area of ​​the first doping type on a partial surface of the well area of ​​the first doping type, and then the second photoresist mask is removed. In the process of forming the isolation structure, the active area is used as a part of a hard mask, and then the active area is removed.

16. The manufacturing method according to claim 14, wherein: The process of forming the well region of the second doping type and the well region of the first doping type includes: Using a first photoresist mask, forming an active region in a first region and a second region on the substrate; Removing the first photoresist mask, using a third photoresist mask for shielding, so as to form the second well region and the seventh well region of the second doping type in the first region of the substrate, and forming the third well region of the second doping type in the second region of the substrate, and then removing the third photoresist mask; Using a second photoresist mask to cover at least a portion of the substrate where the well region of the second doping type is formed, forming a first well region and a sixth well region of the first doping type in the first region of the substrate, and forming a fourth well region and a fifth well region of the first doping type in the second region of the substrate; The second photoresist mask is used for shielding, and the active area is used as a hard mask to form a compensation area of ​​the first doping type on a partial surface of the well area of ​​the first doping type, and then the second photoresist mask is removed. In the process of forming the isolation structure, the active area is used as a part of a hard mask, and then the active area is removed.

17. The manufacturing method according to claim 15 or 16, wherein: The implantation energy of the dopant of the first doping type forming the well region of the first doping type enables the dopant to penetrate the active region.

18. The manufacturing method according to claim 15 or 16, wherein: The implantation energy of the dopant of the first doping type implanted when forming the compensation region is such that the dopant cannot penetrate the active region.

19. The manufacturing method according to claim 14, wherein: Also includes: In the step of forming the isolation structure, a field oxide region extending downward is formed on a surface in the third well region, a surface in the fourth well region, and a surface in the sixth well region.

20. The manufacturing method according to claim 19, wherein: Also includes: In the step of forming the first gate stack, the second gate stack and the third gate stack, a fourth gate stack is formed on the field oxide region to serve as a field plate, and the third gate stack includes at least a portion located on the field oxide region to serve as a field plate.

21. The manufacturing method according to claim 14, wherein: The isolation structure includes at least one of a field oxide region and a trench isolation.

22. The manufacturing method according to claim 1, wherein: The first doping type is P type, and the second doping type is N type.

23. A semiconductor device comprising: substrate; A first well region of a first doping type and a second well region of a second doping type located in a first region of the substrate, a third well region of a second doping type and a fourth well region of a first doping type located in a second region of the substrate, the first doping type is opposite to the second doping type, the first region and the second region are adjacent to each other, the first well region and the second well region are adjacent to each other, and the fourth well region is located in the third well region; a first gate stack located on the first well region, a second gate stack located on the second well region, and a third gate stack located on the third well region and the fourth well region; a first source region and a first drain region of the second doping type located in the first well region, a second source region and a second drain region of the first doping type located in the second well region, and a third source region and a third drain region of the second doping type located in the third well region and the fourth well region, Among them, part of the second doping type dopant of the first source region and the first drain region is combined with the first doping type dopant injected when the second source region and the second drain region are formed by general injection, so that the equivalent dopant of the first source region and the first drain region is maintained as the second doping type, that is, the second doping type dopant in the first source region and the first drain region includes the first doping type dopant, and part of the second doping type dopant of the third source region and the third drain region is combined with the first doping type dopant injected when the second source region and the second drain region are formed by general injection, so that the equivalent dopant of the third source region and the third drain region is maintained as the second doping type, that is, the second doping type dopant in the third source region and the third drain region includes the first doping type dopant.

24. The semiconductor device according to claim 23, wherein: The second drain region and the second source region have the same doping dose.

25. The semiconductor device according to claim 23, wherein: Also includes: an interlayer dielectric layer, located above the first gate stack, the second gate stack, and the third gate stack; A plurality of channel holes, penetrating the interlayer dielectric layer and reaching at least the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region respectively; as well as A plurality of conductive channels are formed by filling the plurality of channel holes with a conductive material.

26. The semiconductor device according to claim 25, wherein: The portions of the first source region and the first drain region that are in contact with the conductive channel serve as the first source ohmic contact region and the first drain ohmic contact region, the portions of the second source region and the second drain region that are in contact with the conductive channel serve as the second source ohmic contact region and the second drain ohmic contact region, and the portions of the third source region and the third drain region that are in contact with the conductive channel serve as the third source ohmic contact region and the third drain ohmic contact region.

27. The semiconductor device according to claim 25, wherein: Also includes: A fifth well region of the first doping type located in the second region of the substrate, the fifth well region and the third well region being adjacent to each other; A first channel region of the first doping type is located in the fourth well region, and a second channel region of the first doping type is located in the fifth well region, and the doping doses in the first channel region and the second channel region are the same as the doping doses in the second source region and the second drain region.

28. The semiconductor device according to claim 27, wherein: The plurality of channel holes include channel holes penetrating the interlayer dielectric layer and reaching the first channel region and the second channel region respectively. The first channel region includes a first channel contact region, and the second channel region includes a second channel contact region.

29. The semiconductor device according to claim 25, wherein: Also includes: A sixth well region of the first doping type located in the first region of the substrate, the sixth well region being adjacent to the second well region; a first doped region of a second doping type located in the substrate; as well as A second doping region of the first doping type extending outward is formed from the sixth well region, wherein the first doping region contacts the second doping region to form a PN structure. Part of the second doping type dopant in the first doping region is recombined with the first doping type dopant injected when the second source region and the second drain region are formed, so that the equivalent dopant in the first doping region is maintained as the second doping type, and the doping dose in the second doping region is the same as the doping dose in the second source region and the second drain region.

30. The semiconductor device according to claim 29, wherein Also includes: A fourth doping region of the first doping type is located in the sixth well region, the multiple channel holes include channel holes that penetrate the interlayer dielectric layer and reach the first doping region and the fourth doping region respectively, the fourth doping region includes a fourth doping contact region, the first doping region includes a first doping contact region, and the doping dose in the fourth doping region is the same as the doping dose in the second source region and the second drain region.

31. The semiconductor device according to claim 25, wherein: Also includes: A seventh well region of the second doping type located in the first region of the substrate, the seventh well region being arranged in parallel with the well region in the first region; as well as A third doping region of the first doping type is formed in the seventh well region to form a body resistor, and a doping dose in the third doping region is the same as a doping dose in the second source region and the second drain region.

32. The semiconductor device according to claim 26, wherein: The first gate stack and the second gate stack respectively include a gate conductor and a gate dielectric, the gate dielectric is located between the gate conductor and the substrate, the equivalent dopant of the gate conductor is a first doping type or a second doping type, and the multiple channel holes include at least one channel hole that penetrates the interlayer dielectric layer to reach the gate conductor.

33. The semiconductor device according to claim 23, wherein: Also includes: The isolation structure is located between adjacent well regions and extends downward from the surface of the substrate.

34. The semiconductor device according to claim 23, wherein: Also includes: A compensation region of the first doping type is located on a portion of the surface of the well region of the first doping type.

35. The semiconductor device according to claim 33, wherein: The isolation structure includes at least one of a field oxide region and a trench isolation.

36. The semiconductor device according to claim 23, wherein: Also includes: a field oxygen region located on the surface of the third well region and extending downward; A fourth gate stack is located on the field oxide region and serves as a field plate. The third gate stack includes at least a portion located on the field oxide region and serves as a field plate.

37. The semiconductor device according to claim 23, wherein: The first doping type is P type, and the second doping type is N type.

38. The semiconductor device according to claim 23, wherein: The semiconductor device is a BCD device.

39. The semiconductor device according to claim 23, wherein: The semiconductor device at least includes a CMOS device and at least one of a diode, a resistor, a capacitor, a low-voltage lateral transistor, a low-voltage vertical transistor, and a high-voltage semiconductor device.

40. The semiconductor device according to claim 39, wherein The high-voltage semiconductor devices include, but are not limited to: high-voltage JFET devices, gate-oxide high-voltage MOS devices, and field-oxide high-voltage MOS devices.

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