Semiconductor device and method for forming the same

Abstract

The embodiment of the present invention provides a semiconductor device and a method for forming the same. In the embodiment of the present invention, a first epitaxial layer with a lower doping concentration and a second epitaxial layer and a third epitaxial layer with a higher doping concentration than the first epitaxial layer are sequentially formed. The concentration of doped ions in the source and drain regions from the sidewall of the channel region to the region of the third epitaxial layer is gradually increased, so that the rate of ion diffusion can be controlled and transient enhanced diffusion caused by a large concentration difference can be avoided. In addition, the short channel effect can be suppressed and the performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a forming method thereof. Background Art

[0002] With the continuous development of semiconductor manufacturing technology, the integration of semiconductor devices is getting higher and higher, and the characteristic size of semiconductor devices is gradually shrinking. However, the performance of semiconductor devices still needs to be improved. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.

[0004] In a first aspect, an embodiment of the present invention provides a method for forming a semiconductor device, the method comprising:

[0005] Providing a front-end device layer, the front-end device layer comprising a plurality of discrete fins and a gate structure spanning the fins, wherein the region of the fins located below the gate structure is a channel region;

[0006] Using the gate structure as a mask, etching the fins on both sides of the gate structure to form a recessed area on the fins, exposing the sidewalls of the channel area;

[0007] A source-drain region is formed in the recessed region, and the source-drain region includes a first epitaxial layer, a second epitaxial layer and a third epitaxial layer stacked in sequence, wherein the doping concentration of doped ions in the first epitaxial layer is less than the doping concentration of doped ions in the second epitaxial layer and the third epitaxial layer.

[0008] Further, the doping concentrations of doped ions in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase sequentially, and the first epitaxial layer covers the sidewalls of the channel region and the bottom of the recessed region.

[0009] Further, the doping concentration of the first epitaxial layer is E18-E19 / cubic centimeter, the doping concentration of the second epitaxial layer is E20-E21 / cubic centimeter, and the doping concentration of the third epitaxial layer is E21-E22 / cubic centimeter.

[0010] Furthermore, the semiconductor device is a P-type transistor, and the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer include at least one of boron ions, gallium ions and indium ions.

[0011] Furthermore, the semiconductor device is an N-type transistor, and the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer include at least one of phosphorus ions or arsenic ions.

[0012] Furthermore, the semiconductor device is a P-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon germanium layers, wherein the germanium content of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increases successively.

[0013] Furthermore, the molar fraction of germanium in the first epitaxial layer is 10%-20%; the molar fraction of germanium in the second epitaxial layer is 20%-50%; and the molar fraction of germanium in the third epitaxial layer is 30%-50%.

[0014] Furthermore, the semiconductor device is an N-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon carbon layers, wherein the carbon contents of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase in sequence.

[0015] Furthermore, the semiconductor device is an N-type transistor, the molar fraction of carbon in the first epitaxial layer is 10%-20%; the molar fraction of carbon in the second epitaxial layer is 20%-50%; and the molar fraction of carbon in the third epitaxial layer is 30%-50%.

[0016] Furthermore, the gate structure includes a dummy gate and an isolation layer covering the sidewall of the dummy gate, and the forming of the source and drain regions is specifically:

[0017] Thinning the isolation layer;

[0018] Using the dummy gate and the thinned isolation layer as masks, a first epitaxial process is used to form the first epitaxial layer on the bottom surface of the recessed region and the sidewalls of the channel region;

[0019] forming the second epitaxial layer on the first epitaxial layer;

[0020] The third epitaxial layer is formed on the second epitaxial layer.

[0021] Further, the forming of the second epitaxial layer on the first epitaxial layer specifically includes:

[0022] forming a second epitaxial material layer on the first epitaxial layer by a second epitaxial process;

[0023] Performing ion implantation on the second epitaxial material layer by using a first ion implantation process;

[0024] The second epitaxial material layer is annealed to form a second epitaxial layer.

[0025] Further, the forming of the third epitaxial layer on the second epitaxial layer specifically includes:

[0026] forming a third epitaxial material layer on the second epitaxial layer by a third epitaxial process;

[0027] forming a sidewall covering the sidewall of the thinned isolation layer;

[0028] Using the dummy gate, the thinned isolation layer and the sidewall as masks, a second ion implantation process is used to implant ions into the third epitaxial material layer to form a third epitaxial layer.

[0029] Furthermore, the first ion implantation process is specifically as follows: the implanted ions are one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions, the implantation energy is 0.5K-2K, and the doping concentration is 2E14-5E14.

[0030] Furthermore, the first ion implantation process is specifically as follows: the implanted ions include ions of a type opposite to that of the doping ions in the source and drain regions.

[0031] Furthermore, the thickness of the first epitaxial layer is 3 nanometers to 7 nanometers; the thickness of the second epitaxial layer is 5 nanometers to 17 nanometers; and the upper surface of the third epitaxial layer is substantially flush with the upper surface of the fin.

[0032] In a second aspect, an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device comprises:

[0033] A front-end device layer, the front-end device layer comprising a plurality of discrete fins and a gate structure spanning the fins, the region of the fins located below the gate structure being a channel region, and the fins on both sides of the gate structure having recessed regions;

[0034] A source / drain region, wherein the source / drain region is located in the recessed region, and the source / drain region includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked in sequence, wherein the doping concentration of the doped ions in the first epitaxial layer is less than the doping concentration of the doped ions in the second epitaxial layer and the third epitaxial layer, and the first epitaxial layer covers the sidewalls of the channel region and the bottom of the recessed region.

[0035] Furthermore, the doping concentrations of the doping ions in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase sequentially.

[0036] Furthermore, the semiconductor device is a P-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon germanium layers, wherein the germanium content of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increases successively.

[0037] Furthermore, the semiconductor device is an N-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon carbon layers, wherein the carbon contents of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase in sequence.

[0038] Furthermore, the thickness of the first epitaxial layer is 3 nanometers to 7 nanometers; the thickness of the second epitaxial layer is 5 nanometers to 17 nanometers; and the upper surface of the third epitaxial layer is substantially flush with the upper surface of the fin.

[0039] In the embodiment of the present invention, a first epitaxial layer with a lower doping concentration and a second epitaxial layer and a third epitaxial layer with a higher doping concentration than the first epitaxial layer are sequentially formed. The concentration of doped ions in the source and drain regions from the sidewall of the channel region to the third epitaxial layer is gradually increased, which can control the rate of ion diffusion and avoid transient enhanced diffusion caused by a large concentration difference. In addition, the short channel effect can be suppressed and the performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0041] Figure 1-Figure 4 is a schematic diagram of a structure formed by each step of a method for forming a semiconductor device of a comparative example;

[0042] Figure 5 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0043] Figure 6-Figure 12 is a schematic diagram of a structure formed by each step of a method for forming a semiconductor device according to an embodiment of the present invention;

[0044] Fig.13 Schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0046] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0047] Unless the context clearly requires otherwise, words such as “include”, “including” and the like in this application document should be interpreted as including rather than being exclusive or exhaustive; that is, as including but not limited to.

[0048] In the description of this application document, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" is two or more.

[0049] In the description of the present application document, it should be understood that the term "layer" is used in its broadest sense to include a film, a cover layer or the like, and one layer may include a plurality of sublayers.

[0050] In the description of the present application document, it is to be understood that conventional etching techniques known in the field of semiconductor manufacturing for selectively removing polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide or similar materials are mentioned throughout the specification, including, for example, wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical polishing (CMP) and similar processes. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and reference to specific deposition techniques should not be limited to those described. In some examples, two such techniques may be interchangeable. For example, stripping the photoresist may include immersing the sample in a wet chemical bath or alternatively spraying the wet chemical directly on the sample.

[0051] “Spanning” means that, for example, the gate structure spans the fin, indicating that the dummy gate structure covers part of the top surface and part of the sidewall surface of the fin, and the dummy gate structure and the fin have a crossing positional relationship, and the height of the dummy gate structure is greater than the height of the fin.

[0052] Semiconductor devices are electronic devices with conductivity between good conductors and insulators. They use the special electrical properties of semiconductor materials to complete specific functions. They can be used to generate, control, receive, transform, amplify signals and perform energy conversion. Commonly used semiconductor devices include Fin Field-Effect Transistors (Fin-FET). Fin Field-Effect Transistors include different types of transistors, such as P-type Fin Field-Effect Transistors and N-type Fin Field-Effect Transistors.

[0053] As the gate length of transistors continues to shrink, oxidation enhanced diffusion (OED) becomes a key factor affecting the diffusion of boron and phosphorus ions. Due to the oxidation enhanced diffusion effect, transient enhanced diffusion effect (TED) is caused, and transient enhanced diffusion effect not only causes short channel effects (SCE) of transistors, but also affects transistor channel mobility, junction capacitance and junction leakage current. Short channel effect is some effects that appear in transistors when the conductive channel length of metal oxide field effect transistors is reduced to more than ten nanometers or even a few nanometers. These effects mainly include the decrease of threshold voltage as the channel length decreases, the decrease of drain-induced potential barrier, carrier surface scattering, velocity saturation, ionization and hot electron effect. Therefore, a new method for forming semiconductor devices is urgently needed to suppress the transient enhanced diffusion effect in the manufacturing process of semiconductor devices, thereby effectively suppressing the short channel effect and improving the performance of semiconductor devices.

[0054] refer to Figure 1-Figure 4 , the method for forming a semiconductor device of the comparative example comprises the following steps:

[0055] Step S1, providing a front-end device layer. The front-end device layer includes a plurality of discrete fins and a gate structure spanning the fins, and the region of the fins located below the gate structure is a channel region.

[0056] Step S2, etching the fins using the gate structure as a mask, and etching the fins on both sides of the gate structure to form recessed areas on the fins to expose the sidewalls of the channel area.

[0057] Step S3, forming source and drain regions on the fins at both sides of the channel region.

[0058] Figure 1 It is a schematic diagram of the front-end device layer of a semiconductor device of a comparative example. Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA'. Figure 1 and Figure 2 In step S1 , a front-end device layer 1 is provided. The front-end device layer 1 includes a plurality of discrete fins 2 and a gate structure 3 spanning across the fins 2 .

[0059] The gate structure 3 includes: an isolation layer 3a and a dummy gate 3b, wherein the dummy gate 3b includes a gate dielectric layer, a dummy gate layer and a cap layer stacked in sequence.

[0060] A shallow trench isolation (STI) structure 4 is provided between adjacent fins 11 .

[0061] refer to Figure 3 In step S2 , the fins 11 on both sides of the gate structure are etched using the gate structure 3 as a mask to form recessed regions 5 on the fins 11 .

[0062] refer to Figure 4 In step S3 , a source / drain region 6 is formed in the recessed region 5 .

[0063] However, the semiconductor device formed by the semiconductor device forming method of the comparative example still has transient enhanced diffusion effect and has a higher leakage current.

[0064] In view of this, in order to improve the performance of semiconductor devices, an embodiment of the present invention provides a method for forming a semiconductor device. In the embodiment of the present invention, the formation of a fin field effect transistor is taken as an example for explanation. Furthermore, the method of the embodiment of the present invention can be used to form a fin field effect transistor at a 14nm process node and below, for example, to form a 7nm or 14nm field effect transistor. Furthermore, the method of forming a fin field effect transistor by the method of the embodiment of the present invention can also be used to form other semiconductor devices such as complementary metal oxide semiconductor (CMOS), NAND memory (NAND Flash Memory) and static random access memory (SRAM).

[0065] Figure 5 FIG. 1 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 5 As shown, the method for forming a semiconductor device according to an embodiment of the present invention comprises the following steps:

[0066] Step S100: providing a front-end device layer, wherein the front-end device layer comprises a plurality of discrete fins and a gate structure spanning the fins, wherein the region of the fins below the gate structure is a channel region.

[0067] Step S200: using the gate structure as a mask, etching the fins on both sides of the gate structure to form recessed areas on the fins, exposing the sidewalls of the channel region.

[0068] Step S300, forming a source-drain region in the recessed region, the source-drain region comprising a first epitaxial layer, a second epitaxial layer and a third epitaxial layer stacked in sequence, wherein the doping concentration of doped ions in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increases in sequence, and the first epitaxial layer covers the sidewalls of the channel region and the bottom of the recessed region.

[0069] Figure 6-Figure 12 It is a schematic diagram of a structure formed in each step of a method for forming a semiconductor device according to an embodiment of the present invention.

[0070] Figure 6 It is a three-dimensional structural diagram of the front-end device layer. Figure 7 This is a cross-sectional diagram of the front-end device layer along the AA' line. Figure 6 and Figure 7 In step S100 , a front-end device layer 10 is provided, wherein the front-end device layer 10 includes a plurality of discrete fins 11 and a gate structure 12 spanning the fins 11 , and a region of the fins 11 below the gate structure is a channel region C.

[0071] Specifically, the front-end device layer 10 provided in step S100 may include a silicon single crystal substrate, a germanium single crystal substrate or a silicon germanium single crystal substrate. Alternatively, the front-end device layer 10 may also include a silicon-on-insulator (SOI) substrate, a stacked silicon-on-insulator (SSOI), a stacked silicon-germanium-on-insulator (S-SiGeOI), a silicon-germanium-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, a compound front-end device layer or an alloy front-end device layer. The compound front-end device layer includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium, the alloy front-end device layer includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof, the SOI substrate includes a semiconductor layer (such as a silicon layer, a silicon germanium layer, a carbon silicon layer or a germanium layer) disposed on an insulating material layer, the semiconductor layer has active devices and passive devices, and the insulating material layer protects the active devices and passive devices disposed on the semiconductor layer. Several structures such as epitaxial interface layers or strained layers can also be formed on the surface of the front-end device layer to improve the electrical performance of the semiconductor device.

[0072] The plurality of fins 11 are parallel or substantially parallel.

[0073] The gate structure 12 includes an isolation layer 12a and a dummy gate 12b, wherein the dummy gate 12b includes a gate dielectric layer, a dummy gate layer and a cap layer stacked in sequence.

[0074] The material of the isolation layer 12a may be silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4) or silicon oxycarbide (SiOC). In the present embodiment, the material of the isolation layer 12a is silicon nitride.

[0075] In an optional implementation, the front-end device layer 10 also includes a shallow trench isolation structure 13. The shallow trench isolation structure 13 fills the bottom of adjacent fins 11. The shallow trench isolation structure 13 is used for electrical isolation between adjacent fins 11. The shallow trench isolation structure 13 can avoid doping ions from being implanted into the front-end device layer 10 in a subsequent ion implantation process. The material of the shallow trench isolation structure 13 may be silicon dioxide (SiO2), silicon oxynitride (SiON) or silicon oxycarbide (SiOC). The material of the shallow trench may also be a low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (dielectric constant less than 2.5). In the present embodiment, the material of the shallow trench isolation structure 13 is silicon dioxide.

[0076] refer to Figure 8 In step S200, the fins 11 on both sides of the gate structure are etched using the gate structure 12 as a mask to form a recessed region 20 on the fins 11 and expose the sidewalls of the channel region C.

[0077] The etching process may be dry etching or wet etching. In the present embodiment, dry etching is used to etch the fin 11. The etching gas may be selected according to the selected material. Trifluoromethane (CHF3), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), carbon tetrafluoride (CF4) / oxygen (O2) and carbon tetrafluoride (CF4) / hydrogen (H2) may be selected as the etching gas. In the embodiment of the present invention, CHF3 is used as the etching gas, and the etching pressure may be 5-300 mTorr.

[0078] Optionally, after etching the fins, a cleaning process is used to remove impurity ions on the surface of the fins. After the wet cleaning process is used, the intermediate structure formed in the above steps is dried.

[0079] refer to Figure 9-11 In step S300, a source / drain region 30 is formed in the recessed region 20, and the source / drain region 30 includes a first epitaxial layer 30a, a second epitaxial layer 30b, and a third epitaxial layer 30c stacked in sequence, wherein the doping concentrations of the doped ions in the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c increase in sequence, and the first epitaxial layer 30a covers the sidewalls of the channel region and the bottom of the recessed region.

[0080] Specifically, the thickness of the first epitaxial layer 30 a is 3 nanometers to 7 nanometers; the thickness of the second epitaxial layer 30 b is 5 nanometers to 17 nanometers; and the upper surface of the third epitaxial layer 30 c is substantially flush with the upper surface of the fin.

[0081] Specifically, the doping concentration of the first epitaxial layer 30a is E18-E19 / cubic centimeter, the doping concentration of the second epitaxial layer 30b is E20-E21 / cubic centimeter, and the doping concentration of the third epitaxial layer 30c is E21-E22 / cubic centimeter.

[0082] Further, the doping ions of the first epitaxial layer 30 a , the second epitaxial layer 30 b and the third epitaxial layer 30 c include one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions.

[0083] In an optional implementation, the semiconductor device is a P-type transistor, and the first epitaxial layer 30a, the second epitaxial layer 30b and the third epitaxial layer 30c are all silicon germanium layers, wherein the germanium content of the first epitaxial layer 30a, the second epitaxial layer 30b and the third epitaxial layer 30c increases successively.

[0084] Specifically, the germanium content in the first epitaxial layer 30a is 10%-20%; the germanium content in the second epitaxial layer 30b is 20%-50%; and the germanium content in the third epitaxial layer 30c is 30%-50%.

[0085] In another optional implementation, the semiconductor device is an N-type transistor, and the first epitaxial layer 30a, the second epitaxial layer 30b and the third epitaxial layer 30c are all silicon carbon layers, wherein the carbon content of the first epitaxial layer 30a, the second epitaxial layer 30b and the third epitaxial layer 30c increases successively.

[0086] Specifically, the semiconductor device is an N-type transistor, the carbon content in the first epitaxial layer 30a is 10%-20%; the carbon content in the second epitaxial layer 30b is 20%-50%; the germanium content in the third epitaxial layer 30c is 30%-50%.

[0087] In an optional implementation, the gate structure includes a dummy gate and an isolation layer covering the sidewall of the dummy gate, and the forming of the source and drain regions specifically includes:

[0088] Step S310, thinning the isolation layer.

[0089] Step S320 , using the dummy gate and the thinned isolation layer as masks, and adopting a first epitaxial process to form the first epitaxial layer on the bottom surface of the recessed region and the sidewalls of the channel region.

[0090] Step S330 , forming the second epitaxial layer on the first epitaxial layer.

[0091] Step S340: forming the third epitaxial layer on the second epitaxial layer.

[0092] refer to Fig. 9In step S310, the isolation layer is thinned.

[0093] Specifically, the isolation layer 12a is thinned to a thickness of 4 nanometers to 7 nanometers. The thickness is Fig.11 In the cross section shown in , the isolation layer 12a has a horizontal dimension. By thinning the isolation layer 12a, the source and drain regions can be better formed in the recessed region 20 later, and the formation of gaps at the sidewalls of the channel region due to the isolation layer 12a being too thick can be avoided.

[0094] Specifically, the isolation layer 12 a may be thinned by an etching process. The etching process may be dry etching, and specifically may be an etching process with a high selectivity to the fin 11 .

[0095] In an optional implementation, the etching gas used may be one or a combination of fluoromethane (CH3F), difluoromethane (CH2F2) and trifluoromethane (CHF3), and oxygen is mixed in the etching gas as an auxiliary gas. The flow rate of the etching gas is in the range of 20 standard milliliters per minute, and the etching time range is from 20 seconds to 100 seconds.

[0096] refer to Fig. 9 In step S320, the dummy gate 12b and the thinned isolation layer 12a are used as masks, and a first epitaxial process is adopted to form the first epitaxial layer 30a on the bottom surface of the recessed region and the sidewalls of the channel region.

[0097] In an optional implementation, the thickness of the first epitaxial layer 30 a is 5 nanometers.

[0098] For an N-type semiconductor device, silicon (Si) may be epitaxially grown in the recessed region 20. For a P-type semiconductor device, silicon germanium (SiGe) may be epitaxially grown in the recessed region 20. Epitaxial growth may form elevated source and drain regions in subsequent processes to facilitate the introduction of stress into the device. In-situ doping may be performed during epitaxial growth, such as doping with phosphorus (P) or boron (B).

[0099] The epitaxial layer is formed by an epitaxial growth process so that the width of the subsequently formed source and drain regions is greater than the width of the fins, which can reduce the series resistance and increase the drive current; at the same time, the position of the source and drain regions can be raised to reduce the parasitic junction capacitance, thereby improving the performance of the semiconductor device.

[0100] Specifically, the epitaxial growth process can be selected from vapor phase epitaxy (VPE), liquid phase epitaxy (Liquid-Phase Epitaxy), molecular beam epitaxy (MBE) and ion beam epitaxy (IBE).

[0101] In an optional implementation, the first epitaxial layer 30a is epitaxially grown in an atmosphere having Si, SiGe, SiC and other precursors at a pressure of 5TORR-500TORR. Specifically, the precursor may include silicon dichlorosilane SiH2Cl2 (as a silicon precursor), germanium (GeH4) and methylsilane (CH3-SiH3) for deposition. At the same time, in-situ doping may be performed during the epitaxial growth process, and gases such as diborane (B2H6), phosphine (PH3) and arsine (ASH3) may be introduced.

[0102] In an optional implementation, the semiconductor device is a P-type transistor, the first epitaxial layer 30a is germanium silicon, the proportion of germanium is 15%, and the doping concentration of boron in the first epitaxial layer 30a is 5E18 / cubic centimeter.

[0103] In this step, the first epitaxial layer 30a has a first stress by controlling the proportion of germanium and the concentration of doped ions in the first epitaxial layer 30a. The silicon germanium epitaxial layer can introduce compressive stress, making the molecular arrangement in the channel region more compact, which helps to improve the mobility of holes.

[0104] refer to Fig.10 In step S330, the second epitaxial layer 30b is formed on the first epitaxial layer 30a.

[0105] Specifically, forming the second epitaxial layer 30b includes the following steps:

[0106] Step S331 : forming a second epitaxial material layer on the first epitaxial layer by using a second epitaxial process.

[0107] Specifically, the second epitaxial process is different from the first epitaxial process in that the proportion of germanium in the reaction gas is increased and the concentration of doped ions is increased.

[0108] Step S332: perform ion implantation on the second epitaxial layer using a first ion implantation process.

[0109] Specifically, the implanted ions are one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions, the implantation energy is 0.5K-2K, and the doping concentration is 2E14-5E14.

[0110] Furthermore, ions of opposite ion type to the in-situ doping are implanted into the second epitaxial layer 30b. Specifically, in a P-type transistor, phosphorus ions are implanted into the second epitaxial layer 30b; in an N-type transistor, boron ions are implanted into the second epitaxial layer 30b.

[0111] Through simulation calculation, it can be determined that the smaller the dose of ion implantation, the less damage to the epitaxial layer. Therefore, a lower dose of ion implantation is performed in the second epitaxial material layer to fill the gaps in the second epitaxial material layer, which can hinder the diffusion of ions. The rate of ion diffusion is controlled. Implanted ions of opposite types can further hinder the diffusion of ions in the epitaxial layer. Low energy can avoid damage to the second epitaxial material layer during ion implantation.

[0112] Step S333: annealing the second epitaxial material layer to form a second epitaxial layer.

[0113] Specifically, the annealing may be rapid thermal annealing (RTA), which may specifically include laser annealing (LSA), spike rapid thermal annealing (SA) or flash lamp annealing (FLA).

[0114] The annealing temperature may range from 800°C to 1200°C.

[0115] Annealing can relax the second epitaxial layer 30 b and reduce the defect density and junction leakage current of the second epitaxial layer 30 b.

[0116] In an optional implementation, the second epitaxial layer 30b is germanium silicon, and the proportion of germanium is 30%. The doping concentration of boron in the first epitaxial layer 30a is 5E120 / cubic centimeter.

[0117] In this step, the proportion of germanium and the doping concentration of doped ions in the second epitaxial layer are greater than those in the first epitaxial layer. This allows the concentration of doped ions in the region from the channel region to the second epitaxial layer to gradually increase, which can avoid transient enhanced diffusion caused by a large difference in the concentration of doped ions in the epitaxial layer and the channel region. At the same time, the proportion of germanium in the first epitaxial layer and the second epitaxial layer is also increased in a gradient, which avoids curling or breaking of the epitaxial layer due to excessive stress.

[0118] refer to Fig.11 In step S340, the third epitaxial layer 30c is formed on the second epitaxial layer 30b.

[0119] Specifically, forming the third epitaxial layer 30c includes the following steps:

[0120] Step S341 : forming a third epitaxial material layer on the second epitaxial layer 30 b by adopting a third epitaxial process.

[0121] Specifically, the third epitaxial process is different from the second epitaxial process in that the proportion of germanium in the reaction gas is increased and the concentration of doped ions is increased.

[0122] Step S342 , forming a sidewall covering the sidewall of the thinned isolation layer.

[0123] The sidewall spacer 40 is used as a mask in the subsequent ion implantation process to prevent ions from being implanted into the channel region and the dummy gate. The thickness of the sidewall spacer 40 may be 5 nanometers to 20 nanometers.

[0124] The material of the sidewall spacer 40 may be a low-K dielectric material (with a dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (with a dielectric constant less than 2.5). In this embodiment, the material of the sidewall spacer 20 is silicon dioxide.

[0125] Specifically, the sidewall 40 can be formed by a chemical vapor deposition (CVD) method, such as low temperature chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), and fluid chemical vapor deposition (FCVD).

[0126] Step S343 , using the dummy gate, the thinned isolation layer and the sidewall spacer as masks, adopting a second ion implantation process to implant ions into the third epitaxial material layer to form a third epitaxial layer.

[0127] Specifically, the implanted ions in the ion implantation process are one or more of phosphorus ions, arsenic ions, boron ions, indium ions, gallium ions and antimony ions. The implantation angle of the ion implantation is 0-5 degrees, and the implantation dose is E14atom / cm 2 -5E15atom / cm2 , the injection energy is 6Kev-50Kev.

[0128] The dummy gate 12b, the thinned isolation layer 12a and the sidewall 40 are used as masks to prevent ions from being implanted into the channel region C and the dummy gate 12b. At the same time, the region where ions are implanted can be kept at a certain distance from the channel region C to prevent ions in the source and drain region 40 from diffusing into the channel region.

[0129] In this step, a first epitaxial layer with a lower doping concentration and a second epitaxial layer and a third epitaxial layer with a higher doping concentration than the first epitaxial layer are formed in sequence. The concentration of doped ions in the source and drain regions from the sidewall of the channel region to the third epitaxial layer is gradually increased, which can control the rate of ion diffusion and avoid transient enhanced diffusion caused by a large concentration difference. In turn, the short channel effect can be suppressed and the performance of the semiconductor device can be improved.

[0130] At the same time, since the first epitaxial layer has not been ion-implanted, the energy of the ion implantation in the second epitaxial layer is relatively small, and therefore, the number of defects formed in the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer due to the ion implantation gradually increases. In other words, there are very few defects in the first epitaxial layer near the channel region, which can further control the rate of ion diffusion.

[0131] The ratio of components in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer also gradually changes. For example, in a P-type transistor, the material of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer is silicon germanium, and the ratio of germanium in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer gradually increases, which can avoid curling or breaking of the epitaxial layer due to excessive stress.

[0132] refer to Fig.12 , in the subsequent process, it also includes: annealing the first epitaxial layer, the second epitaxial layer and the third epitaxial layer. Forming an etch stop layer 60 covering the sidewalls of the fin 11, the source and drain regions 30 and the sidewalls 40. Forming a dielectric layer 70 on the etch stop layer 60. Replacing the dummy gate with a metal gate. Forming a conductive via electrically connected to the source and drain regions and the metal gate. An interconnection structure electrically connected to the conductive via. And packaging the formed semiconductor structure. To form a complete semiconductor device.

[0133] In the embodiment of the present invention, a first epitaxial layer with a lower doping concentration and a second epitaxial layer and a third epitaxial layer with a higher doping concentration than the first epitaxial layer are sequentially formed. The concentration of doped ions in the source and drain regions from the sidewall of the channel region to the third epitaxial layer is gradually increased, which can control the rate of ion diffusion and avoid transient enhanced diffusion caused by a large concentration difference. In addition, the short channel effect can be suppressed and the performance of the semiconductor device can be improved.

[0134] On the other hand, an embodiment of the present invention further provides a semiconductor device, which includes: a front-end device layer and a source and drain region.

[0135] The front-end device layer includes a plurality of discrete fins and a gate structure spanning the fins. The area of ​​the fins located below the gate structure is a channel area. The fins on both sides of the gate structure have recessed areas.

[0136] The source / drain region is located in the recessed region, and the source / drain region includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked in sequence, wherein the doping concentration of the doping ions in the first epitaxial layer is less than the doping concentration of the doping ions in the second epitaxial layer and the third epitaxial layer, and the first epitaxial layer covers the sidewalls of the channel region and the bottom of the recessed region.

[0137] Fig.13 Schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Fig.13 The semiconductor device described in the embodiment of the present invention includes: a front-end device layer 10' and a source and drain region 30'.

[0138] The front-end device layer 10' includes a plurality of discrete fins 11' and a gate structure 12' spanning the fins 11'. The region of the fins 11' below the gate structure 12' is a channel region C'. The fins 11' on both sides of the gate structure 12' have recessed regions.

[0139] The plurality of fins 11 ′ are parallel or substantially parallel.

[0140] In an optional implementation, the front-end device layer 10' further includes a shallow trench isolation structure 13'. The shallow trench isolation structure 13' fills the bottom of the adjacent fins 11'. The shallow trench isolation structure 13' is used for electrical isolation between adjacent fins 11'.

[0141] The gate structure 12' comprises: an isolation layer 12a' and a dummy gate 12b'. The dummy gate 12b' comprises a gate dielectric layer, a dummy gate layer and a cap layer stacked in sequence.

[0142] In an optional implementation, the sidewalls of the gate structure 12 ′ are covered with spacers 40 ′.

[0143] The source and drain region 30' is located in the recessed region 20', and the source and drain region 30' includes a first epitaxial layer 30a', a first epitaxial layer 30b' and a third epitaxial layer 30c' stacked in sequence, wherein the doping concentration of the doping ions in the first epitaxial layer 30a' is less than the doping concentration of the doping ions in the first epitaxial layer 30b' and the third epitaxial layer 30c', and the first epitaxial layer 30a' covers the sidewalls of the channel region and the bottom of the recessed region.

[0144] Specifically, the doping concentrations of the doping ions of the first epitaxial layer 30 a ′, the first epitaxial layer 30 b ′, and the third epitaxial layer 30 c ′ increase in sequence.

[0145] Specifically, the doping concentration of the first epitaxial layer 30a' is E18-E19 / cm3, the doping concentration of the first epitaxial layer 30b' is E20-E21 / cm3, and the doping concentration of the third epitaxial layer 30c' is E21-E22 / cm3.

[0146] Specifically, the doping ions of the first epitaxial layer 30a', the first epitaxial layer 30b' and the third epitaxial layer 30c' include one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions.

[0147] Specifically, the semiconductor device is a P-type transistor, the first epitaxial layer 30a', the first epitaxial layer 30b' and the third epitaxial layer 30c' are all silicon germanium layers, wherein the germanium content of the first epitaxial layer 30a', the first epitaxial layer 30b' and the third epitaxial layer 30c' increases successively.

[0148] Specifically, the germanium content in the first epitaxial layer 30a' is 10%-20%; the germanium content in the first epitaxial layer 30b' is 20%-50%; and the germanium content in the third epitaxial layer 30c' is 30%-50%.

[0149] Specifically, the semiconductor device is an N-type transistor, the first epitaxial layer 30a', the first epitaxial layer 30b' and the third epitaxial layer 30c' are all silicon carbon layers, wherein the carbon contents of the first epitaxial layer 30a', the first epitaxial layer 30b' and the third epitaxial layer 30c' increase in sequence.

[0150] Specifically, the carbon content in the first epitaxial layer 30a' is 10%-20%; the carbon content in the first epitaxial layer 30b' is 20%-50%; and the germanium content in the third epitaxial layer 30c' is 30%-50%.

[0151] Specifically, the thickness of the first epitaxial layer 30a' is 3 nanometers to 7 nanometers; the thickness of the first epitaxial layer 30b' is 5 nanometers to 17 nanometers; and the upper surface of the third epitaxial layer 30c' is substantially flush with the upper surface of the fin 11'.

[0152] In an embodiment of the present invention, the source and drain regions include a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer and the third epitaxial layer have higher doping concentrations than the first epitaxial layer. The concentration of doped ions in the source and drain regions from the sidewall of the channel region to the region of the third epitaxial layer is gradually increased, which can control the rate of ion diffusion and avoid transient enhanced diffusion caused by a large concentration difference. In addition, the short channel effect can be suppressed and the performance of the semiconductor device can be improved.

[0153] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: The method comprises: Providing a front-end device layer, the front-end device layer comprising a plurality of discrete fins and a gate structure spanning the fins, wherein the region of the fins located below the gate structure is a channel region; Using the gate structure as a mask, etching the fins on both sides of the gate structure to form a recessed area on the fins, exposing the sidewalls of the channel area; and A source-drain region is formed in the recessed region, the source-drain region comprising a first epitaxial layer, a second epitaxial layer and a third epitaxial layer stacked in sequence, wherein the doping concentration of doped ions in the first epitaxial layer is less than the doping concentration of doped ions in the second epitaxial layer and the third epitaxial layer, The forming of the source and drain regions in the recessed region comprises: forming the second epitaxial layer on the first epitaxial layer; and forming the third epitaxial layer on the second epitaxial layer; The forming of the second epitaxial layer on the first epitaxial layer comprises: forming a second epitaxial material layer on the first epitaxial layer by a second epitaxial process; and Performing ion implantation on the second epitaxial material layer by using a first ion implantation process; The forming of the third epitaxial layer on the second epitaxial layer comprises: forming a third epitaxial material layer on the second epitaxial layer by a third epitaxial process; and Performing ion implantation on the third epitaxial material layer by using a second ion implantation process; Among them, the injection energy of the first ion injection process is less than the injection energy of the second ion injection process, the doping concentrations of the doped ions in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase successively, and the first epitaxial layer covers the sidewalls of the channel region and the bottom of the recessed region.

2. The method for forming a semiconductor device according to claim 1, wherein: The doping concentration of the first epitaxial layer is E18-E19 / cubic centimeter, the doping concentration of the second epitaxial layer is E20-E21 / cubic centimeter, and the doping concentration of the third epitaxial layer is E21-E22 / cubic centimeter.

3. The method for forming a semiconductor device according to claim 1, wherein: The semiconductor device is a P-type transistor, and the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer include at least one of boron ions, gallium ions and indium ions.

4. The method for forming a semiconductor device according to claim 1, wherein: The semiconductor device is an N-type transistor, and the doping ions of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer include at least one of phosphorus ions or arsenic ions.

5. The method for forming a semiconductor device according to claim 1, wherein: The semiconductor device is a P-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon germanium layers, wherein the germanium contents of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase in sequence.

6. The method for forming a semiconductor device according to claim 5, wherein: The molar fraction of germanium in the first epitaxial layer is 10%-20%; the molar fraction of germanium in the second epitaxial layer is 20%-50%; and the molar fraction of germanium in the third epitaxial layer is 30%-50%.

7. The method for forming a semiconductor device according to claim 1, wherein: The semiconductor device is an N-type transistor, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon carbon layers, wherein the carbon contents of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase in sequence.

8. The method for forming a semiconductor device according to claim 7, wherein: The semiconductor device is an N-type transistor, the molar fraction of carbon in the first epitaxial layer is 10%-20%; the molar fraction of carbon in the second epitaxial layer is 20%-50%; and the molar fraction of carbon in the third epitaxial layer is 30%-50%.

9. The method for forming a semiconductor device according to claim 1, wherein: The gate structure includes a dummy gate and an isolation layer covering the sidewall of the dummy gate. Before forming the second epitaxial layer on the first epitaxial layer, the forming of the source and drain regions further includes: thinning the isolation layer; The dummy gate and the thinned isolation layer are used as masks, and a first epitaxial process is adopted to form the first epitaxial layer on the bottom surface of the recessed region and the sidewalls of the channel region.

10. The method for forming a semiconductor device according to claim 9, wherein: After ion implantation is performed on the second epitaxial material layer using a first ion implantation process, forming the second epitaxial layer on the first epitaxial layer further comprises: The second epitaxial material layer is annealed to form a second epitaxial layer.

11. The method for forming a semiconductor device according to claim 9, wherein: Before the second ion implantation process is used to implant ions into the third epitaxial material layer, the step of forming the third epitaxial layer on the second epitaxial layer further comprises: forming a sidewall covering the sidewall of the thinned isolation layer; The step of using the second ion implantation process to implant ions into the third epitaxial material layer comprises: Using the dummy gate, the thinned isolation layer and the sidewall as masks, a second ion implantation process is used to implant ions into the third epitaxial material layer to form a third epitaxial layer.

12. The method for forming a semiconductor device according to claim 1, wherein: The first ion implantation process is specifically as follows: the implanted ions are one or more of carbon ions, phosphorus ions, boron ions, gallium ions and arsenic ions, the implantation energy is 0.5K-2K, and the doping concentration is 2E14-5E14.

13. The method for forming a semiconductor device according to claim 1, wherein: The first ion implantation process is specifically as follows: the implanted ions include ions of a type opposite to that of the doping ions in the source and drain regions.

14. The method for forming a semiconductor device according to claim 1, wherein: The thickness of the first epitaxial layer is 3 nanometers to 7 nanometers; the thickness of the second epitaxial layer is 5 nanometers to 17 nanometers; and the upper surface of the third epitaxial layer is substantially flush with the upper surface of the fin.

15. A semiconductor device, characterized in that: The semiconductor device comprises: A front-end device layer, the front-end device layer comprising a plurality of discrete fins and a gate structure spanning the fins, the region of the fins located below the gate structure being a channel region, and the fins on both sides of the gate structure having recessed regions; A source / drain region, wherein the source / drain region is located in the recessed region, and the source / drain region comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer stacked in sequence from bottom to top, wherein the doping concentration of the doped ions in the first epitaxial layer is less than the doping concentration of the doped ions in the second epitaxial layer and the third epitaxial layer, the doping concentrations of the doped ions in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase in sequence, the first epitaxial layer covers the sidewalls of the channel region and the bottom of the recessed region, and the injection energy of ion injection when the second epitaxial layer is formed is less than the injection energy of ion injection when the third epitaxial layer is formed, so that the number of defects in the second epitaxial layer is less than the number of defects in the third epitaxial layer.

16. The semiconductor device according to claim 15, characterized in that The semiconductor device is a P-type transistor, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon germanium layers, wherein the germanium contents of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase in sequence.

17. The semiconductor device according to claim 15, characterized in that The semiconductor device is an N-type transistor, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all silicon carbon layers, wherein the carbon contents of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer increase in sequence.

18. The semiconductor device according to claim 15, characterized in that The thickness of the first epitaxial layer is 3 nanometers to 7 nanometers; the thickness of the second epitaxial layer is 5 nanometers to 17 nanometers; and the upper surface of the third epitaxial layer is substantially flush with the upper surface of the fin.

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