A nanosheet transistor with a heterogeneous gate dielectric and a method for preparing the same

Abstract

The present invention discloses a nanosheet transistor with a heterogeneous gate dielectric and a preparation method thereof; the nanosheet transistor comprises: a substrate, a source region, a drain region, a gate material and a plurality of nanosheet channel layers; wherein the gate material covers the nanosheet channel layer to form a gate structure; the source region, the gate structure and the drain region are sequentially arranged on the substrate along the channel direction; the channel direction is the direction from the source region to the drain region; a heterogeneous gate dielectric layer is arranged between the adjacent surfaces of the gate material and the nanosheet channel layer and between the adjacent surfaces of the gate material and the substrate; the heterogeneous gate dielectric layer comprises a plurality of gate dielectric materials continuously arranged along the channel direction, and the relative dielectric constants of the plurality of gate dielectric materials gradually decrease with the channel direction; the source region is isolated from the gate region by a first isolation dielectric; the drain region is isolated from the gate region by a first isolation dielectric. The present invention reduces the short channel effect of a small-sized field effect transistor, reduces the off-state current leakage, and improves the electrical performance of a small-sized semiconductor device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a nanosheet transistor with a heterogeneous gate dielectric and a preparation method thereof. Background Art

[0002] As the size of semiconductor devices gradually decreases, the short channel effect, which has little effect on large-size devices, gradually poses a threat to the performance of small-size devices. The short channel effect refers to the fact that under the condition of applied voltage, the depletion region formed at the source-drain PN junction will shorten the channel length in disguise. For small-size devices, the impact of the short channel effect begins to become difficult to ignore. In addition, due to the increase in the electric field strength at the drain end caused by the shortening of the channel, it is very easy for carriers to reach the drain end through tunneling, causing off-state current leakage; this phenomenon is like the lowering of the drain barrier in effect, which is called the drain-induced barrier lowering effect. In small-size devices, the short channel effect reduces the threshold voltage of the device, which increases the leakage current of the device in the off state; the resulting increase in power consumption and loss of electrical performance are unacceptable for large-scale integrated circuits. Therefore, it is necessary to optimize the device so that it can adapt to the reduction of process size without deteriorating performance.

[0003] In related technologies, in order to reduce the impact of short channel effects on devices, field effect transistors with special structures such as fin field effect transistors, stacked nanowire field effect transistors, and stacked nanosheet field effect transistors have been proposed. Among them, in the fin field effect transistor, the channel is made into a three-dimensional vertical structure similar to a fish fin, and the gate is covered around the channel; the nanowire field effect transistor is an improvement on the fin field effect transistor, separating the fin into nanowires and completely surrounding the nanowires with gate materials; the nanosheet field effect transistor increases the channel width on the basis of the nanowire, making the conductive channel thin sheet-like.

[0004] However, even for nano field effect transistors with the best gate control capability, their performance will still be suppressed by the short channel effect due to the higher electric field strength at the drain end when the size is small; and if high dielectric constant materials are used as gate dielectrics to improve the on-state characteristics, the short channel effect and the current leakage effect in the off state will become more obvious, greatly increasing the static power consumption of the device. Summary of the invention

[0005] In order to reduce the short channel effect and off-state current leakage of small-sized field effect transistors and improve the electrical performance of small-sized field effect transistors, the present invention provides a nanosheet transistor with a heterogeneous gate dielectric and a preparation method thereof.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] A nanosheet transistor with a heterogeneous gate dielectric comprises: a substrate, a source region, a drain region, a gate material, and a plurality of nanosheet channel layers arranged in parallel; wherein:

[0008] The gate material covers the multiple nanosheet channel layers to form a surrounding gate structure;

[0009] The source region, the gate structure and the drain region are sequentially arranged on the substrate along a channel direction, and electrodes are respectively provided on the three regions; the channel direction is a direction from the source region to the drain region;

[0010] A heterogeneous gate dielectric layer is disposed between the gate material and the adjacent surface of the nanosheet channel layer and the adjacent surface of the substrate; the heterogeneous gate dielectric layer includes a plurality of gate dielectric materials continuously disposed along the channel direction, and the relative dielectric constants of the plurality of gate dielectric materials gradually decrease along the channel direction;

[0011] The source region is isolated from the gate region by a first isolation dielectric; the drain region is isolated from the gate region by the first isolation dielectric; and the gate region includes the gate material and the heterogeneous gate dielectric layer.

[0012] In one embodiment, the source region and the drain region both include: epitaxial silicon and a second isolation dielectric;

[0013] The inner surface of the epitaxial silicon is in contact with the nanosheet channel layer and the first isolation medium;

[0014] The second isolation dielectric is attached to the remaining surface of the epitaxial silicon.

[0015] In one embodiment, the heterogeneous gate dielectric layer includes: hafnium dioxide HfO2 material and silicon dioxide SiO2 material continuously arranged along the channel direction.

[0016] In one embodiment, the gate material includes titanium nitride TiN.

[0017] In one embodiment, the material of the nanosheet channel layer includes Group IV semiconductor material or Group III-V semiconductor material.

[0018] In one embodiment, the first isolation medium includes silicon nitride Si3N4.

[0019] In a second aspect, an embodiment of the present invention provides a method for preparing a nanosheet transistor having a heterogeneous gate dielectric, comprising:

[0020] Step 1: alternately depositing multiple layers of sacrificial materials and multiple nanosheet channel layers on a substrate to form a superlattice structure; in the superlattice structure, the multiple nanosheet channel layers are arranged in parallel;

[0021] Step 2: forming a pseudo gate stack layer in the middle section of the upper surface of the superlattice structure, and depositing a first isolation dielectric on both sides of the middle section;

[0022] Step 3: using the pseudo gate stack layer as a mask to etch the sacrificial material at both ends of the superlattice structure, so that the sacrificial material under each of the nanosheet channel layers is moved inward relative to the nanosheet channel layer to form a groove;

[0023] Step 4: Filling the first isolation medium into the groove;

[0024] Step 5: Making source regions and drain regions on both sides of the superlattice structure;

[0025] Step 6: etching away the dummy gate stack layer and the sacrificial material to form an exposed gap; the exposed gap is used to make a gate region;

[0026] Step 7: Based on a plurality of preset masks, in the exposed gap, continuously depositing a plurality of gate dielectric materials on the surface of the nanosheet channel layer along a preset channel direction to form a heterogeneous gate dielectric layer on the surface of the nanosheet channel layer; wherein the relative dielectric constants of the plurality of gate dielectric materials gradually decrease along the channel direction; and the channel direction is a direction from the source region to the drain region;

[0027] Step 8: Filling the remaining space of the exposed gap with a gate material, and making the gate material cover the multiple nanosheet channel layers to form a surrounding gate structure;

[0028] Step 9: Electrodes are fabricated on the source region, the drain region and the gate structure respectively.

[0029] In one embodiment, the heterogeneous gate dielectric layer includes: hafnium dioxide HfO2 material and silicon dioxide SiO2 material continuously arranged along the channel direction.

[0030] In one embodiment, step 5 includes:

[0031] Fabricating epitaxial silicon on both sides of the superlattice structure; wherein the inner surface of the epitaxial silicon is in contact with the nanosheet channel layer and the first isolation medium;

[0032] A second isolation dielectric is deposited on the remaining surfaces of the epitaxial silicon on both sides to obtain the source region and the drain region.

[0033] In one embodiment, the gate material includes titanium nitride TiN.

[0034] In the nanosheet transistor with heterogeneous gate dielectric provided by the present invention, a variety of gate dielectric materials with different relative dielectric constants are deposited along the channel direction, and the relative dielectric constants of these gate dielectric materials gradually decrease along the channel direction; thus, the present invention can make the electric field intensity appear a peak in the center of the channel, thereby improving the channel mobility, improving the turn-on current of the nanosheet transistor, and suppressing the leakage current of the nanosheet structure in the off state; based on this, the present invention can also effectively reduce the static power consumption of the nanosheet structure, while improving the driving ability of the nanosheet structure. In summary, the present invention reduces the short channel effect of small-sized field effect transistors, reduces the off-state current leakage, and improves the electrical performance of small-sized semiconductor devices.

[0035] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a three-dimensional diagram of the appearance of a nanosheet transistor with a heterogeneous gate dielectric provided by an embodiment of the present invention;

[0037] Figure 2 yes Figure 1 A cross-sectional view in the front direction;

[0038] Figure 3 is along Figure 1 A cross-sectional view in the left direction made on a plane perpendicular to each nanosheet channel layer;

[0039] Figure 4 is a three-dimensional diagram of the appearance of another nanosheet transistor with a heterogeneous gate dielectric provided by an embodiment of the invention;

[0040] Figure 5 and Figure 6 It is a leakage current simulation diagram of the nanosheet transistor provided by the embodiment of the invention and the existing nanosheet transistor using a single gate dielectric material;

[0041] Figure 7 It is a flow chart of a method for preparing a nanosheet transistor with a heterogeneous gate dielectric provided by an embodiment of the present invention;

[0042] Figure 8(a) to Figure 8(j) yes Figure 7 Schematic diagram of the sample structure obtained after each step is completed. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0044] In order to reduce the short channel effect and off-state current leakage of small-sized field effect transistors and improve the electrical performance of small-sized field effect transistors, the present invention provides a nanosheet transistor with a heterogeneous gate dielectric and a preparation method. First, the nanosheet transistor with a heterogeneous gate dielectric provided by the present invention is described in detail. Figure 1 and Figure 2 As shown, the nanosheet transistor includes: a substrate 10, a source region 20, a drain region 30, a gate material 40, and a plurality of nanosheet channel layers 50 arranged in parallel; Figure 1 This is a three-dimensional structural diagram of the nanosheet transistor. Figure 2 This is a cross-sectional view of the nanosheet transistor from the front direction.

[0045] Among them, the gate material 40 covers the above-mentioned multiple nanosheet channel layers 50 to form a surrounding gate structure; the source region 20, the surrounding gate structure and the drain region 30 are sequentially arranged on the substrate 10 along the channel direction, and the three are respectively provided with electrodes; the channel direction is the direction from the source region 20 to the drain region 30; a heterogeneous gate dielectric layer is arranged between the adjacent surfaces of the gate material 40 and the nanosheet channel layer 50 and between the adjacent surfaces of the gate material 40 and the substrate 10; the heterogeneous gate dielectric layer includes a plurality of gate dielectric materials continuously arranged along the channel direction, and the relative dielectric constants of these gate dielectric materials gradually decrease along the channel direction; Figure 2 In the figure, mark 601 and mark 602 represent two different gate dielectric materials respectively; the source region 20 is isolated from the gate region by the first isolation dielectric 70; the drain region 30 is isolated from the gate region by the first isolation dielectric 70; the gate region includes a gate material 40 and a heterogeneous gate dielectric layer.

[0046] In the nanosheet transistor, a heterogeneous gate dielectric layer is disposed between the adjacent surfaces of the gate material 40 and the nanosheet channel layer 50 in the surrounding gate structure, that is, this portion of the heterogeneous gate dielectric layer forms a structure covering the surface of the nanosheet channel layer 50; Figure 3 It is a cross-sectional view in the left-view direction along a plane perpendicular to each nanosheet channel layer 50, and it can be seen that a gate dielectric material 601 of the heterogeneous gate dielectric layer is coated on the surface of the nanosheet channel layer 50. It can be understood that for the nanosheet transistor, the nanosheet channel layer 50 is in contact with the source region 20 and the drain region 30, so as to form a conductive channel during operation; that is, the gate material 40 coats multiple nanosheet channel layers 50, but does not completely coat these nanosheet channel layers 50 without leaving any gaps, and the two end faces of each nanosheet layer are not attached with the gate material 40.

[0047] In addition, the specific structure and material of the components such as the source region 20, the drain region 30, the heterogeneous gate dielectric layer, the gate material 40 and the nanosheet channel layer 50 are not limited in this example, and any solution that can realize the above-mentioned nanosheet transistor can be applied to the embodiments of the present invention.

[0048] In the embodiment of the present invention, a plurality of gate dielectric materials with different relative dielectric constants are deposited along the channel direction, and the relative dielectric constants of these gate dielectric materials gradually decrease along the channel direction; thus, the embodiment of the present invention can make the electric field strength appear a peak value in the center of the channel, thereby improving the channel mobility, improving the on-current of the nanosheet transistor, and suppressing the leakage current of the nanosheet structure in the off state; based on this, the embodiment of the present invention can also effectively reduce the static power consumption of the nanosheet structure, while improving the driving ability of the nanosheet structure. In summary, the embodiment of the present invention reduces the short channel effect and off-state current leakage of small-sized field effect transistors, and improves the electrical performance of small-sized semiconductor devices.

[0049] In one embodiment, the specific composition structure of the source region 20 and the drain region 30 can be seen in Figure 4 As shown, it includes: epitaxial silicon 80 and a second isolation dielectric 90 ; the inner surface of the epitaxial silicon 80 is in contact with the nanosheet channel layer 50 and the first isolation dielectric 70 ; and the second isolation dielectric 90 is attached to the remaining surface of the epitaxial silicon 80 .

[0050] In this embodiment, under the premise that the inner surface of the epitaxial silicon 80 is in contact with the nanosheet channel layer 50 and the first isolation medium 70, the upper and lower sides and the outer side of the epitaxial silicon 80 can be moved inward for a distance; in this way, the source region 20 and the drain region 30 are in contact with the underlying substrate 10 by the second isolation medium 90, and the second isolation medium 90 can also be in contact with a portion of the isolation medium located at the top of the nanosheet transistor.

[0051] There are many types of materials for the second isolation medium 90. For example, the second isolation medium 90 may include silicon dioxide SiO2, but it is not limited thereto.

[0052] In one embodiment, the above-mentioned heterogeneous gate dielectric layer may include: hafnium dioxide HfO2 material and silicon dioxide SiO2 material continuously arranged along the channel direction.

[0053] It can be understood that in the heterogeneous gate dielectric layer, the HfO 2 material has a higher relative dielectric constant and is close to the source region 20 , while the SiO 2 material has a lower relative dielectric constant and is close to the drain region 30 .

[0054] In one embodiment, the gate dielectric material at one end of the heterogeneous gate dielectric layer close to the source region 20 may also be silicon nitride Si3N4 or aluminum oxide Al2O3, and the gate dielectric material at one end close to the drain region 30 may also be a composite material formed by HfO2 and SiO2; the relative dielectric constant of the composite material is between that of HfO2 and SiO2.

[0055] It should be noted that the gate dielectric materials that can be used in the heterogeneous gate dielectric layer are not limited to two types. Three or even more different gate dielectric materials can be selected according to the requirement that the relative dielectric constant decreases from the source region 20 to the drain region 30 and the actual performance requirements of the device. Due to space limitations, the embodiments of the present invention will not list them one by one.

[0056] In one embodiment, the gate material 40 may include titanium nitride TiN; or, the gate material 40 may also be tantalum, tungsten or tantalum nitride N5Ta3 and the like.

[0057] In one embodiment, the material of the nanosheet channel layer 50 includes a Group IV semiconductor material or a Group III-V semiconductor material. Preferably, the nanosheet channel layer 50 may be a silicon nanosheet channel layer.

[0058] In one embodiment, the first isolation medium 70 may include Si 3 N 4 , but is not limited thereto.

[0059] In one embodiment, the substrate 10 may include a SOI (Silicon On Insulator) substrate or other commonly used substrates; wherein the SOI substrate refers to a substrate composed of a bottom silicon substrate and an upper buried oxide layer.

[0060] In a specific embodiment, the substrate in the nanosheet transistor is an SOI substrate, and two parallel silicon nanosheet channel layers 50 are used; the gate material 40 is TiN, the first isolation dielectric 70 is Si3N4, and the source region 20 and the drain region 30 are both structures of epitaxial silicon covered with silicon dioxide; wherein the length of the silicon nanosheet channel layer 50 is set to 10 nanometers, and the width is set to 25 nanometers. Based on the above parameter settings, the drain current of the nanosheet transistor is simulated as the gate voltage changes. The simulation results can be seen in Figure 5 and Figure 6 shown.

[0061] Figure 5 and Figure 6 In the figure, the horizontal axis data is the gate voltage applied to the nanosheet transistor, in volts; the vertical axis data is the drain current of the nanosheet transistor, in amperes. The gray curve is the drain current 2 presented when the nanosheet transistor in the embodiment of the present invention uses a heterogeneous gate dielectric layer composed of two materials, HfO2 and SiO2, when it is turned off. The black curve is the drain current 1 presented when the nanosheet transistor in the prior art uses a heterogeneous gate dielectric layer composed of a single material when it is in the off state. Comparison Figure 5 and Figure 6 It can be seen that the nanosheet transistor using a heterogeneous gate dielectric layer provided by the embodiment of the present invention has a significantly lower drain current when in the off state.

[0062] Corresponding to the nanosheet transistor with heterogeneous gate dielectric provided by the embodiment of the present invention, the embodiment of the present invention also provides a method for preparing the nanosheet transistor, which is described in detail below. It should be noted that in the subsequent description, the unfinished nanosheet transistors are uniformly referred to as samples.

[0063] As shown in FIG8 , the method may include the following steps:

[0064] Step 1: Multiple layers of sacrificial material 100 and multiple nanosheet channel layers 50 are alternately deposited on a substrate 10 to form a superlattice structure; in the superlattice structure, multiple nanosheet channel layers 50 are arranged in parallel.

[0065] Specifically, in this step, the sacrificial material 100 and the nanosheet channel layer 50 may be alternately deposited layer by layer on the substrate 10 by using a chemical vapor deposition process.

[0066] Among them, the material selection of the substrate 10 and the nanosheet channel layer 50 can be the same as the above-mentioned nanosheet transistor embodiment. The sacrificial material 100 is a material used in the process of preparing the nanosheet transistor, and the sacrificial material 100 does not exist in the final prepared nanosheet transistor. The sacrificial material 100 and the nanosheet channel layer 50 need to have different chemical etching selectivities; that is, the chemical substance that can chemically etch the sacrificial material 100 cannot etch the nanosheet channel layer 50; the chemical substance that can chemically etch the nanosheet channel layer 50 cannot etch the sacrificial material 100. For example, when the nanosheet channel layer 50 is a silicon nanosheet channel layer, the sacrificial material 100 can use silicon germanium.

[0067] The sample obtained after step 1 is completed can be seen in Figure 8(a).

[0068] Step 2: fabricate a dummy gate stack layer 110 in the middle section of the upper surface of the superlattice structure, and deposit a first isolation dielectric 70 on both sides of the middle section.

[0069] The first isolation dielectric 70 is used to subsequently isolate the source region 20 from the gate region, and to isolate the gate region from the drain region 30. Exemplarily, the first isolation dielectric 70 may be Si3N4 or the like.

[0070] The dummy gate stack layer 110 is mainly used as a mask in subsequent steps to etch the sacrificial material 100. In practical applications, the dummy gate stack layer 110 may be a polysilicon layer.

[0071] Specifically, step 2 may include the following sub-steps:

[0072] Step 2-1: depositing a layer of amorphous silicon on the middle section of the upper surface of the superlattice structure;

[0073] Step 2-2: Performing solid phase recrystallization treatment on the current sample using a solid phase recrystallization process to form a polycrystalline silicon layer from amorphous silicon;

[0074] Step 2-3: etching both ends of the amorphous silicon layer to expose two regions of the upper surface of the underlying superlattice structure;

[0075] Step 2-4: Deposit Si3N4 on the two regions using a chemical vapor deposition process.

[0076] The sample obtained after step 2 is completed can be seen in Figure 8(b).

[0077] Step 3: Using the dummy gate stack layer 110 as a mask, the sacrificial material 100 at both ends of the superlattice structure is etched so that the sacrificial material 100 under each nanosheet channel layer 50 is moved inward relative to the nanosheet channel layer 50 to form a groove.

[0078] It is understandable that the sacrificial material 100 located below each nanosheet channel layer 50 at both ends of the superlattice structure is mainly etched in step 3. It is also understandable that the sacrificial material 100 at both ends of the superlattice structure is etched using the pseudo gate stack layer 110 as a mask, and the etching depth when etching the groove is to reach the boundaries on both sides of the mask.

[0079] In practical applications, the sacrificial material 100 located below each nanosheet channel layer 50 at both ends of the superlattice structure can be etched using a wet etching process, so that the space occupied by the etched sacrificial material 100 is formed into a groove that evades inward. For example, when the sacrificial material 100 is silicon germanium, the sacrificial material 100 can be wet-etched using chemicals such as hydrogen peroxide and hydrofluoric acid, nitric acid and hydrofluoric acid. When the sacrificial material 100 is not silicon germanium, an appropriate selective wet etching agent or other etching process should be selected according to the selected sacrificial material 100 for etching. It should be emphasized that when a wet etching process is selected, the selected wet etching agent must meet the condition that the nanosheet channel layer 50 cannot be etched.

[0080] In addition, in this step, isotropic etching is preferably used to etch the sacrificial material 100 so that the etching rates in each crystal direction are equal when etching the sacrificial material 100 .

[0081] The sample obtained after step 3 is completed can be seen in Figure 8(c).

[0082] Step 4: Fill the groove with a first isolation medium 70 .

[0083] The first isolation dielectric 70 filled in this step plays the same role as the first isolation dielectric 70 deposited in step 2 , both of which are for the subsequent isolation of the source region 20 from the gate region, and the isolation of the gate region from the drain region 30 .

[0084] In practical applications, the first isolation medium 70 can be deposited into the groove using a highly conformal deposition process of atomic layer deposition to ensure that the first isolation medium 70 in the groove is fully filled; alternatively, the first isolation medium 70 can be deposited into the groove using a similar method such as a chemical vapor deposition process.

[0085] The sample obtained after step 4 is completed can be seen in Figure 8(d).

[0086] Step 5: Make source and drain regions on both sides of the superlattice structure.

[0087] Specifically, epitaxial silicon 80 can be grown on both sides of the superlattice structure using an epitaxial growth process, and the epitaxial silicon 80 can be doped accordingly according to the required conductivity type. According to the different conductivity types, the epitaxial silicon 80 on both sides of the superlattice structure can be N-type doped or P-type doped. When the doping is specifically implemented, an ion implantation process can be used.

[0088] In addition, under the premise of ensuring that the nanosheet transistor can achieve the predetermined performance, the size of the epitaxial silicon 80 is based on being able to fully contact the two end surfaces of each nanosheet channel layer 50 and to achieve contact with each part of the first isolation dielectric 70 prepared previously.

[0089] In practical applications, if the source region and the drain region do not need to further prepare a device electrical isolation region of a dielectric material, the epitaxial silicon 80 can be polished by chemical mechanical polishing to make the outer surface of the epitaxial silicon 80 smooth. In one implementation, the epitaxial silicon 80 can be further etched so that the epitaxial silicon 80 is moved inward relative to the substrate 10 to form a suspended device electrical isolation region.

[0090] In another implementation, the device electrical isolation region may be made of a dielectric material; in this case, step 5 may specifically include:

[0091] Step 5-1: fabricating epitaxial silicon 80 on both sides of the superlattice structure; wherein the inner surface of the epitaxial silicon 80 is in contact with the nanosheet channel layer 50 and the first isolation dielectric 70;

[0092] Step 5-2: Deposit a second isolation dielectric 90 on the remaining surfaces of the epitaxial silicon 80 on both sides to obtain a source region and a drain region.

[0093] In this implementation, under the premise that the inner surface of the epitaxial silicon 80 is in contact with the nanosheet channel layer 50 and the first isolation medium 70, the upper side and the outer side of the epitaxial silicon can be moved inward for a distance; in this way, the epitaxial silicon 80 and the second isolation medium 90 in the source region 20 and the drain region 30 are in contact with the substrate 10 below, and the second isolation medium 90 is also in contact with a portion of the isolation medium located at the top of the nanosheet transistor; therefore, different from the suspended device electrical isolation region, this embodiment uses the second isolation medium 90 to form a device electrical isolation region that completely wraps the epitaxial silicon, which has a better isolation effect.

[0094] In addition, when depositing the second isolation medium 90, a lead hole can be reserved in the middle of the deposited second isolation medium 90 for subsequent preparation of electrodes; the lead hole passes through the second isolation medium 90 from the upper surface of the sample until it reaches the upper surface of the epitaxial silicon 80 below.

[0095] The material of the second isolation medium 90 may include silicon dioxide SiO2, etc. The sample obtained after executing step 5 in this implementation manner can be shown in FIG8(e).

[0096] Step 6: Etch away the dummy gate stack layer 110 and the sacrificial material 100 to form an exposed gap; the exposed gap is used to make the gate region.

[0097] It is understood that the exposed gap refers to the space originally occupied by the dummy gate stack 110 and the sacrificial material 100 etched away in this step. The exposed gap is used for the subsequent deposition of a heterogeneous gate dielectric layer and a gate material 40; the heterogeneous gate dielectric layer and the gate material 40 together form a gate region.

[0098] In this step, a selective etching process may be used to etch away the dummy gate stack layer 110 and the currently remaining sacrificial material 100 .

[0099] The sample obtained after step 6 is completed can be seen in Figure 8(f).

[0100] Step 7: Based on multiple preset masks, in the exposed gap, a variety of gate dielectric materials are continuously deposited on the surface of the nanosheet channel layer 50 along a preset channel direction to form a heterogeneous gate dielectric layer on the surface of the nanosheet channel layer 50; wherein the relative dielectric constants of the multiple gate dielectric materials gradually decrease with the channel direction; the channel direction is the direction from the source region 20 to the drain region 30.

[0101] Each gate dielectric material corresponds to a preset mask, which is used to cover the area outside the target area where the gate dielectric material is to be deposited, so that after the deposition is completed, the gate dielectric material in the target area can be deposited by peeling off the preset mask, while other areas will not be deposited with the gate dielectric material. The preset mask contains a stripping glue.

[0102] Exemplarily, when the heterogeneous gate dielectric layer is composed of HfO2 material and SiO2 material, step 7 may include the following multiple sub-steps:

[0103] Step 7-1: In the exposed gap, a first preset mask is made on the surface of the nanosheet channel layer 50. The first preset mask is used to cover all surfaces except the first target area in the current sample. The first target area is the area on the surface of the nanosheet channel layer 50 in the exposed gap where the HfO2 material is to be deposited.

[0104] Step 7-2: Deposit HfO2 material into the first target area. The sample obtained after this step is completed can be seen in Figure 8(g). In Figure 8(g), the mark 601 represents the HfO2 material at this time.

[0105] Step 7-3: Peel off the first preset mask.

[0106] Step 7-4: In the exposed gap, a second preset mask is made on the surface of the nanosheet channel layer 50. The second preset mask is used to cover all surfaces outside the second target area in the current sample. The second target area is the area on the surface of the nanosheet channel layer 50 in the exposed gap where SiO2 material is to be deposited.

[0107] Step 7-5: Deposit SiO2 material into the second target area. The sample obtained after this step is completed can be seen in Figure 8(h). In Figure 8(h), the mark 602 represents the SiO2 material at this time.

[0108] Step 7-6: Peel off the second preset mask.

[0109] In addition, other combinations of various gate dielectric materials constituting the heterogeneous gate dielectric layer have been described in detail in the embodiments of the nanosheet transistor and will not be repeated here. The relevant manufacturing process of the heterogeneous gate dielectric layer can be adapted by referring to steps 7-1 to 7-6 and will not be repeated here.

[0110] Step 8: Fill the remaining space of the exposed gap with gate material 40, and make the gate material 40 cover the multiple nanosheet channel layers 50 to form a surrounding gate structure.

[0111] In this step, the gate material 40 can be deposited into the remaining space of the exposed gap by using a chemical vapor deposition process; by controlling the deposition amount and deposition time, the exposed gap can be filled while the space between each part of the exposed gap is also deposited with the gate material 40, thereby obtaining a surrounding gate structure capable of covering multiple nanosheet channel layers 50. In particular, as explained in step 5, the two end faces of the nanosheet channel layer 50 are in contact with the bulk silicon in the source region 20 and the drain region 30, so the surrounding gate structure deposited at this time does not completely cover the nanosheet channel layer 50 without leaving any gaps, and the two end faces of each nanosheet layer cannot be deposited with the gate material 40.

[0112] In addition, when depositing the gate material 40, a lead hole can be reserved on the topmost layer of gate material 40 deposited on the sample for subsequent preparation of the gate electrode. The lead hole extends deep into the topmost layer of gate material 40 deposited on the sample and does not contact the heterogeneous gate dielectric layer below.

[0113] The gate material 40 is preferably TiN, but is not limited thereto, and may also be tantalum, tungsten or N5Ta3, etc.

[0114] The sample after step 8 is completed can be seen in FIG8(i).

[0115] Step 9: Electrodes 120 are fabricated on the source region, the drain region and the gate structure respectively.

[0116] Preferably, in order to simplify the manufacturing process, electrodes 120 may be fabricated on the upper surfaces of the source region, the drain region and the gate structure, respectively, as shown in FIG8(j).

[0117] Specifically, step 9 may include the following multiple sub-steps:

[0118] Step 9-1: sputtering metal on the surface of the second isolation medium in the drain region, the source region and the lead hole and performing alloying treatment to form a layer of metal silicide;

[0119] Step 9-2: Etching away the metal on the surface of the metal silicide in the drain region and the source region;

[0120] Step 9-3: sputtering metal into the lead holes of the drain region, the source region and the gate structure until the three lead holes are filled;

[0121] Step 9-4: Using a photolithography process, photolithography electrode patterns are formed on the upper surfaces of the three filled lead holes;

[0122] Step 9-5: evaporating electrode metal into the electrode pattern;

[0123] Step 9-6: Annealing the sample to complete the preparation of the electrode 120.

[0124] The material of the electrode metal may include gold, copper or aluminum.

[0125] In the method for preparing a nanosheet transistor with a heterogeneous gate dielectric provided by an embodiment of the present invention, a plurality of gate dielectric materials with different relative dielectric constants are deposited along the channel direction, and the relative dielectric constants of these gate dielectric materials gradually decrease along the channel direction; thus, the nanosheet transistor prepared by the embodiment of the present invention can make the electric field strength appear a peak in the center of the channel, thereby improving the channel mobility, improving the on-current of the nanosheet transistor, and suppressing the leakage current of the nanosheet structure in the off state; based on this, the nanosheet transistor prepared by the embodiment of the present invention can also effectively reduce the static power consumption of the nanosheet structure, while improving the driving ability of the nanosheet structure. In summary, the nanosheet transistor prepared by the embodiment of the present invention reduces the short channel effect and reduces the off-state current leakage at a small size, and has good electrical performance.

[0126] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0127] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0128] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the present application for which protection is sought, a person skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims.

[0129] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A nanosheet transistor with a heterogeneous gate dielectric, characterized in that: include: A substrate, a source region, a drain region, a gate material, and a plurality of nanosheet channel layers arranged in parallel; wherein, The gate material covers the multiple nanosheet channel layers to form a surrounding gate structure; The source region, the gate structure and the drain region are sequentially arranged on the substrate along a channel direction, and electrodes are respectively provided on the three regions; the channel direction is a direction from the source region to the drain region; A heterogeneous gate dielectric layer is disposed between the gate material and the adjacent surface of the nanosheet channel layer and the adjacent surface of the substrate; the heterogeneous gate dielectric layer comprises a plurality of gate dielectric materials continuously disposed along the channel direction, the relative dielectric constants of the plurality of gate dielectric materials gradually decrease along the channel direction, and the substrate comprises an SOI substrate; The source region is isolated from the gate region by a first isolation dielectric; the drain region is isolated from the gate region by the first isolation dielectric; the gate region includes the gate material and the heterogeneous gate dielectric layer; The source region and the drain region both include: epitaxial silicon and a second isolation medium; The inner surface of the epitaxial silicon is in contact with the nanosheet channel layer and the first isolation medium; The second isolation medium is attached to the remaining surface of the epitaxial silicon, the upper and lower sides and the outer side of the epitaxial silicon are all avoided inward by a preset distance, and the second isolation medium is in contact with a portion of the first isolation medium located at the top of the nanosheet transistor.

2. The nanosheet transistor according to claim 1, characterized in that: The heterogeneous gate dielectric layer includes: hafnium dioxide HfO2 material and silicon dioxide SiO2 material which are continuously arranged along the channel direction.

3. The nanosheet transistor according to claim 1, characterized in that: The gate material includes titanium nitride TiN.

4. The nanosheet transistor according to claim 1, characterized in that: The material of the nanosheet channel layer includes group IV semiconductor material or group III-V semiconductor material.

5. The nanosheet transistor according to claim 1, characterized in that: The first isolation medium includes silicon nitride Si3N4.

6. A method for preparing a nanosheet transistor with a heterogeneous gate dielectric, characterized in that: include: Step 1: alternately depositing multiple layers of sacrificial materials and multiple nanosheet channel layers on a substrate to form a superlattice structure; In the superlattice structure, the plurality of nanosheet channel layers are arranged in parallel, and the substrate comprises an SOI substrate; Step 2: forming a pseudo gate stack layer in the middle section of the upper surface of the superlattice structure, and depositing a first isolation dielectric on both sides of the middle section; Step 3: using the pseudo gate stack layer as a mask to etch the sacrificial material at both ends of the superlattice structure, so that the sacrificial material under each of the nanosheet channel layers is moved inward relative to the nanosheet channel layer to form a groove; Step 4: Filling the first isolation medium into the groove; Step 5: Making source and drain regions on both sides of the superlattice structure, wherein the step 5 comprises: making epitaxial silicon on both sides of the superlattice structure, wherein the inner surface of the epitaxial silicon contacts the nanosheet channel layer and the first isolation medium, depositing a second isolation medium on the remaining surfaces of the epitaxial silicon on both sides, the second isolation medium is attached to the remaining surfaces of the epitaxial silicon, the upper and lower sides and the outer side of the epitaxial silicon are all inwardly avoided by a preset distance, so as to obtain the source region and the drain region, and the second isolation medium contacts a portion of the first isolation medium located at the top of the nanosheet transistor; Step 6: etching away the dummy gate stack layer and the sacrificial material to form an exposed gap; the exposed gap is used to make a gate region; Step 7: Based on a plurality of preset masks, in the exposed gap, continuously depositing a plurality of gate dielectric materials on the surface of the nanosheet channel layer along a preset channel direction to form a heterogeneous gate dielectric layer on the surface of the nanosheet channel layer; wherein the relative dielectric constants of the plurality of gate dielectric materials gradually decrease along the channel direction; and the channel direction is a direction from the source region to the drain region; Step 8: Filling the remaining space of the exposed gap with a gate material, and making the gate material cover the multiple nanosheet channel layers to form a surrounding gate structure; Step 9: Electrodes are fabricated on the source region, the drain region and the gate structure respectively.

7. The method according to claim 6, characterized in that The heterogeneous gate dielectric layer includes: hafnium dioxide HfO2 material and silicon dioxide SiO2 material which are continuously arranged along the channel direction.

8. The method according to claim 6, characterized in that The gate material includes titanium nitride TiN.

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