Improved sense amplifier with bit line precharge circuit for reading flash memory cells in an array

Abstract

The present invention relates to an improved sense amplifier for reading the value of a flash memory cell in an array. In one embodiment, the sense amplifier includes an improved precharge circuit for precharging the bit line during a precharge cycle, thereby increasing the speed of the read operation. In another embodiment, the sense amplifier includes a simplified address decoding circuit to increase the speed of the read operation.

Description

Technical Field

[0001] This application is a divisional application of Application No.: 201610815185.0 Invention Name: Improved sense amplifier with bit line precharge circuit for reading flash memory cells in an array. The present invention relates to an improved sense amplifier for reading the value of a flash memory cell in an array. In one embodiment, the sense amplifier includes an improved precharge circuit for precharging the bit line during a precharge cycle, thereby increasing the speed of the read operation. In another embodiment, the sense amplifier includes a simplified address decoding circuit to increase the speed of the read operation. Background Art

[0002] Non-volatile memory cells are well known in the art. Figure 1 , a prior art nonvolatile split gate memory cell 10 is shown, which includes five terminals. The memory cell 10 includes a semiconductor substrate 12 of a first conductivity type, such as a P-type. The substrate 12 has a surface on which a first region 14 (also referred to as a source line SL) of a second conductivity type, such as an N-type, is formed. A second region 16 (also referred to as a drain line), also of the N-type, is formed on the surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18. A bit line BL 20 is connected to the second region 16. A word line WL 22 is positioned over a first portion of the channel region 18 and is insulated therefrom. The word line 22 barely overlaps or does not overlap the second region 16 at all. A floating gate FG 24 is over another portion of the channel region 18. The floating gate 24 is insulated from the other portion and is adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. The floating gate 24 may overlap the first region 14 to provide coupling from the first region 14 into the floating gate 24. A coupling gate CG (also referred to as a control gate) 26 is located above the floating gate 24 and insulated therefrom. An erase gate EG 28 is located above the first region 14 and adjacent to the floating gate 24 and the coupling gate 26 and insulated therefrom. The top corner of the floating gate 24 may point to the inner corner of the T-shaped erase gate 28 to enhance erase efficiency. The erase gate 28 is also insulated from the first region 14. The memory cell 10 is described in more detail in U.S. Patent No. 7,868,375, the disclosure of which is incorporated herein by reference in its entirety.

[0003] An exemplary operation of erasing and programming of a prior art non-volatile memory cell 10 is as follows. The memory cell 10 is erased by applying a high voltage on the erase gate 28 and making the other terminals equal to zero volts through the Fowler-Nordheim tunneling mechanism. Electrons tunnel from the floating gate 24 into the erase gate 28, causing the floating gate 24 to be positively charged, thereby turning on the cell 10 in the read state. The resulting cell erased state is referred to as the '1' state.

[0004] The memory cell 10 is programmed by applying a high voltage on the coupling gate 26, a high voltage on the source line 14, a medium voltage on the erase gate 28, and a programming current on the bit line 20 through a source-side hot electron programming mechanism. A portion of the electrons flowing through the gap between the word line 22 and the floating gate 24 gain sufficient energy to be injected into the floating gate 24, causing the floating gate 24 to be negatively charged, thereby turning off the cell 10 in the read state. The resulting cell programming state is referred to as the '0' state.

[0005] The memory cell 10 is read in a current sensing mode as follows: a bias voltage is applied to the bit line 20, a bias voltage is applied to the word line 22, a bias voltage is applied to the coupling gate 26, a bias voltage or a zero voltage is applied to the erase gate 28, and a ground potential is applied to the source line 14. For the erased state, there is a cell current flowing from the bit line 20 to the source line 14, and for the programmed state, there is an insignificant or zero cell current flowing from the bit line 20 to the source line 14. Alternatively, the memory cell 10 can be read in a reverse current sensing mode, in which the bit line 20 is grounded and a bias voltage is applied to the source line 14. In this mode, the current reverses direction and flows from the source line 14 to the bit line 20.

[0006] Alternatively, the memory cell 10 may be read in a voltage sensing mode as follows: a bias current is applied on the bit line 20 (ground), a bias voltage is applied on the word line 22, a bias voltage is applied on the coupling gate 26, a bias voltage is applied on the erase gate 28, and a bias voltage is applied on the source line 14. For the erased state, there is a cell output voltage (significantly >0V) on the bit line 20, while for the programmed state, there is an insignificant or near zero output voltage on the bit line 20. Alternatively, the memory cell 10 may be read in a reverse voltage sensing mode, in which the bit line 20 is biased at the bias voltage and a bias current is applied on the source line 14 (ground). In this mode, the memory cell 10 output voltage is on the source line 14 instead of on the bit line 20.

[0007] The prior art also includes decoding circuits for selecting addresses within a memory array and selecting bit lines within the array. Figure 5A prior art memory system 500 is shown. Memory system 500 includes array 530 and array 540, which are typically identical memory arrays of floating gate memory cells. Address line 580 carries address signals for memory locations to which a read or write operation is applied. Address decoder 510 and address decoder 520 decode the address carried on address line 580 and activate the appropriate word lines and bit lines in array 530 or array 540 to read a data word from the correct location, or write a data word to the correct location. As part of this operation, address decoder 510 controls bit line multiplexer 550, and address decoder 520 controls bit line multiplexer 560.

[0008] For example, during a read operation of a particular address in array 530, the appropriate word line X and bit line Y in array 530 will be activated, and bit line multiplexer 550 will output word 95 from that position in array 530 as an input to comparator 570. At the same time, all word lines of array 540 are cut off, because the read operation does not involve array 540. The same bit line Y in array 540 as that activated in array 530 is activated, and bit line multiplexer 560 outputs word 96 from bit line Y as an input to comparator 570. Because the word lines of array 540 are not activated, word 96 will not constitute data stored in array 540, but rather represents a precharge voltage stored in bit line multiplexer 560. This voltage is used as a reference voltage by comparator 570. Comparator 570 will compare word 95 and word 96. One of ordinary skill in the art will understand that word 95 contains one or more bits, and word 96 contains one or more bits. Comparator 570 includes a comparator circuit for each bit in word 95 and for each bit in word 96. That is, if word 95 and word 96 are each 8 bits, comparator 570 will include 8 comparator circuits, each of which will compare a bit from word 95 to a bit at the same position in word 96. Output line 590 contains the comparison result for each bit pair.

[0009] If a bit in word 95 is higher than the corresponding bit in word 96, it is interpreted as a "1", and output line 590 will contain a "1" in that position. If a bit in word 95 is equal to or lower than the corresponding bit in word 96, it is interpreted as a "0", and output line 590 will contain a "0" in that position.

[0010] Those of ordinary skill in the art will recognize that Figure 5 The prior art system includes two stages of multiplexers - address decoders 510 and 520 and bit line multiplexers 550 and 560. The ability to precharge the bit lines is directly affected by the number of multiplexer stages involved in the read operation.

[0011] Fig. 6AMore details are shown Figure 5 The sense amplifier 600 includes a first circuit coupled to a selected memory cell 640 (which may be a cell in the array 530), and a second circuit coupled to a dummy cell 650 (which may be a cell in the array 540). The first circuit includes a portion of an address MUX level 630 (which is a part of the address decoder 510), and the second circuit includes a portion of the address MUX level 630 (which is a part of the address decoder 520). The first circuit also includes a portion of a bit line MUX level 620 (which is a part of the bit line multiplexer 550), and the second circuit includes a portion of a dummy bit line MUX level 620 (which is a part of the bit line multiplexer 560). The first circuit also includes PMOS transistors 601, 602, and 607, and the second circuit also includes PMOS transistors 608, 609, and 614.

[0012] Nodes IOR and DUMIOR are coupled to the input of comparator 615. The output of comparator 615 is coupled to inverter 616. The output of inverter 616 is coupled to buffer 617, which outputs a signal DOUT indicating the value stored in selected cell 640. In this prior art design, PMOS transistors 601 and 608 are asymmetric.

[0013] Figure 6B Certain operational features of sense amplifier 600 are shown. Timing diagram 660 shows the behavior of PCHENB, DUMIOR, IOR, Pre_BL, and BL during a precharge operation, which typically occurs during a precharge cycle and precedes a read operation. It can be seen that delay T1 is undesirable and represents an unnecessary increase in precharge time.

[0014] Schematic 670 shows the case where the selected cell 640 stores a "1". Once a read operation begins, IOR is pulled toward ground, below the pre-charge value of DUMIOR. Schematic 680 shows the case where the selected cell 640 stores a "0". Once a read operation begins, IOR is pulled toward VDD, above the pre-charge value of DUMIOR.

[0015] As flash memory systems become more prevalent in a variety of computing and electronic devices, it becomes increasingly important to create designs that enable faster reads and operations and that can precharge the bit lines as quickly as possible. Summary of the invention

[0016] The present invention reduces the amount of time required for precharge operations, thereby creating a faster system for read operations. One embodiment includes an improved precharge circuit for precharging the bit lines of selected flash memory cells and dummy flash memory cells during a precharge cycle, resulting in faster read operations. Another embodiment eliminates a level of multiplexers used during read operations, which also reduces the amount of time required for precharge operations, thereby also achieving faster read operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a cross-sectional view of a prior art nonvolatile memory cell, to which the method of the present invention can be applied.

[0018] Figure 2 One embodiment of a pre-charge circuit is shown.

[0019] Figure 3 Shown with Figure 2 The precharge circuit is used together with the sense amplifier.

[0020] Figure 4 Shows Figure 2-3 Embodiments of the invention are characterized during precharge and read operations.

[0021] Figure 5 A prior art memory system is shown.

[0022] Fig. 6A A prior art sense amplifier is shown.

[0023] Figure 6B Shows Fig. 6A Characteristics of a prior art sense amplifier during a precharge operation.

[0024] Fig. 7A One embodiment of an improved sense amplifier is shown.

[0025] Figure 7B Shows Fig. 7A characteristics of the sense amplifier.

[0026] Figure 7C Shows Fig. 7A characteristics of the sense amplifier. DETAILED DESCRIPTION

[0027] exist Figure 2 and Figure 3 An embodiment is shown in FIG. Figure 2 , the circuit 200 includes a first subcircuit coupled to a selected memory cell 220, and a second subcircuit coupled to a dummy memory cell 230. Each of the selected memory cell 220 and the dummy memory cell 230 may be Figure 1Other types are also known in the prior art.

[0028] The first subcircuit includes PMOS transistors 202, 203 and 204 configured as shown and an NMOS transistor 205. The second subcircuit includes PMOS transistors 206, 207 and 208 configured as shown and an NMOS transistor 209. The first subcircuit and the second subcircuit are each coupled to the reference current generator 201 and to the PMOS transistor 210.

[0029] During the precharge cycle, ATD_B (address transition detect) is pulled low, turning on PMOS transistors 202, 206, and 210. SENB is pulled low, turning on PMOS transistors 203 and 207, which are coupled to VDD12. This causes nodes IOR and DUMIOR to be at the same voltage, which will be approximately VDD12, which is 1.2 volts in this example. YENB_B (column enable) is pulled high, turning on NMOS transistors 205 and 209 and turning off PMOS transistors 204 and 208, which causes nodes BL (bit line) and DUMBL (dummy bit line) to be pulled to ground.

[0030] During a read operation, ATD_B is pulled high, thereby turning off PMOS transistors 202, 206, and 210. At the moment when the read operation begins, nodes IOR and DUMIOR are still at voltage VDD12. During a read operation, YENB_B is pulled low, thereby turning on PMOS transistors 204 and 208 and turning off NMOS transistors 205 and 209. Bit line BL is coupled to the selected memory cell 220, and dummy bit line DUMBL is coupled to dummy memory cell 230. The selected memory cell 220 is also coupled to word line WL_TOP, and dummy memory cell 230 is coupled to word line WL_BOT. The voltage on bit line BL and dummy bit line DUMBL will be affected by the current drawn by the selected memory cell 220 and dummy memory cell 230. During read mode, BL and DUMBL will maintain the same potential as IO and DUMIOR, respectively.

[0031] refer to Figure 3 , shows a comparator and signal generation circuit 300. The first circuit 301 receives input ATD_B (address transition detector, which will be activated when a read address is received) and SAL (sense address line), and generates an output SAPCH (sense amplifier precharge signal), which is designed to ensure that the read data will not change before the next read cycle.

[0032] Nodes IOR and DUMIOR are connected to Figure 2308. IOR is coupled to PMOS transistors 302 and 304, inverter 303, and comparator 308, as shown. DUMIOR is coupled to PMOS transistors 305 and 307, inverter 306, and comparator 308, as shown. Comparator 308 is also coupled to NMOS transistor 309.

[0033] During the pre-charge cycle, SAPCH is pulled low, causing nodes VDO and VDO_N to be pulled up to VDD12, and SAL is pulled high, pulling the nodes in comparator 308 down to ground.

[0034] During a read operation, SAL is pulled low and SAPCH is pulled high, causing PMOS transistors 304 and 307 to turn on, while PMOS transistors 302 and 305 are turned off. IOR and DUMIOR will enter a "race" condition in which each will draw current from nodes VDO_N and VDO, respectively. When one of nodes VDO_N and VDO drops below a certain threshold, comparator 308 will cause the other node to be pulled to VDD12, which also causes that node to be pulled to ground. For example, if VDO_N drops below the threshold first, VDO will be pulled up to VDD12 through the PMOS transistor. VDO will then cause VDO_N to be pulled to ground through the NMOS transistor. The end result is that VDO_N and VDO will be at opposite values. One state will reflect that a "1" is stored in the selected memory cell 220, while the other state will reflect that a "0" is stored in the selected memory cell 220.

[0035] Figure 4 A timing diagram 400 showing an exemplary sequence from a precharge cycle to a read mode is shown. Figure 3 The signals shown in, i.e., YENB_B, WL_TOP, ATD_B, SAL, SAPCH, BL / DMBL, IOR / DUMIOR, VDO_N / VDO and SENB_B.

[0036] Fig. 7A An embodiment of an improved sense amplifier is shown, which shortens the Fig. 6A The delay time existing in the prior art sense amplifier 600.

[0037] Sense amplifier 700 includes components similar to sense amplifier 600, and for the sake of efficiency, common components are not described again. Sense amplifier includes PMOS transistors 701, 702, 703 and 704. PMOS transistors 701 and 703 are completely symmetrical. Nodes IOR_T and IOR_B are input to comparator 705. The output of the comparator is fed into inverter 706 and inverter 707. The output of inverter 706 is input into multiplexer 709. The output of inverter 707 is input into inverter 708. The output of inverter 708 is input into multiplexer 709. Multiplexer 709 is controlled by signal SELTOP. The output of multiplexer 709 is fed into buffer 710, which outputs DOUT, which represents the value stored in selected top cell 711 or selected bottom cell 712.

[0038] It is noteworthy that in this embodiment, no bit line / dummy bit line multiplexer level is required. By eliminating the multiplexing level, this embodiment is able to reduce the amount of latency for the precharge operation. Additionally, there are no "dummy cells" in this embodiment. Both cells 711 and 712 can be used to store data. During a read operation of one of these cells, the other cell is disconnected, and the charge stored on the bit line of the disconnected cell is used as a comparison point relative to the selected memory cell that is still connected.

[0039] Figure 7B Some features of the sense amplifier 700 are shown. When it is desired to read a value in the selected top cell 711, WL_TOP is asserted and WL_BOT is deasserted. TOP_SENB is low and BOT_SENDB is high. Therefore, node IOR_B is initially at the voltage level established by the precharge operation. If the selected top cell 711 stores a "1", IOR_T will be pulled down below the value of IOR_B. If the selected top cell 711 stores a "0", IOR_T will be pulled up above the value of IOR_B.

[0040] When it is desired to read a value in the selected bottom cell 712, WL_TOP is asserted and WL_BOT is deasserted. TOP_SENB is high and BOT_SENDB is low. Therefore, node IOR_T is initially at the voltage level established by the precharge operation. If the selected bottom cell 712 stores a "1", IOR_B will be pulled down below the value of IOR_T. If the selected top cell 712 stores a "0", IOR_B will be pulled up above the value of IOR_T.

[0041] Figure 7CAdditional performance characteristics of the sense amplifier 700 are shown. Timing diagram 760 shows the behavior of Pre-BL and BL during a precharge operation. The reader will recall that Figure 6B In the example above, there is a delay of T1 before the precharge starts on the bit line BL. Here, there is no such delay and the precharge operation occurs T1 faster. This is a Fig. 6A and Figure 6B Substantial improvements in design.

[0042] References to the present invention herein are not intended to limit the scope of any claim or claim clause, but are merely references to one or more features that may be covered by one or more claims. The examples of materials, processes and numerical values ​​described above are exemplary only and should not be considered to limit the claims. It should be noted that, as used herein, the terms "above..." and "on..." both include "directly on..." (no intermediate material, element or space is provided between) and "indirectly on..." (intermediate material, element or space is provided between). Similarly, the term "adjacent" includes "directly adjacent" (no intermediate material, element or space is provided between the two) and "indirectly adjacent" (intermediate material, element or space is provided between the two). For example, forming an element "above a substrate" may include forming the element directly on the substrate without an intermediate material / element between the two, and indirectly forming the element on the substrate with one or more intermediate materials / elements between the two.

Claims

1. A sensing circuit for reading a selected flash memory cell in a first array of flash memory cells, comprising: a first circuit coupled to a first bit line in the first array, the first circuit comprising a first NMOS transistor (205) for pulling the first bit line to ground in response to a first control signal (YENB_B), a first PMOS transistor (203) and a second PMOS transistor (202) for precharging a first node to a predetermined voltage in response to a second control signal (SENB) and a third control signal (ATD_B), respectively, during a precharge cycle, and a third PMOS transistor (204) for isolating the first bit line from the first node during the precharge cycle; a second circuit coupled to a second bit line in a second array of flash memory cells, the second circuit comprising a second NMOS transistor (209) for pulling the second bit line to ground in response to the first control signal (YENB_B), a fourth PMOS transistor (207) and a fifth PMOS transistor (206) for precharging a second node to the predetermined voltage in response to the second control signal (SENB) and the third control signal (ATD_B), respectively, during the precharge cycle, and a sixth PMOS transistor (208) for isolating the second bit line from the second node during the precharge cycle; a transistor coupled between the first node and the second node to ensure that the first node and the second node are precharged to the predetermined voltage during the precharge cycle; as well as A comparator includes a first input coupled to the first node in the first circuit and a second input coupled to the second node in the second circuit, an output of the comparator indicating a value stored in the selected flash memory cell.

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