Frequency divider and control method thereof, clock signal generating circuit and electronic device

Abstract

The present application provides a frequency divider and its control method, a clock signal generating circuit and an electronic device. The frequency divider includes: a first signal generating unit generates a first signal sequence including at least one first signal, each group of clock signals in the clock signal sequence includes 2n+1 clock signals; the transition edge of the first signal corresponds to the transition edge of the n+2th clock signal in a group of clock signals; an inverting unit; a second signal generating unit generates a second signal sequence including at least one second signal, in which the transition edge corresponds to the transition edge of the first inverted clock signal in a group of inverted clock signals, and the inverted transition edge corresponds to the transition edge of the n+1th inverted clock signal; a combinational logic unit performs combinational logic operations on the first signal sequence and the second signal sequence; and a two-frequency division unit is used to generate a 2n+1 frequency division signal sequence with equal duty cycle. The present application can reduce the probability of competition risk and reduce the probability of generating signal glitches.

Description

Technical Field

[0001] The present application relates to the technical field of frequency division circuits, and in particular to a frequency divider and a control method thereof, a clock signal generating circuit and an electronic device. Background Art

[0002] In some circuit designs, a divided frequency signal with an odd-numbered division of the clock frequency and an equal duty cycle is required.

[0003] Currently, the commonly used odd-number dividers with equal duty cycle usually use two circuit branches to detect the rising edge and falling edge of the clock signal respectively, trigger to obtain two intermediate variables, and then obtain the divided frequency signal through a combinational logic circuit.

[0004] However, in actual circuits, there is a certain delay when the signal passes through the wiring of each logic unit of the circuit branch, which makes the frequency division process prone to competition and risk, easily generates burrs, and easily makes the output frequency division signal unpredictable. Summary of the invention

[0005] In view of the shortcomings of the existing methods, the present application proposes a frequency divider and its control method, a clock signal generating circuit and an electronic device to solve the technical problem that the existing odd-numbered frequency divider with equal duty cycle is prone to generate burr signals or competition hazards during the frequency division process.

[0006] In a first aspect, an embodiment of the present application provides a frequency divider, comprising: a first signal generating unit, configured to generate and output a first signal sequence including at least one first signal according to a clock signal sequence; each group of clock signals in the clock signal sequence includes 2n+1 clock signals, where n is a positive integer; a transition edge of the first signal corresponds to a transition edge of an n+2th clock signal in a group of the clock signals; an inverting unit; a second signal generating unit, an input end of which is electrically connected to an output end of the inverting unit, configured to generate a second signal sequence including at least one second signal according to an inverted clock signal sequence having a phase opposite to that of the clock signal sequence. The first signal sequence and the second signal sequence are connected in series and output; in the second signal, the transition edge corresponds to the transition edge of the first inverted clock signal in a group of inverted clock signals, and the inverted transition edge corresponds to the transition edge of the n+1th inverted clock signal; a combinational logic unit, the two input ends of which are electrically connected to the output ends of the first signal generating unit and the second signal generating unit respectively, and a combinational logic operation is performed on the first signal sequence and the second signal sequence to obtain a third signal sequence including at least two third signals and output it; a two-frequency division unit, the input end of which is electrically connected to the output end of the combinational logic unit, and is used to generate a 2n+1 frequency division signal sequence with an equal duty cycle according to the third signal sequence.

[0007] Optionally, the first signal generating unit includes a first counter, and the clock end of the first counter serves as the input end of the first signal generating unit, and is used to receive the clock signal sequence, and the first counter is used to count the clock signals in the clock signal sequence, and generate and output at least one group of the clock signals; the second signal generating unit includes a second counter, and the clock end of the second counter serves as the input end of the second signal generating unit, and is used to receive the inverted clock signal sequence, and the second counter is used to count the inverted clock signals in the inverted clock signal sequence, and generate and output at least one group of the inverted clock signals.

[0008] Optionally, the first signal generating unit includes a first intermediate signal generating unit, which maps a first subset and a second subset of the count values ​​of the first counter to a first potential and a second potential of the first signal, respectively; and the second signal generating unit includes a second intermediate signal generating unit, which maps a first subset and a second subset of the count values ​​of the second counter to a first potential and a second potential of the second signal, respectively.

[0009] Optionally, the first intermediate signal generating unit includes a first comparator, wherein one input end of the first comparator is electrically connected to the output end of the first counter, and the other input end is used to receive a first reference signal sequence, and the first comparator is used to generate the first signal sequence according to at least one group of the clock signals and the first reference signal sequence; in each of the first signals of the first signal sequence, the part corresponding to the first n+1 clock signals in a group of the clock signals is the second potential, and the part corresponding to the last n clock signals is the first potential; the second intermediate signal generating unit includes a second comparator, wherein one input end of the second comparator is electrically connected to the output end of the second counter, and the other input end is used to receive a second reference signal sequence, and the second comparator is used to generate the second signal sequence according to at least one group of the inverted clock signals and the second reference signal sequence; a part of the second signal corresponds to a transition edge from the middle of the first inverted clock signal to the middle of the n+1th inverted clock signal of a group of the inverted clock signals, and the part is the first potential, and the other part of the second signal is the second potential.

[0010] Optionally, the first intermediate signal generating unit includes a first state conversion unit, which converts the potential state of the first signal when the count value of the first counter is equal to a first predetermined value and a second predetermined value, respectively, and maintains the potential state of the first signal at other count values ​​of the first counter; and the second signal generating unit includes a second state conversion unit, which converts the potential state of the second signal when the count value of the second counter is equal to a third predetermined value and a fourth predetermined value, respectively, and maintains the potential state of the second signal at other count values ​​of the second counter.

[0011] Optionally, the combinational logic circuit performs an OR-NOT logic operation on the first signal sequence and the second signal sequence to generate the third signal sequence; or the combinational logic circuit performs an AND logic operation on the first signal sequence and the second signal sequence to generate the third signal sequence.

[0012] Optionally, the combinational logic unit includes a NOR gate, and the two input ends of the NOR gate serve as the two input ends of the combinational logic unit and are electrically connected to the output ends of the first and second signal generating units. In two adjacent third signals of the third signal sequence, the parts corresponding to the first half of the first clock signal and the second half of the n+1th clock signal in a group of the clock signals are both the first potential, and the other parts of the two adjacent third signals are the second potential.

[0013] Optionally, the binary frequency division unit includes a trigger and an inverter; the clock end of the trigger, as the input end of the binary frequency division unit, is electrically connected to the output end of the combinational logic unit for receiving the third signal sequence; the positive and negative poles of the inverter are electrically connected to the output and input ends of the trigger; the trigger is used to output a first potential of a 2n+1 frequency division signal in a 2n+1 frequency division signal sequence with equal duty cycle through the output end when receiving a transition edge of one of two adjacent third signals through the clock end, and receive a second potential inverted by the inverter through the input end; and output the second potential of the 2n+1 frequency division signal when receiving a transition edge of another adjacent third signal.

[0014] Optionally, the first counter and / or the second counter is a Gray code counter.

[0015] Optionally, the first and second counters include: a first transcoder, used to convert Gray code into binary code and output it; an adder, whose output end is electrically connected to the input end, an enable end is electrically connected to the output end of the first transcoder, a clock end as a part of the input end of the first counter is used to receive the clock signal sequence, and a reset end is used to receive a reset signal; the adder is used to accumulate and output the binary code, and reset the accumulated binary code according to the reset signal received once every 2n+1 accumulations; a second transcoder, whose input end is electrically connected to the output end of the adder, and whose output end is electrically connected to the input end of the first transcoder, and is used to convert the accumulated binary code into the accumulated Gray code.

[0016] Optionally, the first and second counters further include: a register, an input end of which is electrically connected to an output end of the second transcoder, a clock end as a part of the input end of the first counter for receiving the clock signal sequence, and a reset end for receiving the reset signal; the register is used to store and output the accumulated Gray code.

[0017] In a second aspect, an embodiment of the present application provides a clock signal generating circuit, comprising: a frequency divider as described in any one of the first aspects above; the frequency divider is used to output a 2n+1 divided signal sequence with equal duty cycle as a designed clock signal sequence.

[0018] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a clock signal generating circuit as described in the second aspect above.

[0019] In a fourth aspect, an embodiment of the present application provides a control method for a frequency divider, comprising: generating a first signal sequence including at least one first signal according to a clock signal sequence; each group of clock signals in the clock signal sequence includes 2n+1 clock signals, where n is a positive integer; a transition edge of the first signal corresponds to a transition edge of an n+2th clock signal in a group of the clock signals; inverting the clock signal sequence into an inverted clock signal sequence; generating a second signal sequence including at least one second signal according to the inverted clock signal sequence; in the second signal, a transition edge corresponds to a transition edge of the first inverted clock signal in a group of inverted clock signals, and an inverted transition edge corresponds to a transition edge of the n+1th inverted clock signal; performing a combinational logic operation on the first signal sequence and the second signal sequence to obtain a third signal sequence including at least two third signals; and generating a 2n+1 frequency division signal sequence with equal duty cycle according to the third signal sequence.

[0020] In a fifth aspect, an embodiment of the present application provides a machine-readable storage medium storing executable instructions, which, when executed, cause one or more processing units to execute the method described in the fourth aspect above.

[0021] The beneficial technical effects brought about by the technical solution provided in the embodiment of the present application include: according to the clock signal sequence, a first signal sequence including at least one first signal is generated, each first signal corresponds to a group of clock signals, that is, the first signal corresponds to 2n+1 clock signals, which is equivalent to converting a clock signal with 2n+1 transition edges into a first signal with only 1 transition edge, so that the number of transition edges of the first signal is greatly reduced; similarly, the number of transition edges of the second signal is greatly reduced, and the transition edges of the first signal and the transition edges of the second signal are staggered in time, that is, the first signal and the second signal will not have a potential reversal at the same time; therefore, when the first signal and the second signal are combined with logical operations, the probability of generating competition hazards can be reduced, and the phenomenon of signal glitches can be reduced, which is beneficial to reduce the probability of competition hazards and the probability of generating signal glitches on the basis of realizing the generation of a 2n+1 frequency-divided signal sequence with equal duty cycle, and can improve the reliability of the signal.

[0022] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0024] Figure 1 A schematic diagram of the structure of a frequency divider provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of timing waveforms of various signal sequences of a frequency divider provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of the structure of a first signal generating unit provided in an embodiment of the present application;

[0027] Figure 4 A schematic diagram of the structure of a first counter provided in an embodiment of the present application;

[0028] Figure 5 A schematic flow chart of a method for controlling a frequency divider provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of timing waveforms of various signal sequences of a divide-by-five frequency divider with equal duty cycle provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of timing waveforms of each signal sequence of a three-frequency divider with equal duty cycle provided in an embodiment of the present application;

[0031] Figure 8 A block diagram of a frequency divider according to another embodiment of the present application;

[0032] Figures 9A-9C Waveform diagram related to the operation of the equal duty cycle five-divider provided in the embodiment of the present application. DETAILED DESCRIPTION

[0033] The present application is described in detail below, and examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. In addition, if the detailed description of the known technology is unnecessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0034] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0035] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0036] First, several terms involved in this application are introduced and explained:

[0037] Frequency division refers to reducing the frequency of a single frequency signal to one-M of the original frequency, which is called M-frequency division. If M is an even number, it is even-number frequency division, and if M is an odd number, it is odd-number frequency division. Through frequency division, a signal of the required frequency can be obtained.

[0038] Frequency divider, the circuit that realizes frequency division is called frequency divider, and frequency dividers include even frequency dividers and odd frequency dividers.

[0039] Duty cycle refers to the proportion of power-on time to the total time in a signal cycle or pulse cycle.

[0040] Equal duty cycle means that the proportion of the power-on time to the total time of the corresponding signal period or pulse cycle is 50%.

[0041] Competition and hazard usually occur in combinational logic circuits in digital circuits. In combinational logic circuits, the same signal arrives at a certain meeting point in the circuit at different times after being transmitted through different paths. This phenomenon is called logic competition, and the phenomenon of generating interference pulses is called hazard. Interference pulses are also called glitch signals or signal glitches, or glitches for short.

[0042] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0043] The present application embodiment provides a frequency divider. The structure diagram of the frequency divider is as follows: Figure 1 As shown, it includes: a first signal generating unit 10, an inverting unit 20, a second signal generating unit 30, a combinational logic unit 40 and a two-frequency dividing unit 50.

[0044] The first signal generating unit 10 is used to generate and output a first signal sequence including at least one first signal according to a clock signal sequence clk; each group of clock signals of the clock signal sequence clk includes 2n+1 clock signals, where n is a positive integer; a transition edge of the first signal corresponds to a transition edge of the n+2th clock signal of a group of clock signals.

[0045] The input end of the second signal generating unit 30 is electrically connected to the output end of the inverting unit 20, and the second signal generating unit 30 is used to generate and output a second signal sequence including at least one second signal according to an inverted clock signal sequence with a phase opposite to that of the clock signal sequence clk; in the second signal, the transition edge corresponds to the transition edge of the first inverted clock signal in a group of inverted clock signals, and the inverted transition edge corresponds to the transition edge of the n+1th inverted clock signal.

[0046] The two input ends of the combinational logic unit 40 are electrically connected to the output end of the first signal generating unit 10 and the output end of the second signal generating unit 30. The combinational logic unit 40 is used to perform a combinational logic operation on the first signal sequence and the second signal sequence to obtain a third signal sequence including at least two third signals and output it.

[0047] The input end of the frequency division unit 50 is electrically connected to the output end of the combinational logic unit 40 . The frequency division unit 50 is used to generate a 2n+1 frequency division signal sequence with an equal duty cycle according to the third signal sequence.

[0048] In the embodiment of the present application, n is a positive integer > 1, and the 2n+1 frequency division signal sequence with equal duty cycle includes 2n+1 frequency division signals with equal duty cycle, which are actually any odd number (greater than 1) of frequency division signals with equal duty cycle.

[0049] The frequency divider provided in the embodiment of the present application can be a frequency divider with three divisions of equal duty cycle, a frequency divider with five divisions of equal duty cycle, a frequency divider with seven divisions of equal duty cycle, or a frequency divider with nine divisions of equal duty cycle, or any other odd-numbered frequency divider (greater than 1).

[0050] In an embodiment of the present application, a first signal sequence including at least one first signal is generated according to a clock signal sequence, and each first signal corresponds to a group of clock signals, that is, the first signal corresponds to 2n+1 clock signals, which is equivalent to converting a clock signal with 2n+1 transition edges into a first signal with only 1 transition edge, so that the number of transition edges of the first signal is greatly reduced; similarly, the number of transition edges of the second signal is greatly reduced, and the transition edges of the first signal and the transition edges of the second signal are staggered in time, that is, the first signal and the second signal will not have a potential flip at the same time; therefore, when the first signal in the first signal sequence and the second signal in the second signal sequence are subjected to an OR / NOT operation, the probability of generating a contention risk can be reduced, and the phenomenon of signal glitches can be reduced, which is beneficial to reduce the probability of contention risk and the probability of generating signal glitches on the basis of realizing the generation of a 2n+1 frequency-divided signal sequence with equal duty cycle, and can improve the reliability of the signal.

[0051] Optionally, a transition edge of a third signal corresponds to a transition edge of the first clock signal in a group of clock signals, and a transition edge of another immediately succeeding third signal corresponds to an inverted transition edge of the (n+1)th clock signal.

[0052] Optionally, the input end of the inverting unit 20 is used to receive a clock signal sequence.

[0053] Optionally, the transition edge is a rising edge, the inverted transition edge is a falling edge, the first potential is a high potential, and the second potential is a low potential; or, the transition edge is a falling edge, the inverted transition edge is a rising edge, the first potential is a low potential, and the second potential is a high potential.

[0054] Optionally, the clock signal and the inverted clock signal in the embodiment of the present application have equal duty cycles.

[0055] Combine the following Figure 2 And Figure 2 Taking as an example, the working principle of the frequency divider in the embodiment of the present application is introduced.

[0056] Figure 2Where clk represents a clock signal sequence, clk_p represents a first signal sequence, clk_inv represents an inverted clock signal sequence, clk_inv_p represents a second signal sequence, ~(clk_p|clk_inv_p) represents a third signal sequence, clk_div_2n+1 represents a 2n+1 frequency-divided signal sequence with equal duty cycle, and n is a positive integer. The left part of the first vertical dotted line from the left is the signal timing waveform of the above signal sequences in the preparatory stage T0, and the right part is the signal timing waveform of the above signal sequences in the working stage. Figure 2 exemplarily shows the signal timing waveforms of each signal sequence in the first working stage T1.

[0057] like Figure 2 In the example shown, the first working stage T1 can represent each working stage, the clock signal sequence clk in each working stage is a group of clock signals (including 2n+1 clock signals), the inverted clock signal sequence clk_inv in each working stage is a group of reverse clock signals (including 2n+1 inverted clock signals), the first signal sequence clk_p in each working stage is a first signal, the second signal sequence clk_inv_p in each working stage is a second signal, the third signal sequence ~(clk_p|clk_inv_p) in each working stage is two third signals, and the 2n+1 frequency division signal sequence clk_div_2n+1 with equal duty cycle is a 2n+1 frequency division signal with equal duty cycle in each working stage.

[0058] Figure 2 In the example, the transition edge is a rising edge, the inverted transition edge is a falling edge, the first potential is a high potential, and the second potential is a low potential.

[0059] Figure 2 In the first working phase T1, the clock signal sequence clk is a group of clock signals, including 2n+1 clock signals with equal duty cycles, the clock signals numbered 1, 2, 3 to n+1 represent the first n+1 clock signals of a group of clock signals, the clock signals numbered n+2 to 2n, and 0 represent the last n clock signals of a group of clock signals, and each clock signal is at a high potential for the first half of the time and at a low potential for the second half of the time. The first signal generating unit 10 generates and outputs a first signal according to a group of clock signals, and the rising edge of the first signal is aligned with the rising edge of the n+2th clock signal.

[0060] The inverting unit 20 will Figure 2 A set of clock signals inverted as Figure 2 A group of inverted clock signals of the inverted clock signal sequence clk_inv. Figure 2As shown, a group of inverted clock signals includes 2n+1 inverted clock signals with equal duty cycles, the inverted clock signals numbered 1, 2, 3 to n+1 represent the first n+1 inverted clock signals of a group of inverted clock signals, the inverted clock signals numbered n+2 to 2n, and 0 represent the last n inverted clock signals of a group of inverted clock signals, and each inverted clock signal is at a low potential in the first half of the time and at a high potential in the second half of the time.

[0061] The second signal generating unit 30 is based on Figure 2 A set of inverted clock signals in Figure 2 A second signal of the second signal sequence clk_inv_p in the clock signal generator. The rising edge of the second signal is aligned with the rising edge of the first inverted clock signal, that is, aligned with the falling edge of the first clock signal; the falling edge of the second signal is aligned with the rising edge of the n+1th inverted clock signal, that is, aligned with the falling edge of the n+1th clock signal.

[0062] Combinational logic unit 40 pairs Figure 2 A first signal of the first signal sequence clk_p and a second signal of the second signal sequence clk_inv_p are performed in an OR operation to obtain Figure 2 The two third signals of the third signal sequence ~(clk_p|clk_inv_p); the rising edge of one third signal is aligned with the rising edge of the first clock signal, and the rising edge of the other third signal is aligned with the falling edge of the n+1th clock signal. Due to the falling edge of the n+1th clock signal, the total duration of the group of clock signals to which it belongs is divided into two equal parts, so the periods of the two third signals are equal.

[0063] The two-way frequency division unit 50 is based on Figure 2 The two third signals of the third signal sequence ~(clk_p|clk_inv_p) in the third signal sequence generate Figure 2 A 2n+1 frequency-divided signal in the 2n+1 frequency-divided signal sequence clk_div_2n+1, the rising edge of the 2n+1 frequency-divided signal is aligned with the rising edge of a third signal (i.e., the rising edge of the first clock signal), and the falling edge of the 2n+1 frequency-divided signal is aligned with the rising edge of another immediately succeeding third signal (i.e., the falling edge of the n+1th clock signal). It can be seen that the 2n+1 frequency-divided signal has an equal duty cycle.

[0064] Alternatively, if Figure 3 As shown, the first signal generating unit 10 of the frequency divider of the embodiment of the present application includes: a first counter 101 and a first comparator 102 (as an example of a "first intermediate signal generating unit"). The first intermediate signal generating unit maps the first subset and the second subset of the count value of the first counter 101 to the first potential and the second potential of the first signal respectively.

[0065] The clock terminal CLK of the first counter 101 serves as an input terminal of the first signal generating unit 10 and is used to receive a clock signal sequence. The first counter 101 is used to count clock signals in the clock signal sequence and generate and output at least one group of clock signals.

[0066] The first comparator 102 has one input terminal B electrically connected to the output terminal Q of the first counter 101, and the other input terminal A is used to receive the first reference signal sequence 1A. The first comparator 102 is used to generate a first signal sequence according to at least one group of clock signals and the first reference signal sequence 1A; in each first signal of the first signal sequence, the part corresponding to the first n+1 clock signals in a group of clock signals is the second potential, and the part corresponding to the last n clock signals is the first potential.

[0067] In the first signal generating unit 10 of the embodiment of the present application, the first counter 101 can count the clock signal from the preparation stage to the working stage, combined with Figure 2 The first counter 101 counts the rising edge of each clock signal, and resets the count value according to rst_2n+1 received by the reset terminal every time 2n+1 (from No. 0 in the preparatory stage to No. 2n in the working stage, or No. 0 in the previous working stage to No. 2n in the next working stage) clock signals are counted, and the counting starts again after the reset. Optionally, each group of clock signals includes 2n+1 clock signals, and the 2n+1 clock signals include the last 2n clock signals of the current counting cycle and the first clock signal of the next counting cycle, for example Figure 2 The clock signals numbered 1 to 2n in clk and the clock signal numbered 0 after 2n.

[0068] By properly designing the first reference signal sequence 1A, the first comparator 102 compares each set of count values ​​with a set of first reference signals of the first reference signal sequence 1A, and the following can be obtained: Figure 2 Specifically, when the count value output by the first counter 101 is 1 to n+1, the first comparator 102 outputs a high potential, and when the count value output by the first counter 101 is n+2 to 0, the first comparator 102 outputs a low potential; so that the portion of the first signal corresponding to the 1st to n+1th clock signals is a low potential, and the portion of the first signal corresponding to the n+2th to 2n+1th (i.e. Figure 2 The part of the clock signal (the one labeled 0 in the T1 phase in clk) corresponding to the part is at a high potential.

[0069] The first signal generating unit 10 of the embodiment of the present application has a relatively simple structure and low cost. By reasonably setting the first reference signal sequence, the required first working signal can be obtained, which can be flexibly applied to a wide range of applications.

[0070] Alternatively, if Figure 3 As shown, the inverting unit 20 in the embodiment of the present application may include an inverter.

[0071] Alternatively, if Figure 3 As shown, the second signal generating unit 30 of the embodiment of the present application includes: a second counter 301 and a second comparator 302 (as an example of a “second intermediate signal generating unit”. The second intermediate signal generating unit maps a first subset and a second subset of the count values ​​of the second counter 301 to a first potential and a second potential of the second signal, respectively.

[0072] The clock terminal CLK of the second counter 301 serves as the input terminal of the second signal generating unit 30 and is used to receive the inverted clock signal sequence. The second counter 301 is used to count the inverted clock signals in the inverted clock signal sequence and generate and output at least one group of inverted clock signals.

[0073] The second comparator 302 has one input terminal B electrically connected to the output terminal Q of the second counter 301, and the other input terminal A is used to receive the second reference signal sequence 2A. The second comparator 302 is used to generate a second signal sequence according to at least one group of inverted clock signals and the second reference signal sequence 2A; a part of the second signal corresponds to a transition edge from the middle of the 1st inverted clock signal to the middle of the n+1th inverted clock signal of a group of inverted clock signals, a part of which is the first potential, and the other part of the second signal is the second potential.

[0074] Each second signal corresponds to a set of inverted clock signals in the sequence of inverted clock signals.

[0075] In the second signal generating unit 30 of the embodiment of the present application, the second counter 301 can count the inverted clock signal from the preparation stage to the working stage. Figure 2 , when counting 2n+1 (from No. 0 in the preparation stage to No. 2n in the working stage, or No. 0 in the previous working stage to No. 2n in the next working stage) rising edges of the inverted clock signal, the count value is reset according to rst_2n+1 received by the reset terminal, and the counting starts again after the reset. Optionally, each group of inverted clock signals includes 2n+1 inverted clock signals, and the 2n+1 inverted clock signals include the last 2n inverted clock signals of the current counting cycle and the first inverted clock signal of the next counting cycle, for example Figure 2 The inverted clock signals numbered 1 to 2n in clk_p and the inverted clock signal numbered 0 after 2n.

[0076] By properly designing the second reference signal sequence 2A, the second comparator 302 compares each group of inverted clock signals with a group of second reference signals of the second reference signal sequence 2A, and the following can be obtained: Figure 2 A second signal as shown. Specifically, the second comparator 302 outputs a high potential from the preparatory stage. When the count value output by the second counter 301 is 1 to n, the second comparator 302 outputs a high potential. When the count value output by the second counter 301 is n+1 to 0, the second comparator 302 outputs a low potential. The portion of the second signal corresponding to the rising edge of the 1st to n+1th inverted clock signals is a high potential, and the other portion of the second signal is a low level. The other portion of the second signal includes the first half of the 1st inverted clock signal, the second half of the n+1th inverted clock signal, and the n+2th to 2n+1th (i.e. Figure 2 The part of the clock signal (the one labeled 0 in the T1 phase in clk_inv) corresponding to the part is at a high potential.

[0077] The second signal generating unit 30 of the embodiment of the present application is relatively simple in structure and low in cost. By reasonably setting the second reference signal sequence, the required second working signal can be obtained by comparison, and can be flexibly applied to a wide range of applications.

[0078] Alternatively, if Figure 3 As shown, the combinational logic unit 40 of the frequency divider of the embodiment of the present application includes a NOR gate.

[0079] The two input terminals of the NOR gate are used as the two input terminals of the combinational logic unit 40 and are electrically connected to the output terminals of the first signal generating unit 10 and the second signal generating unit 30. In two adjacent third signals of the third signal sequence, the parts corresponding to the first half of the first clock signal and the second half of the n+1th clock signal in a group of clock signals are both at the first potential, and the other parts of the two adjacent third signals are at the second potential.

[0080] For example, Figure 2 As shown, in two adjacent third signals of the third signal sequence ~(clk_p|clk_inv_p), the first part of the previous third signal is a high potential, the first part corresponds to the first half of the first clock signal (i.e., the high potential), and the other parts of the previous third signal located after the first part are all low potentials; the first part of the next third signal is a high potential, the first part corresponds to the second half of the (n+1)th clock signal (i.e., the low potential part), and the other parts of the next third signal located after the first part are all low potentials.

[0081] In the embodiment of the present application, the function of the combinational logic unit 40 can be realized by using a simple NOR gate, which is easy to implement and helps to control the cost.

[0082] Alternatively, if Figure 3 As shown, the divide-by-two unit 50 of the frequency divider of the embodiment of the present application includes a trigger 501 and an inverter 502 .

[0083] The clock terminal CLK of the trigger 501, as an input terminal of the two-frequency division unit, is electrically connected to the output terminal of the combinational logic unit 40 for receiving the third signal sequence.

[0084] The positive electrode of the inverter 502 is electrically connected to the output terminal Q of the trigger 501, and the negative electrode of the inverter 502 is electrically connected to the input terminal D of the trigger 501;

[0085] The trigger 501 is used to output the first potential of a 2n+1 frequency-divided signal in a 2n+1 frequency-divided signal sequence with equal duty cycle through the output terminal when the transition edge of one of two adjacent third signals is received through the clock terminal CLK, and receive the second potential inverted by the inverter through the input terminal; and output the second potential of the 2n+1 frequency-divided signal when the transition edge of another immediately subsequent third signal is received.

[0086] Optionally, the trigger 501 may be an edge-change trigger, such as a D trigger, a JK trigger, etc.

[0087] As an example, combining Figure 2 and Figure 3 , the third signal sequence ~(clk_p|clk_inv_p) includes two adjacent third signals, and the trigger 501 is a rising edge trigger. In the initial state or in the preparatory stage, the trigger 501 outputs a low potential; when entering the working stage, when the trigger 501 receives the rising edge of the previous third signal through its CLK terminal, it outputs a high potential through its output terminal Q, and the high potential is inverted by the inverter 502 to a low potential and transmitted to the input terminal D of the trigger 501. However, at this time, since the trigger 501 has not received the rising edge of the subsequent third signal, the output potential remains unchanged and is still a high potential; when the trigger 501 receives the rising edge of the next third signal, the low potential received through the input terminal D is output through the output terminal Q.

[0088] In addition, the reset terminal of the trigger 501 is used to receive the reset signal rst_2n+1, and the trigger 501 is used to reset the output value (or potential) according to the rst_2n+1 received by the reset terminal.

[0089] Alternatively, if Figure 3 As shown, the first counter 101 of the frequency divider in the embodiment of the present application is a Gray code counter.

[0090] From the preparation stage to the working stage, the first counter 101 needs to count from 0, which is equivalent to a decimal number, to 4, reset to 0, and then start counting again. The first counter 101 is a Gray code counter, and the output count value is a Gray code. During the counting process, only one signal jumps between each count value; taking a five-frequency divider as an example, the jump sequence of the count value output by the first counter 101 is 000-001-011-010-110. During the counting process of the Gray code counter, when any adjacent count values ​​jump, only one signal changes, which eliminates the conditions for the occurrence of competition hazards, can avoid the generation of burr-type pulse signals, and is conducive to improving the stability of the output signal of the entire divider.

[0091] Alternatively, if Figure 3 As shown, the second counter 301 of the frequency divider in the embodiment of the present application is a Gray code counter.

[0092] Alternatively, if Figure 4 As shown, in the frequency divider of the embodiment of the present application, the first counter 101 as a Gray code counter includes: a first transcoder 1011 , an adder 1012 and a second transcoder 1013 .

[0093] The first transcoder 1011 is used to convert Gray code gary into binary code bin and output it.

[0094] The adder 1012 has an output terminal Q electrically connected to an input terminal D, an enable terminal EN electrically connected to an output terminal of the first transcoder 1011, a clock terminal CLK as a part of the input terminal of the first counter 101 for receiving a clock signal sequence, and a reset terminal for receiving a reset signal rst_2n+1; the adder 1012 is used to accumulate and output the binary code, and reset the accumulated binary code according to the reset signal received once every 2n+1 accumulations.

[0095] The second transcoder 1013 has an input terminal electrically connected to the output terminal Q of the adder 1012 and an output terminal electrically connected to the input terminal of the first transcoder 1011 , and is used to convert the accumulated binary code into the accumulated Gray code.

[0096] Alternatively, if Figure 4 As shown, bin_dout represents the binary code output by the first transcoder 1011 , bin_cnt represents the accumulated binary code output by the adder 1012 , and gray_temp represents the accumulated Gray code output by the second transcoder 1013 .

[0097] Alternatively, if Figure 4 As shown, the first counter 101 of the frequency divider in the embodiment of the present application further includes: a register 1014 .

[0098] The register 1014, the input terminal D is electrically connected to the output terminal of the second transcoder 1013, the clock terminal CLK is used as a part of the input terminal of the first counter 101 for receiving the clock signal sequence, and the reset terminal is used to receive the reset signal rst_2n+1; the register 1014 is used to store and output the Gray code accumulated by the second transcoder 1013. The buffering of the register is conducive to eliminating the competition risk of the signal and the signal burr, thereby improving the stability of the signal.

[0099] Alternatively, if Figure 4 As shown, gray_out represents the Gray code output by the register 1014.

[0100] Optionally, the structure and working principle of the second counter 301 of the frequency divider in the embodiment of the present application may be the same as or of the same type as the structure and working principle of the first counter 101, and will not be described in detail herein.

[0101] Based on the same inventive concept, the present application embodiment provides a method for controlling a frequency divider, and the flow chart of the method is as follows: Figure 5 As shown, the following steps are included:

[0102] S101: Generate a first signal sequence including at least one first signal according to a clock signal sequence; each group of clock signals in the clock signal sequence includes 2n+1 clock signals, where n is a positive integer; a transition edge of the first signal corresponds to a transition edge of the n+2th clock signal in a group of clock signals, and then execute step S104.

[0103] Optionally, the clock signals in the clock signal sequence are counted to generate and output at least one group of clock signals. A first signal sequence is generated based on at least one group of clock signals and a first reference signal sequence; in each first signal of the first signal sequence, the portion corresponding to the first n+1 clock signals in a group of clock signals is the second potential, and the portion corresponding to the last n clock signals is the first potential.

[0104] Optionally, a first intermediate variable of a register type may be defined to store the first signal sequence. The first potential is a high potential, the second potential is a low potential, for each first signal, the first counter is a rising edge counter, and in the working stage, when the first counter has n+1 consecutive rising edges, the state of the first intermediate variable is a low level, and when the first counter is in other states, the state of the first intermediate variable is a high level.

[0105] For example, when n is 2, 2n+1 is 5. The frequency divider in the embodiment of the present application is specifically a five-frequency divider with an equal duty cycle. The signal sequences of the five-frequency divider with an equal duty cycle are as follows: Figure 6 shown. Figure 6T0 represents the preparatory stage, T1, T2, and T3 represent the first working stage, the second working stage, and the third working stage respectively. The part of the clock signal sequence clk in each working stage is a group of clock signals, including 5 clock signals with equal duty cycles. The numbers 1, 2, and 3 represent the first 3 clock signals of a group of clock signals, and the numbers 4 and 0 represent the last 2 clock signals of a group of clock signals. The clock signal numbered 0 is the fifth clock signal in the T1 stage. The first half of each clock signal is at a high potential and the second half is at a low potential. The first signal sequence clk_p is a first signal in each working stage. The first signal generating unit 10 generates and outputs a first signal based on a group of clock signals, and the rising edge of the first signal is aligned with the rising edge of the fourth clock signal.

[0106] S102: Invert the clock signal sequence into an inverted clock signal sequence.

[0107] For example, Figure 6 As shown, the inverted clock signal sequence clk_inv is a group of inverted clock signals in each working phase. A group of inverted clock signals includes 5 inverted clock signals with equal duty cycles, and the numbers 1, 2 to 3 represent the first 3 inverted clock signals of a group of inverted clock signals, and the numbers 4 to 0 represent the last 2 inverted clock signals of a group of inverted clock signals. Each inverted clock signal is low potential for the first half of the time and high potential for the second half of the time.

[0108] S103: Generate a second signal sequence including at least one second signal according to the inverted clock signal sequence; in the second signal, the transition edge corresponds to the transition edge of the first inverted clock signal in a group of inverted clock signals, and the inverted transition edge corresponds to the transition edge of the n+1th inverted clock signal.

[0109] Optionally, the inverted clock signals in the inverted clock signal sequence are counted to generate and output at least one group of inverted clock signals. A second signal sequence is generated based on at least one group of inverted clock signals and a second reference signal sequence; a portion of the second signal corresponds to a transition edge from the middle of the first inverted clock signal to the middle of the n+1th inverted clock signal of a group of inverted clock signals, a portion of which is a first potential, and the rest of the second signal is a second potential.

[0110] Optionally, a second intermediate variable of a register type may be defined to store the second signal sequence. The first potential is a high potential, the second potential is a low potential, for each second signal, the second counter is a rising edge counter, and in the working stage, when the second counter has n consecutive rising edges, the state of the second intermediate variable is a high level, and when the second counter is in other states, the state of the second intermediate variable is a low level.

[0111] For example, Figure 6As shown, the second signal sequence clk_inv_p is a second signal in each working phase. The second signal generating unit 30 generates a second signal according to a set of inverted clock signals in the above step S102. Figure 6 A second signal of the second signal sequence clk_inv_p in the clock signal generator. The rising edge of the second signal is aligned with the rising edge of the first inverted clock signal, that is, aligned with the falling edge of the first clock signal; the falling edge of the second signal is aligned with the rising edge of the third inverted clock signal, that is, aligned with the falling edge of the third clock signal.

[0112] S104: Perform a combinational logic operation (a NOR operation in this example, and an AND operation in other embodiments) on the first signal sequence and the second signal sequence to obtain a third signal sequence including at least two third signals.

[0113] Optionally, a transition edge of a third signal corresponds to a transition edge of the first clock signal in a group of clock signals, and a transition edge of another immediately succeeding third signal corresponds to an inverted transition edge of the (n+1)th clock signal.

[0114] Optionally, in two adjacent third signals of the third signal sequence, parts corresponding to the first half of the 1st clock signal and the second half of the (n+1)th clock signal in a group of clock signals are both first potentials, and the other parts of the two adjacent third signals are second potentials.

[0115] For example, Figure 6 As shown, the third signal sequence ˜(clk_p|clk_inv_p) is composed of two third signals in each working phase. Figure 6 A first signal of the clock signal sequence clk and a second signal of the second signal sequence clk_inv_p are subjected to an OR operation to obtain Figure 6 The two third signals in the third signal sequence (clk_p|clk_inv_p) are aligned with the rising edge of the first clock signal, and the rising edge of the other third signal is aligned with the falling edge of the third clock signal. Since the falling edge of the third clock signal divides the total duration of the group of clock signals into two equal parts, the periods of the two third signals are equal.

[0116] S105: Generate a 2n+1 frequency-divided signal sequence with an equal duty cycle according to the third signal sequence.

[0117] Optionally, when the trigger 501 receives a transition edge of one of two adjacent third signals through the clock terminal, it outputs a first potential of a 2n+1 frequency-divided signal in a 2n+1 frequency-divided signal sequence with equal duty cycle through the output terminal, and receives a second potential inverted by the inverter through the input terminal; when the trigger 501 receives a transition edge of another immediately adjacent third signal, it outputs a second potential of the 2n+1 frequency-divided signal.

[0118] For example, Figure 6 As shown, the equal duty cycle divided-by-five frequency signal sequence clk_div_5 is a equal duty cycle divided-by-five frequency signal in each working phase. Figure 6 The two third signals of the third signal sequence ~(clk_p|clk_inv_p) in the third signal sequence generate Figure 6 A five-frequency-divided signal in the five-frequency-divided signal sequence clk_div_5 has a rising edge aligned with a rising edge of a third signal (i.e., the rising edge of the first clock signal), and a falling edge of the five-frequency-divided signal with equal duty cycle is aligned with a rising edge of another immediately succeeding third signal (i.e., the falling edge of the third clock signal). It can be seen that the five-frequency-divided signal has an equal duty cycle.

[0119] The control method of the frequency divider of this embodiment is compatible with any frequency divider provided in the embodiments of the present application, and the implementation principles thereof are similar, and the same or similar beneficial effects can be achieved, which will not be described in detail here.

[0120] The frequency divider provided in the embodiment of the present application can be a three-way frequency divider with equal duty cycle, a five-way frequency divider with equal duty cycle, a seven-way frequency divider with equal duty cycle, or a nine-way frequency divider with equal duty cycle, etc., any odd-numbered frequency divider greater than 1.

[0121] Below Figure 7 Taking this as an example, the working principle of the three-frequency divider with equal duty cycle in the embodiment of the present application is introduced.

[0122] n is 1, 2n+1 is 3. Figure 7 In the figure, clk represents a clock signal sequence, clk_p represents a first signal sequence, clk_inv represents an inverted clock signal sequence, clk_inv_p represents a second signal sequence, ~(clk_p|clk_inv_p) represents a third signal sequence, and clk_div_3 represents a three-frequency signal sequence with equal duty cycle. The left part of the first vertical dotted line from the left is the signal timing waveform of each of the above signal sequences in the preparatory stage T0, and the right part is the signal timing waveform of each of the above signal sequences in each working stage, and each working stage includes the first to fifth working stages, namely T1-T5.

[0123] like Figure 7In the example shown, the first working stage T1 can represent each working stage, the clock signal sequence clk is a group of clock signals (including 3 clock signals) in each working stage, the inverted clock signal sequence clk_inv is a group of reverse clock signals (including 3 inverted clock signals) in each working stage, the first signal sequence clk_p is a first signal in each working stage, the second signal sequence clk_inv_p is a second signal in each working stage, the third signal sequence ~(clk_p|clk_inv_p) is two third signals in each working stage, and the equal duty cycle three-frequency signal sequence clk_div_3 is a equal duty cycle three-frequency signal in each working stage.

[0124] Figure 7 In the example, the transition edge is a rising edge, the inverted transition edge is a falling edge, the first potential is a high potential, and the second potential is a low potential.

[0125] Figure 7 In the embodiment, the clock signal sequence clk in the first working phase T1 is a group of clock signals, including three clock signals with equal duty cycles, and numbers 1 to 2 represent the first two clock signals of a group of clock signals, and number 0 represents the third clock signal of a group of clock signals. The first half of each clock signal is high potential and the second half is low potential. The first signal generating unit 10 generates and outputs a first signal according to a group of clock signals, and the rising edge of the first signal is aligned with the rising edge of the third clock signal.

[0126] The inverting unit 20 will Figure 7 A set of clock signals inverted as Figure 7 A group of inverted clock signals of the inverted clock signal sequence clk_inv. Figure 7 As shown, a group of inverted clock signals includes three inverted clock signals with equal duty cycles, and numbers 1 to 2 represent the first two inverted clock signals of a group of inverted clock signals, and number 0 represents the third inverted clock signal of a group of inverted clock signals. Each inverted clock signal is low potential for the first half of the time and high potential for the second half of the time.

[0127] The second signal generating unit 30 is based on Figure 7 A set of inverted clock signals in Figure 7 A second signal of the second signal sequence clk_inv_p in the clock signal generator. The rising edge of the second signal is aligned with the rising edge of the first inverted clock signal, that is, aligned with the falling edge of the first clock signal; the falling edge of the second signal is aligned with the rising edge of the second inverted clock signal, that is, aligned with the falling edge of the second clock signal.

[0128] Combinational logic unit 40 pairs Figure 7A first signal of the clock signal sequence clk and a second signal of the second signal sequence clk_inv_p are subjected to an OR operation to obtain Figure 7 The two third signals of the third signal sequence ~(clk_p|clk_inv_p); the rising edge of one third signal is aligned with the rising edge of the first clock signal, and the rising edge of the other third signal is aligned with the falling edge of the second clock signal. Due to the falling edge of the second clock signal, the total duration of the clock signal of the group to which it belongs is divided into two equal parts, so the periods of the two third signals are equal.

[0129] The two-way frequency division unit 50 is based on Figure 7 The two third signals of the third signal sequence ~(clk_p|clk_inv_p) in the third signal sequence generate Figure 7 A three-way frequency division signal in the three-way frequency division signal sequence clk_div_3, the rising edge of the three-way frequency division signal is aligned with the rising edge of a third signal (i.e., the rising edge of the first clock signal), and the falling edge of the three-way frequency division signal is aligned with the rising edge of another immediately succeeding third signal (i.e., the falling edge of the n+1th clock signal). It can be seen that the 2n+1 frequency division signal has an equal duty cycle.

[0130] Other embodiments

[0131] Figure 8 FIG. 4 is a block diagram of an equal duty cycle odd-number frequency divider according to another embodiment. Figure 8 The equal duty cycle odd frequency divider 500 shown includes a first signal generating unit 10, a second signal generating unit 30, a combinational logic unit 40, a divide-by-two frequency unit 50 and an inverting unit 20. Optionally, the inverting unit 20 includes an inverter 20; the divide-by-two frequency unit 50 includes a divider 50; the first signal generating unit 10 includes an electrically connected first counter 101 and a first intermediate signal generating unit 120; the second signal generating unit 30 includes an electrically connected second counter 301 and a second intermediate signal generating unit 220. It will be appreciated by those skilled in the art that the frequency divider 500 may include other components, but for the sake of clarity, only relevant components are shown herein.

[0132] One difference from the above embodiment is that: Figure 8 The logic combination logic unit 40 shown is implemented as an AND logic unit 40, which performs an AND logic operation on the first signal sequence and the second signal sequence to generate a third signal sequence. Fig.9A and 9B The waveform diagram shown is used to describe Figure 8 The operation of the equal duty cycle odd divider 500 is shown.

[0133] Fig.9A700A shows waveforms related to the operation of an equal duty cycle divide-by-five frequency divider according to one embodiment. Fig.9A and Figure 8 , the input clock clk is provided to the first counter 101, and the inverted clock clk_inv obtained after being inverted by the inverter 20 is provided to the second counter 301. The first counter 101 and the second counter 301 can be Gray code counters, for example Figure 4 The Gray code counter shown may also be other types of counters, such as a binary counter. The first counter 101 and the second counter 301 trigger counting at the rising edges of the clock signals clk and clk_inv, respectively, and provide the count values ​​to the first intermediate signal generating unit 120 and the second intermediate signal generating unit 220, respectively. The first intermediate signal generating unit 120 outputs a high level when the count value is 0, 1, or 2, and outputs a low level when the count value is 3 or 4, thereby outputting Fig.9A The second intermediate signal generating unit 220 outputs a low level when the count value is 0 or 1 and outputs a high level when the count value is 2, 3 or 4, thereby outputting Fig.9A The AND logic unit 40 performs an AND logic operation on the first signal sequence clk_p and the second signal sequence clk_inv_p to obtain Fig.9A The combined signal (third signal sequence) shown is clk_p & clk_inv_p. The combined signal is provided to the divider 50 as the clock signal of the divider 50. Fig.9A As shown, the divider 50 triggers the output signal at the rising edge of the clock signals clk_p and clk_inv_p, thereby obtaining a 5-frequency divided signal with equal duty cycle clk_div5.

[0134] Fig. 9B 700B shows waveforms related to the operation of an equal duty cycle divide-by-five frequency divider according to one embodiment. Fig. 9B and Figure 8 , the input clock clk is provided to the first counter 101, and the inverted clock clk_inv obtained after inversion by the inverter 20 is provided to the second counter 301. The first counter 101 and the second counter 301 trigger counting at the rising edge of the clock signals clk and clk_inv, respectively, and provide the count values ​​to the first intermediate signal generating unit 120 and the second intermediate signal generating unit 220, respectively. The first intermediate signal generating unit 120 outputs a high level when the count value is 0, 1, 2, 3 and outputs a low level when the count value is 4, thereby outputting Fig. 9B The second intermediate signal generating unit 220 outputs a low level when the count value is 1 and outputs a high level when the count value is 0, 2, 3, 4, thereby outputting Fig. 9B The AND logic unit 40 performs an AND logic operation on the first signal sequence clk_p and the second signal sequence clk_inv_p to obtain Fig. 9B The combined signal (third signal sequence) shown is clk_p & clk_inv_p. The combined signal is provided to the divider 50 as the clock signal of the divider 50. Fig. 9B As shown, the divider 50 triggers the output signal at the rising edge of the clock signals clk_p and clk_inv_p, thereby obtaining a 5-frequency divided signal with equal duty cycle clk_div5.

[0135] Fig. 9C FIG. 700C shows a waveform diagram of an equal duty cycle divider by five according to one embodiment. Fig. 9C and Figure 8 , the input clock clk is provided to the first counter 101, and the inverted clock clk_inv obtained after inversion by the inverter 20 is provided to the second counter 301. The first counter 101 and the second counter 301 trigger counting at the rising edge of the clock signals clk and clk_inv, respectively, and provide the count values ​​to the first intermediate signal generating unit 120 and the second intermediate signal generating unit 220, respectively. The first intermediate signal generating unit 120 outputs a high level when the count value is 0, 1, 2, 3 and outputs a low level when the count value is 4, thereby outputting Fig. 9C The second intermediate signal generating unit 220 outputs a low level when the count value is 0 or 1 and outputs a high level when the count value is 2, 3 or 4, thereby outputting Fig. 9C The AND logic unit 40 performs an AND logic operation on the first signal sequence clk_p and the second signal sequence clk_inv_p to obtain Fig. 9C The combined signal (third signal sequence) shown is clk_p & clk_inv_p. The combined signal is provided to the divider 50 as the clock signal of the divider 50. Fig. 9C As shown, the divider 50 triggers the output signal at the rising edge of the clock signals clk_p and clk_inv_p, thereby obtaining a 5-frequency divided signal with equal duty cycle clk_div5.

[0136] In this embodiment, the first intermediate signal generating unit 120 and the second intermediate signal generating unit 220 can adopt the above Figure 3 The comparator approach is described to generate signals clk_p and clk_inv_p based on the count value.

[0137] In other embodiments, the first intermediate signal generating unit 120 does not necessarily use a comparator to implement mapping between the count value and the first signal. The first intermediate signal generating unit 120 may use any state conversion unit that can implement mapping between the count value and the first signal.

[0138] In one embodiment, the first state conversion unit of the replacement comparator converts the level state of the first signal when the count value is equal to a specific predetermined value, and maintains the level state of the first signal at other count values. In another embodiment, the first intermediate signal generation unit 120 does not need a Gray code-binary code conversion unit, and the first state conversion unit of the replacement comparator directly maps the received Gray code count values ​​to the corresponding first level state or second level state. For example, still taking the five-frequency division circuit as an example, the intermediate signal generation unit or the state conversion unit maps Gray codes 000, 001, 011 to the first level and Gray codes 010, 110 to the second level. In other words, the intermediate signal generation unit maps the first subset and the second subset of the count value to the first level and the second level of the first signal, respectively.

[0139] The above describes the specific structures of the first counter and the first intermediate signal generating unit and possible variations thereof, and those skilled in the art will appreciate that: Figure 8 The second counter and the second intermediate signal generating unit shown may have similar structures or be implemented in a similar manner.

[0140] In one embodiment, the first intermediate signal generating unit 120 includes a first state conversion unit, which converts the level state of the first signal when the count value of the first counter is equal to the first predetermined value and the second predetermined value, respectively, and maintains the level state of the first signal at other count values ​​of the first counter. The second intermediate signal generating unit 220 includes a second state conversion unit, which converts the level state of the second signal when the count value of the second counter is equal to the third predetermined value and the fourth predetermined value, respectively, and maintains the level state of the second signal at other count values ​​of the second counter. The first predetermined value is less than the second predetermined value, and the third predetermined value is less than the fourth predetermined value. The first predetermined value is equal to the third predetermined value, or the first predetermined value is not equal to the third predetermined value. For example, Fig.9A In the example shown, the first predetermined value is 0, the second predetermined value is 3, the third predetermined value is 0, and the fourth predetermined value is 2. For another example, Fig. 9B In the example shown, the first predetermined value is 0, the second predetermined value is 4, the third predetermined value is 1, and the fourth predetermined value is 2. For another example, Fig. 9C In the example shown, the first predetermined value is 0, the second predetermined value is 4, the third predetermined value is 0, and the fourth predetermined value is 2. The first predetermined value is the minimum value among the count values ​​of the first counter, and the fourth predetermined value is half of the frequency division factor plus 1 or minus 1. Fig.9A , 9B When the count value shown in 9C starts from 0, the first predetermined value is 0, and the fourth predetermined value is half of the frequency division factor minus 1. For another example, when Fig.9A , 9B When the count value shown in 9C starts from 1, the first predetermined value is 1, and the fourth predetermined value is half of the frequency division factor plus 1.

[0141] Figures 9A-9C Combination Figure 8 In the embodiment shown, the first counter 101 and the second counter 301 are triggered based on the rising edge of the clock signal clk and the inverted clock signal clk_inv, respectively. In one implementation, the inverter 20 may not be required, but the first counter 101 is triggered based on the rising edge of the clock signal clk, and the second counter 301 is triggered based on the falling edge of the clock signal clk, which can also be obtained. Figures 9A-9C The waveform shown no longer includes the inverted clock signal clk_inv.

[0142] Although Figure 8 The clock signal clk shown is directly input into the first counter 101 , but in a specific implementation, the first clock signal clk may first pass through a delay device before being input into the first counter 101 , so that the clock signal clk and its inverted signal clk_inv arrive at the first counter 101 and the second counter 301 simultaneously.

[0143] Although Figure 8 The inverter 20 is shown, but in other embodiments, the inverter may not be included, and the clock signal clk is directly provided to the first counter 101 and the second counter 301 .

[0144] In addition, based on the same inventive concept, an embodiment of the present application provides a clock signal generating circuit, including: a frequency divider as described in the above-mentioned embodiment of the present application and any optional implementation manner; the frequency divider is used to output a 2n+1 divided signal sequence with equal duty cycle as a designed clock signal sequence.

[0145] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including: a clock signal generating circuit as described in the above-mentioned embodiment of the present application.

[0146] Optionally, the electronic device according to the embodiment of the present application may include a display device and the like.

[0147] Based on the same inventive concept, an embodiment of the present application provides a machine-readable storage medium storing executable instructions, which, when executed, enable one or more processing units to implement the control method of the frequency divider of the embodiment of the present application as described above. Figure 1-9 described frequency divider can be implemented by a computer program, such as a hardware description language such as Verilog HDL, VHDL, etc. The computer program can be stored in a machine-readable medium, and when the computer program or instruction is executed by the processing unit, the processing unit executes the above combined Figure 1 -9 describes various operations.

[0148] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0149] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0150] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0151] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A frequency divider, characterized in that: include: A first signal generating unit, configured to generate and output a first signal sequence including at least one first signal according to a clock signal sequence; Each group of clock signals in the clock signal sequence includes 2n+1 clock signals, where n is a positive integer; a transition edge of the first signal corresponds to a transition edge of an n+2th clock signal in a group of the clock signals; Inverting unit; a second signal generating unit, whose input end is electrically connected to the output end of the inverting unit, and is used to generate and output a second signal sequence including at least one second signal according to an inverted clock signal sequence having a phase opposite to that of the clock signal sequence; in the second signal, a transition edge corresponds to a transition edge of the first inverted clock signal in a group of inverted clock signals, and an inverted transition edge corresponds to a transition edge of the n+1th inverted clock signal; a combination logic unit, wherein two input terminals are electrically connected to the output terminals of the first signal generating unit and the second signal generating unit respectively, and performs a combination logic operation on the first signal sequence and the second signal sequence to obtain a third signal sequence including at least two third signals and output the third signal sequence; A two-frequency division unit, whose input end is electrically connected to the output end of the combinational logic unit, and is used to generate a 2n+1 frequency division signal sequence with an equal duty cycle according to the third signal sequence; The combinational logic unit performs a logical operation of OR and NON on the first signal sequence and the second signal sequence to generate the third signal sequence; or, The combinational logic unit performs an AND logic operation on the first signal sequence and the second signal sequence to generate the third signal sequence; The two-frequency division unit includes a trigger and an inverter; The clock terminal of the trigger, as the input terminal of the two-frequency division unit, is electrically connected to the output terminal of the combinational logic unit, and is used to receive the third signal sequence; The positive electrode and the negative electrode of the inverter are electrically connected to the output terminal and the input terminal of the trigger; The trigger is used for, when receiving a transition edge of one of the two adjacent third signals through the clock terminal, outputting a first potential of a 2n+1 frequency-divided signal in a 2n+1 frequency-divided signal sequence with an equal duty cycle through the output terminal, and receiving a second potential inverted by the inverter through the input terminal; When another immediately succeeding transition edge of the third signal is received, the second potential of the 2n+1 frequency-divided signal is output.

2. The frequency divider according to claim 1, characterized in that: The first signal generating unit comprises a first counter, a clock end of the first counter serving as an input end of the first signal generating unit, and configured to receive the clock signal sequence, and the first counter is configured to count clock signals in the clock signal sequence, and generate and output at least one group of the clock signals; The second signal generating unit includes a second counter, and the clock end of the second counter serves as the input end of the second signal generating unit, and is used to receive the inverted clock signal sequence. The second counter is used to count the inverted clock signals in the inverted clock signal sequence, and generate and output at least one group of the inverted clock signals.

3. The frequency divider according to claim 2, characterized in that: The first signal generating unit comprises a first intermediate signal generating unit, which maps a first subset and a second subset of count values ​​of the first counter to a first potential and a second potential of the first signal, respectively; as well as The second signal generation unit includes a second intermediate signal generation unit that maps a first subset and a second subset of count values ​​of the second counter to a first potential and a second potential of the second signal, respectively.

4. The frequency divider according to claim 3, characterized in that: The first intermediate signal generating unit comprises a first comparator, wherein one input terminal of the first comparator is electrically connected to the output terminal of the first counter, and the other input terminal is used to receive a first reference signal sequence, and the first comparator is used to generate the first signal sequence according to at least one group of the clock signals and the first reference signal sequence; in each of the first signals of the first signal sequence, a portion corresponding to the first n+1 clock signals in a group of the clock signals is a second potential, and a portion corresponding to the last n clock signals is a first potential; The second intermediate signal generating unit includes a second comparator, wherein one input end of the second comparator is electrically connected to the output end of the second counter, and the other input end is used to receive a second reference signal sequence, and the second comparator is used to generate the second signal sequence based on at least one group of the inverted clock signals and the second reference signal sequence; a part of the second signal corresponds to a transition edge from the middle of the first inverted clock signal to the middle of the n+1th inverted clock signal of a group of the inverted clock signals, and the part is a first potential, and the other part of the second signal is a second potential.

5. The frequency divider according to claim 3, characterized in that: The first intermediate signal generating unit includes a first state conversion unit, which converts the potential state of the first signal when the count value of the first counter is equal to a first predetermined value and a second predetermined value, respectively, and maintains the potential state of the first signal when the count value of the first counter is other than the first predetermined value; and The second intermediate signal generating unit includes a second state conversion unit which converts the potential state of the second signal when the count value of the second counter is equal to a third predetermined value and a fourth predetermined value, respectively, and maintains the potential state of the second signal at other count values ​​of the second counter.

6. The frequency divider according to claim 1, characterized in that: The combinational logic unit includes a NOR gate, The two input ends of the NOR gate serve as the two input ends of the combinational logic unit and are electrically connected to the output ends of the first signal generating unit and the second signal generating unit. In two adjacent third signals of the third signal sequence, the parts corresponding to the first half of the first clock signal and the second half of the n+1th clock signal in a group of the clock signals are both the first potential, and the other parts of the two adjacent third signals are the second potential.

7. The frequency divider according to claim 2, characterized in that: The first counter and / or the second counter is a Gray code counter.

8. The frequency divider according to claim 7, characterized in that: The first counter and the second counter both include: A first transcoder, used for converting Gray code into binary code and outputting the binary code; An adder, wherein the output end is electrically connected to the input end, the enable end is electrically connected to the output end of the first transcoder, the clock end is used as a part of the input end of the first counter to receive the clock signal sequence, and the reset end is used to receive a reset signal; the adder is used to accumulate and output the binary code, and reset the accumulated binary code according to the reset signal received once every 2n+1 accumulations; The second transcoder has an input end electrically connected to the output end of the adder and an output end electrically connected to the input end of the first transcoder, and is used to convert the accumulated binary code into the accumulated Gray code.

9. The frequency divider according to claim 8, characterized in that: The first counter and the second counter each further include: A register, the input end of which is electrically connected to the output end of the second transcoder, the clock end as a part of the input end of the first counter is used to receive the clock signal sequence, and the reset end is used to receive the reset signal; the register is used to store and output the accumulated Gray code.

10. A clock signal generating circuit, characterized in that: include: A frequency divider as claimed in any one of claims 1 to 9; The frequency divider is used to output a 2n+1 frequency-divided signal sequence with an equal duty cycle as a design clock signal sequence.

11. An electronic device, characterized in that: include: The clock signal generating circuit as claimed in claim 10.

12. A method for controlling a frequency divider, characterized in that: A frequency divider as claimed in any one of claims 1 to 9, comprising: Generate a first signal sequence including at least one first signal according to a clock signal sequence; each group of clock signals in the clock signal sequence includes 2n+1 clock signals, where n is a positive integer; and a transition edge of the first signal corresponds to a transition edge of an n+2th clock signal in a group of the clock signals; Inverting the clock signal sequence into an inverted clock signal sequence; Generate a second signal sequence including at least one second signal according to the inverted clock signal sequence; in the second signal, a transition edge corresponds to a transition edge of the first inverted clock signal in a group of inverted clock signals, and an inverted transition edge corresponds to a transition edge of the n+1th inverted clock signal; Performing a combinational logic operation on the first signal sequence and the second signal sequence to obtain a third signal sequence including at least two third signals; A 2n+1 frequency-divided signal sequence with an equal duty cycle is generated according to the third signal sequence.

13. A machine-readable storage medium storing executable instructions, which when executed cause one or more processing units to perform the method of claim 12.

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