A BMS system

Abstract

The present invention discloses a BMS system, which uses an analog front end to power a processor. When a 485 communication device is connected to a 485 communication chip, a differential signal output terminal outputs a differential signal. At this time, the first output terminal of the wake-up circuit, that is, the level signal of the preset pin of the processor will change, and the control switch is turned on, so that the DC / DC is powered, and the corresponding 485 communication chip is powered; the wake-up pin of the analog front end can receive the first preset level signal output by the second output terminal of the wake-up circuit, so that the analog front end is awakened, which can not only control the switch to be turned on, but also realize the awakening of the analog front end. At this time, whether the BMS system is in a shallow sleep mode or a deep sleep mode, the BMS system can be awakened, and when it is necessary to read the status information of the battery pack, it is only necessary to connect the 485 communication device, and there is no need to use and connect the charger, which improves convenience.

Description

Technical Field

[0001] The present invention relates to the field of battery control, and in particular to a BMS system. Background Art

[0002] With the continuous development of electric vehicle industry technology, in order to suppress common mode interference in the signal transmission process, the 485 communication function is added to the BMS (Battery Management System) communication system. The BMS system communicates with the external 485 communication device through the 485 communication chip. Please refer to Figure 1 , Figure 1 The block diagram is a structural diagram of a BMS system in the prior art. When the switch is turned on, the DC / DC (DC-DC converter) converts the output voltage of the battery pack to power the 485 communication chip and the processor, the analog front end collects the status information of the battery pack, and transmits the collected status information to the processor, and the processor processes the status information through the 485 communication chip and transmits it to the external 485 communication device.

[0003] However, the power consumption of the 485 communication chip is relatively high. If it is kept working, the standby time of the electric vehicle will be reduced. Therefore, in the prior art, when there is no external 485 communication device connected, the BMS system is generally put into a shallow sleep mode. When the battery pack status needs to be obtained, the BMS system is awakened to increase the standby time of the electric vehicle.

[0004] In the prior art, when the BMS system enters a shallow sleep mode, the switch between the battery pack and the DC / DC is disconnected, the DC / DC is powered off, and the 485 communication chip and the processor are in a power-off state. The prior art method for waking up the BMS system is: by inserting a charger, the charger can output a control signal to turn on the switch, so that the DC / DC is powered, and then the processor and the 485 communication chip are powered, and then the processor controls the switch to be in the on state and then unplugs the charger to wake up the BMS system. Using this method, when obtaining the status information of the battery pack, not only the 485 communication device must be connected, but also the charger must be connected, and the steps are cumbersome.

[0005] In order to further increase the standby time of the electric vehicle, the BMS system can be controlled to enter a deep sleep mode. Specifically, the analog front end enters a dormant state, and the switch between the battery pack and the DC / DC is disconnected to reduce the power consumption of the BMS system, thereby increasing the standby time of the electric vehicle. Therefore, it is very necessary to provide a wake-up circuit with simple steps that can not only wake up the BMS system in a shallow sleep mode, but also wake up the BMS system in a deep sleep mode. Summary of the invention

[0006] The purpose of the present invention is to provide a BMS system, which can wake up the BMS system regardless of whether the BMS system is in a light sleep mode or a deep sleep mode, and when it is necessary to read the status information of the battery pack, it only needs to connect a 485 communication device, and there is no need to use and connect a charger, thereby improving convenience.

[0007] In order to solve the above technical problems, the present invention provides a BMS system, including an analog front end, a switch, a DC / DC converter DC / DC, a processor, a 485 communication chip and a wake-up circuit;

[0008] The voltage output end of the analog front end is connected to the power supply end of the processor, the control end of the processor is connected to the control end of the switch, the input ends of the wake-up circuit are respectively connected to the differential signal ends of the 485 communication chip, the first output end of the wake-up circuit is connected to the preset pin of the processor, the second output end of the wake-up circuit is connected to the wake-up pin of the analog front end, and when the differential signal end of the 485 communication chip is connected to an external 485 communication device, the differential signal end has a differential signal output;

[0009] The analog front end is used to convert the output voltage of the battery pack to power the processor;

[0010] The processor is used to control the switch to be turned on when there is an input voltage at its power supply end and the level signal of its preset pin changes;

[0011] The wake-up circuit is used to control the level signal of its first output end to change and control its second output end to output a first preset level signal when a differential signal is input to its input end, so that the analog front end is awakened.

[0012] Preferably, it comprises a first switch circuit, a second switch circuit and a third switch circuit;

[0013] The first end of the first switch circuit is connected to the differential signal end, the second end of the first switch circuit is respectively connected to the first end of the second switch circuit and the first end of the third switch circuit, the second end of the second switch circuit is the first output end of the wake-up circuit, and the second end of the third switch circuit is the second output end of the wake-up circuit;

[0014] The first switch circuit is used to be turned on when the differential signal is input to the first end thereof, so that the second end thereof outputs a second preset level signal;

[0015] The second switch circuit is used to be turned on when the first end thereof receives the second preset level signal, so that the level signal of the second end thereof changes;

[0016] The third switch circuit is used to be turned on when the first end thereof receives the second preset level signal, so that the second end thereof outputs the first preset level signal, so that the analog front end is awakened.

[0017] Preferably, the first switch circuit includes an optical coupler and a capacitor, and the differential signal terminal includes a first signal terminal and a second signal terminal;

[0018] The first end of the optocoupler is connected to the first signal end, the second end of the optocoupler is connected to the second signal end, the third end of the optocoupler is connected to the output end of the power module, the fourth end of the optocoupler is connected to the first end of the capacitor and serves as the second end of the first switching circuit, and the second end of the capacitor is grounded.

[0019] Preferably, the first switch circuit further includes a first diode and a first resistor;

[0020] The first end of the first resistor is connected to the first signal end, the second end of the first resistor is connected to the cathode of the first diode and the first end of the optocoupler, and the anode of the first diode is connected to the second signal end and the second end of the optocoupler respectively.

[0021] Preferably, the second switching circuit includes a controllable switch, a control end of the controllable switch is connected to the second end of the first switching circuit, a first end of the controllable switch is respectively connected to the output end of the power module and the preset pin of the processor, and a second end of the controllable switch is grounded.

[0022] Preferably, the third switch circuit comprises a second diode whose anode is connected to the second end of the first switch circuit and whose cathode is connected to the wake-up end of the analog front end.

[0023] Preferably, the second switch circuit further includes a second resistor, a third resistor and a fourth resistor;

[0024] One end of the second resistor is connected to the output end of the power module, the other end of the second resistor is respectively connected to the first end of the controllable switch and the preset pin, one end of the third resistor is connected to the output end of the first switch circuit, the other end of the third resistor is respectively connected to one end of the fourth resistor and the control end of the controllable switch, and the other end of the fourth resistor is connected to the second end of the controllable switch.

[0025] Preferably, it also includes:

[0026] An isolated power supply provided between the output end of the DC / DC and the power supply end of the 485 communication chip;

[0027] A communication isolation chip is arranged between the output end of the processor and the communication end of the 485 communication chip.

[0028] Preferably, it also includes:

[0029] A linear regulator is arranged between the output terminal of the DC / DC and the power supply terminal of the processor, and is used to adjust the output voltage of the DC / DC to a preset voltage to power the processor.

[0030] The present application provides a BMS system that uses an analog front end to power a processor. When a 485 communication device is connected to a 485 communication chip, the differential signal output terminal outputs a differential signal. At this time, the first output terminal of the wake-up circuit, that is, the level signal of the preset pin of the processor will change, and the control switch is turned on, so that the DC / DC is powered, and the corresponding 485 communication chip is powered; the wake-up pin of the analog front end can receive the first preset level signal output by the second output terminal of the wake-up circuit, so that the analog front end is awakened, which can not only control the switch to be turned on, but also realize the awakening of the analog front end. At this time, whether the BMS system is in a shallow sleep mode or a deep sleep mode, the BMS system can be awakened, and when it is necessary to read the status information of the battery pack, it is only necessary to connect the 485 communication device, and there is no need to use and connect the charger, which improves convenience. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 It is a structural block diagram of a BMS system in the prior art;

[0033] Figure 2 A structural block diagram of a BMS system provided by the present invention;

[0034] Figure 3 A structural block diagram of a wake-up circuit provided by the present invention;

[0035] Figure 4 A specific circuit diagram of a wake-up circuit provided by the present invention;

[0036] Figure 5 This is a structural block diagram of another BMS system provided by the present invention. DETAILED DESCRIPTION

[0037] The core of the present invention is to provide a BMS system. No matter the BMS system is in a light sleep mode or a deep sleep mode, the wake-up circuit can wake up the BMS system. When the status information of the battery pack needs to be read, it only needs to connect a 485 communication device, and there is no need to use and connect a charger, thereby improving convenience.

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Please refer to Figure 2 , Figure 2 This is a structural block diagram of a BMS system provided by the present invention, the BMS system includes an analog front end 2, a switch 4, a DC / DC 5, a processor 3, a 485 communication chip and a wake-up circuit 1;

[0040] The voltage output end of the analog front end 2 is connected to the power supply end of the processor 3, the control end of the processor 3 is connected to the control end of the switch 4, the input ends of the wake-up circuit 1 are respectively connected to the differential signal ends of the 485 communication chip, the first output end of the wake-up circuit 1 is connected to the preset pin of the processor 3, the second output end of the wake-up circuit 1 is connected to the wake-up pin of the analog front end 2, and when the differential signal end of the 485 communication chip is connected to the external 485 communication device, the differential signal end has a differential signal output;

[0041] The analog front end 2 is used to convert the output voltage of the battery pack to power the processor 3;

[0042] The processor 3 is used to control the switch 4 to be turned on when there is an input voltage at its own power supply end and the level signal of its own preset pin changes;

[0043] The wake-up circuit 1 is used to control the level signal of its first output terminal to change and control its second output terminal to output a first preset level signal when a differential signal is input to its input terminal, so that the analog front end 2 is awakened.

[0044] Considering that in the prior art, when the BMS system that only controls the battery enters a shallow sleep mode, although it can increase the standby time of the electric vehicle to a certain extent, the analog front end 2 will also reduce the standby time of the electric vehicle to a certain extent, therefore, the prior art can control the BMS system to enter a deep sleep mode. At this time, the switch 4 in the BMS system is disconnected and the analog front end 2 enters the sleep mode to reduce the power consumption of the BMS, thereby increasing the power consumption of the electric vehicle.

[0045] Based on the above problems, the design idea of ​​the present invention is to provide a wake-up circuit 1, which can not only wake up the BMS system in the shallow sleep mode, but also wake up the BMS system in the deep sleep mode, so that the BMS system exits the sleep mode.

[0046] Therefore, the present application provides a wake-up circuit 1, wherein the BMS system in the present application also uses an analog front end 2 to power the processor 3, so that in the shallow sleep mode, the 485 communication chip is powered off, and the processor 3 is always in a powered state. At this time, when a 485 communication device outputs a differential signal, the level signal of the first output end of the wake-up circuit 1 changes. When the processor 3 detects that the level signal of the preset pin changes, the switch 4 is controlled to be turned on so that the DC / DC5 is powered on, and the 485 communication chip is powered off, so as to complete the wake-up of the shallow sleep mode of the BMS system. In the deep sleep mode, the processor 3 is powered off, the 485 communication chip is also powered off, and the analog front end 2 is in sleep mode, and the 485 communication device outputs a differential signal so that the second output end of the wake-up circuit 1 outputs a first preset level signal, so that the analog front end 2 is awakened. At this time, the analog front end 2 can power the processor 3, and when the preset pin receives a changed level signal, the switch 4 is controlled to be turned on, so as to realize the wake-up of the deep sleep mode of the BMS system.

[0047] It should be noted that the processor 3 in the present application can be but not limited to an MCU, the power supply voltage of the power supply end of the MCU is 3.3V, the power supply voltage of the 485 communication chip can be but not limited to 5V, and can also be other implementation modes, and the present application does not make any special limitations here.

[0048] In summary, the wake-up circuit 1 in the present application can wake up the BMS system regardless of whether the BMS system is in a light sleep mode or a deep sleep mode, and when it is necessary to read the status information of the battery pack, it only needs to connect the 485 communication device, and there is no need to use and connect the charger, which improves convenience.

[0049] Based on the above embodiments:

[0050] Please refer to Figure 3 , Figure 3 This is a structural block diagram of a wake-up circuit provided by the present invention.

[0051] As a preferred embodiment, it includes a first switch circuit 31, a second switch circuit 32 and a third switch circuit 33;

[0052] A first end of the first switch circuit 31 is connected to the differential signal end, a second end of the first switch circuit is connected to a first end of the second switch circuit 32 and a first end of the third switch circuit 33 respectively, a second end of the second switch circuit 32 is a first output end of the wake-up circuit 1, and a second end of the third switch circuit 33 is a second output end of the wake-up circuit 1;

[0053] The first switch circuit 31 is used to be turned on when a differential signal is input to its first end, so that its second end outputs a second preset level signal;

[0054] The second switch circuit 32 is used to be turned on when the first end thereof receives a second preset level signal, so as to change the level signal of the second end thereof;

[0055] The third switch circuit 33 is used to be turned on when the first end thereof receives the second preset level signal, so that the second end thereof outputs the first preset level signal, so that the analog front end 2 is awakened.

[0056] The present embodiment aims to provide a specific implementation of the wake-up circuit 1. Specifically, the wake-up circuit 1 in the present embodiment may include, but is not limited to, three switch circuits, wherein, after the first end of the first switch circuit 31 receives the differential signal, the first switch circuit 31 can output a second preset level signal after being turned on, so that the second switch circuit 32 is turned on based on the second preset level signal to change the level signal of its own second segment, so as to achieve the change of the level signal of the preset pin of the processor 3, and the third switch circuit 33 is turned on based on the second preset level signal to output the first preset level signal, so as to achieve the wake-up of the analog front end 2.

[0057] Among them, the first preset level signal and the second preset level signal in the present application are related to the specific implementation methods of the three switch circuits, and the present application does not make any special limitations here.

[0058] In summary, the three switch circuits in the present application can realize the awakening of the shallow sleep mode and the deep sleep mode of the BMS system, and the implementation method is simple and reliable.

[0059] Please refer to Figure 4 , Figure 4 A specific circuit diagram of a wake-up circuit provided by the present invention.

[0060] As a preferred embodiment, the first switch circuit 31 includes an optical coupler and a capacitor, and the differential signal terminal includes a first signal terminal and a second signal terminal;

[0061] The first end of the optocoupler is connected to the first signal end, the second end of the optocoupler is connected to the second signal end, the third end of the optocoupler is connected to the output end of the power module, the fourth end of the optocoupler is connected to the first end of the capacitor and serves as the second end of the first switching circuit 31, and the second end of the capacitor is grounded.

[0062] Specifically, when the first switch circuit 31 in the present application includes an optocoupler and a capacitor, when the first end and the second end of the optocoupler receive a differential signal, the voltage of the differential signal is different, and at this time, the first end and the second end of the corresponding optocoupler are connected, and the third end and the fourth end of the corresponding optocoupler are connected, and the second end of the fourth end of the corresponding optocoupler outputs a high-level signal, and the capacitor is used to filter the high-level signal to ensure that the second end of the first switch circuit 31 outputs a stable high-level signal. Based on this embodiment, the second preset level signal is a high-level signal.

[0063] It should be noted that in the present application, the anode of the light-emitting diode in the optocoupler can be used as the first end of the optocoupler, the cathode of the light-emitting diode in the optocoupler can be used as the second end of the optocoupler, the collector of the photosensitive semiconductor tube in the optocoupler can be used as the third end of the optocoupler, and the emitter of the photosensitive semiconductor transistor can be used as the fourth end of the optocoupler. At this time, the voltage (485B) output by the first signal end is correspondingly greater than the output voltage (485A) of the second signal end.

[0064] As a preferred embodiment, the first switch circuit 31 further includes a fifth resistor, which is arranged between the power module and the third end of the optical coupler.

[0065] Among them, the first switching circuit 31 in the present application also utilizes the isolation characteristics of the optocoupler to prevent the analog front end 2 and the processor 3 from receiving external interference, protect the analog front end 2 from the high voltage that may be caused by the outside (differential signal), and protect the processor 3 from the high voltage that may be caused by the outside, thereby preventing the components in the BMS system from being damaged.

[0066] In summary, in this embodiment, the function of the first switch circuit 31 can be realized by the optocoupler and the capacitor, and the components in the BMS system can be prevented from being interfered by the outside world, thereby ensuring the reliability of the BMS system. In addition, the capacitor also has a filtering function, further ensuring the reliability of the second preset level signal.

[0067] As a preferred embodiment, the first switch circuit 31 further includes a first diode and a first resistor;

[0068] The first end of the first resistor is connected to the first signal end, the second end of the first resistor is connected to the cathode of the first diode and the first end of the optocoupler, and the anode of the first diode is connected to the second signal end and the second end of the optocoupler respectively.

[0069] Considering that when the voltage outputted by the first signal terminal is greater than the output voltage of the second signal terminal, the output current of the first signal terminal may flow back to the second signal output terminal, thus damaging the connected 485 communication chip and / or 485 communication device.

[0070] In order to solve the above technical problems, in this embodiment, a first diode is arranged between the first signal terminal and the second signal terminal to prevent the output current of the first signal terminal with a higher output voltage from flowing back to the second signal terminal with a lower output voltage, thereby preventing the 485 communication chip and / or 485 communication device in the BMS system from being damaged, thereby ensuring the reliability of the BMS system.

[0071] It should be noted that the device disposed between the first signal terminal and the second signal terminal in the present application is not limited to being a first diode, but may also be other backflow prevention devices, and the present application does not make any special limitation thereto.

[0072] As a preferred embodiment, the second switching circuit 32 includes a controllable switch, the control end of the controllable switch is connected to the second end of the first switching circuit 31, the first end of the controllable switch is respectively connected to the output end of the power module and the preset pin of the processor 3, and the second end of the controllable switch is grounded.

[0073] This embodiment aims to provide a specific implementation method of the second switch circuit 32. Specifically, when the first switch circuit 31 is an optocoupler, when the output second preset level signal is a high level signal, after the control end of the controllable switch receives the high level signal, the controllable switch is turned on, and the output end of the second switch circuit 32 changes from a high level to a low level. At this time, the corresponding processor 3 will control the switch to be turned on, so that the DC / DC5 is powered on, and then the 485 communication chip is powered on.

[0074] Among them, the controllable switch in the present application can be an NPN (Negative-positive-Negative, negative-positive-negative) type transistor, or it can be a controllable switch that is conductive between the first end and the second end when other control ends are high-level signals. The present application does not make any special limitations here.

[0075] In addition, the power module in the present application can be a power module separately arranged in the BMS system that can output power all the time to ensure that the controllable switch can be stably turned on or off, or it can be a battery pack, and then the output voltage of the battery pack is transformed and adjusted to control the controllable switch to be stably turned on or off. The specific implementation method of the power module and the output voltage of the power module are not specifically limited in the present application, as long as reliable control of the controllable switch can be achieved.

[0076] As a preferred embodiment, the third switch circuit 33 includes a second diode whose anode is connected to the second end of the first switch circuit 31 and whose cathode is connected to the wake-up end of the analog front end 2 .

[0077] This embodiment aims to provide a specific implementation method of the third switching circuit 33. Specifically, when the third switching circuit 33 includes a second diode and the first switching circuit 31 includes an optocoupler, when the second end of the first switching circuit 31 outputs a high-level signal, the second diode is turned on and outputs a high level to the wake-up pin of the analog front end 2, and the analog front end 2 is awakened.

[0078] In addition, when the BMS system does not enter the deep sleep mode, the wake-up pin of the analog front end 2 can be controlled to be high level and the switch can be turned on by the wake-up circuit 1, or the wake-up pin of the analog front end 2 can be controlled to be high level and the switch can be turned on after the processor 3 is powered on. The specific situation depends on the actual situation, and this application does not make any special limitation here.

[0079] In summary, the second diode in this embodiment can realize the function of the third switch circuit 33, and the implementation method is simple and reliable.

[0080] As a preferred embodiment, the second switch circuit 32 further includes a second resistor, a third resistor and a fourth resistor;

[0081] One end of the second resistor is connected to the output end of the power supply module, the other end of the second resistor is respectively connected to the first end of the controllable switch and the preset pin, one end of the third resistor is connected to the output end of the first switch circuit 31, the other end of the third resistor is respectively connected to one end of the fourth resistor and the control end of the controllable switch, and the other end of the fourth resistor is connected to the second end of the controllable switch.

[0082] In order to improve the reliability of the second switch circuit 32, the above three resistors are also provided in this embodiment to ensure the stability of the voltage at the control end of the controllable switch so that the control end of the controllable switch can receive a stable high-level signal, thereby ensuring the reliability of the third controllable switch.

[0083] Specifically, when the power module is a battery pack, the resistance values ​​of the three resistors can be adjusted so that the voltage input to the control end of the controllable switch can be a voltage that can control the controllable switch to be stably turned on and off. The corresponding output voltage of the above-mentioned battery pack and the resistance values ​​of the above-mentioned three resistors are not specifically limited in this application, and the specific implementation depends on the actual situation.

[0084] In summary, the controllable switch and the related resistor in this embodiment can realize the function of the second switch circuit 32, and the implementation method is simple and reliable.

[0085] Please refer to Figure 5 , Figure 5 This is a structural block diagram of another BMS system provided by the present invention.

[0086] As a preferred embodiment, it also includes:

[0087] An isolated power supply 51 is provided between the output terminal of the DC / DC 5 and the power terminal of the 485 communication chip;

[0088] A communication isolation chip 52 is provided between the output terminal of the processor 3 and the communication terminal of the 485 communication chip.

[0089] In order to ensure the reliability of power supply with 485 communication chip and prevent the power supply end from being interfered by the outside world, the front end of 485 communication chip in the present application is also provided with an isolated power supply 51.

[0090] In addition, in order to ensure the reliability of communication between the processor 3 and the 485 communication chip and prevent external interference signals during communication, the present embodiment further provides a communication isolation chip 52 to improve the reliability of the BMS system.

[0091] As a preferred embodiment, it also includes:

[0092] The linear regulator 53 disposed between the output terminal of the DC / DC 5 and the power terminal of the processor 3 is used to adjust the output voltage of the DC / DC 5 to a preset voltage to power the processor 3 .

[0093] This embodiment provides another way to power the processor 3, and the linear regulator 53 that adjusts the output voltage of the DC / DC 5 corresponds to Figure 5 The LDO in the circuit is used to enable the DC / DC5 to power the processor 3 through the linear regulator 53. The DC / DC5 outputs 5V to power the 485 communication chip, and the processor 3 requires a 3.3V supply voltage. At this time, the linear regulator 53 converts the 5V voltage into 3.3V to power the processor 3.

[0094] It can be seen that this embodiment provides another power supply mode for the processor 3, thereby increasing the flexibility and diversity of the power supply for the processor 3.

[0095] It should be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0096] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0097] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A BMS system, characterized in that: Including analog front end, switch, DC / DC converter DC / DC, processor, 485 communication chip and wake-up circuit; The voltage output end of the analog front end is connected to the power supply end of the processor, the control end of the processor is connected to the control end of the switch, the input ends of the wake-up circuit are respectively connected to the differential signal ends of the 485 communication chip, the first output end of the wake-up circuit is connected to the preset pin of the processor, the second output end of the wake-up circuit is connected to the wake-up pin of the analog front end, and when the differential signal end of the 485 communication chip is connected to an external 485 communication device, the differential signal end has a differential signal output; The analog front end is used to convert the output voltage of the battery pack to power the processor; The processor is used to control the switch to be turned on when there is an input voltage at its power supply end and the level signal of its preset pin changes; The wake-up circuit is used to control the level signal of its first output end to change and control its second output end to output a first preset level signal when a differential signal is input to its input end, so that the analog front end is awakened.

2. The BMS system according to claim 1, characterized in that: The wake-up circuit includes a first switch circuit, a second switch circuit and a third switch circuit; The first end of the first switch circuit is connected to the differential signal end, the second end of the first switch circuit is respectively connected to the first end of the second switch circuit and the first end of the third switch circuit, the second end of the second switch circuit is the first output end of the wake-up circuit, and the second end of the third switch circuit is the second output end of the wake-up circuit; The first switch circuit is used to be turned on when the differential signal is input to the first end thereof, so that the second end thereof outputs a second preset level signal; The second switch circuit is used to be turned on when the first end thereof receives the second preset level signal, so that the level signal of the second end thereof changes; The third switch circuit is used to be turned on when the first end thereof receives the second preset level signal, so that the second end thereof outputs the first preset level signal, so that the analog front end is awakened.

3. The BMS system according to claim 2, characterized in that: The first switch circuit includes an optical coupler and a capacitor, and the differential signal terminal includes a first signal terminal and a second signal terminal; The first end of the optocoupler is connected to the first signal end, the second end of the optocoupler is connected to the second signal end, the third end of the optocoupler is connected to the output end of the power module, the fourth end of the optocoupler is connected to the first end of the capacitor and serves as the second end of the first switching circuit, and the second end of the capacitor is grounded.

4. The BMS system according to claim 3, characterized in that: The first switch circuit also includes a first diode and a first resistor; The first end of the first resistor is connected to the first signal end, the second end of the first resistor is connected to the cathode of the first diode and the first end of the optocoupler, and the anode of the first diode is connected to the second signal end and the second end of the optocoupler respectively.

5. The BMS system according to claim 3, characterized in that: The second switch circuit includes a controllable switch, a control end of the controllable switch is connected to the second end of the first switch circuit, a first end of the controllable switch is respectively connected to the output end of the power module and the preset pin of the processor, and a second end of the controllable switch is grounded.

6. The BMS system according to claim 5, characterized in that: The third switch circuit includes a second diode whose anode is connected to the second end of the first switch circuit and whose cathode is connected to the wake-up end of the analog front end.

7. The BMS system according to claim 6, characterized in that: The second switch circuit further includes a second resistor, a third resistor and a fourth resistor; One end of the second resistor is connected to the output end of the power module, the other end of the second resistor is respectively connected to the first end of the controllable switch and the preset pin, one end of the third resistor is connected to the output end of the first switch circuit, the other end of the third resistor is respectively connected to one end of the fourth resistor and the control end of the controllable switch, and the other end of the fourth resistor is connected to the second end of the controllable switch.

8. The BMS system according to any one of claims 1 to 7, characterized in that: Also includes: An isolated power supply provided between the output end of the DC / DC and the power supply end of the 485 communication chip; A communication isolation chip is arranged between the output end of the processor and the communication end of the 485 communication chip.

9. The BMS system according to claim 8, characterized in that: Also includes: A linear regulator is arranged between the output terminal of the DC / DC and the power supply terminal of the processor, and is used to adjust the output voltage of the DC / DC to a preset voltage to power the processor.

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