Physical unclonable function structure and registration method based on ferroelectric transistor

Abstract

The present application discloses a physical unclonable function structure based on ferroelectric transistors and a registration method and device, wherein the structure includes: an array circuit is an array structure formed by electrically connecting multiple ferroelectric transistor circuit structure units to form multiple rows and columns, the word lines of each row of circuit structure units are connected and connected to a decoding circuit, the bit lines of each column of circuit structure units are connected to a sensing line, and the bit lines are connected to a driving circuit, and the sensing lines are connected to a sensing circuit; the driving circuit is used to drive the word lines and bit lines of the array circuit; the decoding circuit is used to input a challenge signal and decode the input challenge signal into a corresponding address; the sensing circuit is used to generate an output response signal data from the input challenge signal by utilizing the random flipping characteristics of the polarization state of the ferroelectric transistors in the array circuit. The embodiments of the present application utilize the randomness and diversity of the polarization state of the ferroelectric transistor to realize a reconfigurable physical unclonable function, which has the advantage of low power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of low-power reconfigurable physical unclonable function design, and in particular to a physical unclonable function structure based on ferroelectric transistors and a registration method and device. Background Art

[0002] At present, with the gradual development of information technology, people have higher and higher requirements for hardware security. In order to deal with potential attacks, people have proposed to use physical unclonable functions (PUF) to achieve security applications such as key generation and device identity verification. Figure 1 As shown, PUF, as a physical system, can convert a given input (called an input challenge signal) into a certain unpredictable output (called an output response signal), thereby realizing many subsequent hardware security functions.

[0003] PUF has been implemented in some circuit structures based on various devices, such as CMOS process PUF represented by ring oscillator PUF based on oscillation frequency, decision PUF based on delay, SRAM PUF based on power-on initial state, etc. These CMOS process-based PUFs have good compatibility with other circuits, but the structure is relatively complex, the reliability of the output response signal is relatively low, and they are easily affected by invasive attacks. At the same time, the reconfigurability of these circuits is relatively weak.

[0004] The CMOS-based PUF mentioned above mainly utilizes the randomness brought by the manufacturing process deviation of the corresponding circuit structure, while the emerging non-volatile memory (NVM) can also construct PUF. Some existing NVM-based PUFs have improved reconfigurability and density compared to CMOS-based PUFs, but still have problems such as high power consumption during programming, which to some extent limits their application in mobile terminals with power consumption constraints. Summary of the invention

[0005] The present application provides a physical unclonable function structure based on ferroelectric transistors and a registration method and device, which utilizes the randomness and diversity of the polarization state of the ferroelectric transistors to realize a reconfigurable physical unclonable function, and has the advantage of low power consumption.

[0006] The first aspect of the present application provides a physical unclonable function structure based on ferroelectric transistors, including: an array circuit, a driving circuit, a decoding circuit and a sensing circuit.

[0007] The array circuit is an array structure formed by electrically connecting a plurality of ferroelectric transistor circuit structure units to form a plurality of rows and columns, wherein the word lines of the circuit structure units in each row are connected and connected to the decoding circuit, and the bit lines of the circuit structure units in each column are connected to the sensing lines, and the bit lines are connected to the driving circuit, and the sensing lines are connected to the sensing circuit;

[0008] The driving circuit is used to drive the word lines and bit lines of the array circuit;

[0009] The decoding circuit is used to receive an input of a challenge signal and decode the input challenge signal into a corresponding address;

[0010] The sensing circuit is used to generate output response signal data from the input challenge signal by utilizing the random flipping characteristics of polarization states of ferro-transistors in the array circuit.

[0011] According to one embodiment of the present application, the circuit structure unit includes a ferroelectric transistor, a word line, a bit line, and a sensing line. The drain of the ferroelectric transistor is connected to the sensing line, the gate of the ferroelectric transistor is connected to the word line, the source of the ferroelectric transistor is connected to the bit line, and the physical unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source.

[0012] According to one embodiment of the present application, the sensing circuit includes multiple sensing amplifiers, the positive input terminal of the sensing amplifier is connected to the sensing line of the corresponding column of the array circuit, the negative input terminal is connected to an adjustable reference current source input by an external circuit, and the physical unclonable function outputs the output response signal data through the output terminal of the sensing amplifier.

[0013] According to one embodiment of the present application, the circuit structure unit includes a first ferroelectric transistor, a second ferroelectric transistor, a word line, a first bit line, a second bit line, a first sensing line, and a second sensing line. The drain of the first ferroelectric transistor is connected to the first sensing line, the gate of the first ferroelectric transistor is connected to the word line, and the source of the first ferroelectric transistor is connected to the first bit line; the drain of the second ferroelectric transistor is connected to the second sensing line, the gate of the second ferroelectric transistor is connected to the word line, and the source of the second ferroelectric transistor is connected to the second bit line. The physically unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source.

[0014] According to one embodiment of the present application, the sensing circuit includes multiple sensing amplifiers, the positive and negative input terminals of the sensing amplifiers are connected to the first sensing line and the second sensing line of the corresponding column of the array circuit in a preset manner, and the physical unclonable function outputs the output response signal data through the output terminal of the sensing amplifier.

[0015] According to an embodiment of the present application, the preset connection mode is to swap the connection lines of the positive and negative input terminals and the connection lines of the positive and negative output terminals of the sense amplifier after registering a preset number of units.

[0016] A second aspect of the present application provides a method for registering a challenge-response pair of an array circuit, which is used in the physical unclonable function structure based on a ferroelectric transistor described in the above embodiment, wherein the circuit structure unit of the array circuit includes a ferroelectric transistor, and the registration of the challenge-response pair of the array circuit includes the following steps:

[0017] Initializing all circuit structure units in the array circuit;

[0018] Applying a predefined write pulse to all circuit structure units to randomly change the polarization states of the ferroelectric transistors in all circuit structure units;

[0019] Generate a reference state;

[0020] The polarization states of all circuit structure units are compared with the reference state, and strong positive polarization or strong negative polarization is written back to the circuit structure unit according to the comparison result.

[0021] According to one embodiment of the present application, the initialization of all circuit structure units in the array circuit includes: fixing all bit lines at a low level, applying a negative voltage of a first preset duration and a first preset high level on all word lines, and initializing the ferroelectric transistors in all circuit structure units to a strong negative polarization state.

[0022] According to one embodiment of the present application, the application of a predefined write pulse to all circuit structure units causes the polarization state of the ferroelectric transistors in all circuit structure units to change randomly, including: fixing all bit lines at a low level, applying a high-level pulse of a second preset voltage and a second preset duration to all word lines, so that the ferroelectric transistors in each circuit structure unit reach a random polarization state.

[0023] According to one embodiment of the present application, generating a reference state includes:

[0024] Set the a priori current reference maximum value, current reference minimum value, current initial reference value and preset accuracy;

[0025] Taking the initial current reference value as the current reference value, performing a reading operation on all the circuit structure units of the array circuit row by row, and calculating the normalized Hamming weight of all the circuit structure units of the array circuit through other circuits;

[0026] When the difference between the normalized Hamming weight and the expected value is greater than the preset accuracy, adjusting the current reference value according to a preset ratio, and modifying the current reference maximum value or the current reference minimum value;

[0027] The normalized Hamming weight of all circuit structure units of the array circuit is calculated repeatedly until the difference between the normalized Hamming weight and the expected value is within a preset accuracy, thereby obtaining a reference current.

[0028] According to an embodiment of the present application, comparing the polarization states of all circuit structure units with the reference state, and writing strong positive polarization or strong negative polarization back to the circuit structure unit according to the comparison result, includes:

[0029] The current on the sensing line of each circuit structure unit is compared with the reference current, and the ferroelectric transistor in the circuit structure unit is written to a strong positive polarization state or a strong negative polarization state according to the high level or low level of the output result of each circuit structure unit.

[0030] According to an embodiment of the present application, it also includes: synchronously applying a write voltage to the entire array in a parallel writing manner to initialize or write a random polarization state.

[0031] According to one embodiment of the present application, it also includes: after registration is completed, fixing each bit line in the array circuit at a low level, applying a negative level pulse with a fifth preset duration and a fifth preset high voltage on the word line, and reinitializing each ferroelectric transistor in the array circuit to re-perform the registration process.

[0032] In a third aspect, an embodiment of the present application provides a registration method for a challenge-response pair of an array circuit, which is used in the physical unclonable function structure based on ferroelectric transistors described in the above embodiment, wherein the circuit structure unit of the array circuit includes the first ferroelectric transistor and the second ferroelectric transistor, and the registration of the challenge-response pair of the array circuit includes the following steps:

[0033] Initializing all circuit structure units in the array circuit;

[0034] Applying a predefined write pulse to all circuit structure units to randomly change the polarization states of the ferroelectric transistors in all circuit structure units;

[0035] Comparing the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit to obtain a comparison result;

[0036] Strong positive polarization or strong negative polarization is written back to the first ferroelectric transistor and the second ferroelectric transistor according to the comparison result.

[0037] According to one embodiment of the present application, the initialization of all circuit structure units in the array circuit includes: fixing all first bit lines and second bit lines at a low level, applying a negative voltage of a third preset time length and a third preset high level on all word lines, and initializing all ferroelectric transistors in all circuit structure units to a strong negative polarization state.

[0038] According to one embodiment of the present application, a predefined write pulse is applied to all circuit structure units to randomly change the polarization state of the ferroelectric transistors in all circuit structure units, including: fixing all first bit lines and second bit lines at a low level, and applying a high level pulse of a fourth preset voltage and a fourth preset duration to all word lines, so that each ferroelectric transistor reaches a different polarization state.

[0039] According to one embodiment of the present application, the comparison of the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit includes: fixing all first bit lines and second bit lines at a first sensing voltage, applying a preset read voltage to the word lines row by row, and differentially amplifying the current output on the first sensing line and the current output on the second sensing line through the sensing circuit to obtain the comparison result.

[0040] According to one embodiment of the present application, writing strong positive polarization or strong negative polarization back to the first ferroelectric transistor and the second ferroelectric crystal according to the comparison result includes: writing the first transistor in the circuit structure unit to strong positive polarization or strong negative polarization, and writing the second transistor to strong negative polarization or strong positive polarization state, respectively, according to the high level or low level of the output result of each circuit structure unit.

[0041] According to an embodiment of the present application, it also includes: synchronously applying a write voltage to the entire array in a parallel writing manner to initialize or write a random polarization state.

[0042] According to one embodiment of the present application, it also includes: after registration is completed, fixing each bit line in the array circuit at a low level, applying a negative level pulse with a fifth preset duration and a fifth preset high voltage on the word line, and reinitializing each ferroelectric transistor in the array circuit to re-perform the registration process.

[0043] In a fourth aspect, an embodiment of the present application provides a registration device for a challenge-response pair of an array circuit, which is used in the physical unclonable function structure based on a ferroelectric transistor as described in the above embodiment, wherein a circuit structure unit of the array circuit includes a ferroelectric transistor, and the device includes:

[0044] A first initialization module, used for initializing all circuit structure units in the array circuit;

[0045] A first random write module is used to apply a predefined write pulse to all circuit structure units to randomly change the polarization state of the ferroelectric transistors in all circuit structure units;

[0046] A reference generation module, used for generating a reference state;

[0047] The first write-back module is used to compare the polarization states of all circuit structure units with the reference state, and write strong positive polarization or strong negative polarization back to the circuit structure unit according to the comparison result.

[0048] In a fifth aspect, an embodiment of the present application provides a registration device for a challenge-response pair of an array circuit, which is used for the physical unclonable function structure based on ferroelectric transistors described in the above embodiment, wherein the circuit structure unit of the array circuit includes the first ferroelectric transistor and the second ferroelectric transistor, and the device includes:

[0049] A second initialization module, used for initializing all circuit structure units in the array circuit;

[0050] A second random write module is used to apply a predefined write pulse to all circuit structure units to randomly change the polarization state of the ferroelectric transistors in all circuit structure units;

[0051] A comparison module, used for comparing the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit to obtain a comparison result;

[0052] The second write-back module is used to write the strong positive polarization or the strong negative polarization back to the first ferroelectric transistor and the second ferroelectric transistor according to the comparison result.

[0053] A sixth aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a registration method for challenge-response pairs of an array circuit as described in the above embodiments.

[0054] A seventh aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, the program being executed by a processor to implement a registration method for challenge-response pairs of an array circuit as described in the above embodiments.

[0055] The physical unclonable function structure based on ferroelectric transistors and the registration method and device of the embodiment of the present application use the diversity of polarization states inside ferroelectric transistors and the randomness of polarization state flipping as entropy sources, so that the input challenge signal is mapped to a random and unpredictable output response signal through the polarization state of the ferroelectric transistor. At the same time, by utilizing the characteristics of ferroelectric transistors such as no write DC power consumption, high switching ratio and CMOS compatibility, on the basis of achieving good uniform randomness, uniqueness and repeatability of the output response signal, it has the characteristics of low power consumption, reconfigurability and strong robustness.

[0056] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0058] Figure 1 It is a functional diagram of a physical unclonable function;

[0059] Figure 2 A schematic diagram of a physical unclonable function structure based on a ferroelectric transistor according to an embodiment of the present application;

[0060] Figure 3 (a) is a circuit symbol of a ferroelectric transistor provided according to an embodiment of the present application, (b) is a schematic diagram of a structure of a ferroelectric transistor, and (c) is a schematic diagram of a drain-source current-gate voltage characteristic curve changing with polarization state;

[0061] Figure 4 A schematic diagram of a physical unclonable function structure based on a ferroelectric transistor according to a specific embodiment of the present application;

[0062] Figure 5 A schematic diagram of the structure of a unit circuit in a physical unclonable function structure based on a ferroelectric transistor provided according to an embodiment of the present application;

[0063] Figure 6 A schematic diagram of the structure of a unit circuit in another physical unclonable function structure based on a ferroelectric transistor provided according to an embodiment of the present application;

[0064] Figure 7 A distribution diagram of polarization states of a ferroelectric transistor provided by an embodiment of the present application obtained by simulation and experimental measurement under the same pulse;

[0065] Figure 8 A flowchart of a registration method for a challenge-response pair of an array circuit provided according to an embodiment of the present application;

[0066] Fig. 9 A flowchart of another registration method for challenge-response pairs of an array circuit provided according to an embodiment of the present application;

[0067] Fig.10 A polarization state distribution diagram obtained by simulation before and after a reprogramming operation is performed in a registration operation according to an embodiment of the present application;

[0068] Fig.11 A flowchart of a registration operation provided according to an embodiment of the present application;

[0069] Fig.12 A schematic diagram of a flow chart of a reference current selection operation according to an embodiment of the present application;

[0070] Fig.13 A distribution diagram of simulation results and experimental results of HD and HW related parameters after a registration operation according to an embodiment of the present application;

[0071] Fig.14 A polarization state distribution diagram under different write voltage pulses provided according to an embodiment of the present application;

[0072] Fig.15 A comparison table of simulation results on parameters such as HD and HW under different numbers of ferroelectric chips provided according to an embodiment of the present application;

[0073] Fig.16 A distribution diagram of simulation results of HDinter at different ferroelectric layer thicknesses provided according to an embodiment of the present application;

[0074] Fig.17 A comparison table of the worst delay-average energy performance of each operation provided according to an embodiment of the present application and the prior art;

[0075] Fig.18 A schematic diagram of the structure of a registration device for a challenge-response pair of an array circuit provided according to an embodiment of the present application;

[0076] Fig.19 A schematic diagram of the structure of a registration device for a challenge-response pair of another array circuit provided according to an embodiment of the present application;

[0077] Fig. 20 A schematic diagram of the structure of an electronic device provided for an application embodiment.

[0078] Explanation of the accompanying drawings: 100-physical unclonable function structure based on ferroelectric transistor, 1-array circuit, 2-driving circuit, 3-decoding circuit, 4-sensing circuit, 5-physical unclonable function circuit structure unit based on ferroelectric transistor, 5-1-ferroelectric transistor, 5-2-word line, 5-3-bit line, 5-4-sensing line, 6-physical unclonable function circuit structure unit based on ferroelectric transistor, 6-1-first ferroelectric transistor, 6-2-second ferroelectric transistor, 6-3-word line, 6-4-first bit line, 6-5-second bit line, 6-6-first sensing line, 6-7-second sensing line. DETAILED DESCRIPTION

[0079] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0080] Figure 2 A schematic diagram of a physical unclonable function structure based on a ferroelectric transistor provided according to an embodiment of the present application.

[0081] like Figure 2 As shown, the physical unclonable function structure 100 based on ferroelectric transistors includes: an array circuit 1, a driving circuit 2, a decoding circuit 3 and a sensing circuit 4.

[0082] Among them, the array circuit 1 is an array structure with multiple rows and columns formed by electrically connecting multiple ferroelectric transistor circuit structure units, the word lines WL of each row of circuit structure units are connected and connected to the decoding circuit 3, the bit lines BL and the sensing lines SL of each column of circuit structure units are connected, and the bit lines BL are connected to the driving circuit 2, and the sensing lines SL are connected to the sensing circuit 4.

[0083] The driving circuit 2 is used to drive the word lines WL and the bit lines BL of the array circuit 1 .

[0084] The decoding circuit 3 is used for receiving the input of the challenge signal and decoding the input challenge signal into a corresponding address.

[0085] The sensing circuit 4 is used to generate an output response signal data from an input challenge signal by utilizing the random flipping characteristics of the polarization states of the ferroelectric transistors in the array circuit 1 .

[0086] In the embodiment of the present application, the circuit structure unit of the array circuit includes a ferroelectric field effect transistor (FeFET). The structure and characteristics of the ferroelectric transistor are as follows: Figure 3As shown in the figure, it uses different polarization states of the ferroelectric layer to store information, and different polarization states are manifested as threshold voltages of different sizes. Ferroelectric transistors have extremely high switching ratios, and the three-terminal structure of ferroelectric transistors allows their write operations to be achieved only by controlling the gate-source voltage, thereby further reducing write power consumption. At the same time, the transistor-type access interface also provides a certain degree of CMOS compatibility. In addition, ferroelectric transistors have random polarization state flipping characteristics, which provides an effective way to achieve PUF randomness.

[0087] like Figure 4 As shown, the specific structure of the array circuit composed of ferroelectric transistors is shown. In the embodiment of the present application, the number of ferroelectric transistors in the circuit structure unit of the array circuit can be one or two or other numbers. Figure 4 The circuit structure unit in the array circuit shown includes a ferroelectric transistor.

[0088] When the number of ferroelectric transistors in the circuit structure unit of the array circuit is one, the word lines of the circuit structure units in the same row are connected, the bit lines of the circuit structure units in the same column are connected, and the sensing lines of the circuit structure units in the same column are connected. The driving circuit drives the word lines and bit lines of the array circuit, the decoding circuit decodes the input question into a corresponding address, the positive and negative input terminals of the sensing amplifier in the sensing circuit are respectively connected to the sensing line of the array circuit and the reference current source input by other circuits, and the physical unclonable function outputs the response signal data through the output terminal of the sensing amplifier.

[0089] As a specific example, Figure 5 As shown, the circuit structure unit of the array circuit includes a ferroelectric transistor 5-1, a word line 5-2, a bit line 5-3, and a sensing line 5-4. The drain of the transistor 5-1 is connected to the sensing line 5-4, the gate of the transistor 5-1 is connected to the word line 5-2, the source of the transistor 5-1 is connected to the bit line 5-3, and the physical unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source.

[0090] Based on the above embodiment, the sensing circuit includes multiple sensing amplifiers, the positive input terminal of the sensing amplifier is connected to the sensing line of the corresponding column of the array circuit, the negative input terminal is connected to the adjustable reference current source input by the external circuit, and the physical unclonable function outputs the response signal data through the output terminal of the sensing amplifier.

[0091] When the number of ferroelectric transistors in the circuit structure unit of the array circuit is two, the word lines of the circuit structure units in the same row are connected, the first bit lines of the circuit structure units in the same column are connected, the second bit lines of the circuit structure units in the same column are connected, the first sensing lines of the circuit structure units in the same column are connected, and the second sensing lines of the circuit structure units in the same column are connected. The driving circuit drives the word lines, the first bit lines and the second bit lines of the array circuit, the decoding circuit decodes the input question into the corresponding address, the positive and negative input terminals of the sensing amplifier in the sensing circuit are respectively connected to the first sensing line and the second sensing line of the array circuit 1, and the physical unclonable function outputs the response signal data through the output terminal of the sensing amplifier.

[0092] As a specific example, Figure 6 As shown, the circuit structure unit of the array circuit includes a first ferroelectric transistor 6-1, a second ferroelectric transistor 6-2, a word line 6-3, a first bit line 6-4, a second bit line 6-5, a first sensing line 6-6 and a second sensing line 6-7. The drain of the first ferroelectric transistor 6-1 is connected to the first sensing line 6-6, the gate of the first ferroelectric transistor 6-1 is connected to the word line 6-3, the source of the first ferroelectric transistor 6-1 is connected to the first bit line 6-4, the drain of the second ferroelectric transistor 6-2 is connected to the second sensing line 6-7, the gate of the second ferroelectric transistor 6-2 is connected to the word line 6-3, and the source of the second ferroelectric transistor 6-2 is connected to the second bit line 6-5. The physical unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source.

[0093] Based on the above embodiment, the sensing circuit includes multiple sensing amplifiers, the positive and negative input terminals of the sensing amplifiers are connected to the first sensing line and the second sensing line of the corresponding columns of the array circuit in a preset manner, and the physical unclonable function outputs the response signal data through the output terminal of the sensing amplifier.

[0094] As a specific implementation manner, the preset connection is to swap the connection lines of the positive and negative input terminals and the connection lines of the positive and negative output terminals of the sense amplifier after registering a preset number of units.

[0095] It should be noted that for Figure 5When the circuit structure unit shown is operated, the polarization state of the ferroelectric transistor 5-1 can be changed or read by changing the level of the word line 5-2 and the bit line 5-3. When performing a write operation, if you want to achieve positive polarization of the ferroelectric transistor 5-1, set the bit line 5-3 to a low level and the word line 5-2 to a high level, and keep it for a long time. At this time, the ferroelectric transistor 5-1 is in a low resistance state; if you want to achieve negative polarization of the ferroelectric transistor 5-1, set the bit line 5-3 to a low level and the word line 5-2 to a negative high level, and keep it for a long time. At this time, the ferroelectric transistor 5-1 is in a high resistance state. When performing a read operation, set the bit line 5-3 to a lower sensing voltage and the word line 5-2 to a lower read voltage. At this time, a current flows out from the sensing line 5-4, and the magnitude of this current can measure the polarization state of the ferroelectric transistor 5-1.

[0096] For Figure 6 When the circuit structure unit shown is operated, the polarization state of the first ferroelectric transistor 6-1 and the second ferroelectric transistor 6-2 can be changed or read by changing the level of the word line 6-3, the first bit line 6-4 and the second bit line 6-5. When performing a write operation, if it is desired to realize positive polarization of the first ferroelectric transistor 6-1 and the second ferroelectric transistor 6-2, the first bit line 6-4 and the second bit line 6-5 are set to a low level, the word line 6-3 is set to a high level, and it lasts for a long time, at which time the first ferroelectric transistor 6-1 and the second ferroelectric transistor 6-2 are in a low resistance state; if it is desired to realize negative polarization of the first ferroelectric transistor 6-1 and the second ferroelectric transistor 6-2, the first bit line 6-4 and the second bit line 6-5 are set to a low level, the word line 6-3 is set to a negative high level, and it lasts for a long time, at which time the first ferroelectric transistor 6-1 and the second ferroelectric transistor 6-2 are in a high resistance state. When performing a read operation, the first bit line 6-4 and the second bit line 6-5 are placed at a lower sensing voltage, and the word line 6-3 is placed at a lower read voltage. At this time, current flows out from the first sensing line 6-6 and the second sensing line 6-7 respectively, and the sizes of the two can respectively measure the polarization states of the first ferroelectric transistor 6-1 and the second ferroelectric transistor 6-2.

[0097] Without loss of generality, the embodiment of the present application selects the following state mapping method: when the number of ferroelectric transistors in the circuit structure unit of the array circuit is one, the state in which the ferroelectric layer of the ferroelectric transistor 5-1 is forward polarized and shows low-resistance conduction is mapped to "1", otherwise it is "0"; the state in which the word line 5-2 and the bit line 5-3 have a zero voltage to the ground is mapped to "0", and the state of a high level is mapped to "1"; when the number of ferroelectric transistors in the circuit structure unit of the array circuit is one, the state in which the ferroelectric layer of the first ferroelectric transistor 6-1 and the second ferroelectric transistor 6-2 are forward polarized and show low-resistance conduction is mapped to "1", otherwise it is "0"; the state in which the word line 6-3, the first bit line 6-4, and the second bit line 6-5 have a zero voltage to the ground is mapped to "0", and the state of a high level is mapped to "1".

[0098] Furthermore, in any circuit structure unit, when the state of the ferroelectric transistor is "0", the corresponding bit line is fixed at the state "0", and a high-level pulse of a specific time and a specific voltage is applied to the corresponding word line, such as Figure 7 As shown, due to the characteristics of ferroelectric materials, the polarization state of the transistor is randomly distributed in a large range, and this distribution serves as the entropy source of the physical unclonable function.

[0099] According to the physical unclonable function structure based on ferroelectric transistors proposed in the embodiment of the present application, the gate of the ferroelectric transistor is connected by a controllable word line, the corresponding bit line is fixed at a low level, and a high-level pulse of a specific time and a specific voltage is applied to the corresponding word line. For the ferroelectric transistor that has been initialized to a high-resistance state, due to the randomness of the polarization state reversal of the ferroelectric material and the process production deviation between different transistors, the polarization state can be randomly distributed in a larger range. The polarization state is characterized by a certain circuit parameter, and an output response signal with randomness and unpredictability can be obtained, thereby realizing the physical unclonable function.

[0100] Next, a registration method for challenge-response pairs of an array circuit proposed in an embodiment of the present application is described with reference to the accompanying drawings.

[0101] Figure 8 It is a flowchart of a registration method of a challenge-response pair of an array circuit according to an embodiment of the present application.

[0102] like Figure 8 As shown, the circuit structure unit of the array circuit includes a ferroelectric transistor, and the registration of the challenge response pair of the array circuit includes the following steps:

[0103] Step S101, initializing all circuit structure units in the array circuit.

[0104] In one embodiment of the present application, all circuit structure units in the array circuit are initialized, including: fixing all bit lines at a low level, applying a negative voltage of a first preset duration and a first preset high level on all word lines, and initializing all ferroelectric transistors in all circuit structure units to a strong negative polarization state.

[0105] Step S102 : applying a predefined write pulse to all circuit structure units to randomly change the polarization states of the ferroelectric transistors in all circuit structure units.

[0106] In one embodiment of the present application, a predefined write pulse is applied to all circuit structure units to randomly change the polarization state of the ferroelectric transistors in all circuit structure units, including: fixing all bit lines at a low level, applying a high level pulse of a second preset voltage and a second preset duration on all word lines, so that the ferroelectric transistors in each circuit structure unit reach a random polarization state

[0107] Step S103, generating a reference state.

[0108] In one embodiment of the present application, generating a reference state includes:

[0109] Set the a priori current reference maximum value, current reference minimum value, current initial reference value and preset accuracy;

[0110] Taking the initial current reference value as the current current reference value, performing a reading operation on all the circuit structure units of the array circuit row by row, and calculating the normalized Hamming weight of all the circuit structure units of the array circuit through other circuits;

[0111] When the difference between the normalized Hamming weight and the expected value is greater than a preset accuracy, the current reference value is adjusted according to a preset ratio, and the current reference maximum value or the current reference minimum value is modified;

[0112] The normalized Hamming weight of all circuit structural units of the array circuit is calculated repeatedly until the difference between the normalized Hamming weight and the expected value is within a preset accuracy, thereby obtaining a reference current.

[0113] Step S104, comparing the polarization states of all circuit structure units with the reference state, and writing strong positive polarization or strong negative polarization back to the circuit structure unit according to the comparison result.

[0114] In one embodiment of the present application, the polarization states of all circuit structure units are compared with a reference state, and strong positive polarization or strong negative polarization is written back to the circuit structure unit based on the comparison result, including: comparing the current on the sensing line of each circuit structure unit with the reference current, and writing the ferroelectric transistors in the circuit structure unit to a strong positive polarization or strong negative polarization state according to the high level or low level of the output results of each circuit structure unit.

[0115] As a specific embodiment, when registering this application, the first step is to fix all bit lines at a low level, apply a negative voltage of a higher level for a longer time on all word lines, and initialize the ferroelectric transistors in all circuit structure units to a high-resistance state; the second step is to fix all bit lines at a low level, apply a high-level pulse of a specific voltage and a specific duration on all word lines, so that the ferroelectric transistors in each unit reach different polarization states; the third step is to fix all bit lines at a lower sensing voltage, apply a lower read voltage to the word lines row by row, and differentially amplify the current output on the sensing line and the reference current through the sensing circuit; the fourth step is to write the ferroelectric transistors in the circuit structure unit to a low-resistance state and a high-resistance state respectively according to the high level and low level of the output results of each unit.

[0116] In the above embodiment, when determining the reference current, the a priori maximum current value, minimum current value, initial current, adjustment step size and accuracy are first preset. On this basis, the first step is to set the reference current as the initial current, so as to read and calculate the normalized Hamming weight (HW) of the stored data once; the second step is that when the difference between HW and 0.5 exceeds the accuracy, if the reference current is too large, the reference current at this time is set to the maximum current value, and the new reference current is set to the sum of the step size multiplied by the minimum current value and the difference between 1 and the step size multiplied by the maximum current value; if the reference current is too small, the reference current at this time is set to the minimum current value, and the new reference current is set to the sum of the step size multiplied by the maximum current value and the difference between 1 and the step size multiplied by the minimum current value; the third step is to repeat the above two steps until the difference between HW and 0.5 is within the accuracy requirement, and the reference current at this time is determined as the reference current for subsequent operations.

[0117] Fig. 9 It is a flowchart of a registration method of a challenge-response pair of an array circuit according to another embodiment of the present application.

[0118] like Fig. 9 As shown, the circuit structure unit of the array circuit includes a first ferroelectric transistor and a second ferroelectric transistor, and the registration of the challenge response pair of the array circuit includes the following steps:

[0119] Step S201, initializing all circuit structure units in the array circuit.

[0120] In one embodiment of the present application, all circuit structure units in the array circuit are initialized, including: fixing all first bit lines and second bit lines at a low level, applying a negative voltage of a third preset time length and a third preset high level on all word lines, and initializing all ferroelectric transistors in all circuit structure units to a strong negative polarization state.

[0121] Step S202: applying a predefined write pulse to all circuit structure units to randomly change the polarization states of the ferroelectric transistors in all circuit structure units.

[0122] In one embodiment of the present application, a predefined write pulse is applied to all circuit structure units to randomly change the polarization state of the ferroelectric transistors in all circuit structure units, including: fixing all first bit lines and second bit lines at a low level, and applying a high-level pulse with a fourth preset voltage and a fourth preset duration to all word lines, so that each ferroelectric transistor reaches a different polarization state.

[0123] Step S203 , comparing the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit to obtain a comparison result.

[0124] In one embodiment of the present application, the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit are compared, including: fixing all first bit lines and second bit lines at a first sensing voltage, applying a preset read voltage to the word lines row by row, and differentially amplifying the current output on the first sensing line and the current output on the second sensing line through a sensing circuit to obtain a comparison result.

[0125] Step S204 , writing the strong positive polarization or the strong negative polarization back to the first ferroelectric transistor and the second ferroelectric transistor according to the comparison result.

[0126] In one embodiment of the present application, writing strong positive polarization or strong negative polarization back to the first ferroelectric transistor and the second ferroelectric transistor according to the comparison result includes:

[0127] According to the high level or low level of the output result of each circuit structure unit, the first transistor in the circuit structure unit is written to a strong positive polarization or a strong negative polarization, and the second transistor is written to a strong negative polarization or a strong positive polarization state.

[0128] Furthermore, to eliminate the effect of the sense amplifier offset, as Figure 6 As shown, after every several registrations, the connections of the positive and negative input terminals of each sense amplifier in the sense circuit are swapped, and the connections of the positive and negative output terminals are swapped. In this way, the offset of the sense amplifier in the sense circuit can be averaged in a time sense, thereby eliminating the offset and its influence.

[0129] As a specific embodiment, when the present application is registered, the first step is to fix all first bit lines and second bit lines at a low level, apply a negative voltage of a higher level for a longer time on all word lines, and initialize all ferroelectric transistors in all circuit structure units to a high resistance state; the second step is to fix all first bit lines and second bit lines at a low level, apply a high level pulse of a specific voltage and a specific duration on all word lines, so that the ferroelectric transistors in each unit reach different polarization states; the third step is to fix all first bit lines and second bit lines at a lower sensing voltage, apply a lower read voltage to the word lines row by row, and differentially amplify the current output on the first sensing line and the current output on the second sensing line through the sensing circuit; the fourth step is to write the first transistor in the circuit structure unit to a low resistance state and a high resistance state, respectively, and the second transistor to a high resistance state and a low resistance state, respectively, according to the high level and low level of the output results of each unit.

[0130] Furthermore, in the above embodiment, in order to eliminate the influence of the offset of the sense amplifier during differential amplification, the connections of the positive and negative input terminals of the sense amplifier are swapped, and the connections of the positive and negative output terminals are swapped after registering every few units. In this way, the offset of the sense amplifier can be averaged in a time sense, thereby eliminating the offset.

[0131] In one embodiment of the present application, a write voltage is synchronously applied to the entire array in a parallel writing manner to initialize or write a random polarization state.

[0132] Specifically, when the circuit structure unit of the array circuit includes one ferroelectric transistor or two ferroelectric transistors, in the first and second steps of the registration process, a large number of parallel write modes are adopted to synchronously write all word lines (WL1, WL2, ..., WL 2^m, ) simultaneously applies a write voltage pulse to initialize or write a random polarization state. The implementation of this parallel writing method relies on the characteristic that the ferroelectric transistor presents a capacitive load when writing. Compared with existing similar works, this method greatly improves the parallelism of the writing process.

[0133] Furthermore, when the circuit structure unit of the array circuit includes one ferroelectric transistor or two ferroelectric transistors, in the fourth step of the registration process, a write pulse of a longer time and a higher voltage is applied to the ferroelectric transistor, so that the transistor enters a strong positive polarization state or a strong negative polarization state. This operation enables the transistor to have a higher switching ratio, greatly increases the noise margin of the read operation and the hold operation, and improves the reliability and sensing efficiency of the circuit structure.

[0134] Specifically, in the fourth step of the registration process, it is necessary to write the corresponding state into the ferroelectric transistor in the corresponding circuit structure unit in the array circuit according to the result of the sensing circuit output in the third step, so that the transistor enters a strong positive polarization state or a strong negative polarization state. Fig.10 As shown in FIG. 1 , this operation makes the source-drain current corresponding to the states "0" and "1" significantly differentiated. Compared with the original state, the ratio of the average source-drain current in the "1" state to the average source-drain current in the "0" state increases from 1.23 to 1200, an increase of 976 times. It can be seen that the operation corresponding to the fourth step greatly increases the noise tolerance of the array circuit 1 during the read operation and the hold operation, thereby improving the reliability of the circuit structure and the sensing efficiency.

[0135] In one embodiment of the present application, after registration is completed, each bit line in the array circuit is fixed at a low level, and a negative level pulse with a fifth preset duration and a fifth preset high voltage is applied to the word line to reinitialize each ferroelectric transistor in the array circuit to re-perform the registration process.

[0136] Furthermore, when the circuit structure unit of the array circuit includes one ferroelectric transistor or two ferroelectric transistors, after the registration is completed, each bit line in the array circuit can be fixed at a low level, and a negative level pulse with a longer time and higher voltage can be applied to the word line, so as to reinitialize each ferroelectric transistor in the array circuit and repeat the above-mentioned registration operation process. Due to the randomness of the polarization state reversal of the ferroelectric material, the polarization state of the ferroelectric transistor will generate a new random distribution, thereby realizing the reconfigurability of the physically unclonable function.

[0137] Furthermore, combined with Figure 5 and Fig.11 As shown, when the number of ferroelectric transistors in the circuit structure unit of the array circuit is one, the registration process of the circuit structure unit is as follows: the first step is to initialize the ferroelectric transistors in all the circuit structure units in the array circuit to the state "0"; the second step is to fix the bit line 5-3 to the state "0", and apply a high-level pulse of a specific time and a specific voltage to the word line 5-2, so that the ferroelectric transistor 5-1 in each unit reaches a different polarization state; the third step is to read all the circuit structure units in the array circuit row by row, and the current output on the sensing line 5-4 and the reference current are differentially amplified and output through the sensing circuit; the fourth step is to write the ferroelectric transistor 5-1 to the state "0" or "1" correspondingly according to the "0" or "1" state of the output result.

[0138] Furthermore, combined with Figure 6 and Fig.11As shown, when the number of ferroelectric transistors in the circuit structure unit of the array circuit is two, the registration process of the circuit structure unit is as follows: the first step is to initialize the ferroelectric transistors in all the circuit structure units in the array circuit to state "0"; the second step is to fix the first bit line 6-4 and the second bit line 6-5 to state "0", and apply a high-level pulse of a specific time and a specific voltage to the word line 6-3, so that the first ferroelectric transistor 6-1 and the second ferroelectric transistor 6-2 in each unit reach different polarization states; the third step is to read all the circuit structure units in the array circuit row by row, and differentially amplify the current output on the first sensing line 6-6 and the current output on the second sensing line 6-7 through the sensing circuit; the fourth step is to write the first ferroelectric transistor 6-1 to state "0", "1", and the second ferroelectric transistor 6-2 to state "1", "0" according to the "0" and "1" states of the output results.

[0139] Furthermore, when the number of ferroelectric transistors in the circuit structure unit of the array circuit is one, in order to determine the reference current, as Fig.12 As shown, firstly, the a priori maximum current value (I DS_HIGH ), minimum current (I DS_LOW ), initial current (I DS_0 ), step size (α) and accuracy (δ). The first step is to set the reference current (I DS ) is set to I DS_0 Under this condition, all circuit structure units of the array circuit are read row by row, and the normalized Hamming weight (HW) of the stored data is calculated by other circuits. The second step is that when HW-0.5 is greater than δ, let I DS_HIGH Set to I DS , I DS Let αI DS_LOW +(1-α)I DS ; When HW-0.5 is less than -, let I DS_LOW Set to I DS , I DS Let αI DS_HIGH +(1-α)I DS Step 3: Repeat the above two steps until HW-0.5 is between -δ and δ. DS That is the determined reference current.

[0140] According to the above embodiment, when the simulation parameters: ferroelectric layer thickness (T FE ) is 8nm; the number of ferroelectric domains is 200; the sense amplifier offset is 1.0% of the source-drain current; experimental parameters: gate area is 500x500nm 2The simulation and test results of the normalized Hamming weight (HW), normalized inter-chip Hamming distance (HDinter), and normalized intra-chip Hamming distance (HDintra) of the circuit after the registration operation are shown in Figure 2. Fig.13 As shown in Figure 2, some circuit parameters and device parameters may deviate in the actual manufacturing process, such as Fig.14 , 15 As shown in , 16, the robustness simulation test results of the write voltage pulse, the number of ferroelectric domains and the thickness of the ferroelectric layer show that the embodiment of the present invention has high robustness. In addition, the embodiment of the present invention can rewrite all transistors in the array circuit 1 to state "0", repeat the registration operation and obtain a new polarization state distribution, which has high reconfigurability. Compared with other related technologies, the physical unclonable function proposed in the embodiment of the present invention has high robustness during the registration operation and the read operation. Fig.17 As shown, it shows good delay and power consumption performance. Comparing the first embodiment and the second embodiment of the present invention, the former occupies a small area but is complex to operate and has high requirements on the computing performance of other circuits; the latter occupies a large area but is simple to operate.

[0141] It should be noted that the above explanation of the embodiment of the physical unclonable function structure based on ferroelectric transistors is also applicable to the registration method of the challenge-response pair of the array circuit of this embodiment, which will not be repeated here.

[0142] According to the registration method of challenge response pairs of array circuits proposed in the embodiment of the present application, the gate of the ferroelectric transistor is connected by a controllable word line, the corresponding bit line is fixed at a low level, and a high-level pulse of a specific time and a specific voltage is applied to the corresponding word line. For the ferroelectric transistor that has been initialized to a high-resistance state, due to the randomness of the polarization state reversal of the ferroelectric material and the process production deviation between different transistors, the polarization state can be randomly distributed in a larger range. The polarization state is characterized by a certain circuit parameter, and an output response signal with randomness and unpredictability can be obtained, thereby realizing the function of a physical unclonable function.

[0143] Fig.18 The present invention is a schematic diagram of a registration device structure of a challenge-response pair of an array circuit provided according to an embodiment of the present application.

[0144] The registration device for challenge-response pairs of the array circuit of the embodiment of the present application is used for the physical unclonable function structure based on ferroelectric transistors in the above-mentioned embodiment. The circuit structure unit of the array circuit includes a ferroelectric transistor. The device 10 includes: a first initialization module 1801, a first random write module 1802, a reference generation module 1803 and a first write back module 1804.

[0145] The first initialization module 1801 is used to initialize all circuit structure units in the array circuit.

[0146] The first random write module 1802 is used to apply a predefined write pulse to all circuit structure units to randomly change the polarization states of the ferroelectric transistors in all circuit structure units.

[0147] The reference generation module 1803 is used to generate a reference state.

[0148] The first write-back module 1804 is used to compare the polarization states of all circuit structure units with the reference state, and write strong positive polarization or strong negative polarization back to the circuit structure unit according to the comparison result.

[0149] In one embodiment of the present application, the first initialization module 1801 is further used to fix all bit lines at a low level, apply a negative voltage of a first preset duration and a first preset high level to all word lines, and initialize all ferroelectric transistors in all circuit structure units to a strong negative polarization state.

[0150] In one embodiment of the present application, the first random write module 1802 is further used to fix all bit lines at a low level, apply a high-level pulse of a second preset voltage and a second preset duration to all word lines, so that the ferroelectric transistors in each circuit structure unit reach a random polarization state.

[0151] In one embodiment of the present application, the reference generation module 1803 is further used to set a priori current reference maximum value, current reference minimum value, current initial reference value and preset accuracy; use the current initial reference value as the current reference value, read all circuit structure units of the array circuit row by row, and calculate the normalized Hamming weight of all circuit structure units of the array circuit through other circuits; when the difference between the normalized Hamming weight and the expected value is greater than the preset accuracy, adjust the current current reference value according to a preset ratio, and modify the current reference maximum value or the current reference minimum value; repeatedly calculate the normalized Hamming weight of all circuit structure units of the array circuit until the difference between the normalized Hamming weight and the expected value is within the preset accuracy, and obtain the reference current.

[0152] According to one embodiment of the present application, the first write-back module 1804 is further used to compare the current on the sensing line of each circuit structure unit with the reference current, and write the ferroelectric transistor in the circuit structure unit to a strong positive polarization state or a strong negative polarization state according to the high level or low level of the output result of each circuit structure unit.

[0153] Fig.19 The present invention is a schematic diagram of the structure of a registration device for a challenge-response pair of another array circuit provided according to an embodiment of the present application.

[0154] The registration device for challenge-response pairs of the array circuit of the embodiment of the present application is used for the physical unclonable function structure based on ferroelectric transistors in the above-mentioned embodiment. The circuit structure unit of the array circuit includes a first ferroelectric transistor and a second ferroelectric transistor. The device 20 includes: a second initialization module 1901, a second random write module 1902, a comparison module 1903 and a second write-back module 1904.

[0155] The second initialization module 1901 is used to initialize all circuit structure units in the array circuit.

[0156] The second random write module 1902 is used to apply a predefined write pulse to all circuit structure units to randomly change the polarization states of the ferroelectric transistors in all circuit structure units.

[0157] The comparison module 1903 is used to compare the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit to obtain a comparison result.

[0158] The second write-back module 1904 is used to write the strong positive polarization or the strong negative polarization back to the first ferroelectric transistor and the second ferroelectric transistor according to the comparison result.

[0159] In one embodiment of the present application, the second initialization module 1901 is further used to fix all first bit lines and second bit lines at a low level, and to apply a negative voltage of a third preset time length and a third preset high level on all word lines, so as to initialize all ferroelectric transistors in all circuit structure units to a strong negative polarization state.

[0160] In one embodiment of the present application, the second random write module 1902 is further used to fix all first bit lines and second bit lines at a low level, and apply a high level pulse of a fourth preset voltage and a fourth preset duration to all word lines, so that each ferroelectric transistor reaches a different polarization state.

[0161] In one embodiment of the present application, the comparison module 1903 is further used to fix all first bit lines and second bit lines at a first sensing voltage, apply a preset read voltage to the word lines row by row, and differentially amplify the current output on the first sensing line and the current output on the second sensing line through a sensing circuit to obtain a comparison result.

[0162] In one embodiment of the present application, the second write-back module 1904 is further used to write the first transistor in the circuit structure unit to a strong positive polarization or a strong negative polarization, and the second transistor to a strong negative polarization or a strong positive polarization state, respectively, according to the high level or low level of the output result of each circuit structure unit.

[0163] In one embodiment of the present application, the registration devices 10 and 20 of the challenge response pair of the array circuit also include: an update module, which is used to fix each bit line in the array circuit at a low level after the registration is completed, and apply a negative level pulse with a fifth preset duration and a fifth preset high voltage to the word line to reinitialize each ferroelectric transistor in the array circuit to re-perform the registration process.

[0164] In one embodiment of the present application, the registration devices 10 and 20 of the challenge-response pair of the array circuit further include: a writing module for synchronously applying a writing voltage to the entire array in a parallel writing manner to initialize or write a random polarization state.

[0165] Fig. 20 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0166] Memory 2001 , processor 2002 , and a computer program stored in the memory 2001 and executable on the processor 2002 .

[0167] When the processor 2002 executes the program, the registration method of the challenge-response pair of the array circuit provided in the above embodiment is implemented.

[0168] Furthermore, the electronic device further comprises:

[0169] The communication interface 2003 is used for communication between the memory 2001 and the processor 2002 .

[0170] The memory 2001 is used to store computer programs that can be executed on the processor 2002 .

[0171] The memory 2001 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0172] If the memory 2001, the processor 2002 and the communication interface 2003 are implemented independently, the communication interface 2003, the memory 2001 and the processor 2002 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnection (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 20Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0173] Optionally, in a specific implementation, if the memory 2001, the processor 2002 and the communication interface 2003 are integrated on a chip, the memory 2001, the processor 2002 and the communication interface 2003 can communicate with each other through an internal interface.

[0174] The processor 2002 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0175] This embodiment also provides a computer-readable storage medium on which a computer program is stored, wherein the program, when executed by a processor, implements the above-mentioned registration method for challenge-response pairs of an array circuit.

[0176] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0177] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0178] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0179] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0180] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

Claims

1. A method for registering challenge-response pairs of an array circuit, characterized in that: A physical unclonable function structure based on ferroelectric transistors, the physical unclonable function structure based on ferroelectric transistors comprising: an array circuit, a driving circuit, a decoding circuit and a sensing circuit; the array circuit is an array structure formed by electrically connecting a plurality of ferroelectric transistor circuit structure units to form a plurality of rows and columns, the word lines of the circuit structure units in each row are connected and connected to the decoding circuit, the bit lines of the circuit structure units in each column are connected to the sensing line, the bit lines are connected to the driving circuit, and the sensing lines are connected to the sensing circuit; the driving circuit is used to drive the word lines and bit lines of the array circuit; the decoding circuit is used to input a challenge signal and decode the input challenge signal into a corresponding address; the sensing circuit is used to generate output response signal data from the input challenge signal by utilizing the random flipping characteristics of the polarization state of the ferroelectric transistors in the array circuit; The circuit structure unit includes a ferroelectric transistor, a word line, a bit line, and a sensing line, wherein the drain of the ferroelectric transistor is connected to the sensing line, the gate of the ferroelectric transistor is connected to the word line, the source of the ferroelectric transistor is connected to the bit line, and the physical unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source; The sensing circuit comprises a plurality of sensing amplifiers, wherein the positive input terminal of the sensing amplifier is connected to the sensing line of the corresponding column of the array circuit, and the negative input terminal is connected to an adjustable reference current source input by an external circuit, and the physical unclonable function outputs the output response signal data through the output terminal of the sensing amplifier; The circuit structure unit includes a first ferroelectric transistor, a second ferroelectric transistor, a word line, a first bit line, a second bit line, a first sensing line, and a second sensing line. The drain of the first ferroelectric transistor is connected to the first sensing line, the gate of the first ferroelectric transistor is connected to the word line, and the source of the first ferroelectric transistor is connected to the first bit line; the drain of the second ferroelectric transistor is connected to the second sensing line, the gate of the second ferroelectric transistor is connected to the word line, and the source of the second ferroelectric transistor is connected to the second bit line. The physically unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source; The sensing circuit comprises a plurality of sensing amplifiers, positive and negative input terminals of the sensing amplifiers are connected to the first sensing line and the second sensing line of the corresponding column of the array circuit in a preset manner, and the physical unclonable function outputs the output response signal data through the output terminals of the sensing amplifiers; The preset mode connection is to swap the connection of the positive and negative input terminals and the connection of the positive and negative output terminals of the sense amplifier after registering the preset number of units; The circuit structure unit of the array circuit includes a ferroelectric transistor, and the registration of the challenge response pair of the array circuit includes the following steps: Initializing all circuit structure units in the array circuit; Applying a predefined write pulse to all circuit structure units to randomly change the polarization states of the ferroelectric transistors in all circuit structure units; Generate a reference state; Comparing the polarization states of all circuit structure units with the reference state, and writing strong positive polarization or strong negative polarization back to the circuit structure unit according to the comparison result; Initializing all circuit structure units in the array circuit includes: fixing all bit lines at a low level, applying a negative voltage of a first preset duration and a first preset high level to all word lines, and initializing the ferroelectric transistors in all circuit structure units to a strong negative polarization state; The step of applying a predefined write pulse to all circuit structure units to randomly change the polarization state of the ferroelectric transistors in all circuit structure units includes: fixing all bit lines at a low level, applying a high level pulse of a second preset voltage and a second preset duration to all word lines, so that the ferroelectric transistors in each circuit structure unit reach a random polarization state; The generating reference state includes: setting a priori current reference maximum value, current reference minimum value, current initial reference value and preset precision; using the current initial reference value as the current reference value, performing a reading operation on all circuit structure units of the array circuit row by row, and calculating the normalized Hamming weight of all circuit structure units of the array circuit through other circuits; when the difference between the normalized Hamming weight and the expected value is greater than the preset precision, adjusting the current reference value according to a preset ratio, and modifying the current reference maximum value or the current reference minimum value; repeatedly calculating the normalized Hamming weight of all circuit structure units of the array circuit until the difference between the normalized Hamming weight and the expected value is within the preset precision, thereby obtaining a reference current; The method of comparing the polarization states of all circuit structure units with the reference state and writing strong positive polarization or strong negative polarization back to the circuit structure unit according to the comparison result includes: comparing the current on the sensing line of each circuit structure unit with the reference current, and writing the ferroelectric transistor in the circuit structure unit to a strong positive polarization or a strong negative polarization state according to the high level or low level of the output result of each circuit structure unit.

2. A method for registering challenge-response pairs of an array circuit, characterized in that: A physical unclonable function structure based on ferroelectric transistors, the physical unclonable function structure based on ferroelectric transistors comprising: an array circuit, a driving circuit, a decoding circuit and a sensing circuit; the array circuit is an array structure formed by electrically connecting a plurality of ferroelectric transistor circuit structure units to form a plurality of rows and columns, the word lines of the circuit structure units in each row are connected and connected to the decoding circuit, the bit lines of the circuit structure units in each column are connected to the sensing line, the bit lines are connected to the driving circuit, and the sensing lines are connected to the sensing circuit; the driving circuit is used to drive the word lines and bit lines of the array circuit; the decoding circuit is used to input a challenge signal and decode the input challenge signal into a corresponding address; the sensing circuit is used to generate output response signal data from the input challenge signal by utilizing the random flipping characteristics of the polarization state of the ferroelectric transistors in the array circuit; The circuit structure unit includes a ferroelectric transistor, a word line, a bit line, and a sensing line, wherein the drain of the ferroelectric transistor is connected to the sensing line, the gate of the ferroelectric transistor is connected to the word line, the source of the ferroelectric transistor is connected to the bit line, and the physical unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source; The sensing circuit comprises a plurality of sensing amplifiers, wherein the positive input terminal of the sensing amplifier is connected to the sensing line of the corresponding column of the array circuit, and the negative input terminal is connected to an adjustable reference current source input by an external circuit, and the physical unclonable function outputs the output response signal data through the output terminal of the sensing amplifier; The circuit structure unit includes a first ferroelectric transistor, a second ferroelectric transistor, a word line, a first bit line, a second bit line, a first sensing line, and a second sensing line. The drain of the first ferroelectric transistor is connected to the first sensing line, the gate of the first ferroelectric transistor is connected to the word line, and the source of the first ferroelectric transistor is connected to the first bit line; the drain of the second ferroelectric transistor is connected to the second sensing line, the gate of the second ferroelectric transistor is connected to the word line, and the source of the second ferroelectric transistor is connected to the second bit line. The physically unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source; The sensing circuit comprises a plurality of sensing amplifiers, positive and negative input terminals of the sensing amplifiers are connected to the first sensing line and the second sensing line of the corresponding column of the array circuit in a preset manner, and the physical unclonable function outputs the output response signal data through the output terminals of the sensing amplifiers; The preset mode connection is to swap the connection of the positive and negative input terminals and the connection of the positive and negative output terminals of the sense amplifier after registering the preset number of units; The circuit structure unit of the array circuit includes the first ferroelectric transistor and the second ferroelectric transistor, and the registration of the challenge response pair of the array circuit includes the following steps: Initializing all circuit structure units in the array circuit; Applying a predefined write pulse to all circuit structure units to randomly change the polarization states of the ferroelectric transistors in all circuit structure units; Comparing the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit to obtain a comparison result; Writing strong positive polarization or strong negative polarization back to the first ferroelectric transistor and the second ferroelectric transistor according to the comparison result; initializing all circuit structure units in the array circuit, including: fixing all first bit lines and second bit lines at a low level, applying a negative voltage of a third preset duration and a third preset high level on all word lines, initializing all ferroelectric transistors in all circuit structure units to a strong negative polarization state; applying a predefined write pulse to all circuit structure units to randomly change the polarization state of the ferroelectric transistors in all circuit structure units, including: fixing all first bit lines and second bit lines at a low level, applying a high level pulse of a fourth preset voltage and a fourth preset duration on all word lines, so that each ferroelectric transistor reaches a different polarization state; The comparing the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit comprises: fixing all first bit lines and second bit lines at a first sensing voltage, applying a preset read voltage to word lines row by row, differentially amplifying the current output on the first sensing line and the current output on the second sensing line through the sensing circuit, and obtaining the comparison result; Writing strong positive polarization or strong negative polarization back to the first ferroelectric transistor and the second ferroelectric transistor according to the comparison result includes: writing the first ferroelectric transistor in the circuit structure unit to strong positive polarization or strong negative polarization, and writing the second ferroelectric transistor to strong negative polarization or strong positive polarization state according to the high level or low level of the output result of each circuit structure unit.

3. The method according to claim 1 or 2, characterized in that: The reconstruction of the challenge response pairs of the array circuit comprises the following steps: reinitializing all circuit structural units in the array circuit based on the previous registration or reconstruction; Applying a predefined write pulse to all circuit structure units, so that the polarization states of the ferroelectric transistors in all circuit structure units undergo a random change different from the previous registration or reconstruction; Re-registration process for comparison and write-back; The method of reinitializing all circuit structure units in the array circuit based on the previous registration or reconstruction includes: fixing each bit line in the array circuit at a low level, applying a negative level pulse of a fifth preset duration and a fifth preset high voltage to the word line, and reinitializing each ferroelectric transistor in the array circuit to a strong negative polarization state; The applying of a predefined write pulse to all circuit structure units causes the polarization state of the ferroelectric transistors in all circuit structure units to undergo a random change different from the previous registration, including: fixing all bit lines or all first bit lines and second bit lines at a low level, applying a high level pulse of a second preset voltage and a second preset duration or a fourth preset voltage and a fourth preset duration to all word lines, so that the ferroelectric transistors in each circuit structure unit reach a random polarization state, and the state in this reconstruction is different from the random polarization state obtained in the previous registration or reconstruction; The re-comparison and write-back registration process includes: according to the method described in claim 1, generating a reference state, comparing the polarization states of all circuit structure units with the reference state, and writing strong positive polarization or strong negative polarization back to the circuit structure unit according to the comparison result, or according to the method described in claim 2, comparing the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit to obtain a comparison result, and writing strong positive polarization or strong negative polarization back to the first ferroelectric transistor and the second ferroelectric transistor according to the comparison result.

4. A registration device for challenge-response pairs of an array circuit, characterized in that: A physical unclonable function structure based on ferroelectric transistors, the physical unclonable function structure based on ferroelectric transistors comprising: an array circuit, a driving circuit, a decoding circuit and a sensing circuit; the array circuit is an array structure formed by electrically connecting a plurality of ferroelectric transistor circuit structure units to form a plurality of rows and columns, the word lines of the circuit structure units in each row are connected and connected to the decoding circuit, the bit lines of the circuit structure units in each column are connected to the sensing line, the bit lines are connected to the driving circuit, and the sensing lines are connected to the sensing circuit; the driving circuit is used to drive the word lines and bit lines of the array circuit; the decoding circuit is used to input a challenge signal and decode the input challenge signal into a corresponding address; the sensing circuit is used to generate output response signal data from the input challenge signal by utilizing the random flipping characteristics of the polarization state of the ferroelectric transistors in the array circuit; The circuit structure unit includes a ferroelectric transistor, a word line, a bit line, and a sensing line, wherein the drain of the ferroelectric transistor is connected to the sensing line, the gate of the ferroelectric transistor is connected to the word line, the source of the ferroelectric transistor is connected to the bit line, and the physical unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source; The sensing circuit comprises a plurality of sensing amplifiers, wherein the positive input terminal of the sensing amplifier is connected to the sensing line of the corresponding column of the array circuit, and the negative input terminal is connected to an adjustable reference current source input by an external circuit, and the physical unclonable function outputs the output response signal data through the output terminal of the sensing amplifier; The circuit structure unit includes a first ferroelectric transistor, a second ferroelectric transistor, a word line, a first bit line, a second bit line, a first sensing line, and a second sensing line. The drain of the first ferroelectric transistor is connected to the first sensing line, the gate of the first ferroelectric transistor is connected to the word line, and the source of the first ferroelectric transistor is connected to the first bit line; the drain of the second ferroelectric transistor is connected to the second sensing line, the gate of the second ferroelectric transistor is connected to the word line, and the source of the second ferroelectric transistor is connected to the second bit line. The physically unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source; The sensing circuit comprises a plurality of sensing amplifiers, positive and negative input terminals of the sensing amplifiers are connected to the first sensing line and the second sensing line of the corresponding column of the array circuit in a preset manner, and the physical unclonable function outputs the output response signal data through the output terminals of the sensing amplifiers; The preset mode connection is to swap the connection of the positive and negative input terminals and the connection of the positive and negative output terminals of the sense amplifier after registering the preset number of units; The circuit structure unit of the array circuit includes a ferroelectric transistor, and the registration device of the challenge response pair of the array circuit includes: A first initialization module, used to initialize all circuit structure units in the array circuit; A first random write module is used to apply a predefined write pulse to all circuit structure units to randomly change the polarization state of the ferroelectric transistors in all circuit structure units; A reference generation module, used for generating a reference state; The first write-back module is used to compare the polarization states of all circuit structure units with the reference state, and write strong positive polarization or strong negative polarization back to the circuit structure unit according to the comparison result.

5. A registration device for challenge-response pairs of an array circuit, characterized in that: A physical unclonable function structure based on ferroelectric transistors, the physical unclonable function structure based on ferroelectric transistors comprising: an array circuit, a driving circuit, a decoding circuit and a sensing circuit; the array circuit is an array structure formed by electrically connecting a plurality of ferroelectric transistor circuit structure units to form a plurality of rows and columns, the word lines of the circuit structure units in each row are connected and connected to the decoding circuit, the bit lines of the circuit structure units in each column are connected to the sensing line, the bit lines are connected to the driving circuit, and the sensing lines are connected to the sensing circuit; the driving circuit is used to drive the word lines and bit lines of the array circuit; the decoding circuit is used to input a challenge signal and decode the input challenge signal into a corresponding address; the sensing circuit is used to generate output response signal data from the input challenge signal by utilizing the random flipping characteristics of the polarization state of the ferroelectric transistors in the array circuit; The circuit structure unit includes a ferroelectric transistor, a word line, a bit line, and a sensing line, wherein the drain of the ferroelectric transistor is connected to the sensing line, the gate of the ferroelectric transistor is connected to the word line, the source of the ferroelectric transistor is connected to the bit line, and the physical unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source; The sensing circuit comprises a plurality of sensing amplifiers, wherein the positive input terminal of the sensing amplifier is connected to the sensing line of the corresponding column of the array circuit, and the negative input terminal is connected to an adjustable reference current source input by an external circuit, and the physical unclonable function outputs the output response signal data through the output terminal of the sensing amplifier; The circuit structure unit includes a first ferroelectric transistor, a second ferroelectric transistor, a word line, a first bit line, a second bit line, a first sensing line, and a second sensing line. The drain of the first ferroelectric transistor is connected to the first sensing line, the gate of the first ferroelectric transistor is connected to the word line, and the source of the first ferroelectric transistor is connected to the first bit line; the drain of the second ferroelectric transistor is connected to the second sensing line, the gate of the second ferroelectric transistor is connected to the word line, and the source of the second ferroelectric transistor is connected to the second bit line. The physically unclonable function uses the polarization state of the ferroelectric material of the ferroelectric transistor as an entropy source; The sensing circuit comprises a plurality of sensing amplifiers, positive and negative input terminals of the sensing amplifiers are connected to the first sensing line and the second sensing line of the corresponding column of the array circuit in a preset manner, and the physical unclonable function outputs the output response signal data through the output terminals of the sensing amplifiers; The preset mode connection is to swap the connection of the positive and negative input terminals and the connection of the positive and negative output terminals of the sense amplifier after registering the preset number of units; The circuit structure unit of the array circuit includes the first ferroelectric transistor and the second ferroelectric transistor, and the registration device of the challenge response pair of the array circuit includes: A second initialization module, used for initializing all circuit structure units in the array circuit; A second random write module is used to apply a predefined write pulse to all circuit structure units to randomly change the polarization state of the ferroelectric transistors in all circuit structure units; A comparison module, used for comparing the polarization states of the first ferroelectric transistor and the second ferroelectric transistor in the array circuit to obtain a comparison result; The second write-back module is used to write the strong positive polarization or the strong negative polarization back to the first ferroelectric transistor and the second ferroelectric transistor according to the comparison result.

6. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the registration method for challenge-response pairs of an array circuit as claimed in any one of claims 1 to 2.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the registration method of challenge-response pairs of an array circuit as described in any one of claims 1-2.

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