Array substrate and preparation method thereof, and display panel

Abstract

The present application provides an array substrate and a preparation method thereof, and a display panel, which relate to the field of display technology. The array substrate comprises a substrate; a gate layer, comprising a plurality of gates and a plurality of gate lines; a semiconductor light-transmitting layer, located on a side of the gate layer away from the substrate, comprising a plurality of active layers and a plurality of first storage electrode lines; and a plurality of pixel electrodes, located on a side of the semiconductor light-transmitting layer away from the substrate; wherein the orthographic projection of the active layer on the substrate is located within the orthographic projection of the gate on the substrate, the first storage electrode line extends in a direction parallel to the gate line, the orthographic projection of the first storage electrode line on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the first storage electrode line on the substrate does not overlap with the orthographic projection of the gate layer on the substrate. The aperture ratio of the array substrate is improved, thereby being able to improve the overall light transmittance of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] With the rapid development of display technology, people's demand for high-transmittance display panels continues to increase. In the related art, the storage capacitor of the display panel is composed of a partial area of ​​the gate metal layer and the pixel electrode, and the orthographic projection of the pixel electrode on the substrate of the display panel and the orthographic projection of the gate metal layer on the substrate of the display panel do not overlap each other. In this way, since the gate metal layer is not light-transmissive, the light transmittance of the display panel is seriously reduced.

[0003] Currently, there is an urgent need for a display panel to solve the above problems. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a method for manufacturing the same, and a display panel. The aperture ratio of the array substrate is improved, thereby being able to improve the overall light transmittance of the display panel.

[0005] The embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides an array substrate, comprising:

[0007] substrate;

[0008] A gate layer, comprising a plurality of gates and a plurality of gate lines;

[0009] A semiconductor light-transmitting layer, located on a side of the gate layer away from the substrate, comprising a plurality of active layers and a plurality of first storage electrode lines;

[0010] A plurality of pixel electrodes are located on a side of the semiconductor light-transmitting layer away from the substrate;

[0011] The orthographic projection of the active layer on the substrate is within the orthographic projection of the gate on the substrate, the first storage electrode line extends in a direction parallel to the gate line, the orthographic projection of the first storage electrode line on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the first storage electrode line on the substrate does not overlap with the orthographic projection of the gate layer on the substrate.

[0012] In some embodiments of the present application, materials of the active layer and the first storage electrode line are both metal oxide semiconductor materials, and the oxygen content of the material of the first storage electrode line is less than the oxygen content of the material of the active layer.

[0013] In some embodiments of the present application, the array substrate further comprises a source-drain metal layer, and the source-drain metal layer is located on a side of the semiconductor light-transmitting layer away from the substrate;

[0014] The source-drain metal layer includes a plurality of source electrodes and a plurality of drain electrodes, and the source electrodes and the drain electrodes are in direct contact with the active layer respectively.

[0015] In some embodiments of the present application, the source-drain metal layer further includes a plurality of data lines, the data lines intersect and are insulated from the gate lines, and the data lines and the gate lines define an area where the pixel electrode is located;

[0016] Wherein, the first storage electrode line and the data line intersect and are insulated;

[0017] Alternatively, the first storage electrode line is disconnected at a region where it overlaps with the data line in a direction perpendicular to the substrate.

[0018] In some embodiments of the present application, the semiconductor light-transmitting layer further includes a plurality of second storage electrode lines, the second storage electrode lines extend in a direction parallel to the data lines and intersect with the first storage electrode lines, and are electrically connected at the intersection of the two;

[0019] In a case where the first storage electrode lines intersect and are insulated from the data lines, each of the second storage electrode lines is disconnected at a region where it overlaps with the gate line in a direction perpendicular to the substrate.

[0020] In some embodiments of the present application, the semiconductor light-transmitting layer further includes a plurality of second storage electrode lines, the second storage electrode lines extend in a direction parallel to the data lines and intersect with the first storage electrode lines, and are electrically connected at the intersection of the two;

[0021] In a case where the first storage electrode line is disposed disconnected at a region overlapping the data line in a direction perpendicular to the substrate, the second storage electrode line intersects and is insulated from the gate line.

[0022] In some embodiments of the present application, the array substrate further comprises a plurality of auxiliary data lines, and the data lines are located on a side of the auxiliary data lines away from the substrate;

[0023] The orthographic projection of the data line on the substrate is located within the orthographic projection of the auxiliary data line on the substrate, the auxiliary data line and the first storage electrode line are arranged in the same layer, and the orthographic projection of the auxiliary data line on the substrate and the orthographic projection of the first storage electrode line on the substrate do not overlap each other.

[0024] In some embodiments of the present application, the orthographic projection of the first storage electrode line on the substrate overlaps with the orthographic projection of the side of the pixel electrode parallel to the gate line on the substrate;

[0025] An orthographic projection of the second storage electrode line on the substrate overlaps with an orthographic projection of a side of the pixel electrode parallel to the data line on the substrate.

[0026] In some embodiments of the present application, the orthographic projection of the first storage electrode line on the substrate overlaps with the orthographic projection of the middle area of ​​the pixel electrode on the substrate, and the orthographic projection of the second storage electrode line on the substrate overlaps with the orthographic projection of the side of the pixel electrode parallel to the data line on the substrate.

[0027] In some embodiments of the present application, the gate electrode, the source electrode, the drain electrode and the active layer constitute a thin film transistor;

[0028] The region where the gate line overlaps with the active layer in a direction perpendicular to the substrate serves as the gate, and the orthographic projection of the thin film transistor on the substrate is within the orthographic projection of the gate line on the substrate.

[0029] In some embodiments of the present application, the array substrate further comprises a passivation layer, the passivation layer is located on a side of the source-drain metal layer away from the substrate, the passivation layer has a plurality of penetrating vias, the drain electrode is electrically connected to the pixel electrode through the vias, and the source electrode is electrically connected to the data line;

[0030] The orthographic projection of the outer contour of the via hole on the substrate is located within the orthographic projection of the pixel electrode on the substrate.

[0031] In some embodiments of the present application, an orthographic projection of an outer contour of the via hole on the substrate is also located within an orthographic projection of the first storage electrode line on the substrate.

[0032] In a second aspect, an embodiment of the present application provides a display panel, comprising the array substrate as described above.

[0033] In a third aspect, an embodiment of the present application provides a method for preparing an array substrate, the method comprising:

[0034] providing a substrate;

[0035] forming a gate layer, wherein the gate layer includes a plurality of gates and a plurality of gate lines;

[0036] forming a semiconductor light-transmitting layer, the semiconductor light-transmitting layer being located on a side of the gate layer away from the substrate and comprising a plurality of active layers and a plurality of first storage electrode lines; the orthographic projection of the active layer on the substrate being located within the orthographic projection of the gate on the substrate, the first storage electrode line extending in a direction parallel to the gate line; the orthographic projection of the first storage electrode line on the substrate and the orthographic projection of the gate layer on the substrate not overlapping each other;

[0037] A plurality of pixel electrodes are formed, wherein the pixel electrodes are located on a side of the semiconductor light-transmitting layer away from the substrate; and an orthographic projection of the first storage electrode line on the substrate overlaps with an orthographic projection of the pixel electrode on the substrate.

[0038] In some embodiments of the present application, after forming the gate layer and before forming the plurality of pixel electrodes, the method further includes:

[0039] Forming an auxiliary data line; wherein the auxiliary data line and the semiconductor light-transmitting layer are prepared by a single patterning process;

[0040] A data line is formed on the auxiliary data line; and an orthographic projection of the data line on the substrate is located within an orthographic projection of the auxiliary data line on the substrate.

[0041] In some embodiments of the present application, forming a semiconductor light-transmitting layer includes:

[0042] Patterning to form a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, wherein the second metal oxide semiconductor layer covers the first metal oxide semiconductor layer;

[0043] Conducting the second metal oxide semiconductor layer to form a conductor layer; a shielding layer is provided on a side of the conductor layer away from the substrate; the shielding layer exposes a part of the conductor layer;

[0044] Under the shielding of the shielding layer, the conductor layer is patterned to obtain the active layer and the first storage electrode line at the same time.

[0045] An embodiment of the present application provides an array substrate and a preparation method thereof, and a display panel, wherein the array substrate includes a substrate; a gate layer, including a plurality of gates and a plurality of gate lines; a semiconductor light-transmitting layer, located on a side of the gate layer away from the substrate, including a plurality of active layers and a plurality of first storage electrode lines; and a plurality of pixel electrodes, located on a side of the semiconductor light-transmitting layer away from the substrate; wherein the orthographic projection of the active layer on the substrate is located within the orthographic projection of the gate on the substrate, the first storage electrode line extends in a direction parallel to the gate line, the orthographic projection of the first storage electrode line on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the first storage electrode line on the substrate does not overlap with the orthographic projection of the gate layer on the substrate.

[0046] In an embodiment of the present application, the semiconductor light-transmitting layer includes an active layer and a first storage electrode line, the first storage electrode line extends in a direction parallel to the gate line, and the orthographic projection of the first storage electrode line on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate. In this way, the first storage electrode line and the pixel electrode constitute a light-transmitting storage capacitor, thereby increasing the aperture ratio of the array substrate, thereby improving the transmittance of the array substrate, improving the transmittance of the display panel, and reducing the power consumption of the display panel.

[0047] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1-Figure 4 Structural schematic diagrams of array substrates in four related technologies provided in the embodiments of the present application;

[0050] Figure 5-Figure 12 Structural schematic diagrams of eight array substrates with different structures provided in the embodiments of the present application;

[0051] Fig.13 A flow chart of a method for preparing an array substrate provided in an embodiment of the present application;

[0052] Figure 14-17 A schematic diagram of an intermediate structure of an array substrate preparation process provided in an embodiment of the present application;

[0053] Figure 18-Figure 20 A schematic diagram of an intermediate structure of a process for preparing a semiconductor light-transmitting layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings represent the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present application and are not necessarily drawn to scale.

[0056] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0057] In the embodiments of the present application, words such as "first" and "second" are used to indicate parts of identical or similar items having substantially the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0058] The embodiment of the present application provides an array substrate, referring to Figure 6 , Figure 7 and Figure 8 As shown, including:

[0059] Substrate 100;

[0060] A gate layer, comprising a plurality of gates and a plurality of gate lines 1;

[0061] The semiconductor light-transmitting layer 6 is located on a side of the gate layer away from the substrate 100 and includes a plurality of active layers 31 and a plurality of first storage electrode lines 22;

[0062] A plurality of pixel electrodes 5 are located on a side of the semiconductor light-transmitting layer 6 away from the substrate 100;

[0063] Among them, the orthographic projection of the active layer 31 on the substrate 100 is located within the orthographic projection of the gate on the substrate 100, the first storage electrode line 22 extends in a direction parallel to the gate line 1, the orthographic projection of the first storage electrode line 22 on the substrate 100 overlaps with the orthographic projection of the pixel electrode 5 on the substrate 100, and the orthographic projection of the first storage electrode line 22 on the substrate 100 does not overlap with the orthographic projection of the gate layer (including the gate and the gate line 1) on the substrate 100.

[0064] The first storage electrode line 22 and the pixel electrode 5 constitute a storage capacitor of the array substrate; wherein the semiconductor light-transmitting layer 6 is made of a light-transmitting material, and the pixel electrode 5 is also made of a light-transmitting material, thereby constituting a storage capacitor with light-transmitting properties.

[0065] In an exemplary embodiment, the material of the active layer 31 is a metal oxide semiconductor material, the material of the first storage electrode line 22 is formed by conducting the metal oxide semiconductor material of the active layer 31, and the active layer 31 and the first storage electrode line 22 are formed by patterning the same metal oxide semiconductor layer using a single patterning process. Since the metal oxide semiconductor layer is light-transmitting, in this application, the metal oxide semiconductor layer is referred to as a semiconductor light-transmitting layer 6.

[0066] The one-time patterning process refers to a process of forming a required layer structure through one exposure, and the one-time patterning process includes masking, exposure, development, etching and stripping.

[0067] In practical applications, the first metal oxide semiconductor layer and the second metal oxide semiconductor layer can be patterned by a half-tone mask process, the second metal oxide semiconductor layer covers the first metal oxide semiconductor layer, and the second metal oxide semiconductor layer is subjected to a conductor treatment to form a conductor layer; a shielding layer is provided on the side of the conductor layer away from the substrate; under the shielding of the shielding layer, the conductor layer is patterned to remove the conductor layer in a part of the area, and a part of the area of ​​the first metal oxide semiconductor layer is exposed to simultaneously obtain the active layer 31 and the first storage electrode line 22. It can be understood that the active layer 31 includes a semiconductor layer, and the first storage electrode line 22 includes a semiconductor layer and a conductor layer located on the side of the semiconductor layer away from the substrate. Before the conductor treatment, the first metal oxide semiconductor layer and the second metal oxide semiconductor layer are made of the same material.

[0068] In an exemplary embodiment, the region where the gate line 1 overlaps the active layer 31 in a direction perpendicular to the substrate 100 serves as a gate. It can be understood that a portion of the gate line 1 serves as a gate.

[0069] In some embodiments of the present application, the materials of the active layer 31 and the first storage electrode line 22 are both metal oxide semiconductor materials, and the oxygen content of the material of the first storage electrode line 22 is less than that of the material of the active layer 31 .

[0070] In an exemplary embodiment, the metal oxide semiconductor material may be any one of metal oxides such as IGZO (Indium Gallium Zinc Oxide) or ITZO (Indium Tin Zinc Oxide).

[0071] The above-mentioned orthographic projection of the active layer 31 on the substrate 100 is located within the orthographic projection of the gate on the substrate 100. This means that the projection of the outer contour of the active layer 31 on the substrate 100 in the direction perpendicular to the substrate 100 is located within the projection of the outer contour of the gate on the substrate 100 in the direction perpendicular to the substrate 100; or, the projection of the outer contour of the active layer 31 on the substrate 100 in the direction perpendicular to the substrate 100 overlaps with the projection of the outer contour of the gate on the substrate 100 in the direction perpendicular to the substrate 100.

[0072] In this application, the meaning of “orthographic projection on the substrate” is: the projection on the substrate in a direction perpendicular to the substrate, which will not be elaborated.

[0073] refer to Figure 6-Figure 8 As shown, the orthographic projection of the first storage electrode line 22 on the substrate 100 overlaps with the orthographic projection of the pixel electrode 5 on the substrate 100, but the overlap is not complete, so that the electric field of the storage capacitor formed by the first storage electrode line 22 and the pixel electrode 5 is not completely a parallel electric field. The size of the overlapping area between the first storage electrode line 22 and the pixel electrode 5 is not limited here, and is determined according to actual conditions.

[0074] In an exemplary embodiment, the thickness of the gate layer along the direction perpendicular to the substrate 100 ranges from

[0075] In an exemplary embodiment, the material of the gate layer may be any one or more combinations of copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), molybdenum niobium (MoNb), and molybdenum niobium titanium (MoNiTi).

[0076] In an exemplary embodiment, the material of the pixel electrode 5 is ITO (Indium Tin Oxides) or IZO (Indium Zinc Oxide).

[0077] It should be noted that the array substrate is an LCD (Liquid Crystal Display) type array substrate, and the array substrate is applied to an LCD display panel.

[0078] In an embodiment of the present application, the semiconductor light-transmitting layer 6 includes an active layer 31 and a first storage electrode line 22, the first storage electrode line 22 extends in a direction parallel to the gate line 1, and the orthographic projection of the first storage electrode line 22 on the substrate 100 overlaps with the orthographic projection of the pixel electrode 5 on the substrate 100. In this way, the first storage electrode line 22 and the pixel electrode 4 constitute a light-transmitting storage capacitor, thereby increasing the aperture ratio of the array substrate, and then improving the transmittance of the array substrate, improving the transmittance of the display panel, and reducing the power consumption of the display panel.

[0079] Among them, relative to Figure 1 and Figure 2 The array substrate of the related art shown in the figure makes the storage electrode lines (21 and 22) and the gate line 1 prepared in the same layer by a single patterning process, the orthographic projection of the storage electrode line on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate, and the aperture ratio of the array substrate is 66.5%. Figure 6 The aperture ratio of the array substrate shown is increased to 85.5%, and the aperture ratio is increased by 19%, which greatly improves the light transmittance of the array substrate. Figure 1 yes Figure 2 Cross-sectional view along direction A1A2.

[0080] Compared to Figure 3 The array substrate of the related art shown in FIG. 1 has an aperture ratio of 65.9%. The embodiment of the present application provides Figure 7 The aperture ratio of the array substrate shown is increased to 80%, and the aperture ratio is increased by 14.1%, which greatly improves the light transmittance of the array substrate.

[0081] In some embodiments of the present application, reference Figure 5 As shown, the array substrate also includes a source-drain metal layer, which is located on the side of the semiconductor light-transmitting layer 6 (including the active layer 31 and the second storage electrode line 21) away from the substrate 100; the source-drain metal layer includes a plurality of source electrodes 32 and a plurality of drain electrodes 33, and the source electrodes 32 and the drain electrodes 33 are in direct contact with the active layer 31 respectively.

[0082] In an embodiment of the present application, by arranging the source 32 and the drain 33 on the active layer 31 so that the source 32 and the drain 33 are in direct contact with the active layer 31 respectively, the contact resistance can be reduced to a great extent. When a conductive channel is formed in the active layer 31, the loss of channel current due to resistance heat generation is reduced.

[0083] In some embodiments of the present application, the source-drain metal layer further includes a plurality of data lines 4, the data lines 4 intersect and are insulated from the gate lines 1, and the data lines 4 and the gate lines 1 define an area where the pixel electrodes 5 are located;

[0084] Among them, reference Figure 6 , Figure 7 and Figure 8 As shown, the first storage electrode line 22 and the data line 4 intersect and are insulated;

[0085] Or, refer to Fig.11 and Fig.12 As shown, the first storage electrode line 22 is disconnected at a region where it overlaps with the data line 4 in a direction perpendicular to the substrate 100 .

[0086] In an exemplary embodiment, reference Figure 6 and Figure 7 As shown, the first storage electrode line 22 and the data line 4 intersect and are insulated, and the first storage electrode line 22 passes through the area where the plurality of pixel electrodes 5 are located along a direction parallel to the gate line 1. It can be understood that the orthographic projection of the same row of pixel electrodes 5 along the direction parallel to the gate line 1 on the substrate 100 overlaps with the orthographic projection of the same first storage electrode line 22 on the substrate 100.

[0087] In an exemplary embodiment, reference Fig.11 and Fig.12 As shown, the first storage electrode line 22 is disconnected at the area where it overlaps with the data line 4 in a direction perpendicular to the substrate 100. It can be understood that the first storage electrode line 22 includes a plurality of first storage electrode line segments, and the number of first storage electrode line segments included in one first storage electrode line 22 is the same as the number of pixel electrodes 5 in the same row in a direction parallel to the gate line 1. Fig.11 and Fig.12 In the embodiment, the position where the first storage electrode line 22 is disconnected is marked as D2.

[0088] In some embodiments of the present application, reference Figure 6 and Figure 7 As shown, the semiconductor light-transmitting layer 6 further includes a plurality of second storage electrode lines 21, which extend in a direction parallel to the data lines 4 and intersect with the first storage electrode lines 22, and are electrically connected at the intersection of the two.

[0089] In a case where the first storage electrode lines 22 intersect and are insulated from the data lines 4 , each second storage electrode line 21 is disconnected at a region where it overlaps with the gate line 1 in a direction perpendicular to the substrate 100 .

[0090] Among them, Figure 6 and Figure 7 In the embodiment, the position where the second storage electrode line 21 is disconnected is marked as D1.

[0091] In some embodiments of the present application, reference Fig.11 and Fig.12 As shown, the semiconductor light-transmitting layer 6 further includes a plurality of second storage electrode lines 21, which extend in a direction parallel to the data lines 4 and intersect with the first storage electrode lines 22, and are electrically connected at the intersection of the two.

[0092] In the case where the first storage electrode line 22 is disconnected at the region where it overlaps with the data line 4 in a direction perpendicular to the substrate 100, the second storage electrode line 21 intersects and is insulated from the gate line 1. It can be understood that, at this time, the orthographic projection of the same row of pixel electrodes 5 arranged parallel to the data line 4 on the substrate 100 overlaps with the orthographic projection of the same second storage electrode line 21 on the substrate 100.

[0093] In some embodiments of the present application, reference Fig.11 and Fig.12 As shown, the array substrate further includes a plurality of auxiliary data lines 41, and the data lines 4 are located on a side of the auxiliary data lines 41 away from the substrate 100;

[0094] The orthographic projection of the data line 4 on the substrate 100 is located within the orthographic projection of the auxiliary data line 41 on the substrate 100, the auxiliary data line 41 and the first storage electrode line 22 are arranged in the same layer, and the orthographic projection of the auxiliary data line 41 on the substrate 100 and the orthographic projection of the first storage electrode line 22 on the substrate 100 do not overlap each other. Fig.10 for Fig.11 Cross-section along C1C2 analysis.

[0095] In an exemplary embodiment, the orthographic projection of the data line 4 on the substrate 100 is located within the orthographic projection of the auxiliary data line 41 on the substrate, which means that the orthographic projection of the outer contour of the data line 4 on the substrate 100 is located within the orthographic projection of the outer contour of the auxiliary data line 41 on the substrate 100; or, the orthographic projection of the outer contour of the data line 4 on the substrate 100 and the orthographic projection of the outer contour of the auxiliary data line 41 on the substrate 100 overlap.

[0096] In the drawings provided in the embodiments of the present application, in order to illustrate the position of the auxiliary data line 41 , it is drawn as an example that the orthographic projection of the outer contour of the data line 4 on the substrate 100 is located within the orthographic projection of the outer contour of the auxiliary data line 41 on the substrate 100 .

[0097] In the embodiment of the present application, the material of the auxiliary data line 41 is a metal oxide semiconductor material that has been conductorized. The auxiliary data line 41 and the first storage electrode line 22 are arranged in the same layer and made of the same material. In addition, since the auxiliary data line 41 and the first storage electrode line 22 are arranged in the same layer, the auxiliary data line 41 and the data line 4 are electrically connected. In order to avoid a short circuit between the first storage electrode line 22 and the data line 4, the orthographic projection of the auxiliary data line 41 on the substrate 100 and the orthographic projection of the first storage electrode line 22 on the substrate 100 are arranged not to overlap each other.

[0098] In the embodiment of the present application, by providing an auxiliary data line 41 on the same layer as the first storage electrode line 22, the resistance of the data line 4 is reduced and the carrier transmission channel of the data line 4 is increased without increasing the preparation process steps. In practical applications, on the basis of the current line width of the data line 4, the line widths of the data line 4 and the auxiliary data line 41 can be further reduced, and the transmittance of the array substrate can be improved, while ensuring the normal electrical signal transmission function of the data line 4.

[0099] In some embodiments of the present application, reference Figure 6 and Figure 8 As shown, the orthographic projection of the first storage electrode line 22 on the substrate 100 overlaps with the orthographic projection of the side of the pixel electrode 5 parallel to the gate line 1 on the substrate 100;

[0100] refer to Figure 6 As shown, the orthographic projection of the second storage electrode line 21 on the substrate 100 overlaps with the orthographic projection of the side of the pixel electrode 5 parallel to the data line 4 on the substrate 100 .

[0101] In some embodiments of the present application, reference Figure 7 As shown, the orthographic projection of the first storage electrode line 22 on the substrate 100 overlaps with the orthographic projection of the middle area of ​​the pixel electrode 5 on the substrate 100 , and the orthographic projection of the second storage electrode line 21 on the substrate 100 overlaps with the orthographic projection of the side of the pixel electrode 5 parallel to the data line 4 on the substrate 100 .

[0102] In an embodiment of the present application, by setting the orthographic projection of the storage electrode line (21 or 22) on the substrate 100 to not completely overlap with the orthographic projection of the pixel electrode 5 on the substrate 100, the transmittance of the array substrate is improved while meeting the capacitance requirement of the storage capacitor formed by the storage electrode line and the pixel electrode 5.

[0103] In some embodiments of the present application, Figure 5 and Figure 6 As shown, the gate electrode, the source electrode 32, the drain electrode 33 and the active layer 31 constitute a thin film transistor 3;

[0104] The area where the gate line 1 overlaps with the active layer 31 in a direction perpendicular to the substrate 100 serves as a gate, and the orthographic projection of the thin film transistor 3 on the substrate 100 is located within the orthographic projection of the gate line 1 on the substrate 100 .

[0105] In an embodiment of the present application, the area where the gate line 1 overlaps with the active layer 31 in a direction perpendicular to the substrate 100 is used as a gate, and the orthographic projection of the thin film transistor 3 on the substrate 100 is set to be within the orthographic projection of the gate line 1 on the substrate 100. On the one hand, the gate line plays a shading role for the thin film transistor 3, thereby improving the electrical performance of the thin film transistor. On the other hand, the negative impact on the aperture ratio caused by setting the thin film transistor 3 in the area where the pixel electrode 5 is located is avoided, thereby improving the light transmittance of the array substrate.

[0106] In some embodiments of the present application, reference Figure 5 and Fig. 9 As shown, the array substrate further includes a passivation layer 102, which is located on a side of the source-drain metal layer (including the data line 4, the source electrode 32 and the drain electrode 33) away from the substrate 100, and the passivation layer 102 has a plurality of through-holes, the drain electrode 33 is electrically connected to the pixel electrode 5 through the via holes, and the source electrode 32 is electrically connected to the data line 4;

[0107] Among them, reference Figure 6 and Figure 7 As shown, the orthographic projection of the outer contour of the via hole 7 on the substrate 100 is located within the orthographic projection of the pixel electrode 5 on the substrate 100 .

[0108] In an exemplary embodiment, the passivation layer 102 may be a single-layer silicon nitride, or a single-layer silicon oxide, or a double-layer silicon oxide layer and a silicon nitride layer, which may be determined according to the design and is not limited here.

[0109] The embodiment of the present application further includes a gate insulating layer 101 . The gate insulating layer 101 covers the gate layer. The gate insulating layer 101 is located between the gate layer and the semiconductor light-transmitting layer 6 .

[0110] In an exemplary embodiment, the material of the gate insulating layer 101 may be any one of silicon nitride (SiNx), silicon oxide (SiO2), and silicon oxynitride (SiNxOy).

[0111] In some embodiments of the present application, reference Figure 8 As shown, the orthographic projection of the outer contour of the via hole 7 on the substrate 100 is also located within the orthographic projection of the first storage electrode line 22 on the substrate 100 .

[0112] Figure 4An array substrate in the related art is shown, wherein the storage electrode line (22) and the gate line 1 are prepared in the same layer by a one-time patterning process, and the storage electrode line blocks light, thereby greatly reducing the aperture ratio.

[0113] Relative to Figure 4 The array substrate shown in the embodiment of the present application provides Figure 8 In the array substrate shown, the semiconductor light-transmitting layer 6 includes an active layer 31 and a first storage electrode line 22. The first storage electrode line 22 extends in a direction parallel to the gate line 1. The orthographic projection of the first storage electrode line 22 on the substrate 100 overlaps with the orthographic projection of the pixel electrode 5 on the substrate 100. In this way, the first storage electrode line 22 and the pixel electrode 4 constitute a light-transmitting storage capacitor, thereby increasing the aperture ratio of the array substrate, thereby improving the transmittance of the array substrate, improving the transmittance of the display panel, and reducing the power consumption of the display panel.

[0114] It should be noted that in the drawings provided in the embodiments of the present application, the light-transmitting area is marked as T. Figure 1 The light-transmissive region T in the related art shown in FIG. Figure 5 As shown in the light-transmitting area T, it is obvious that the size of the light-transmitting area T is significantly increased.

[0115] An embodiment of the present application provides a display panel, comprising the above array substrate.

[0116] The specific structure of the array substrate included in the display panel will not be described in detail here, and the details can be referred to the above description.

[0117] The above-mentioned display panel is a liquid crystal display panel, wherein the liquid crystal display panel can be a TN (Twisted Nematic) type, VA (Vertical Alignment) type, IPS (In-Plane Switching) type or ADS (Advanced Super Dimension Switch) type liquid crystal display screen. The liquid crystal display screen may include an array substrate and a color filter substrate, and may also include a liquid crystal located between the array substrate and the color filter substrate; of course, it may also include other structures such as a driving circuit. Only structures related to the invention point are introduced here, and other structures included in the display panel can be obtained according to relevant technologies or common knowledge, and will not be repeated here.

[0118] In the display panel provided by the embodiment of the present application, since the semiconductor light-transmitting layer 6 includes an active layer 31 and a first storage electrode line 22, the first storage electrode line 22 extends in a direction parallel to the gate line 1, and the orthographic projection of the first storage electrode line 22 on the substrate 100 overlaps with the orthographic projection of the pixel electrode 5 on the substrate 100. In this way, the first storage electrode line 22 and the pixel electrode 4 constitute a light-transmitting storage capacitor, thereby increasing the aperture ratio of the display panel, improving the transmittance of the display panel, and reducing the power consumption of the display panel.

[0119] The embodiment of the present application provides a method for preparing an array substrate. Fig.13 As shown, the method includes:

[0120] S901, provide Fig.14 The substrate 100 is shown;

[0121] S902, forming Fig.14 The gate layer 103 shown includes a plurality of gates and a plurality of gate lines 1;

[0122] S903, forming Fig.15 The semiconductor light-transmitting layer 6 shown is located on the side of the gate layer 103 away from the substrate 100, and includes a plurality of active layers 31 and a plurality of first storage electrode lines 22; the orthographic projection of the active layer 31 on the substrate 100 is located within the orthographic projection of the gate on the substrate 100, and the first storage electrode line 22 extends in a direction parallel to the gate line 1; the orthographic projection of the first storage electrode line 22 on the substrate 100 does not overlap with the orthographic projection of the gate layer 103 on the substrate 100;

[0123] In some embodiments of the present application, the materials of the active layer 31 and the first storage electrode line 22 are both metal oxide semiconductor materials, and the oxygen content of the material of the first storage electrode line 22 is less than that of the material of the active layer 31 .

[0124] In an exemplary embodiment, the metal oxide semiconductor material may be any one of metal oxides such as IGZO (Indium Gallium Zinc Oxide) or ITZO (Indium Tin Zinc Oxide).

[0125] S904, forming Figure 5 The multiple pixel electrodes 5 shown are located on a side of the semiconductor light-transmitting layer 6 away from the substrate 100 ; the orthographic projection of the first storage electrode line 22 on the substrate 100 overlaps with the orthographic projection of the pixel electrode 5 on the substrate 100 .

[0126] In the array substrate prepared by the preparation method provided in the embodiment of the present application, since the semiconductor light-transmitting layer 6 includes an active layer 31 and a first storage electrode line 22, the first storage electrode line 22 extends in a direction parallel to the gate line 1, and the orthographic projection of the first storage electrode line 22 on the substrate 100 overlaps with the orthographic projection of the pixel electrode 5 on the substrate 100. In this way, the first storage electrode line 22 and the pixel electrode 4 constitute a storage capacitor that is capable of transmitting light, thereby increasing the aperture ratio of the array substrate, improving the transmittance of the array substrate, and reducing the power consumption of the display panel prepared by the array substrate.

[0127] In some embodiments of the present application, after forming the gate layer in step S902 and before forming a plurality of pixel electrodes in step S904, the method further includes:

[0128] S905, forming an auxiliary data line 41; wherein the auxiliary data line 41 and the semiconductor light-transmitting layer 6 are prepared by a single patterning process;

[0129] S906 , forming a data line 4 on the auxiliary data line 41 ; the orthographic projection of the data line 4 on the substrate 100 is located within the orthographic projection of the auxiliary data line 41 on the substrate 100 .

[0130] In practical applications, when forming the auxiliary data line 41, a metal oxide semiconductor layer is patterned by a half-tone mask process, and the surface of the metal oxide semiconductor layer is subjected to conductor processing and then patterned again to expose part of the semiconductor layer, and the exposed semiconductor layer is used as the active layer 31, and a part of the conductorized metal oxide semiconductor layer is used as the first storage electrode line 22, and a part of the conductorized metal oxide semiconductor layer is used as the auxiliary data line 41. It can be understood that the active layer 31 includes a semiconductor layer, and the first storage electrode line 22 and the auxiliary data line 41 both include a semiconductor layer and a conductor layer located on a side of the semiconductor layer away from the substrate.

[0131] In the embodiment of the present application, by providing an auxiliary data line 41 on the same layer as the first storage electrode line 22, the resistance of the data line 4 is reduced and the carrier transmission channel of the data line 4 is increased without increasing the preparation process steps. In practical applications, on the basis of the current line width of the data line 4, the line widths of the data line 4 and the auxiliary data line 41 can be further reduced, and the transmittance of the array substrate can be improved, while ensuring the normal electrical signal transmission function of the data line 4.

[0132] In some embodiments of the present application, step S903, forming a semiconductor light-transmitting layer, includes:

[0133] S9031, Reference Fig.18As shown, a first metal oxide semiconductor layer 61 and a second metal oxide semiconductor layer 62 are patterned to form, and the second metal oxide semiconductor layer 62 covers the first metal oxide semiconductor layer 61;

[0134] S9032, conducting the second metal oxide semiconductor layer 62 to form Fig.19 The conductor layer 63 shown; a shielding layer 10 is provided on one side of the conductor layer 63 away from the substrate 100; the shielding layer 10 exposes a part of the conductor layer 63;

[0135] S9033, under the shielding of the shielding layer 10, the conductor layer 63 is patterned to obtain Fig. 20 The active layer 31 and the first storage electrode line 22 are shown. Fig. 20 The structure of the first storage electrode line 22 is not shown in the figure. The structure of the first storage electrode line 22 can be seen in FIG. Fig. 20 The second storage electrode line 21 is formed in the middle.

[0136] In the embodiment of the present application, the first metal oxide semiconductor layer 61 and the second metal oxide semiconductor layer 62 are patterned by a half-tone mask process, the second metal oxide semiconductor layer 62 covers the first metal oxide semiconductor layer 61, and the second metal oxide semiconductor layer 62 is subjected to a conductor treatment to form a conductor layer 63; a shielding layer 10 is provided on the side of the conductor layer 63 away from the substrate 100; under the shielding of the shielding layer 10, the conductor layer 63 is patterned to remove the conductor layer in a part of the area, and expose a part of the first metal oxide semiconductor layer 61, so as to obtain the active layer 31 and the first storage electrode line 22 at the same time. It can be understood that the active layer 31 includes a semiconductor layer, and the first storage electrode line 22 includes a semiconductor layer and a conductor layer located on the side of the semiconductor layer away from the substrate. Before the conductor treatment, the first metal oxide semiconductor layer 61 and the second metal oxide semiconductor layer 62 are made of the same material.

[0137] It should be noted that the above method for forming a semiconductor light-transmitting layer can be applied in a 5-Mask preparation process, or can also be applied in a 4-Mask preparation process.

[0138] Below Figure 5 Taking the structure shown as an example, the preparation method of the array substrate in the embodiment of the present application is specifically described, and the method is a 5Mask preparation process:

[0139] S01, providing a substrate 100; forming a gate film on the substrate, using a first mask plate for exposure, and etching to obtain a gate film as shown in FIG. Fig.14 The gate layer shown; a gate insulating layer 101 is formed on the gate layer;

[0140] S02, forming a metal oxide semiconductor film (semiconductor light-transmitting film), using a second mask plate for a first exposure to obtain an oxide semiconductor layer, performing surface conductor treatment, and then using a second mask plate for a second exposure to remove the conductorized surface of a portion of the oxide semiconductor layer after the conductorization, so as to simultaneously obtain Fig.15 The semiconductor light-transmitting layer 6 shown (including the active layer 31, the first storage electrode line 22 and the second storage electrode line 21); the specific preparation method of the semiconductor light-transmitting layer can be referred to the above, which will not be described in detail here.

[0141] The material of the active layer 31 is a metal oxide semiconductor material, the material of the first storage electrode line 22 and the second storage electrode line 21 is the same as the material of the active layer 31, and the oxygen content of the surface of the first storage electrode line 22 and the second storage electrode line 21 away from the substrate 100 is low, so that it has conductivity.

[0142] S03, forming a source and drain metal film, using a third mask plate for exposure, and etching to obtain Fig.16 The source and drain metal layers shown;

[0143] The source-drain metal layer includes a source electrode 32 , a drain electrode 33 and a data line 4 .

[0144] S04, forming a passivation film, using the fourth mask plate for exposure, and etching to obtain the following Fig.17 A passivation layer 102 is shown.

[0145] The passivation layer 102 has a plurality of via holes, so that the pixel electrode can be electrically connected to the source-drain metal layer through the via holes.

[0146] S05 , forming a pixel electrode thin film, using a fifth mask plate for exposure, and etching to obtain a pixel electrode 5 .

[0147] Below Fig.10 Taking the structure shown as an example, the preparation method of the array substrate in the embodiment of the present application is specifically described, and the method is a 4Mask preparation process:

[0148] S01, providing a substrate 100; forming a gate film on the substrate, exposing it using a first mask, and etching it to obtain a gate layer; forming a gate insulating layer 101 on the gate layer;

[0149] S02, forming a metal oxide semiconductor film (semiconductor light-transmitting film), and performing a first exposure using a second mask through a half-tone mask process to obtain an oxide semiconductor layer;

[0150] After the surface conductor treatment, a second exposure is performed using a second mask to remove the conductorized surface of a portion of the oxide semiconductor layer after the conductor treatment, so as to simultaneously obtain a semiconductor light-transmitting layer 6 (including an active layer 31, a first storage electrode line 22, a second storage electrode line 21, and an auxiliary data line 41); the specific preparation method of the semiconductor light-transmitting layer can be referred to in the previous text and will not be described in detail here.

[0151] Forming a source-drain metal film, performing a third exposure using a second mask, and etching to obtain a source-drain metal layer;

[0152] The material of the active layer 31 is a metal oxide semiconductor material, the material of the first storage electrode line 22, the second storage electrode line 21 and the auxiliary data line 41 is the same as the material of the active layer 31, and the surface of the first storage electrode line 22, the second storage electrode line 21 and the auxiliary data line 41 away from the substrate 100 has a low oxygen content to make it conductive. The source-drain metal layer includes a source electrode 32, a drain electrode 33 and a data line 4.

[0153] S03 , forming a passivation film, using a third mask to perform exposure, and etching to obtain a passivation layer 102 .

[0154] The passivation layer 102 has a plurality of via holes, so that the pixel electrode can be electrically connected to the source-drain metal layer through the via holes.

[0155] S04, forming a pixel electrode thin film, using a fourth mask plate for exposure, and etching to obtain a pixel electrode 5.

[0156] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: substrate; A gate layer, comprising a plurality of gates and a plurality of gate lines; A semiconductor light-transmitting layer, located on a side of the gate layer away from the substrate, comprising a plurality of active layers and a plurality of first storage electrode lines; A plurality of pixel electrodes are located on a side of the semiconductor light-transmitting layer away from the substrate; The orthographic projection of the active layer on the substrate is within the orthographic projection of the gate on the substrate, the first storage electrode line extends in a direction parallel to the gate line, the orthographic projection of the first storage electrode line on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the first storage electrode line on the substrate does not overlap with the orthographic projection of the gate layer on the substrate.

2. The array substrate according to claim 1, characterized in that: Materials of the active layer and the first storage electrode line are both metal oxide semiconductor materials, and the oxygen content of the material of the first storage electrode line is lower than the oxygen content of the material of the active layer.

3. The array substrate according to claim 1, characterized in that: The array substrate further comprises a source-drain metal layer, wherein the source-drain metal layer is located on a side of the semiconductor light-transmitting layer away from the substrate; the source-drain metal layer comprises a plurality of data lines; The source-drain metal layer includes a plurality of source electrodes and a plurality of drain electrodes, and the source electrodes and the drain electrodes are in direct contact with the active layer respectively.

4. The array substrate according to claim 3, characterized in that: The data line and the gate line intersect and are insulated from each other, and the data line and the gate line define an area where the pixel electrode is located; Wherein, the first storage electrode line and the data line intersect and are insulated; Alternatively, the first storage electrode line is disconnected at a region where it overlaps with the data line in a direction perpendicular to the substrate.

5. The array substrate according to claim 4, characterized in that: The semiconductor light-transmitting layer further includes a plurality of second storage electrode lines, the second storage electrode lines extend in a direction parallel to the data lines and intersect with the first storage electrode lines, and are electrically connected at the intersection of the two; In a case where the first storage electrode lines intersect and are insulated from the data lines, each of the second storage electrode lines is disconnected at a region where it overlaps with the gate line in a direction perpendicular to the substrate.

6. The array substrate according to claim 4, characterized in that: The semiconductor light-transmitting layer further includes a plurality of second storage electrode lines, the second storage electrode lines extend in a direction parallel to the data lines and intersect with the first storage electrode lines, and are electrically connected at the intersection of the two; In a case where the first storage electrode line is disposed disconnected at a region overlapping the data line in a direction perpendicular to the substrate, the second storage electrode line intersects and is insulated from the gate line.

7. The array substrate according to claim 6, characterized in that: The array substrate further comprises a plurality of auxiliary data lines, wherein the data lines are located on a side of the auxiliary data lines away from the substrate; The orthographic projection of the data line on the substrate is located within the orthographic projection of the auxiliary data line on the substrate, the auxiliary data line and the first storage electrode line are arranged in the same layer, and the orthographic projection of the auxiliary data line on the substrate and the orthographic projection of the first storage electrode line on the substrate do not overlap each other.

8. The array substrate according to any one of claims 5 to 7, characterized in that: The orthographic projection of the first storage electrode line on the substrate overlaps with the orthographic projection of the side of the pixel electrode parallel to the gate line on the substrate; An orthographic projection of the second storage electrode line on the substrate overlaps with an orthographic projection of a side of the pixel electrode parallel to the data line on the substrate.

9. The array substrate according to any one of claims 5 to 7, characterized in that: The orthographic projection of the first storage electrode line on the substrate overlaps with the orthographic projection of the middle area of ​​the pixel electrode on the substrate, and the orthographic projection of the second storage electrode line on the substrate overlaps with the orthographic projection of the side of the pixel electrode parallel to the data line on the substrate.

10. The array substrate according to claim 3, characterized in that: The gate electrode, the source electrode, the drain electrode and the active layer constitute a thin film transistor; The region where the gate line overlaps with the active layer in a direction perpendicular to the substrate serves as the gate, and the orthographic projection of the thin film transistor on the substrate is within the orthographic projection of the gate line on the substrate.

11. The array substrate according to claim 10, characterized in that: The array substrate further comprises a passivation layer, the passivation layer is located on a side of the source-drain metal layer away from the substrate, the passivation layer has a plurality of penetrating vias, the drain electrode is electrically connected to the pixel electrode through the vias, and the source electrode is electrically connected to the data line; The orthographic projection of the outer contour of the via hole on the substrate is located within the orthographic projection of the pixel electrode on the substrate.

12. The array substrate according to claim 11, characterized in that: An orthographic projection of an outer contour of the via hole on the substrate is also located within an orthographic projection of the first storage electrode line on the substrate.

13. A display panel, characterized in that: It comprises an array substrate as described in any one of claims 1 to 12.

14. A method for preparing an array substrate, applied to prepare the array substrate according to any one of claims 1 to 12, characterized in that: The method comprises: providing a substrate; forming a gate layer, wherein the gate layer includes a plurality of gates and a plurality of gate lines; forming a semiconductor light-transmitting layer, the semiconductor light-transmitting layer being located on a side of the gate layer away from the substrate and comprising a plurality of active layers and a plurality of first storage electrode lines; the orthographic projection of the active layer on the substrate being located within the orthographic projection of the gate on the substrate, the first storage electrode line extending in a direction parallel to the gate line; the orthographic projection of the first storage electrode line on the substrate and the orthographic projection of the gate layer on the substrate not overlapping each other; A plurality of pixel electrodes are formed, wherein the pixel electrodes are located on a side of the semiconductor light-transmitting layer away from the substrate; and an orthographic projection of the first storage electrode line on the substrate overlaps with an orthographic projection of the pixel electrode on the substrate.

15. The preparation method according to claim 14, characterized in that: After forming the gate layer and before forming a plurality of pixel electrodes, the method further includes: Forming an auxiliary data line; wherein the auxiliary data line and the semiconductor light-transmitting layer are prepared by a single patterning process; A data line is formed on the auxiliary data line; and an orthographic projection of the data line on the substrate is located within an orthographic projection of the auxiliary data line on the substrate.

16. The preparation method according to claim 14, characterized in that: The forming of the semiconductor light-transmitting layer comprises: Patterning to form a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, wherein the second metal oxide semiconductor layer covers the first metal oxide semiconductor layer; Conducting the second metal oxide semiconductor layer to form a conductor layer; a shielding layer is provided on a side of the conductor layer away from the substrate; the shielding layer exposes a part of the conductor layer; Under the shielding of the shielding layer, the conductor layer is patterned to obtain the active layer and the first storage electrode line at the same time.

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