Method for manufacturing non-volatile memory device

Abstract

The present invention provides a method for manufacturing a non-volatile memory device. The method includes forming a groove through a sacrificial layer and extending into a substrate, filling a first insulating material in the groove, and implanting a dopant into the first insulating material by an implantation process. Afterwards, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess, and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The method includes forming a first polysilicon layer in the second recess, and sequentially forming a dielectric layer and a second polysilicon layer on the first polysilicon layer.

Description

Technical Field

[0001] The invention relates to a memory device, and more particularly to a method for manufacturing a non-volatile memory device. Background Art

[0002] In the existing flash memory process, in the wet etching process for recessing the spin-on-glass, the spin-on-glass at different locations may have different etching depths. In other words, the uniformity of the wet etching is poor, and the heights of the spin-on-glass are different from each other. In the subsequent etching process, the spin-on-glass protruding from the tunnel oxide layer may be deformed, which in turn causes deformation of the floating gate formed subsequently. This will reduce the performance, yield, operation consistency and data retention capability of the memory device.

[0003] As the process shrinks, the isolation structure between the floating gates usually has a high aspect ratio. Therefore, the above problems will become more serious. How to improve the performance, yield, operation consistency and data retention capability of the memory device has become a project that the industry in this field is eager to improve. Summary of the invention

[0004] The embodiment of the present invention provides a method for manufacturing a non-volatile memory device, which can improve the performance, yield, operation consistency and data retention capability of the memory device.

[0005] One embodiment of the present invention discloses a method for manufacturing a non-volatile memory device, comprising: forming a sacrificial layer on a substrate, and forming a groove through the sacrificial layer and extending into the substrate. The manufacturing method also includes filling a first insulating material in the groove. The manufacturing method also includes: performing an implantation process to implant a dopant into the first insulating material. The manufacturing method also includes: after performing the implantation process, partially removing the first insulating material to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The manufacturing method also includes: filling a second insulating material in the first recess, and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The manufacturing method also includes forming a first polysilicon layer in the second recess. The manufacturing method also includes: partially removing the second insulating material so that the top surface of the second insulating material is lower than the top surface of the first polysilicon layer. The manufacturing method also includes: forming a dielectric layer on the first polysilicon layer, and forming a second polysilicon layer on the dielectric layer.

[0006] According to the method for manufacturing a non-volatile memory device provided by an embodiment of the present invention, before etching the spin-on glass, an implantation process is performed to implant appropriate dopants into the surface of the spin-on glass. After the implantation process, a portion of the silicon-oxygen bonds in the spin-on glass are broken, thereby making the molecular weight distribution of the spin-on glass on the surface more uniform. Therefore, the uniformity of the etching process can be improved, and deformation of the spin-on glass and the floating gate can be avoided. In this way, the performance, yield, operation consistency and data retention capability of the memory device can be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1G Schematic cross-sectional views of non-volatile memory devices at various stages of the process according to some embodiments of the present invention.

[0008] Figure 2 for Figure 1C Schematic diagram of the enlarged cross section of region R.

[0009] Figure 3A and Figure 3B The experimental results of the variability of the first depth D1 and the shortest distance T1 of the non-volatile memory devices of Comparative Example 1 and Embodiment 1 are shown.

[0010] Figure 4 Schematic cross-sectional views of non-volatile memory devices at process stages according to other embodiments of the present invention.

[0011] Reference numerals:

[0012] 100: non-volatile memory device

[0013] 102:Substrate

[0014] 104: tunnel oxide layer

[0015] 105: First notch

[0016] 106: Sacrificial layer

[0017] 108: Insulation lining

[0018] 112: first insulating material

[0019] 114: Second insulating material

[0020] 115: Second notch

[0021] 122: first polysilicon layer (floating gate)

[0022] 124: Dielectric layer

[0023] 126: second polysilicon layer (control gate)

[0024] 150:Injection process

[0025] 200: non-volatile memory device

[0026] D1: First Depth

[0027] H1: First Height

[0028] H2: Second Height

[0029] H3: The third height

[0030] R: Region

[0031] T1: Shortest distance

[0032] W1: First width

[0033] W2: Second width

[0034] W3: Third width DETAILED DESCRIPTION

[0035] In order to make the above and other purposes, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments in conjunction with the accompanying drawings. Furthermore, repeated reference symbols and / or words may be used in different examples of the present invention. These repeated symbols or words are for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and / or the structures described.

[0036] Here, the terms "about" and "approximately" generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific instructions, the meaning of "about" and "approximately" can still be implied.

[0037] The present invention provides a method for manufacturing a non-volatile memory device. Figures 1A to 1G Schematic diagrams of cross-sections of a non-volatile memory device 100 at various stages of a process according to some embodiments of the present invention. In some embodiments, the non-volatile memory device is a NOR flash memory.

[0038] Please refer to Figure 1A, a tunneling oxide layer 104 and a sacrificial layer 106 are sequentially formed on the substrate 102. In some embodiments, the substrate 102 may be a semiconductor substrate. In some embodiments, the material of the substrate 102 may include silicon, gallium arsenide, gallium nitride, silicon germanium, silicon on insulator (SOI), other suitable materials or combinations of the above materials. In some embodiments, other structures may also be formed in the substrate 102, for example, a doped region (not shown). In the present embodiment, the substrate 102 is a silicon substrate. The tunneling oxide layer 104 may be formed by a thermal oxidation process. The sacrificial layer 106 may be a nitride, an oxynitride, a carbide or other suitable insulating material. The sacrificial layer 106 may be formed by a deposition process, for example, a chemical vapor deposition process, an atomic layer deposition process, other suitable deposition processes or combinations of the above. In the present embodiment, the sacrificial layer 106 is silicon nitride.

[0039] Afterwards, a patterning process is performed to form a plurality of trenches that pass through the sacrificial layer 106, the tunnel oxide layer 104 and extend into the substrate 102. Next, an insulating liner 108 is conformally formed in the plurality of trenches. The insulating liner 108 may be a single-layer structure formed of a single material or a multi-layer structure formed of a plurality of different materials. In this specification, in order to simplify the drawings, Figures 1A to 1G The insulating liner 108 is shown as a single-layer structure.

[0040] In some embodiments, the insulating liner 108 is a double-layer structure. In such an embodiment, an in-situ steam generation (ISSG) method is used to conformally form a first silicon oxide layer in the above-mentioned multiple grooves, and then a high aspect ratio trench filling process (e-HARP) is used to conformally form a second silicon oxide layer on the first silicon oxide layer. After forming the first silicon oxide layer and the second silicon oxide layer, an annealing process is performed to improve the compactness of the insulating liner 108. In such an embodiment, the first silicon oxide layer has excellent uniformity and compactness. On the other hand, the second silicon oxide layer can increase the thickness of the insulating liner 108 without consuming silicon atoms in the substrate 102, so that more available area of ​​the substrate 102 can be retained. In such an embodiment, the adhesion between the substrate 102 and the subsequent spin-on glass can be increased. In addition, the first insulating material 112 formed subsequently may include spin-on glass (SOG). Spin-on glass includes impurities such as polymers. The insulating liner 108 formed between the first insulating material 112 and the tunnel oxide layer 104 can prevent the spin-on-glass from directly contacting the tunnel oxide layer 104 , thereby further improving the yield of the non-volatile memory device 100 .

[0041] Next, a first insulating material 112 is formed and filled into the trenches. Afterwards, a planarization process (eg, a chemical mechanical polishing process) is performed to make the top surfaces of the sacrificial layer 106 , the insulating liner 108 , and the first insulating material 112 coplanar.

[0042] The first insulating material 112 is formed between the active regions of the substrate 102 and is used to electrically isolate these active regions. The active region is located below the tunnel oxide layer 104. In order to achieve a good electrical insulation effect, the first insulating material 112 may include nitride, oxide, oxynitride, other suitable insulating materials or a combination thereof. In order to make the subsequent etching process have good etching selectivity, the insulating liner 108 and the first insulating material 112 may be different materials. In some embodiments, the first silicon oxide layer and the second silicon oxide layer of the insulating liner 108 are oxide materials different from the first insulating material 112. In this embodiment, the first insulating material 112 is spin-on glass. Spin-on glass has good hole filling ability, which is conducive to completely filling the above-mentioned groove when the above-mentioned groove has a higher aspect ratio, and avoiding the generation of voids. In one embodiment, after the first insulating material 112 is filled into the above-mentioned groove, the hardness of the first insulating material 112 is increased by a hardening process.

[0043] Next, please refer to Figure 1B , an implantation process 150 is performed to implant dopants into the first insulating material 112 .

[0044] Next, please refer to Figure 1C After the implantation process 150, a first etching process is performed to partially remove the first insulating material 112, thereby forming a first recess 105 between the sacrificial layers 106. The first etching process may be dry etching, wet etching, or a combination thereof. In one embodiment, the first etching process is wet etching.

[0045] Next, please refer to Figure 1D , the second insulating material 114 is filled into the first recess 105. Then, a planarization process (eg, chemical mechanical polishing process) is performed to make the top surfaces of the sacrificial layer 106, the insulating liner 108, and the second insulating material 114 coplanar.

[0046] The second insulating material 114 is used to electrically isolate the floating gate 122 (shown in FIG. Figure 1FIn order to achieve a good electrical insulation effect, the second insulating material 114 may include nitride, oxide, oxynitride, other suitable insulating materials or a combination thereof. Furthermore, in order to make the subsequent etching process have good etching selectivity, the sacrificial layer 106, the insulating liner 108 and the second insulating material 114 may be different materials. In the present embodiment, the second insulating material 114 is a high-density plasma (HDP) oxide. Compared with spin-on glass, high-density plasma oxide has higher hardness and better etching resistance. Therefore, the second insulating material 114 will not be deformed in the subsequent second etching process.

[0047] Next, please refer to Figure 1E , a cleaning process is performed to remove residues (e.g., oxide) on the surface of the sacrificial layer 106 after the planarization process. Thereafter, a second etching process is performed to remove all of the sacrificial layer 106 and a portion of the insulating liner 108, thereby forming a second recess 115 between the second insulating material 114 and exposing the tunnel oxide layer 104. The second etching process may be dry etching, wet etching, or a combination thereof. In some embodiments, the second etching process is wet etching.

[0048] Next, please refer to Figure 1F , forming a first polysilicon layer 122 in the second recess 115. Then, a planarization process (eg, chemical mechanical polishing process) is performed to make the top surface of the second insulating material 114 and the top surface of the first polysilicon layer 122 coplanar.

[0049] Next, please refer to Figure 1G , a third etching process is performed to partially remove the second insulating material 114 so that the top surface of the second insulating material 114 is lower than the top surface of the first polysilicon layer 122. The third etching process can be dry etching, wet etching, or a combination thereof. In some embodiments, the third etching process is dry etching.

[0050] Next, a dielectric layer 124 is conformally formed on the first polysilicon layer 122 and the second insulating material 114. The dielectric layer 124 may be a single-layer structure formed of a single material or a multi-layer structure formed of a plurality of different materials. Figure 1G The dielectric layer 124 is shown as a single-layer structure. The material of the dielectric layer 124 may include oxide, nitride, oxynitride, other suitable dielectric materials, or a combination thereof. In some embodiments, the dielectric layer 124 is a three-layer structure formed of silicon oxide / silicon nitride / silicon oxide. The dielectric layer 124 may be formed by a chemical vapor deposition process.

[0051] Next, a second polysilicon layer 126 is formed on the dielectric layer 124. The first polysilicon layer 122 and the second polysilicon layer 126 may be independently formed by a suitable deposition process, such as a chemical vapor deposition process, an atomic layer deposition process, other suitable deposition processes, or a combination of the above processes. In some embodiments, the first polysilicon layer 122 and the second polysilicon layer 126 may be independently doped polysilicon (e.g., p-type doped polysilicon or n-type doped polysilicon), so as to have better conductivity. In such an embodiment, an annealing process may be performed as needed to uniformly diffuse the dopant in the first polysilicon layer 122 and the second polysilicon layer 126. In this specification, the first polysilicon layer 122 may be used as a floating gate, and the second polysilicon layer 126 may be used as a control gate. Therefore, the first polysilicon layer 122 may also be referred to as a "floating gate 122", and the second polysilicon layer 126 may also be referred to as a "control gate 126".

[0052] After forming the control gate 126, other known processes (eg, patterning the floating gate 122 and the control gate 126) may be performed to complete the non-volatile memory device 100. Other known processes will not be described in detail herein.

[0053] In the present embodiment, the first insulating material 112 is a spin-on glass, and the hardness of the first insulating material 112 is increased by a hardening process. However, since the spin-on glass is a polymer based material, after the hardening process, the molecular weight of the first insulating material 112 at different depths of the groove will be different. More specifically, in the same groove, the hardening effect of the first insulating material 112 is better in the top area of ​​the groove than in the center area or the bottom area of ​​the groove, and the molecular weight of the hardened first insulating material 112 is larger. On the other hand, the hardening effect of the first insulating material 112 located in different grooves is also different.

[0054] Due to the different molecular weights, the etching resistance of the first insulating material 112 will be different. If the first etching process is performed directly after the hardening process, the etching depths of the first insulating material 112 located at different positions on the same wafer will also be different. If the first insulating material 112 located in the top area of ​​the groove has a larger molecular weight, the depth of the first recess 105 will be shallower after the first etching process. Similarly, if the first insulating material 112 with a large molecular weight located in the top area of ​​the groove is thicker, the depth of the first recess 105 will also be shallower. If the depth of the first recess 105 is shallower, the first insulating material 112 may protrude from the tunnel oxide layer 104 and be located between the sacrificial layers 106. In this way, when the second etching process is performed later, the first insulating material 112 protruding from the tunnel oxide layer 104 will be partially removed and deformed (for example, the width becomes narrower). If the first insulating material 112 is deformed, the adjacent second recesses 115 will be too close or even connected. When the floating gate 122 is subsequently formed, the floating gate 122 will also be deformed according to the cross-sectional profile of the second notch 115 (that is, the width of the cross-sectional profile of the floating gate 122 will become wider than expected). Therefore, adjacent floating gates 122 are too close or even in contact, which may cause operation errors or short circuits of the memory device. As a result, the performance, yield, operation consistency and data retention capability of the memory device are reduced.

[0055] According to the manufacturing method of the non-volatile memory device 100 provided in this embodiment, the uniformity of the etching process can be improved, and deformation of the first insulating material 112 and the floating gate 122 can be avoided. More specifically, in this embodiment, after the first etching process, it can be ensured that the first insulating material 112 does not protrude from the top surface of the tunnel oxide layer 104, and it can be ensured that the active region and the tunnel oxide layer 104 are covered by the insulating liner 108 and the first insulating material 112. In this way, the performance, yield, operation consistency and data retention capability of the memory device can be greatly improved.

[0056] In more detail, in the present embodiment, before the first etching process is performed, an implantation process 150 is performed to implant dopants into the first insulating material 112. Affected by the implantation process 150, a portion of the silicon-oxygen bonds in the first insulating material 112 are broken, and therefore, the molecular weight of the first insulating material 112 located in the top region of the trench becomes smaller, which can increase the etching rate of the first insulating material 112 during the first etching process. On the other hand, affected by the implantation process 150, the molecular weight distribution of the first insulating material 112 located in the top region of the trench becomes more uniform. Therefore, the molecular weight uniformity of the first insulating material 112 can be improved, which helps to make the etching rates of the first insulating material 112 located at different positions the same or similar to each other. In this way, during the first etching process, the uniformity of the etching depth of the first insulating material 112 can be greatly improved.

[0057] As described above, in this embodiment, before forming the second notch 115, a planarization process (such as Figure 1D ) and cleaning process to partially remove the sacrificial layer 106 and the second insulating material 114. Figure 1C After the first notch 105 is formed, the sacrificial layer 106 has a first height H1, and the top area of ​​the sacrificial layer 106 has a first width W1. Figure 1E , after forming the second recess 115, the second recess 115 has a second height H2 less than the first height H1, and the top of the second recess 115 has a second width W2 greater than the first width W1. In other words, in this embodiment, even if the second width of the sacrificial layer 106 is narrowed due to the implantation process 150, after the planarization process and the cleaning process are performed, the opening width of the second recess 115 (i.e., the second width W2) can still be controlled within a suitable range. In some embodiments, the ratio H2 / H1 of the second height H2 to the first height H1 is 0.65-0.85. In such an embodiment, the opening width of the second recess 115 can be maintained within a suitable range. In this way, the performance and yield of the memory device can be further improved.

[0058] Please refer to Figure 1E After the second recess 115 is formed, the top of the second recess 115 has a second width W2, and the bottom of the second recess 115 has a third width W3. In order to facilitate the formation of the first polysilicon layer 122 in the second recess 115 and avoid the generation of voids or gaps in the first polysilicon layer 122, in one embodiment, the ratio W2 / W3 of the second width W2 to the third width W3 is at least 0.50. In one embodiment, the ratio H2 / W2 of the second height H2 to the second width W2 is 2.0-5.0.

[0059] Furthermore, the opening width of the second recess 115 can also be controlled by adjusting the implantation energy of the implantation process 150. In some embodiments, the implantation energy is 0.1-5.0 keV, so that the implantation depth can be easily controlled within 10-30 nm, thereby preventing the width of the middle portion of the sacrificial layer 106 from being narrowed due to the implantation process 150, and further improving the performance and yield of the memory device.

[0060] In addition, the opening width of the second recess 115 can also be controlled by selecting a suitable dopant. In some embodiments, the atomic weight or molecular weight of the dopant is 30-75. In this way, the dopant can be injected to the desired injection depth without a large injection energy, and the uniformity of the injection depth is better. In addition, such dopants are not easy to move to other layers (for example, the tunneling oxide layer 104 or the active area) after entering the first insulating material 112 and the sacrificial layer 106. Therefore, the possibility of affecting the characteristics of other components (for example, resistance value) can be reduced. In this way, the performance and yield of the memory device can be further improved. In some embodiments, the dopant includes but is not limited to phosphorus, arsenic, fluorine or boron fluoride (BF2). In the present embodiment, the dopant is phosphorus. In some embodiments, the dopant concentration ranges from 10 13 -10 14 Atom / cm 3 .

[0061] Figure 2 for Figure 1C During the first etching process, the etching rate of the first insulating material 112 is much greater than the etching rate of the insulating liner 108. Therefore, compared with the first insulating material 112 located at the edge area of ​​the first notch 105, the first insulating material 112 located at the center area of ​​the first notch 105 has a greater etching depth.

[0062] In the conventional flash memory process, when the second etching process is performed, the first insulating material 112 protruding from the tunnel oxide layer 104 will be partially removed and deformed, thereby reducing the performance, yield, operation consistency and data retention capability of the memory device. Figure 1C and Figure 2 In this embodiment, the lowest point of the first notch 105 is lower than the top surface of the substrate 102, and the highest point of the first insulating material 112 is flush with or lower than the top surface of the tunnel oxide layer 104. In this way, deformation of the first insulating material 112 caused by the second etching process can be avoided, thereby improving the performance, yield, operation consistency and data retention capability of the memory device.

[0063] Please also refer to Figure 1C and Figure 2In this embodiment, after the first etching process, the insulating liner 108 and the first insulating material 112 located on the sidewalls of the active region and the sidewalls of the tunnel oxide layer 104 are not removed. In other words, the active region and the tunnel oxide layer 104 are still covered by the insulating liner 108 and the first insulating material 112 and are not exposed. During the deposition of the second insulating material 114, the insulating liner 108 and the first insulating material 112 can protect the active region and the tunnel oxide layer 104, so that the active region and the tunnel oxide layer 104 will not be damaged by the plasma used in the deposition process. In this way, damage to the active region and the tunnel oxide layer 104 can be avoided, and the performance, yield, operation consistency and data retention capability of the memory device can be further improved.

[0064] Please refer to Figure 2 After the first notch 105 is formed, the distance from the lowest point of the first notch 105 to the top surface of the substrate 102 is the first depth D1, and there is a shortest distance T1 between the top surface of the substrate 102 and the top surface of the first insulating material 112. In order to avoid deformation of the first insulating material 112 and damage to the active region and the tunnel oxide layer 104, in one embodiment, the ratio of the shortest distance T1 to the first depth D1 is 1.5-4.

[0065] In some embodiments, the first etching process is a two-step wet etching process, and buffered hydrofluoric acid (BHF) is used as an etching solution, which helps to improve the etching uniformity of the first insulating material 112 during the first etching process.

[0066] Furthermore, in the present embodiment, the first etching process includes a first step and a second step. In the first step, the concentration of the buffered hydrofluoric acid of the first etching solution is relatively high, and the etching rate of the first insulating material 112 is relatively high. Therefore, it is beneficial to etch the first recess 105 with a high aspect ratio, and the time required for the etching step can be reduced. In the second step, the concentration of the buffered hydrofluoric acid of the second etching solution is relatively low, and the isotropicity of the etching is relatively high. Therefore, it is helpful to make the bottom portion of the first recess 105 have a cross-sectional profile as described above, and it is helpful to improve the etching uniformity of the first insulating material 112.

[0067] In order to prove the influence of the implantation process on the etching uniformity of the first insulating material 112, the inventors of this case conducted an experiment and showed the results in Figure 3A and Figure 3B . Figure 3A and Figure 3B The experimental results of the uniformity of the shortest distance T1 and the first depth D1 of the test structures of Comparative Example 1 and Example 1 are shown.

[0068] The test structure of Example 1 is as described above. Figure 1A to Figure 1C The relevant steps described are manufactured and carried out as follows Figure 1B The first etching process is performed after the implantation process 150 shown in FIG. 1 . The test structure of Comparative Example 1 is manufactured according to the steps similar to those of Example 1, except that before the first etching process, Comparative Example 1 does not perform the steps shown in FIG. Figure 1B The implantation process 150 is shown. Five positions (one sampling position is located at the center of the wafer and the other four sampling positions are located at the edge of the wafer) are selected for the test structures of Example 1 and Comparative Example 1, and the cross-sectional profile of the first notch 105 is measured. The statistical results of the shortest distance T1 and the first depth D1 are respectively displayed in Figure 3A and Figure 3B .

[0069] exist Figure 3A In , if the difference between the maximum and minimum values ​​of the shortest distance T1 is smaller, it means that the uniformity of the shortest distance T1 is better. Figure 3B In the embodiment, if the difference between the maximum value and the minimum value of the first depth D1 is smaller, it means that the uniformity of the first depth D1 is better.

[0070] Please refer to Figure 3A For the test structure of Comparative Example 1, the difference between the maximum and minimum values ​​of the shortest distance T1 is about 5.8 nm. For the test structure of Example 1, the difference between the maximum and minimum values ​​of the shortest distance T1 is about 3.8 nm. Figure 3B For the test structure of Comparative Example 1, the difference between the maximum and minimum values ​​of the first depth D1 is about 11.0 nm. For the test structure of Example 1, the difference between the maximum and minimum values ​​of the first depth D1 is about 4.0 nm.

[0071] The above experimental results show that performing the implantation process 150 before the first etching process can significantly improve the etching uniformity of the first insulating material 112. Therefore, the performance, yield, operation consistency and data retention capability of the memory device can be improved.

[0072] Figure 4 Schematic cross-sectional views of a non-volatile memory device 200 at a process stage according to some other embodiments of the present invention. Figure 4 Similar to Figure 1A .exist Figure 4 , the same as Figure 1A The same reference numerals are used to designate the components shown. Figure 1A The illustrated components and their manufacturing process steps are not described in detail here.

[0073] Please refer to Figure 4In the present embodiment, after the planarization process, the top surface of the first insulating material 112 is higher than the top surface of the sacrificial layer 106. In other words, when the implantation process 150 is performed, the top surface of the sacrificial layer 106 is not exposed. The distance between the top surface of the first insulating material 112 and the top surface of the sacrificial layer 106 is the third height H3. In the present embodiment, the third height H3 is 15-40 nm, which can greatly reduce the dopants entering the sacrificial layer 106 and the insulating liner 108. Therefore, even if the implantation process 150 is performed, the etching rate of the sacrificial layer 106 and the insulating liner 108 will not increase significantly, and the deformation of the cross-sectional profile of the sacrificial layer 106 (that is, the width of the cross-sectional profile of the sacrificial layer 106 becomes narrower) can be avoided. In this way, the performance and yield of the memory device can be improved.

[0074] In summary, according to the manufacturing method of the non-volatile memory device provided by the embodiment of the present invention, before etching the first insulating material, an implantation process is performed to implant appropriate dopants into the surface of the first insulating material. This can improve the uniformity of the first insulating material in the etching process and avoid deformation of the first insulating material and the floating gate. In this way, the performance, yield, operation consistency and data retention capability of the memory device can be greatly improved. Furthermore, the manufacturing method of the non-volatile memory device provided by the embodiment of the present invention can be easily integrated into the existing process without additional replacement or modification of the production equipment. In this way, the complexity of the process and the production cost will not be significantly increased.

[0075] According to the method for manufacturing a non-volatile memory device provided by an embodiment of the present invention, before etching the spin-on glass, an implantation process is performed to implant appropriate dopants into the surface of the spin-on glass. After the implantation process, a portion of the silicon-oxygen bonds in the spin-on glass are broken, thereby making the molecular weight distribution of the spin-on glass on the surface more uniform. Therefore, the uniformity of the etching process can be improved, and deformation of the spin-on glass and the floating gate can be avoided. In this way, the performance, yield, operation consistency and data retention capability of the memory device can be greatly improved.

[0076] Although the present invention has been disclosed as above with several preferred embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the technical field may make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on that defined by the claims.

Claims

1. A method for manufacturing a non-volatile memory device, characterized in that: include: forming a tunnel oxide layer on a substrate; forming a sacrificial layer on the tunnel oxide layer; forming a trench through the sacrificial layer and extending into the substrate; Filling a first insulating material into the trench; Performing an implantation process to implant a dopant into the first insulating material; After performing the implantation process, partially removing the first insulating material to form a first recess between the sacrificial layers, wherein a lowest point of the first recess is lower than a top surface of the substrate, and a highest point of the first insulating material is not higher than a top surface of the tunnel oxide layer; Filling a second insulating material into the first recess; removing the sacrificial layer to form a second recess adjacent to the second insulating material; forming a first polysilicon layer in the second recess; Partially removing the second insulating material so that a top surface of the second insulating material is lower than a top surface of the first polysilicon layer; forming a dielectric layer on the first polysilicon layer; as well as A second polysilicon layer is formed on the dielectric layer.

2. The method for manufacturing a non-volatile memory device according to claim 1, wherein: The atomic weight or molecular weight of the dopant is 30-75.

3. The method for manufacturing a non-volatile memory device according to claim 1, wherein: The dopant includes phosphorus, arsenic, fluorine or boron fluoride.

4. The method for manufacturing a non-volatile memory device according to claim 1, wherein: The implantation energy of the implantation process is 0.1-5.0 keV.

5. The method for manufacturing a non-volatile memory device as claimed in claim 1, wherein: The implantation depth of this implantation process is 10-30 nm.

6. The method for manufacturing a non-volatile memory device according to claim 1, wherein: After forming the first recess, the distance from the lowest point of the first recess to the top surface of the substrate is a first depth D1, there is a shortest distance T1 between the top surface of the substrate and a top surface of the first insulating material, and the ratio of the shortest distance T1 to the first depth D1 is 1.5-4.

7. The method for manufacturing a non-volatile memory device as claimed in claim 1, wherein: After forming the first notch, the sacrificial layer has a first height H1 , and after forming the second notch, the second notch has a second height H2 , and a ratio H2 / H1 of the second height H2 to the first height H1 is 0.65-0.

85.

8. The method for manufacturing a non-volatile memory device as claimed in claim 7, wherein: After forming the second notch, a top region of the second notch has a second width W2, a bottom portion of the second notch has a third width W3, and a ratio W2 / W3 of the second width W2 to the third width W3 is at least 0.

50.

9. The method for manufacturing a non-volatile memory device as claimed in claim 8, wherein: After the second notch is formed, a ratio H2 / W2 of the second height H2 to the second width W2 is 2.0-5.

0.

10. The method for manufacturing a non-volatile memory device as claimed in claim 1, wherein: The first insulating material is partially removed by a wet etch, wherein the wet etch comprises: Etching the first insulating material using a first etching solution, wherein the first etching solution has a first concentration; and The first insulating material is etched using a second etching solution, wherein the second etching solution has a second concentration less than the first concentration.

11. The method for manufacturing a non-volatile memory device according to claim 1, wherein: Also includes: After forming the trench, an insulating liner is conformally formed on the substrate and the sacrificial layer, wherein forming the insulating liner includes using an in-situ steam generation method and a high aspect ratio trench filling process.

12. The method for manufacturing a non-volatile memory device as claimed in claim 1, wherein: Also includes: Before the implantation process is performed, a planarization process is performed to make a top surface of the first insulating material flush with a top surface of the sacrificial layer.

13. The method for manufacturing a non-volatile memory device as claimed in claim 1, wherein: Also includes: Before the implantation process is performed, a planarization process is performed to make a top surface of the first insulating material higher than a top surface of the sacrificial layer.

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