Display panel and display device

Abstract

The present invention provides a display panel and a display device, wherein the display panel includes a display area and a non-display area surrounding the display area, wherein the non-display area includes a first non-display area; at least two driver chips, wherein the driver chips are located in the first non-display area; the display panel includes a plurality of scan lines extending along a first direction; a plurality of test pads, an information identification code, and a plurality of alignment marks, wherein along the first direction, at least one of the plurality of test pads, the information identification code, and the plurality of alignment marks, or a portion of at least one of the plurality of test pads, the information identification code, and the plurality of alignment marks, is located between the driver chips. The present invention can achieve a narrow frame of a display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] At present, terminal products such as vehicles, tablets, and notebooks have medium and large-sized display screens, and medium and large-sized display screens are developing towards high resolution, special shapes, and narrow bezels. On existing display panels, test pads, information identification codes, alignment marks, etc. are generally set in the lower left and right corners of the display panel. In addition to the need to integrate test pads, information identification codes, alignment marks, etc., the lower left and right corners of the display panel also need to set up some gate drive circuits and provide signal lines for the gate drive circuits, which in turn increases the size of the left and right bezels of the display panel to a certain extent, making it impossible to achieve a narrow bezel of the display panel; and if the size of the test pads, information identification codes, and alignment marks is compressed, it will cause the equipment accuracy to be unmatched, such as the test probe cannot be accurately connected to the specific test pad, the identification instrument cannot recognize the information in the information identification code, and the identification instrument cannot accurately recognize the alignment mark. Therefore, how to achieve a narrow bezel of the display panel without compressing the size of the existing test pads, information identification codes, and alignment marks is an urgent problem to be solved. Summary of the invention

[0003] In view of this, embodiments of the present invention provide a display panel and a display device, which can achieve a narrow frame of the display panel without compressing the size of the existing test pads, information identification codes, and alignment marks.

[0004] In a first aspect, the present application provides a display panel, comprising:

[0005] A display area and a non-display area surrounding the display area, wherein the non-display area includes a first non-display area;

[0006] At least two driving chips, wherein the driving chips are located in the first non-display area;

[0007] a plurality of scanning lines extending along a first direction;

[0008] A plurality of test pads, an information identification code, and a plurality of alignment marks. Along the first direction, at least one of the plurality of test pads, the information identification code, and the plurality of alignment marks or a portion of at least one of the plurality of test pads, the information identification code, and the plurality of alignment marks is located between the driving chips.

[0009] In a second aspect, the present application provides a display device, which includes the display panel.

[0010] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0011] The present application provides a display panel and a display device. A medium or large-sized display panel generally includes two or more driver chips. Since there is a certain empty area between the driver chips, it is convenient to bind the driver chip and the display panel. Then, along the extension direction of the scan line, at least one of a plurality of test pads, information identification codes, and a plurality of alignment marks, or a part of at least one of them is arranged between the driver chips, such as only the plurality of test pads are arranged between the driver chips, or a part of the plurality of test pads is arranged between the driver chips; on the one hand, it is not necessary to reduce the border size of the non-display area of ​​the display panel by compressing the size of the test pads, the information identification code, and the alignment mark, or , it is only necessary to reasonably compress the size of the above-mentioned part of the components, that is, to reduce the number of components that need to be compressed, and the compressed size does not affect the test or instrument recognition, and the compressed size of the above-mentioned components can reduce the size of a part of the non-display area; on the other hand, by arranging at least one or part of at least one of the multiple test pads, information identification codes, and multiple alignment marks between the driver chips, the empty area between the driver chips can be reasonably utilized to avoid integrating the test pads, information identification codes, alignment marks, driver circuits, signal lines, etc. at the same time in the lower left and right corners of the display panel, which leads to the left and right borders or the lower border being too large, thereby ensuring the narrow border of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments are briefly introduced below. The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention.

[0013] Figure 1 A schematic top view of a display panel provided by an embodiment of the present invention;

[0014] Figure 2 A schematic top view of another display panel provided by an embodiment of the present invention;

[0015] Figure 3 A schematic top view of another display panel provided by an embodiment of the present invention;

[0016] Figure 4 A schematic top view of another display panel provided by an embodiment of the present invention;

[0017] Figure 5 A schematic top view of another display panel provided by an embodiment of the present invention;

[0018] Figure 6 A schematic top view of another display panel provided by an embodiment of the present invention;

[0019] Figure 7 A schematic top view of another display panel provided by an embodiment of the present invention;

[0020] Figure 8 A schematic top view of another display panel provided by an embodiment of the present invention;

[0021] Fig. 9 A schematic top view of another display panel provided by an embodiment of the present invention;

[0022] Fig.10 A schematic top view of another display panel provided by an embodiment of the present invention;

[0023] Fig.11 for Fig.10 An enlarged view of the S region;

[0024] Fig.12 A schematic top view of another display panel provided by an embodiment of the present invention;

[0025] Fig.13 A schematic top view of another display panel provided by an embodiment of the present invention;

[0026] Fig.14 A schematic top view of another display panel provided by an embodiment of the present invention;

[0027] Fig.15 A schematic top view of another display panel provided by an embodiment of the present invention;

[0028] Fig.16 A schematic top view of another display panel provided by an embodiment of the present invention;

[0029] Fig.17 A schematic top view of a portion of another display panel provided by an embodiment of the present invention;

[0030] Fig.18 A schematic top view of a portion of another display panel provided by an embodiment of the present invention;

[0031] Fig.19 A schematic top view of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] like Figure 1 and Figure 2 As shown, Figure 1 A schematic top view of a display panel provided by an embodiment of the present invention, Figure 2 A top view schematic diagram of another display panel provided for an embodiment of the present invention; the display panel 1 includes a display area AA and a non-display area NA surrounding the display area AA, the non-display area NA includes a first non-display area NA1, the first non-display area NA1 is located in the lower frame area of ​​the display panel, the display panel 1 includes at least two driver chips 11, and the at least two driver chips 11 are located in the first non-display area NA1, that is, the lower frame area of ​​the display panel 1. The display panel 1 further includes a plurality of scan lines SL extending along a first direction X, and data lines DL extending along a second direction Y, the first direction X and the second direction Y intersect, that is, the scan lines SL and the data lines DL intersect in the display area AA to define pixel units; the display panel 1 further includes a plurality of test pads 14, an information identification code 13, and a plurality of alignment marks 12, wherein the plurality of test pads 14 are used to test the drive circuit and signal lines of the display panel before the display panel 1 is bound to the drive chip 11, so as to screen out defective products and prevent the defective products from flowing into the subsequent process, thereby causing resource waste in the subsequent process; the information identification code 13 can be a field, a two-dimensional code, etc. prepared by film layer graphics, which is used for identifying and controlling each display panel 1; the alignment mark 12 can be a cross pattern, a comb-shaped pattern, etc., which is used to align and bond the array substrate and the opposing substrate of the display panel 1.

[0034] In the extending direction of the scan line SL, that is, the first direction X, at least one of the plurality of test pads 14, the information identification code 13, and the plurality of alignment marks 12, or a portion of at least one of the plurality of test pads 14, the information identification code 13, and the plurality of alignment marks 12 is arranged between the driving chips 11, such as Figure 1 In the embodiment, only a plurality of test pads 14 are arranged between the driving chips 11, and the information identification code 13 and the alignment mark 12 are still arranged in the left and right lower corner areas of the display panel 1, such as Figure 2Part of the test pads 14 is set between the driver chips 11, and part of the test pads 14 is still set in the left and right lower corners of the display panel 1. According to the specific size and wiring conditions of the display panel 1, at least one of the multiple test pads 14, the information identification code 13, and the multiple alignment marks 12, or part of at least one of them can be selected to be set between the driver chips 11. On the one hand, there is no need to compress the size of the test pads 14, the information identification code 13, and the alignment mark 12, or only the size of part of the components needs to be reasonably compressed, such as only needing to compress the size of the information identification code 13 and the alignment mark 12 to the minimum size recognizable by the identification instrument, without compressing the size of the test pads 14, thereby reducing the number of components that need to be compressed. The compressed size of the above components can reduce the size of a part of the non-display area; on the other hand, the empty area between the driver chips 11 can be reasonably utilized to avoid integrating the test pads 14, the information identification code 13, the alignment mark 12 with the driver circuit, the signal line, etc. at the same time in the left and right lower corners of the display panel, thereby causing the left and right borders or the lower border to be too large, thereby ensuring the narrow border of the display panel 1.

[0035] It should be noted that Figure 1 and Figure 2 The number and size of the multiple test pads 14, information identification codes 13, and multiple alignment marks 12 shown in the figure do not represent the number and size actually used in the display panel. The number and size of the test pads 14, information identification codes 13, and multiple alignment marks 12 in the display panel can be reasonably set. Optionally, the number of test pads 14 is 30, with a size of 600×800μm and a spacing of 300μm. The number of information identification codes 13 is 1, with a size of 2×2mm. The number of alignment marks 12 is at least 2, and is an even number, with a size of 500×500μm.

[0036] Optional, such as Figure 1 As shown, multiple test pads 14 are placed between the driver chips 11. Since the number of test pads 14 is relatively greater than that of the information identification code 13 and the alignment mark 12, and gaps need to be left between the multiple test pads 14, the overall size of the test pads 14 along the first direction X is also larger. Therefore, placing multiple test pads 14 between the driver chips 11 can, to a certain extent, greatly reduce the size of the left and right lower corner areas occupied by the display panel 1, thereby ensuring the narrow frame of the display panel 1.

[0037] Optional, such as Figure 2 and Figure 3 As shown, Figure 3A top view schematic diagram of another display panel provided by an embodiment of the present invention; or part of the test pads 14 are set between the driving chips 11. Since the test pads 14 are used to test the driving circuit and signal lines of the display panel 1 before the display panel 1 is bound to the driving chip 11, the test pads 14 need to be connected to multiple driving circuits and signal lines on the display panel 1 so that the detection signal can be input to the driving circuit and signal line through the test pads 14. Because part of the driving circuit and signal line are set on the display panel 1, the display area AA is set on both sides opposite to each other along the first direction X, that is, on the left and right frames of the display panel 1, only part of the test pads 14 are set between the driving chips 11, and part of the test pads 14 are still set in the left and right lower corner areas of the display panel 1, so that the connection lines connecting the test pads 14 in this area to part of the driving circuit and signal lines can be straight lines, or the probability of bending of the connection lines is reduced.

[0038] Optional, please continue to refer to Figure 3 The driver chip 11 includes an edge driver chip 111 and a middle driver chip 112, wherein the edge driver chip 111 is a driver chip close to the edge of the display panel 1, and along the first direction X, there are at least two edge driver chips 111; the middle driver chip 112 is located between at least two edge driver chips 111; the plurality of test pads 14 include a first pad 141, and the first pad 141 is located between the edge driver chip 111 and the edge of the display panel 1, and a driving circuit and / or a signal are arranged in the second non-display area NA2 of the display panel 1. Line, wherein the second non-display area NA2 is located on both sides of the display area AA along the first direction X, that is, the second non-display area NA2 is the left and right frame areas of the display panel 1, and the first pad 141 is electrically connected to this part of the driving circuit and signal line, and the first pad 141 still arranged in the left and right lower corner areas of the display panel 1 is connected to the driving circuit and signal line of the second non-display area NA2, so that the connection line connecting the test pad 14 to the driving circuit and signal line in this area can be a straight line, or the probability of bending of the connection line is reduced, thereby reducing the probability of breaking of the connection line.

[0039] Optional, please continue to refer to Figure 3 The display panel 1 includes a grounding line D located in the non-display area NA and partially surrounding the display area AA. The first pad 141 is electrically connected to the grounding line D, so that the connection line connecting the first pad 141 to the grounding line D is shorter, and the resistance of the connection line is smaller, thereby avoiding unnecessary power consumption. The connection line is a straight line, thereby reducing the probability of disconnection of the connection line and facilitating test signal transmission.

[0040] Optional, such as Figure 4 As shown, Figure 4A top view schematic diagram of another display panel provided for an embodiment of the present invention; along the first direction X, only the first pad 141 is set in the left and right lower corner areas of the display panel 1, and the other test pads 14, the information identification code 13 and the plurality of alignment marks 12 are all set between the driver chip 11, which can significantly reduce the size of the left and right lower corner areas of the display panel 1 occupied by these designs, thereby ensuring the narrow frame of the display panel 1.

[0041] Optional, such as Figure 5 As shown, Figure 5 A top view schematic diagram of another display panel provided for an embodiment of the present invention; the display panel 1 includes at least one group of gate driving circuits 15, at least one group of gate driving circuits 15 includes a plurality of cascaded shift register circuits (not shown in the figure), and at least one group of gate driving circuits 15 is located in the second non-display area NA2, at least one group of gate driving circuits 15 is electrically connected to the scan line SL, and in the display stage, provides a scan signal to the scan line SL for controlling the specific pixel unit to turn on; part of the first pad 141 is electrically connected to the ground line D, and part of the first pad 141 is electrically connected to the gate driving circuit 15; by electrically connecting part of the first pad 141 to at least part of the ground line D and the gate driving circuit 15 located in the second non-display area NA2, the connection line connecting the first pad 141 to the above-mentioned drive circuit and the signal line can be shorter, so that the connection line resistance is small, avoiding unnecessary power consumption, and the connection line is a straight line, thereby reducing the probability of disconnection of the connection line and facilitating test signal transmission.

[0042] Optional, such as Figure 6 and Figure 7 As shown, Figure 6 A schematic top view of another display panel provided by an embodiment of the present invention, Figure 7A schematic top view of another display panel provided by an embodiment of the present invention; the plurality of test pads 14 include a second pad 142, along the first direction X, the second pad 142 is located between the driver chips 11, the second pad 142 includes a first sub-pad 1421, the first sub-pad 1421 is located between the edge driver chip 111 and the middle driver chip 112, that is, the first sub-pad 1421 is arranged between the edge driver chip 111 closest to the edge of the display panel 1 and the middle driver chip 112 adjacent to the edge driver chip 111, and compared with the middle driver chip 112, the first sub-pad 1421 is arranged between the edge driver chip 111 closest to the edge of the display panel 1 and the middle driver chip 112 adjacent to the edge driver chip 111. The first sub-pad 1421 is arranged closer to the edge driving chip 111; the first sub-pad 1421 arranged close to the edge driving chip 111 is electrically connected to the gate driving circuit 15. Without occupying the left and right lower corner areas of the display panel 1, the length of the connection line from the first sub-pad 1421 to the gate driving circuit 15 can be shortened to a large extent. The resistance of the connection line is relatively small, avoiding unnecessary power consumption, and can further reduce the probability of bending of the connection line, thereby reducing the probability of breaking of the connection line and ensuring the normal transmission of the test signal.

[0043] Optional, such as Figure 7 As shown, all the test pads 14 except the first pad 141 electrically connected to the ground line D can be arranged between the driving chips 11, and the first sub-pad 1421 electrically connected to the gate driving circuit 15 can be arranged between the edge driving chip 111 and the middle driving chip 112. This can not only reduce the size of the left and right lower corner areas of the display panel 1 to a large extent, thereby ensuring the narrow frame of the display panel 1, but also make it easier to route the connecting lines connecting the test pads 14 to the driving circuit and the signal lines, without too much avoidance and bending, thereby ensuring the normal transmission of the test signals.

[0044] Optional, please continue to refer to Figure 6 and Figure 7, the connection line between the first sub-pad 1421 and the gate driving circuit 15 is the first connection line L1, that is, one end of the first connection line L1 is electrically connected to the first sub-pad 1421, and the other end of the first connection line L1 is electrically connected to the gate driving circuit 15; the display panel 1 includes a binding area BB, the binding area BB includes a plurality of binding terminals, specifically including an input terminal IN and an output terminal OUT, the input terminal IN and the output terminal OUT are respectively bound and connected to the input pin and the output pin (not shown) of the driving chip 11, then the first connection line L1 runs through the binding area BB, And the first connection line L1 is located between the input terminal IN and the output terminal OUT, that is, one end of the first connection line L1 is electrically connected to the first sub-pad 1421, and then passes through the gap area between the input terminal IN and the output terminal OUT in the binding area BB, and then is electrically connected to the gate drive circuit 15. This setting can reduce the length of the first connection line L1, so that the resistance of the first connection line L1 is smaller, thereby avoiding unnecessary power consumption, and avoiding the first connection line L1 from winding at the binding area BB, reducing the probability of the first connection line L1 bending, thereby ensuring the normal transmission of the test signal.

[0045] Optional, such as Figure 8 As shown, Figure 8 A schematic top view of another display panel provided by an embodiment of the present invention; the display panel 1 further includes a multi-way selection circuit 16, wherein the multi-way selection circuit 16 includes a plurality of multi-way selectors, at least part of which is located between the display area AA and the driver chip 11; the plurality of test pads 14 include a second pad 142, along the first direction X, the second pad 142 is located between the driver chips 11, and the second pad 142 is electrically connected to the multi-way selector. Figure 8 In the embodiment, since the multi-way selection circuit 16 is arranged between the data line DL and the driving chip 11, by electrically connecting part of the second pad 142 located between the driving chip 11 to the multi-way selector, compared with electrically connecting the first pad 141 located between the driving chip 11 and the edge of the display panel 1 to the multi-way selector, the wiring is simpler and it can also ensure that the length of the connecting line connected to the multi-way selection circuit 16 will not differ too much, thereby ensuring the accuracy of the test.

[0046] Optional, such as Fig. 9 As shown, Fig. 9A schematic top view of another display panel provided by an embodiment of the present invention; the display panel 1 further includes a test control circuit 17, the test control circuit 17 is used to control the input of the test signal, and the test control circuit 17 is located between the multiplexer circuit 16 and the driver chip 11, then part of the second pads 142 are electrically connected to the multiplexer circuit 16, and part of the second pads are electrically connected to the test control circuit 17. As described above, since the multiplexer circuit 16 and the test control circuit 17 are both arranged between the data line DL and the driver chip 11, by electrically connecting the second pads 142 located between the driver chip 11 to the multiplexer and the test control circuit 17, the wiring is simpler than electrically connecting the first pads 141 located between the driver chip 11 and the edge of the display panel 1 to the multiplexer and the test control circuit 17, and it can also ensure that the length of the connection line connected to the multiplexer circuit 16 and the test control circuit 17 will not differ too much, thereby ensuring the accuracy of the test.

[0047] Optional, such as Fig.10 As shown, Fig.10 A top view schematic diagram of another display panel provided for an embodiment of the present invention; along a first direction X, a second pad 142 electrically connected to a test control circuit 17 is located on both sides of a second pad 142 electrically connected to a multi-way selection circuit 16, that is, the second pad 142 electrically connected to the multi-way selection circuit 16 is closer to the center of the spacing area of ​​the driver chip 11 than the second pad 142 electrically connected to the test control circuit 17, thereby ensuring that the distance between a test signal output from the test pad 14 and both ends of the multi-way selector electrically connected thereto is as equal as possible, thereby ensuring that the test signal does not deviate too much and ensuring the accuracy of the test.

[0048] Optional, such as Fig.11 As shown, Fig.11 for Fig.10An enlarged view of the S region, the connection line between the second pad 142 and the multi-way selection circuit 16 is the second connection line L2, one end of the second connection line L2 is electrically connected to the multi-way selector, and the other end is electrically connected to the second pad 142, wherein the end of the second connection line L2 connected to the second pad 142 is in the second metal layer, which is the second metal routing L22, and the end of the second connection line L2 connected to the multi-way selector is also in the second metal layer, which is the second metal routing L22, and the second connection line L2 located between the above two ends includes at least a section of routing in the first metal layer, which is the first metal routing L21 (indicated by a dotted line in the figure), wherein the first metal layer and the second metal layer are different metal layers, and optionally, the display panel 1 includes a scan line SL in the first metal layer, and a data line DL in the second metal layer, then part of the second connection line L2 is in the same layer as the data line DL, and part The second connection line L2 is on the same layer as the scanning line SL; because the second connection line L2 is an electrical connection line between the second pad 142 and the multi-way selection circuit 16, it needs to cross the area between the second pad 142 and the multi-way selection circuit 16, then there may be a signal line along the first direction X in this area, and this signal line is also located in the second metal layer at the same time, then the second connection line L2 may be short-circuited with this signal line. If there is a signal line along the first direction X in the test control circuit 17, and the second connection line L2 needs to cross the signal line in the test control circuit 17 to connect to the multi-way selection circuit 16, the line is changed at the intersection with the signal line on the same layer, that is, the connection line at the intersection is set in other metal layers, and then the two metal layers are connected by perforating the film layer, so as to ensure the transmission of the signal on the connection line, and at the same time ensure the normal transmission of the signal on the display panel 1.

[0049] Optional, such as Fig.12 As shown, Fig.12 A schematic top view of another display panel provided by an embodiment of the present invention; when the display panel 1 includes an odd number of driver chips 11 greater than or equal to 3, the driver chip 11 includes a central driver chip 113, and the central driver chip 113 is located at the center of the driver chip 11 arrangement area, such as Fig.12 In the embodiment, the number of the driving chips 11 is 3. Then, whether from the left side to the right side of the display panel 1 or from the right side to the left side, the central driving chip 113 is the second one in the arrangement of the driving chips 11, that is, along the first direction X, the number of driving chips 11 between the central driving chip 113 and the edge of the display panel 1 is the same; when the number of driving chips 11 is n, the second pad 142 electrically connected to the multi-way selection circuit 16 and the test control circuit 17 can be set as the second sub-pad 1422, wherein the second sub-pad 1422 can be m groups, m is less than or equal to n-1, such as Fig.12In the figure, the number of driving chips 11 is 3, the second sub-pads 1422 are 2 groups, and along the first direction X, the number of the second sub-pads 1422 on both sides of the central driving chip 113 is the same. Optionally, the second sub-pads 1422 are symmetrically distributed relative to the central driving chip 113. This setting can ensure that the distance between the test signal output from the test pad 14 and the multiplexer and the test control circuit 17 electrically connected thereto is as equal as possible, and can ensure that the test signal input to the display area AA of the display panel 1 is symmetrically distributed, thereby ensuring that the test signal will not deviate too much and ensuring the accuracy of the test.

[0050] Optional, such as Fig.13 As shown, Fig.13 A schematic top view of another display panel provided by an embodiment of the present invention; when the display panel 1 includes an even number of driver chips 11 greater than or equal to 2, the driver chips 11 include a middle driver chip 114, and the middle driver chip 114 is located on both sides of the central axis ZZ of the driver chip 11 arrangement area, and the middle driver chip 114 is closest to the central axis ZZ, such as Fig.10 In the embodiment, taking the number of driver chips 11 as 4 as an example, whether from the left side to the right side or from the right side to the left side of the display panel 1, the middle driver chip 114 is the second and third in the arrangement of the driver chips 11, that is, along the first direction X, the number of driver chips 11 between the central axis ZZ of the driver chip 11 arrangement area and the edge of the display panel 1 is the same; the second pads 142 electrically connected to the multi-way selection circuit 16 and the test control circuit 17 can be arranged to be located between the middle driver chips 114.

[0051] Optional, such as Fig.10 As shown, when the display panel 1 includes an even number of driving chips 11 greater than or equal to 2, when the number of driving chips 11 is n, the second sub-pads 1422 can be set to m groups, m is less than or equal to n-1, as shown in FIG. Fig.10 In the figure, the number of driving chips 11 is 4, the number of second sub-pads 1422 is 3 groups, and the number of second sub-pads 1422 on both sides of the central axis ZZ along the first direction X is the same. Optionally, the second sub-pads 1422 are symmetrically distributed relative to the central axis ZZ. This setting can ensure that the distance between the test signal output from the test pad 14 and the two ends of the multiplexer and the test control circuit 17 electrically connected thereto is as equal as possible, and can ensure that the test signal input to the display area AA of the display panel 1 is symmetrically distributed, thereby ensuring that the test signal will not deviate too much and ensuring the accuracy of the test.

[0052] Optional, such as Fig.14 As shown, Fig.14A top view schematic diagram of another display panel provided for an embodiment of the present invention; multiple test pads 14 can be located between a driver chip 11 and an edge of a display panel 1, and multiple alignment marks 12 are arranged between the driver chips 11, that is, multiple test pads 14 are still located in the left and right lower corner areas of the display panel 1, and the alignment marks 12 are moved between the driver chips 11, then multiple test pads 14 are distributed relatively concentratedly, which is beneficial to the integration of test signals at the test signal input device end, facilitates the centralized input of test signals, and is beneficial to the wiring of connecting wires led out from the test pads 14, reducing the probability of short circuit or overlap between the connecting wires and other signal lines on the display panel, and the alignment marks 12 are arranged between the driver chips 11, which reduces the size of the left and right lower corner areas of the display panel 1 to a certain extent, thereby ensuring the narrow frame of the display panel 1.

[0053] Optional, please continue to refer to Fig.14 When the display panel 1 includes an odd number of driving chips 11 greater than or equal to 3, along the first direction X, the plurality of alignment marks 12 on both sides of the central driving chip 113 may be arranged to be the same in number, and optionally, the plurality of alignment marks 12 are symmetrically distributed relative to the central driving chip 113. Since the number of the alignment marks 12 is an even number, and is at least 2, the alignment marks 12 are symmetrically distributed relative to the central driving chip 113, which is conducive to accurate bonding of the array substrate and the counter substrate of the display panel 1.

[0054] Optional, such as Fig.15 and Fig.16 , Fig.15 A schematic top view of another display panel provided by an embodiment of the present invention, Fig.16 Another schematic top view of a display panel provided by an embodiment of the present invention; when the display panel 1 includes an even number of driver chips 11 greater than or equal to 2, along the first direction X, the same number of the multiple alignment marks 12 can be set on both sides of the central axis ZZ, and optionally, the multiple alignment marks 12 are symmetrically distributed relative to the central axis ZZ, or the multiple alignment marks 12 are located between two middle driver chips 114 and are also symmetrically distributed relative to the central axis ZZ. As described above, since the number of alignment marks 12 is an even number, and at least 2, the alignment marks 12 are symmetrically distributed relative to the central axis ZZ, which is conducive to the accurate fitting of the array substrate and the opposing substrate of the display panel 1.

[0055] Optional, such as Fig.17 As shown, Fig.17A partial top view schematic diagram of another display panel provided in an embodiment of the present invention, wherein the display panel 1 further comprises at least one irregularly shaped edge C, an extension direction C' of the irregularly shaped edge C forms an angle with both the first direction X and the second direction Y, and the angle is greater than 0° and less than 90°. The above-mentioned embodiment of the present invention may also be applied to irregularly shaped display panels. Compared with non-irregularly shaped display panels, irregularly shaped display panels have more limited dimensions for the left and right lower corner regions. That is, due to the presence of irregularly shaped edges, irregularly shaped display panels have more stringent restrictions on the size of the frame than non-irregularly shaped display panels. Therefore, it is more necessary to arrange at least one of the multiple test pads 14, the information identification code 13, and the multiple alignment marks 12, or a portion of at least one of them, between the driver chips 11.

[0056] Optional, please continue to refer to Fig.17 The display panel 1 includes at least one group of gate driving circuits 15, and at least one group of gate driving circuits 15 includes multiple cascaded shift register circuits, and the gate driving circuit 15 partially extends to the non-display area NA3 corresponding to the irregular edge of the display panel 1, that is, part of the shift register circuit is located in the non-display area NA3 corresponding to the irregular edge of the display panel 1, and part of the test pads 14 located partially or entirely between the driving chips 11 are electrically connected to the shift register circuit located in the non-display area NA3 corresponding to the irregular edge.

[0057] Optional, such as Fig.18 As shown, Fig.18 A partial top view schematic diagram of another display panel provided in an embodiment of the present invention, wherein the display panel 1 includes a multi-way selection circuit 16, the multiple selection circuits 16 include multiple multi-way selectors, and the multi-way selection circuit 16 partially extends to the non-display area NA3 corresponding to the irregular edge of the display panel 1, that is, some of the multi-way selectors are located in the non-display area NA3 corresponding to the irregular edge of the display panel 1, and some of the test pads 14 located partially or entirely between the driving chips 11 are electrically connected to the multi-way selectors located in the non-display area NA3 corresponding to the irregular edge.

[0058] like Fig.19 As shown, Fig.19 A schematic top view of a display device provided in an embodiment of the present invention; an embodiment of the present invention provides a display device 2, the display device 2 includes display terminal products such as a flat-panel display device, a notebook display device, and a vehicle-mounted central control, especially a terminal product with a medium or large-sized display panel, the display device 2 includes the above-mentioned display panel 1, and the beneficial effects produced by the display device 2 are also the beneficial effects described in the above-mentioned embodiment, which will not be repeated here.

[0059] The above description shows and describes several preferred embodiments of the present application, but as mentioned above, it should be understood that the present application is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the invention concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present application, and should be within the scope of protection of the claims attached to the present application.

Claims

1. A display panel, characterized in that: include: A display area and a non-display area surrounding the display area, wherein the non-display area includes a first non-display area; At least two driving chips, wherein the driving chips are located in the first non-display area; a plurality of scanning lines extending along a first direction; A plurality of test pads, an information identification code, and a plurality of alignment marks, wherein along the first direction, at least one of the plurality of test pads, the information identification code, and the plurality of alignment marks or a portion of at least one of the plurality of test pads, the information identification code, and the plurality of alignment marks is located between the driving chips; The display panel comprises at least one irregular edge, an extending direction of the irregular edge forms an angle with the first direction, and the angle is greater than 0° and less than 90°; A plurality of alignment marks are symmetrically distributed relative to the central axis.

2. The display panel according to claim 1, characterized in that: The plurality of test pads are all placed between the driving chips.

3. The display panel according to claim 1, characterized in that: Some of the test pads are placed between the driving chips.

4. The display panel according to claim 3, characterized in that: The driving chip comprises an edge driving chip and a middle driving chip, wherein the edge driving chip is a driving chip close to the edge of the display panel, and along the first direction, the middle driving chip is located between the edge driving chips; The plurality of test pads include a first pad, and the first pad is located between the edge driving chip and the edge of the display panel; The display panel includes a driving circuit and a signal line arranged in a second non-display area, the second non-display area is located on both sides of the display area along the first direction, and the first pad is electrically connected to the driving circuit and the signal line at least partially located in the second non-display area.

5. The display panel according to claim 4, characterized in that: The display panel includes a ground line located in the non-display area and partially surrounding the display area, and the first pad is electrically connected to the ground line.

6. The display panel according to claim 5, characterized in that: Along the first direction, the information identification code and the plurality of alignment marks are located between the driving chips.

7. The display panel according to claim 5, characterized in that: The display panel includes at least one group of gate driving circuits, the at least one group of gate driving circuits includes a plurality of cascaded shift register circuits, the at least one group of gate driving circuits is located in the second non-display area, and the at least one group of gate driving circuits is electrically connected to the scan line; A portion of the first pad is electrically connected to the ground line, and a portion of the first pad is electrically connected to the gate driving circuit.

8. The display panel according to claim 2 or 3, characterized in that: The driving chip comprises an edge driving chip and a middle driving chip, wherein the edge driving chip is a driving chip close to the edge of the display panel, and the middle driving chip is located between the edge driving chips; The plurality of test pads include a second pad, the second pad is located between the driver chips along the first direction, the second pad includes a first sub-pad, and the first sub-pad is located between the edge driver chip and the middle driver chip; The display panel comprises at least one group of gate driving circuits, the at least one group of gate driving circuits comprises a plurality of cascaded shift register circuits, and the at least one group of gate driving circuits is located at one side of the display area along the first direction; The first sub pad is electrically connected to the gate driving circuit.

9. The display panel according to claim 8, characterized in that: The display panel comprises a first connection line, one end of the first connection line is electrically connected to the first sub-pad, and the other end of the first connection line is electrically connected to the gate driving circuit; The display panel includes a binding area, the driving chip is electrically connected to the binding area, the binding area includes binding terminals, the binding terminals include input terminals and output terminals, the first connecting line runs through the binding area, and the first connecting line is located between the input terminal and the output terminal.

10. The display panel according to claim 2 or 3, characterized in that: The plurality of test pads include a second pad, and along the first direction, the second pad is located between the driving chips; The display panel includes a plurality of multiplexers, at least some of which are located between the display area and the driving chip; Some of the second pads are electrically connected to the multiplexer.

11. The display panel according to claim 10, characterized in that: The display panel includes a test control circuit, which is located between the multiplexer and the driving chip. Some of the second pads are electrically connected to the multiplexer, and some of the second pads are electrically connected to the test control circuit.

12. The display panel according to claim 11, characterized in that: Along the first direction, the second pad electrically connected to the test control circuit is located at both sides of the second pad electrically connected to the multiplexer.

13. The display panel according to claim 11, characterized in that: The display panel includes a second connecting line, one end of the second connecting line is electrically connected to the second pad, the other end of the second connecting line is electrically connected to the multiplexer, and the second connecting line includes a first metal routing line and a second metal routing line, wherein the first metal routing line and the second metal routing line are located in different metal layers.

14. The display panel according to claim 11, characterized in that: The number of the driver chips is n, wherein n is an odd number greater than or equal to 3, and the driver chips include a central driver chip, and the central driver chip is located at the center of the driver chip arrangement area; The second pad electrically connected to the multiplexer and the test control circuit is a second sub-pad, the second sub-pad includes m groups, m is less than or equal to n-1, and along the first direction, the number of the second sub-pads on both sides of the central driving chip is the same.

15. The display panel according to claim 11, characterized in that: The number of the driver chips is n, wherein n is an even number greater than or equal to 2, and the driver chips include a middle driver chip, the middle driver chip is located on both sides of the central axis of the driver chip arrangement area, and the middle driver chip is closest to the central axis; The second pads electrically connected to the multiplexer and the test control circuit are both located between the middle driving chips.

16. The display panel according to claim 11, characterized in that: The number of the driver chips is n, wherein n is an even number greater than or equal to 2, and the driver chips include a middle driver chip, the middle driver chip is located on both sides of the central axis of the driver chip arrangement area, and the middle driver chip is closest to the central axis; The second pad electrically connected to the multiplexer and the test control circuit is a second sub-pad, which includes m groups, m is less than or equal to n-1, and along the first direction, the number of the second sub-pads on both sides of the central axis is the same.

17. The display panel according to claim 1, characterized in that: The driving chip includes an edge driving chip and a middle driving chip. The edge driving chip is a driving chip close to the edge of the display panel. Along the first direction, the multiple test pads are all located between the edge of the display panel and the edge driving chip, and the multiple alignment marks are all located between the driving chips.

18. The display panel according to claim 17, characterized in that: The number of the driver chips is n, wherein n is an odd number greater than or equal to 3, and the driver chips include a central driver chip, and the central driver chip is located at the center of the driver chip arrangement area; Along the first direction, the plurality of alignment marks on two sides of the central driving chip are of the same number.

19. The display panel according to claim 17, characterized in that: The number of the driver chips is n, wherein n is an even number greater than or equal to 2, and the driver chips include a middle driver chip, the middle driver chip is located on both sides of the central axis of the driver chip arrangement area, and the middle driver chip is closest to the central axis; Along the first direction, the plurality of alignment marks are located between the middle driving chips, or the plurality of alignment marks on both sides of the central axis are the same in number.

20. The display panel according to claim 1, characterized in that: The display panel includes at least one group of gate driving circuits, and the at least one group of gate driving circuits includes a plurality of cascaded shift register circuits, and at least part of the shift register circuits are located in the non-display area corresponding to the irregular edge.

21. The display panel according to claim 20, characterized in that: Some of the plurality of test pads are electrically connected to the shift register circuit located in the non-display area corresponding to the irregular edge.

22. The display panel according to claim 1, characterized in that: The display panel includes a plurality of multiplexers, and at least part of the multiplexers are located in the non-display area corresponding to the irregular edge.

23. The display panel according to claim 22, characterized in that: Some of the plurality of test pads are electrically connected to the multiplexer located in the non-display area corresponding to the irregular edge.

24. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 23.

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