A low power consumption CMOS image sensor structure and implementation method thereof

Abstract

The present invention discloses a low-power CMOS image sensor structure and its implementation method, including a pixel array, a sampling and amplification unit, a comparison unit, a DAC code value generator, a DAC slope generator, a register processing unit and an output circuit unit; after sampling and amplifying the analog signal of the pixel array, an input signal is obtained, which is transmitted to one input end of the comparison unit, the digital code value of the DAC code value generator is transmitted to the DAC slope generator, and the ramp signal is transmitted to the other input end of the comparison unit. When the ramp signal is greater than the input signal, the comparison unit generates a flip signal, and the register processing unit stores the digital code value at this time, processes it, and outputs the result. The code value generator has both digital generation and counting functions, avoiding a large number of flips and counts generated by traditional counters during A / D conversion, effectively reducing the overall power consumption of the image sensor and the heat accumulation phenomenon caused by high power consumption, and improving the performance of temperature-sensitive image sensors.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and relates to a low-power CMOS image sensor structure and a realization method thereof. Background Art

[0002] CMOS image sensors are widely used in consumer electronics, industrial detection, and aerospace exploration due to their high integration, low power consumption, and good noise characteristics. CMOS image sensors are temperature-sensitive devices, and dark current will increase exponentially with the increase in temperature. Increased power consumption will lead to increased temperature and reduced performance. In addition, in order to achieve high-speed A / D conversion, high-frequency digital signals are inverted, resulting in high substrate noise. Since all transistors in the CMOS P-substrate process share a common substrate, the noise generated by high-frequency signals in the digital domain will interfere with analog devices through the common substrate, resulting in an increase in the overall noise of the CMOS image sensor.

[0003] The overall architecture of the CMOS image sensor in the prior art is as follows: Figure 3 As shown, it includes a pixel array, a column-parallel programmable gain amplifier, a column-parallel comparator, a column-parallel counter, a column logic, an LVDS output interface, a phase-locked loop, a DAC bit generator, and a DAC slope generator. The analog signal output by the pixel array is sampled and amplified by the column-parallel programmable gain amplifier. The DAC code value generator generates a digital signal from low to high, controls the DAC slope generator to generate an upward slope, and compares it with the column-parallel programmable gain amplifier through the column-parallel comparator, which serves as a trigger signal for the column-parallel counter to control the start and end of counting. The column-parallel counter is controlled by a high-frequency phase-locked loop to flip and count. One counter per column consumes a lot of power and generates a lot of flip noise. The code value output by the counter is converted from parallel to serial by the column logic and output to the outside of the chip by the LVDS output interface as the digital output of the overall image sensor.

[0004] The specific structure of the CMOS image sensor in the prior art is as follows: Figure 4 As shown, it includes a second pixel circuit, a programmable gain amplifier, a column ADC comparator, and a column ADC counter. The Vramp signal is compared with the Column input signal. When the ramp signal amplitude exceeds the Column input signal, the comparator flips. ADC_Clock is a high-frequency clock generated by a phase-locked loop. The comparator starts and ends counting under the control of ADC_Clock and the comparator flip signal. The ADC counter is a digital signal converted by A / D. The high-frequency flipping of the ADC counter not only consumes a lot of power, but also introduces a lot of noise. Summary of the invention

[0005] The purpose of the present invention is to solve the problem in the prior art that the temperature of a CMOS image sensor rises during operation due to increased power consumption, and the dark current increases exponentially with the increase in temperature, thereby causing the performance of the sensor to deteriorate, and to provide a low-power CMOS image sensor structure and an implementation method thereof.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A low-power CMOS image sensor structure, comprising a pixel array, a sampling and amplification unit, a comparison unit, a DAC code value generator, a DAC slope generator, a register processing unit and an output circuit unit;

[0008] The analog signal output by the pixel array is sampled and amplified by the sampling and amplification unit to obtain an input signal, and the input signal is transmitted to an input end of the comparison unit. The digital code value signal generated by the DAC code value generator is transmitted to the DAC slope generator through the storage processing unit. The ramp signal generated by the DAC slope generator is transmitted to the other input end of the comparison unit. When the ramp signal is greater than the input signal, the comparison unit generates a flip signal, and the storage processing unit stores the digital code value signal when the flip signal is generated. After the storage processing unit processes the digital code value signal, the result is output through the output circuit unit.

[0009] A further improvement of the present invention is:

[0010] The pixel array includes n first pixel circuits, and the first pixel circuit includes NMOS S4, NMOS S5, NMOS S6, a first NOMS and a diode;

[0011] The D poles of NMOS S4 and the first NMOS are both connected to VDD, the S pole of NMOS S4 is connected to the D pole of NMOS S5 and then connected to the G pole of the first NMOS, the S pole of NMOS S5 is grounded through a diode, the S pole of the first NMOS is connected to the S pole of NMOS S6, and the D pole of NMOS S6 outputs a reset signal and a photoelectric signal.

[0012] The sampling and amplification unit includes n single-column analog front ends, which receive analog signals output by the pixel array and output them to the comparison unit after sampling and amplification.

[0013] The comparison unit includes n single-column comparators, the positive input end of the single-column comparator receives the ramp signal of the DAC ramp generator, and the negative input end receives the signal transmitted by the sampling and amplifying unit.

[0014] The register processing unit includes n single-column register processors, which store digital code value signals when a flip signal is generated, and perform subtraction processing on the stored digital code value signals.

[0015] The output circuit unit includes a column logic and an LVDS output interface. After the column logic completes parallel-to-serial conversion of the output signal, the result is output through the LVDS output interface.

[0016] The DAC code value generator is a D flip-flop that is cascaded one by one.

[0017] A transmission control unit is arranged between the DAC code value generator and the register processing unit.

[0018] A method for realizing a low-power CMOS image sensor comprises the following steps:

[0019] The first pixel circuit generates a reset signal V rst and photoelectric signal V sig , the reset signal V rst and photoelectric signal V sig Transmitted to a single-column analog front end;

[0020] The single-column analog front end responds to the reset signal V at different times. rst and photoelectric signal V sig After sampling, holding and amplification, we get V IN , V IN Input to one input terminal of a single column comparator;

[0021] The DAC code value generator generates digital code values ​​from small to large, and the DAC ramp generator generates an upward ramp signal V according to the digital code value. ramp , V ramp Input to the other input terminal of the single column comparator;

[0022] When V ramp >V IN When the single column comparator flips, the single column register processor stores the digital code value of the DAC code value generator when the comparator flips;

[0023] After the conversion cycle is completed, the digital code values ​​stored in the single-column register processor are subtracted and output as the result.

[0024] The digital code value of the DAC code value generator is stored in a single-column register processor through a transmission control unit.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] By adopting a DAC code value generator, the digital code values ​​output by it are generated successively from low to high, thereby generating a linear upward slope. According to the characteristic of the gradual linear increase of the output code values, which is consistent with the characteristic of the linear counting of the counter count number from small to large, the DAC code value generator is multiplexed as a counter in the image sensor. Therefore, the DAC code value generator has the functions of digital generation and ADC counting, avoiding a large number of flips and counts generated by traditional counters during A / D conversion, greatly reducing the overall power consumption of the image sensor, reducing the heat accumulation phenomenon caused by high power consumption, and improving the performance of temperature-sensitive image sensors.

[0027] By using the flip signal of the single-column comparator as a trigger signal to generate a switch closing pulse, the digital code value output by the DAC code value generator is stored in the single-column register processor. Since the comparator flips twice in each conversion cycle, the two stored digital code values ​​are subtracted as the result output. Therefore, in each cycle, only three operations are required, namely, registering two digital code values ​​and performing one subtraction operation, which reduces the column-level operating frequency, not only reduces power consumption, but also reduces the noise interference of high-frequency signals on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 This is the overall architecture diagram of the low-power CMOS image sensor of the present invention;

[0030] Figure 2 This is a specific architecture diagram of the low-power CMOS image sensor of the present invention;

[0031] Figure 3 It is the overall structure diagram of the CMOS image sensor in the prior art;

[0032] Figure 4 It is a specific structural diagram of a CMOS image sensor in the prior art;

[0033] Figure 5 It is a schematic diagram of the structure of the DAC code value generator in the present invention;

[0034] Figure 6 Schematic diagram of the structure of the DAC ramp generator in the present invention;

[0035] Figure 7 It is a schematic diagram of the specific structure of the transmission control unit in the present invention.

[0036] Among them: 10-pixel array; 11-sampling and amplifying unit; 12-comparison unit; 13-column parallel counter; 14-column logic; 15-LVDS output interface; 16-phase-locked loop; 17-DAC code value generator; 18-DAC slope generator; 19-register processing unit; 20-second pixel circuit; 21-programmable gain amplifier; 22-column ADC comparator; 23-column ADC counter; 30-first pixel circuit; 31-analog front end; 32-single column comparator; 35-single column register processor; 36-transmission control unit. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0040] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0041] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", which does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0042] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0044] See also Figure 1 , which is an overall architecture diagram of the low-power CMOS image sensor of the present invention, includes a pixel array 10, a sampling and amplifying unit 11, a comparing unit 12, a column logic 14, an LVDS output interface 15, a DAC code value generator 17, a DAC slope generator 18 and a register processing unit 19. The analog signal output by the pixel array 10 is sampled and amplified by the sampling and amplifying unit 11 to obtain an input signal, and the input signal is transmitted to an input end of the comparing unit 12. The digital code value signal generated by the DAC code value generator 17 is transmitted to the DAC slope generator 18 through the register processing unit 19. The ramp signal generated by the DAC slope generator 18 is transmitted to the other input end of the comparing unit 12. When the ramp signal is greater than the input signal, the comparing unit 12 generates a flip signal, and the register processing unit 19 stores the digital code value signal when the flip signal is generated. After the register processing unit 19 processes the digital code value signal, the column logic 14 performs parallel-to-serial conversion, and the result is output through the LVDS output interface 15.

[0045] See also Figure 2 , is a specific structural diagram of the low-power CMOS image sensor of the present invention, including a first pixel circuit 30, a single-column analog front end 31, a single-column comparator 32, a single-column register processor 35, a transmission control unit 36, a DAC code value generator 17 and a DAC slope generator 18. The first pixel circuit 30 is a pixel circuit in columns, which is composed of a diode and four NMOS tubes. The D poles of NMOS S4 and the first NMOS are both connected to VDD, the S pole of NMOS S4 is connected to the D pole of NMOS S5 and then connected to the G pole of the first NMOS, the S pole of NMOS S5 is grounded through a diode, the S pole of the first NMOS is connected to the S pole of NMOS S6, and the D pole of NMOS S6 outputs a reset signal and a photoelectric signal; the D pole of NMOS S6 is connected to the input end of the single-column analog front end 31, and the input signal V is obtained after sampling and amplification processing. IN , V INThe positive input terminal of the single column comparator 32 receives the ramp signal of the DAC ramp generator 18. When the ramp signal is greater than the input signal V IN When the single-column comparator 32 is flipped, the flip signal of the single-column comparator 32 is used as a trigger signal, and the digital code value of the DAC code value generator 17 at the time of flipping is stored in the single-column register processor 35 through the transmission control unit 36. Since two samplings are performed in each cycle, there are two ramp signals, the first one is used to quantize the reset signal, and the second one is used to quantize the photoelectric signal. Therefore, the comparator is flipped twice in each conversion cycle, and the digital code values ​​stored during the two flips are subtracted as the output data.

[0046] See also Figure 5 , is a schematic diagram of the specific structure of the DAC code value generator 17 in the present invention. The DAC code value generator 17 uses a cascaded D flip-flop to generate a count and ramp signal from low to high. Figure 6 , is a schematic diagram of the specific structure of the DAC ramp generator 18 in the present invention. The DAC ramp generator 18 is a switched capacitor array. As the code value generated by the DAC code value generator 17 gradually increases, the analog ramp signal output by the DAC ramp generator increases upward. Figure 7 , is the specific structure of the transmission control unit 36. The digital code value signals D0~Dn generated by the DAC code value generator 17 are transmitted from left to right perpendicular to the column direction. In order to enhance the driving performance, a digital buffer is added in the middle to ensure the integrity of the waveform and the normal duty cycle. On the path connecting the single-column register processor, a switch-controlled connection is used. The on and off of the switch is controlled by the flip signal generated by the single-column comparator 32, and the digital code value signals D0~Dn generated by the DAC code value generator 17 are stored in the single-column register processor 35.

[0047] According to the digital code values ​​output by the DAC code value generator 17, they are generated successively from low to high, thereby generating a linear upward slope. According to the characteristic that the code values ​​output by the DAC code value generator 17 gradually increase linearly, which is consistent with the characteristic that the counter counts linearly from small to large, the DAC code value generator 17 can be reused as the counter of the entire image sensor, which can greatly reduce the area of ​​the entire structure. Therefore, in the image sensor, the DAC code value generator 17 has the functions of both digital generation and ADC counting, avoiding a large number of flips and counts generated by the traditional counter during A / D conversion, greatly reducing the overall power consumption of the image sensor, reducing the heat accumulation phenomenon caused by high power consumption, and improving the performance of the temperature-sensitive image sensor.

[0048] The specific implementation method of the present invention comprises the following steps:

[0049] S1, the first pixel circuit 30 generates a reset signal V rstand photoelectric signal V sig , the reset signal V rst and photoelectric signal V sig Transmitted to the single column analog front end 31;

[0050] S2, single column analog front end 31 pairs of reset signals V rst and photoelectric signal V sig After sampling, holding and amplification, we get V IN , V IN Input to an input terminal of the single column comparator 32;

[0051] S3, the DAC code value generator 17 generates digital code values ​​from small to large, and the DAC slope generator 18 generates an upward slope signal V according to the digital code values. ramp , V ramp Input to the other input terminal of the single column comparator 32;

[0052] S4, when V ramp >V IN When the single column comparator 32 flips, the single column register processor 35 stores the digital code value of the DAC code value generator 17 when the comparator flips;

[0053] S5, after the conversion cycle is completed, the digital code values ​​stored in the single-column register processor 35 are subtracted and output as the result.

[0054] The flip signal of the single-column comparator 32 is used as a trigger signal to generate a switch closing pulse, and the digital code value output by the DAC code value generator 17 is stored in the single-column register processor 35. Since the comparator flips twice in each conversion cycle, the two stored digital code values ​​are subtracted and output as the result. Therefore, in each A / D conversion cycle, only three operations are required, namely, registering two digital code values ​​and performing one subtraction operation. In the prior art, for an ADC with a 12-bit resolution, the average number of counts per column is about 0.5×(4096+512)=2304 times. For an image sensor with a 1k-column array scale, the total number of counts is 2304000 times. In the present invention, by reducing the number of operations per column to three times, for an image sensor with a 1k-column array scale, the number of counts is only 3000 times, which significantly reduces the column-level operation frequency, not only reduces power consumption, but also reduces the noise interference of high-frequency signals to the substrate.

[0055] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A low power CMOS image sensor structure, characterized in that: It comprises a pixel array (10), a sampling and amplification unit (11), a comparison unit (12), a DAC code value generator (17), a DAC slope generator (18), a register processing unit (19) and an output circuit unit; The analog signal output by the pixel array (10) is sampled and amplified by the sampling and amplification unit (11) to obtain an input signal, which is transmitted to an input end of the comparison unit (12); the digital code value signal generated by the DAC code value generator (17) is transmitted to the DAC slope generator (18) through the register processing unit (19); the ramp signal generated by the DAC slope generator (18) is transmitted to the other input end of the comparison unit (12); when the ramp signal is greater than the input signal, the comparison unit (12) generates a flip signal; the register processing unit (19) stores the digital code value signal when the flip signal is generated; the register processing unit (19) processes the digital code value signal and outputs the result through the output circuit unit; the analog ramp signal output by the DAC slope generator (18) increases upward; and the DAC code value generator (17) is a D flip-flop that is cascaded one by one.

2. A low power consumption CMOS image sensor structure as claimed in claim 1, characterized in that: The pixel array (10) comprises n first pixel circuits (30), and the first pixel circuit (30) comprises NMOSS4, NMOSS5, NMOSS6, a first NOMS and a diode; The D poles of NMOSS4 and the first NMOS are both connected to VDD, the S pole of NMOSS4 is connected to the D pole of NMOSS5 and then connected to the G pole of the first NMOS, the S pole of NMOSS5 is grounded through a diode, the S pole of the first NMOS is connected to the S pole of NMOSS6, and the D pole of NMOSS6 outputs a reset signal and a photoelectric signal.

3. A low power consumption CMOS image sensor structure as claimed in claim 1, characterized in that: The sampling and amplification unit (11) comprises n single-column analog front ends (31), which receive analog signals output by the pixel array (10) and output them to the comparison unit (12) after sampling and amplification.

4. A low power consumption CMOS image sensor structure as claimed in claim 1, characterized in that: The comparison unit (12) comprises n single-column comparators (32), wherein the positive input end of the single-column comparator (32) receives the ramp signal of the DAC ramp generator (18), and the negative input end receives the signal transmitted by the sampling and amplification unit (11).

5. A low power consumption CMOS image sensor structure as claimed in claim 1, characterized in that: The register processing unit (19) comprises n single-column register processors (35), wherein the single-column register processors (35) store digital code value signals when a flip signal is generated, and perform subtraction processing on the stored digital code value signals.

6. A low power consumption CMOS image sensor structure as claimed in claim 1, characterized in that: The output circuit unit comprises a column logic (14) and an LVDS output interface (15); after the column logic (14) completes parallel-to-serial conversion of the output signal, the result is output via the LVDS output interface (15).

7. A low power consumption CMOS image sensor structure as claimed in claim 1, characterized in that: A transmission control unit (36) is provided between the DAC code value generator (17) and the register processing unit (19).

8. A method for realizing a low-power CMOS image sensor, characterized in that: The following steps are involved: The first pixel circuit (30) generates a reset signal V rst and photoelectric signal V sig , the reset signal V rst and photoelectric signal V sig Transmitted to a single column analog front end (31); The single-column analog front end (31) responds to the reset signal V at different times. rst and photoelectric signal V sig After sampling, holding and amplification, we get V IN , V IN Input to an input terminal of a single column comparator (32); The DAC code value generator (17) generates digital code values ​​from small to large, and the DAC ramp generator (18) generates an upward ramp signal V according to the digital code values. ramp , V ramp Input to the other input terminal of the single column comparator (32); When V ramp >V IN When the single column comparator (32) flips, the single column register processor (35) stores the digital code value of the DAC code value generator (17) when the comparator flips; After the conversion cycle is completed, the digital code values ​​stored in the single-column register processor (35) are subtracted and output as the result.

9. The method for realizing a low power consumption CMOS image sensor according to claim 8, characterized in that: The digital code value of the DAC code value generator (17) is stored in the single-column register processor (35) through the transmission control unit (36).

Images