Simulating high stress edge effect optimization integration method of BiCMOS process and high linearity dual polycrystalline capacitor

Abstract

The present invention discloses an optimized integration method for high stress edge effect of analog BiCMOS process and a high linearity dual polycrystalline capacitor, the steps of which include: 1) depositing a polycrystalline film layer of a polycrystalline capacitor lower plate of P1 angstrom above a field oxide layer on the surface of an N-type well, and completing N-type photolithography implantation doping; 2) depositing a first dielectric layer of a dual polycrystalline capacitor of d1 angstrom, and completing the production of a protective film layer at the edge of the lower electrode of the dual polycrystalline capacitor by an exposure and etching process; 3) depositing a polycrystalline capacitor dielectric composite film layer of d2 angstroms, and completing the production of a capacitor dielectric layer structure by an exposure and etching process; the high linearity dual polycrystalline capacitor includes a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well, a self-aligned P-type well, etc. The present invention significantly improves the edge effect of the dual polycrystalline capacitor by integrating a high stress edge effect optimization technical solution of a high linearity dual polycrystalline capacitor in an analog integrated circuit.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuits, in particular to a high stress edge effect optimization integration method of analog BiCMOS process and a high linearity dual polycrystalline capacitor. Background Art

[0002] With the trend of lightweight and miniaturization of electronic equipment, the integration complexity of integrated circuits, which are the main components of electronic equipment, is also getting higher and higher. Especially for analog integrated circuits based on process device parameters, it is a process of multi-dimensional optimization and compromise selection of circuit parameters such as linearity, noise, drift, etc. It is an organic unity of the artistry and science of circuit design and process manufacturing in pursuit of the ultimate circuit performance (for example, high speed, high precision, low drift, low offset, etc.). High linearity integrated dual polycrystalline capacitors are widely used in high-precision analog integrated circuits due to their superior process compatibility, especially for high-precision detection in deep space, deep earth, deep sea, etc. and in complex working environments. These small voltage modulation effects become particularly important especially when working in precisely matched capacitors of different voltages (such as in charge redistribution analog-to-digital converters ADC and digital-to-analog converters DAC).

[0003] On the other hand, in analog BiCMOS integrated circuits with integrated high-linearity dual polycrystalline capacitors, the stress mismatch and electric field concentration caused by the edge effects of the integrated polycrystalline capacitors significantly affect the grain regrowth in the polycrystalline thin layer, the impurity redistribution in the grains, the grain depletion, and the grain boundary size and shape. These effects have an important impact on the electrical performance stability and long-term reliability of the integrated dual polycrystalline capacitors.

[0004] Therefore, the use of effective process technology to optimize the high mechanical stress and local electric field concentration caused by the edge effect of integrated high-linear dual polycrystalline capacitors can better meet the technical development requirements of improving the high precision, high linearity and long-term reliability of analog integrated circuits, and is an important task for the development of analog BiCMOS integrated circuits towards high speed, high precision and miniaturization. Summary of the invention

[0005] The object of the present invention is to provide a method for optimizing integration of high stress edge effects of analog BiCMOS process, comprising the following steps:

[0006] 1) Forming an N-type buried layer, a P-type buried layer, and an N-type epitaxial growth on the substrate;

[0007] 2) Forming an N-type well, a P-type well and a vertical NPN bipolar transistor collector N+ implant on the epitaxial layer and completing the well push junction;

[0008] 3) completing P-type implantation of the base region of the vertical NPN bipolar transistor in the N-type well;

[0009] 4) depositing a silicon nitride film, and exposing and etching away the silicon nitride film layer outside the active device area, and using a thermal oxidation process to grow a field oxide layer of m angstroms;

[0010] 5) depositing a polycrystalline film layer of the lower plate of the polycrystalline capacitor of P1 angstrom above the field oxide layer on the surface of the N-type well, and completing N-type photolithography implantation doping;

[0011] 6) growing an n angstrom thermal oxide layer using wet oxygen process conditions;

[0012] 7. Deposit the first dielectric layer of the dual polycrystalline capacitor of d1 angstrom, and use an exposure and etching process to complete the production of the protective film layer at the edge of the lower electrode of the dual polycrystalline capacitor;

[0013] 8) depositing a polycrystalline capacitor dielectric composite film layer of d2 angstroms, and completing the capacitor dielectric layer structure by using an exposure and etching process;

[0014] 9) Complete the conventional process before the gate poly deposition of analog CMOS integrated circuits;

[0015] 10) depositing a P2 angstrom MOS transistor gate polycrystalline film layer and completing MOS transistor gate polycrystalline doping;

[0016] 11) Complete the subsequent conventional processes of analog CMOS integrated circuits.

[0017] Furthermore, the method for depositing the polycrystalline film layer of the lower plate of the polycrystalline capacitor, the first dielectric layer of the double polycrystalline capacitor, and the polycrystalline film layer of the gate of the MOS transistor includes a low-pressure chemical vapor deposition method.

[0018] Further, the polycrystalline film layer of the lower plate of the polycrystalline capacitor is used as the lower plate of the high linearity dual polycrystalline capacitor;

[0019] The polycrystalline film layer of the upper plate of the polycrystalline capacitor serves as the upper plate of the high linearity dual polycrystalline capacitor.

[0020] Furthermore, the dielectric constant of the first layer of the dual polycrystalline capacitor is ε1, and the dielectric constant of the polycrystalline capacitor dielectric composite film layer is ε2.

[0021] Furthermore, the conventional process before the gate poly deposition of the analog CMOS integrated circuit includes sacrificial oxidation, channel adjustment implantation, exposure etching, and gate oxide oxidation.

[0022] Furthermore, the subsequent conventional processes of analog CMOS integrated circuits include source and drain implantation, emitter implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

[0023] Furthermore, in step 3), a low pressure chemical vapor deposition method is also used to deposit a polycrystalline film layer of the upper plate of the high linear dual polycrystalline capacitor and an edge protection film layer of the upper plate polycrystalline film layer;

[0024] Furthermore, the edge protection film layer of the polycrystalline film layer (105) of the upper plate of the high linearity dual polycrystalline capacitor adopts the same polycrystalline side protection structure as the MOS transistor gate in the conventional analog CMOS or BiCMOS integrated circuit process.

[0025] A high-linearity dual polycrystalline capacitor based on the high-stress edge effect optimization integration method of the analog BiCMOS process includes a substrate, an N-type buried layer, a P-type buried layer, an N-type epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a low dielectric constant filling film layer, a metal interconnect film layer, and a passivation layer;

[0026] The substrate is located at the bottom;

[0027] The epitaxial layer is located on the substrate;

[0028] The N-type buried layer and the P-type buried layer are located at the bottom of the epitaxial layer;

[0029] The N-type well and the self-aligned P-type well are located on the surface of the epitaxial layer;

[0030] The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well;

[0031] The double polycrystalline capacitor polycrystalline film layer is located above the field oxide layer above the N-well;

[0032] The top surface and side walls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers, silicon nitride composite dielectric layers, and high dielectric constant capacitor dielectric layers.

[0033] The low dielectric constant filling film layer fills the area between silicon-metal, polysilicon-metal, field oxygen-metal and multi-layer metal.

[0034] Furthermore, a polycrystalline capacitor upper plate sidewall film layer is deposited on the sidewall of the polycrystalline film layer of the polycrystalline capacitor upper plate.

[0035] The technical effect of the present invention is unquestionable. The present invention significantly improves the edge effect of the dual polycrystalline capacitor by integrating a high-stress edge effect optimization manufacturing method of a high-linear dual polycrystalline capacitor in an analog BiCMOS integrated circuit process, reduces the mechanical stress of the integrated dual polycrystalline capacitor, alleviates the electric field concentration in the edge area of ​​the dual polycrystalline capacitor, and improves the electrical performance stability and process consistency of the voltage modulation of the dual polycrystalline capacitor in the analog integrated circuit.

[0036] The present invention improves the uniformity of grain regrowth and impurity redistribution in the polycrystalline thin layer by simulating the high stress edge effect optimization technical solution of high linearity dual polycrystalline capacitor integrated in BiCMOS integrated circuit process, and effectively improves the ability of high linearity integrated dual polycrystalline capacitor in analog integrated circuit to perform complex and high precision detection in deep space, deep earth, deep sea and other working environments.

[0037] The present invention adopts a high stress edge effect optimization manufacturing method for integrated high linearity dual polycrystalline capacitors in an analog BiCMOS integrated circuit process, improves grain depletion and grain boundary size and shape in the polycrystalline thin layer of the polycrystalline capacitor plate under electrical stress, and effectively improves the long-term reliability of high linearity integrated dual polycrystalline capacitor products in analog integrated circuits.

[0038] By means of the optimized manufacturing method for high stress edge effect of integrated high linearity dual polycrystalline capacitor in the BiCMOS integrated circuit process of the present invention, the matching degree of the integrated dual polycrystalline capacitor can be improved from the mismatch of ±0.1% to the precisely matched mismatch level of ±0.01%, which can be applicable to high precision A / D and D / A converters with a resolution of more than 14 bits, thus improving the process compatibility and device integration density and enhancing the market competitiveness of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a cross-sectional view of the growth of the shield oxide layer after completing the conventional analog BiCMOS integrated circuit processes such as buried layer implantation, epitaxial growth, well implantation, annealing, and field oxidation;

[0040] Figure 2 It is a cross-sectional view of the lower plate of the double polycrystalline capacitor after the polycrystalline film layer is deposited and doped;

[0041] Figure 3 It is a cross-sectional view of the edge protective film layer of the polycrystalline film layer of the lower plate of the polycrystalline capacitor;

[0042] Figure 4 It is a cross-sectional view of the polycrystalline capacitor capacitor dielectric layer deposition and exposure etching structure;

[0043] Figure 5 It is a partial enlarged cross-sectional view of the edge area of ​​the dual polycrystalline capacitor structure after the subsequent wet etching and oxidation processes are completed without using the edge optimization technology solution;

[0044] Figure 6 It is a partial enlarged cross-sectional view of the edge area of ​​the dual polycrystalline capacitor structure after the subsequent wet etching and oxidation processes are completed using the edge optimization technology solution;

[0045] Figure 7 It is a schematic diagram of the 3D structure after the polycrystalline film layer of the upper plate of the polycrystalline capacitor is deposited and doped, and then exposed and etched;

[0046] Figure 8This is a schematic diagram of the main device structure of the analog BiCMOS process integration before the metal interconnection process: including polycrystalline emitter vertical bipolar transistor VNPN, MOS transistor NMOS, high linearity dual polycrystalline capacitor PIP-Capacitor, low temperature coefficient polycrystalline resistor Poly-Resistor;

[0047] Fig. 9 After completing the two-layer metal interconnection process, the main device structure diagram of the BiCMOS process integration is simulated: including polycrystalline emitter vertical bipolar transistor VNPN, MOS transistor NMOS, high linearity dual polycrystalline capacitor PIP-Capacitor, low temperature coefficient polycrystalline resistor Poly-Resistor;

[0048] Fig.10 Schematic diagram of the structure of the analog BiCMOS integrated high linearity dual polycrystalline capacitor after edge optimization in Example 1;

[0049] In the figure, field oxide layer 101, N-type well 102, polycrystalline film layer 103 of the lower plate of polycrystalline capacitor, polycrystalline capacitor dielectric composite film layer 104, polycrystalline film layer 105 of the upper plate of polycrystalline capacitor, side wall film layer 106 of the upper plate of polycrystalline capacitor, tungsten plug structure 107 of contact hole between polycrystalline capacitor plate and metal layer, edge protection film layer 108 of lower electrode of double polycrystalline capacitor, ILD dielectric planarization layer 201 between polycrystalline silicon / field oxide and metal layer, first metal film layer area 202, tungsten plug structure area 203 of through hole between multi-layer metal layers, IMD dielectric planarization layer 204 between multi-layer metal layers, and top metal layer area 205. DETAILED DESCRIPTION

[0050] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0051] Embodiment 1:

[0052] See also Figures 1 to 10 , a method for optimizing integration by simulating high stress edge effect of BiCMOS process, comprising the following steps:

[0053] 1) Forming an N-type buried layer, a P-type buried layer, and an N-type epitaxial growth on the substrate;

[0054] 2) Forming an N-type well, a P-type well and a vertical NPN bipolar transistor collector N+ implant on the epitaxial layer and completing the well push junction;

[0055] 3) completing P-type implantation of the base region of the vertical NPN bipolar transistor in the N-type well;

[0056] 4) depositing a silicon nitride film, and exposing and etching away the silicon nitride film layer outside the active device area, and using a thermal oxidation process to grow a field oxide layer of m angstroms;

[0057] 5) depositing a polycrystalline film layer of the lower plate of the polycrystalline capacitor of P1 angstrom above the field oxide layer on the surface of the N-type well, and completing N-type photolithography implantation doping;

[0058] 6) A n angstrom thermal oxide layer is grown using wet oxygen process conditions; m, n, d1, d2, p1, p2, ε1, ε2 are real numbers.

[0059] 7. Deposit the first dielectric layer of the dual polycrystalline capacitor of d1 angstrom, and use an exposure and etching process to complete the production of the protective film layer at the edge of the lower electrode of the dual polycrystalline capacitor;

[0060] 8) depositing a polycrystalline capacitor dielectric composite film layer of d2 angstroms, and completing the capacitor dielectric layer structure by using an exposure and etching process;

[0061] 9) Complete the conventional process before the gate poly deposition of analog CMOS integrated circuits;

[0062] 10) depositing a P2 angstrom MOS transistor gate polycrystalline film layer and completing MOS transistor gate polycrystalline doping;

[0063] 11) Complete the subsequent conventional processes of analog CMOS integrated circuits.

[0064] The method for depositing the polycrystalline film layer of the lower plate of the polycrystalline capacitor, the first dielectric layer of the double polycrystalline capacitor, and the gate polycrystalline film layer of the MOS transistor includes a low-pressure chemical vapor deposition method.

[0065] The polycrystalline film layer of the lower plate of the polycrystalline capacitor is used as the lower plate of the high linearity dual polycrystalline capacitor;

[0066] The polycrystalline film layer of the upper plate of the polycrystalline capacitor serves as the upper plate of the high linearity dual polycrystalline capacitor.

[0067] The dielectric constant of the first layer of the dual polycrystalline capacitor is ε1, and the dielectric constant of the polycrystalline capacitor dielectric composite film layer is ε2.

[0068] The conventional processes before gate poly deposition of analog CMOS integrated circuits include sacrificial oxidation, channel injection, exposure etching, and gate oxide oxidation.

[0069] The subsequent conventional processes of analog CMOS integrated circuits include source and drain implantation, emitter region implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

[0070] In step 3), a low pressure chemical vapor deposition method is also used to deposit a polycrystalline film layer of the upper plate of the high linear dual polycrystalline capacitor and an edge protection film layer of the upper plate polycrystalline film layer;

[0071] The edge protection film layer of the polycrystalline film layer of the upper plate of the high linearity dual polycrystalline capacitor adopts the same structure as the polycrystalline side protection of the gate of the MOS transistor in the conventional analog CMOS or BiCMOS integrated circuit process.

[0072] A high-linearity dual polycrystalline capacitor based on the high-stress edge effect optimization integration method of the analog BiCMOS process includes a substrate, an N-type buried layer, a P-type buried layer, an N-type epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a low dielectric constant filling film layer, a metal interconnect film layer, and a passivation layer;

[0073] The substrate is located at the bottom;

[0074] The epitaxial layer is located on the substrate;

[0075] The N-type buried layer and the P-type buried layer are located at the bottom of the epitaxial layer;

[0076] The N-type well and the self-aligned P-type well are located on the surface of the epitaxial layer;

[0077] The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well;

[0078] The double polycrystalline capacitor polycrystalline film layer is located above the field oxide layer above the N-well;

[0079] The top surface and side walls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers, silicon nitride composite dielectric layers, and high dielectric constant capacitor dielectric layers.

[0080] The low dielectric constant filling film layer fills the area between silicon-metal, polysilicon-metal, field oxygen-metal and multi-layer metal.

[0081] A polycrystalline capacitor upper plate sidewall film layer is deposited on the sidewall of the polycrystalline film layer of the polycrystalline capacitor upper plate.

[0082] Embodiment 2:

[0083] The method for optimizing integration of high stress edge effect of simulated BiCMOS process includes the following steps:

[0084] 1) Forming an N-type buried layer, a P-type buried layer, and an N-type epitaxial growth on the substrate;

[0085] 2) Forming an N-type well, a P-type well and a vertical NPN bipolar transistor collector N+ implant on the epitaxial layer and completing the well push junction;

[0086] 3) completing P-type implantation of the base region of the vertical NPN bipolar transistor in the N-type well;

[0087] 4) depositing a silicon nitride film, and exposing and etching away the silicon nitride film layer outside the active device area, and using a thermal oxidation process to grow a field oxide layer of m angstroms;

[0088] 5) depositing a polycrystalline film layer of the lower plate of the polycrystalline capacitor of P1 angstrom above the field oxide layer on the surface of the N-type well, and completing N-type photolithography implantation doping;

[0089] 6) growing an n angstrom thermal oxide layer using wet oxygen process conditions;

[0090] 7. Deposit the first dielectric layer of the dual polycrystalline capacitor of d1 angstrom, and use an exposure and etching process to complete the production of the protective film layer at the edge of the lower electrode of the dual polycrystalline capacitor;

[0091] 8) depositing a polycrystalline capacitor dielectric composite film layer of d2 angstroms, and completing the capacitor dielectric layer structure by using an exposure and etching process;

[0092] 9) Complete the conventional process before the gate poly deposition of analog CMOS integrated circuits;

[0093] 10) depositing a P2 angstrom MOS transistor gate polycrystalline film layer and completing MOS transistor gate polycrystalline doping;

[0094] 11) Complete the subsequent conventional processes of analog CMOS integrated circuits.

[0095] Embodiment 3:

[0096] The optimized integration method of high stress edge effect of simulated BiCMOS process, the main steps are shown in Example 2, wherein the method of depositing the polycrystalline film layer of the lower plate of the polycrystalline capacitor, the first dielectric layer of the double polycrystalline capacitor, and the polycrystalline film layer of the gate of the MOS transistor includes a low-pressure chemical vapor deposition method.

[0097] Embodiment 4:

[0098] The optimized integration method for simulating high stress edge effect of BiCMOS process, the main steps are shown in Example 2, wherein the polycrystalline film layer of the lower plate of the polycrystalline capacitor is used as the lower plate of the high linearity dual polycrystalline capacitor;

[0099] The polycrystalline film layer of the upper plate of the polycrystalline capacitor serves as the upper plate of the high linearity dual polycrystalline capacitor.

[0100] Embodiment 5:

[0101] The optimized integration method for simulating high stress edge effect of BiCMOS process has main steps as shown in Example 2, wherein the dielectric constant of the first layer of the dual polycrystalline capacitor is ε1, and the dielectric constant of the polycrystalline capacitor dielectric composite film layer is ε2.

[0102] Embodiment 6:

[0103] The main steps of the high stress edge effect optimization integration method of the simulated BiCMOS process are shown in Example 2, wherein the conventional process before the gate polycrystalline deposition of the simulated CMOS integrated circuit includes sacrificial oxidation, channel injection, exposure etching, and gate oxide oxidation.

[0104] Embodiment 7:

[0105] The high stress edge effect optimization integration method of the simulated BiCMOS process, the main steps are shown in Example 2, wherein the subsequent conventional processes of the simulated CMOS integrated circuit include source and drain injection, emitter injection, annealing activation, dielectric layer deposition, reflow filling and flattening, contact hole etching, and metal interconnection.

[0106] Embodiment 8:

[0107] The high stress edge effect optimization integration method of the simulated BiCMOS process, the main steps are shown in Example 2, wherein, in step 3), a low pressure chemical vapor deposition method is also used to deposit the upper plate polycrystalline film layer of the high linear dual polycrystalline capacitor and the edge protection film layer of the upper plate polycrystalline film layer; Example 9:

[0108] The invention relates to an optimized integration method for high stress edge effect in analog BiCMOS process. The main steps are shown in Example 2, wherein the edge protection film layer of the polycrystalline film layer (105) of the upper plate of the high linearity dual polycrystalline capacitor adopts the same structure as the MOS transistor gate polycrystalline side protection structure in the conventional analog CMOS or BiCMOS integrated circuit process.

[0109] Embodiment 10:

[0110] A high-linearity dual polycrystalline capacitor based on the high-stress edge effect optimization integration method of the analog BiCMOS process includes a substrate, an N-type buried layer, a P-type buried layer, an N-type epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a low dielectric constant filling film layer, a metal interconnect film layer, and a passivation layer;

[0111] The substrate is located at the bottom;

[0112] The epitaxial layer is located on the substrate;

[0113] The N-type buried layer and the P-type buried layer are located at the bottom of the epitaxial layer;

[0114] The N-type well and the self-aligned P-type well are located on the surface of the epitaxial layer;

[0115] The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well;

[0116] The double polycrystalline capacitor polycrystalline film layer is located above the field oxide layer above the N-well;

[0117] The top surface and sidewall of the polycrystalline film layer are covered with different silicon dioxide and silicon nitride composite dielectric layers and a high dielectric constant capacitor dielectric layer.

[0118] The low dielectric constant filling film layer fills the area between silicon-metal, polysilicon-metal, field oxygen-metal and multi-layer metal.

[0119] Embodiment 11:

[0120] The high linearity dual polycrystalline capacitor based on the high stress edge effect optimization integration method of the analog BiCMOS process, the main content of which is shown in Example 10, wherein the side wall of the polycrystalline film layer of the upper plate of the polycrystalline capacitor is deposited with a polycrystalline capacitor upper plate side wall film layer.

[0121] Embodiment 12:

[0122] See also Figures 1 to 8 , a method for optimizing integration by simulating high stress edge effect of BiCMOS process, comprising the following steps:

[0123] 1) An N-type well 102 is formed on the substrate, and a self-aligned P-type well is formed in a region outside the N-type well 102 .

[0124] 2) A field oxide layer 101 with a thickness of m angstroms is formed on the surfaces of the N-type well 102 and the self-aligned P-well. m, n, d1, d2, P2, and P1 are all real numbers greater than 0.

[0125] 3) Deposit a polycrystalline film layer 103 of the polycrystalline capacitor bottom plate with a thickness of P1 angstrom above the field oxide layer on the surface of the N-type well, and complete N-type photolithography implantation doping.

[0126] 4) Grow an n angstrom thermal oxide layer using wet oxygen process conditions.

[0127] 5) Deposit the first layer of the dual polycrystalline capacitor dielectric of d1 angstroms, and use an exposure and etching process to complete the production of the dual polycrystalline capacitor bottom electrode edge protection film layer 108.

[0128] This optimization step is particularly suitable for high-low voltage compatible analog CMOS integrated circuits. The process integration of high-voltage MOS transistors and low-voltage MOS transistors requires the compatibility of double-layer gate oxide layers with a difference of more than several hundred millimeters. Therefore, wet lateral etching of a gate oxide film layer thicker than 1.3 times thick is inevitable. If the edge protection film layer of the lower electrode of the polycrystalline capacitor is not used, this will cause oxide layer voids of corresponding thickness to appear at the edge of the lower plate of the polycrystalline capacitor above the field oxide layer. After completing subsequent oxidation, annealing and other thermal processes, the edge of the film layer of the lower plate of the polycrystalline capacitor will be warped, resulting in stress mismatch, such as Figure 5 shown.

[0129] 6) Deposit a polycrystalline capacitor dielectric composite film layer 104 of d2 angstroms, and use an exposure and etching process to complete the capacitor dielectric layer structure.

[0130] 7) Complete the conventional process before the gate poly deposition of the simulated CMOS integrated circuit.

[0131] 8) Deposit a P2 angstrom MOS transistor gate polycrystalline film layer and complete the MOS transistor gate polycrystalline doping.

[0132] 9) Complete the subsequent conventional processes of analog CMOS integrated circuits.

[0133] The method of depositing the polycrystalline film layer 103 of the lower plate of the polycrystalline capacitor, the first dielectric layer of the double polycrystalline capacitor, and the gate polycrystalline film layer of the MOS transistor includes a low-pressure chemical vapor deposition method.

[0134] The polycrystalline film layer 103 of the polycrystalline capacitor bottom plate serves as a high linearity dual polycrystalline capacitor bottom plate.

[0135] The polycrystalline film layer 103 of the polycrystalline capacitor upper plate serves as the upper plate of a high linearity dual polycrystalline capacitor.

[0136] The dielectric constant of the first layer of the dual polycrystalline capacitor is ε1, and the dielectric constant of the polycrystalline capacitor dielectric composite film layer 104 is ε2.

[0137] The conventional processes before gate poly deposition of analog CMOS integrated circuits include sacrificial oxidation, channel injection, exposure etching, and gate oxide oxidation.

[0138] The subsequent conventional processes of analog CMOS integrated circuits include source and drain implantation, emitter region implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

[0139] In step 3), a low pressure chemical vapor deposition method is also used to deposit the polycrystalline film layer 105 of the upper plate of the high linearity dual polycrystalline capacitor and the edge protection film layer of the upper plate polycrystalline film layer.

[0140] The edge protection film layer of the polycrystalline film layer 105 of the upper plate of the high linearity dual polycrystalline capacitor adopts the same structure as the polycrystalline side protection of the gate of the MOS transistor in the conventional analog CMOS or BiCMOS integrated circuit process.

[0141] The high linearity dual polycrystalline capacitor based on the high stress edge effect optimization integration method of the analog BiCMOS process includes a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well 102, a self-aligned P-type well, a field oxide layer 101, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a low dielectric coefficient filling film layer, a polycrystalline capacitor plate-metal layer contact hole tungsten plug structure 107, a polysilicon / field oxygen-metal layer ILD dielectric planarization layer 201, a first metal film layer region 202, a multi-layer metal layer interlayer through hole tungsten plug structure region 203, a multi-layer metal layer interlayer IMD dielectric planarization layer 204, and a top metal layer region 205.

[0142] The substrate is located at the bottom.

[0143] The epitaxial layer is located on the substrate.

[0144] The N-type buried layer and the P-type buried layer are located at the bottom of the epitaxial layer.

[0145] The N-type well 102 and the self-aligned P-type well are located on the surface of the epitaxial layer.

[0146] The field oxide layer 101 , the sacrificial oxide layer, and the gate oxide layer cover different regions of the well respectively.

[0147] The polycrystalline film layer of the double polycrystalline capacitor is located above the field oxide layer on the surface of the N-type well 102 .

[0148] The polycrystalline film layer of the dual polycrystalline capacitor includes a polycrystalline film layer 103 of a lower plate of the polycrystalline capacitor and a polycrystalline film layer 105 of an upper plate of the polycrystalline capacitor.

[0149] The surface of the polycrystalline film layer 103 of the lower plate of the polycrystalline capacitor is covered with a silicon dioxide dielectric layer, which serves as the polycrystalline capacitor dielectric composite film layer 104 .

[0150] The surface of the polycrystalline capacitor dielectric composite film layer 104 is covered with a polycrystalline capacitor lower plate edge protection film layer 108 .

[0151] The polycrystalline film layer 105 of the upper plate of the polycrystalline capacitor is located above the edge protection film layer 108 of the lower plate of the polycrystalline capacitor.

[0152] The surface of the polycrystalline film layer 105 of the upper plate of the polycrystalline capacitor is covered with a silicon oxynitride dielectric layer.

[0153] The polycrystalline capacitor bottom plate edge protection film layer 108 is connected to the first metal film layer region 202 through the polycrystalline capacitor plate-metal layer contact hole tungsten plug structure 107 .

[0154] The polysilicon / field oxygen-metal interlayer ILD dielectric planarization layer 201 is filled between a plurality of polycrystalline capacitor plate-metal interlayer contact hole tungsten plug structures 107 , the polycrystalline capacitor lower plate edge protection film layer 108 , and the polycrystalline film layer 105 of the polycrystalline capacitor upper plate.

[0155] The first metal film layer region 202 is connected to the top metal layer region 205 through a multi-layer metal interlayer via tungsten plug structure region 203 .

[0156] The multi-layer metal interlayer IMD dielectric planarization layer 204 is filled between the multi-layer metal interlayer via tungsten plug structure regions 203 and the first metal film layer region 202 .

[0157] A polycrystalline capacitor upper plate sidewall film layer 106 is deposited on the sidewall of the polycrystalline film layer 105 of the polycrystalline capacitor upper plate.

[0158] Embodiment 13:

[0159] The high stress edge effect optimization integration method of the analog BiCMOS process is implemented in the dual-gate oxide layer high and low voltage compatible analog CMOS integrated circuit process, mainly including the following steps:

[0160] 1) forming an N-type well in the substrate and forming a self-aligned P-type well in the area outside the N-type well;

[0161] 2) forming a field oxide layer of m angstroms on the surface of the N-well and the self-aligned P-well;

[0162] 3) A P1 angstrom polycrystalline film layer is deposited on the field oxide layer by low-pressure chemical vapor deposition, and N-type photolithography implantation doping is completed according to the performance requirements of the capacitor. The polycrystalline film layer can be used as the lower plate of a high-linear dual polycrystalline capacitor;

[0163] A polycrystalline film layer of the lower plate of the double polycrystalline capacitor is deposited on the field oxide layer above the N-type well, and the doping oxidation enhancement effect is utilized to reduce the influence of parasitic capacitance and substrate noise and improve the performance of the polycrystalline capacitor device.

[0164] 4) growing an n angstrom thermal oxide layer using wet oxygen process conditions;

[0165] The main process temperature of wet oxygen is ≤850℃, and the main process time is ≤30min, which is conducive to process compatibility and reduces the impact on the main process devices of analog CMOS integrated circuits.

[0166] 5) Using low pressure chemical vapor deposition to deposit the first layer of dielectric (dielectric constant is ε1) of d1 angstrom dual polycrystalline capacitor and exposure etching process, the edge protection structure of the lower electrode of the dual polycrystalline capacitor is fabricated.

[0167] 6) Deposit the required capacitor dielectric film layer according to the parameter performance of the high linear dual polycrystalline capacitor, with a dielectric constant of ε2 and a film thickness of d2 angstroms. Use exposure and etching process to complete the capacitor dielectric layer structure;

[0168] The capacitor dielectric film layer can be a high dielectric constant film layer to increase the unit capacitance of the dual polycrystalline capacitor.

[0169] Under the premise of ensuring the performance requirements of the polycrystalline capacitor, the capacitor dielectric film layer can be the same film layer as the dielectric film layer of the polycrystalline capacitor edge protection structure described in 5) to simplify the process steps.

[0170] 7) forming a m1 angstrom thick gate oxide layer in the area of ​​the well surface not covered by the field oxide layer; removing the m1 angstrom thick gate oxide layer in the active area of ​​the low voltage device, and forming a m2 angstrom thin gate oxide layer after cleaning;

[0171] After the thick gate oxide layer is generated, the threshold adjustment and implantation of the CMOS device are completed as required. Then the thick gate oxide layer is removed in the active area of ​​the low voltage device, and the required thin gate oxide layer is generated after cleaning, which is conducive to improving the integrity of the gate oxide layer.

[0172] Especially for the integrated dual polycrystalline capacitor array circuit layout, the polycrystalline film layer of the polycrystalline capacitor bottom electrode with edge protection structure significantly improves Figure 5 The stress mismatch warping phenomenon of the polycrystalline film layer shown in the figure improves the matching degree and integration density of the integrated dual polycrystalline capacitor. The optimized structure is as follows Figure 6 shown.

[0173] 8) using low pressure chemical vapor deposition to deposit a P2 angstrom MOS transistor gate polycrystalline film layer, and completing MOS transistor gate polycrystalline doping according to MOS device performance requirements;

[0174] 9) Next, complete the normal analog CMOS integrated circuit source and drain implantation, annealing activation, dielectric layer deposition, reflow filling and flattening, contact hole etching, metal interconnection and other processes;

[0175] Embodiment 14:

[0176] The main contents of the optimized integration method of high stress edge effect of analog BiCMOS process are shown in Examples 1-13, wherein, for the analog BiCMOS integrated circuit process, the integrated production of high linearity dual polycrystalline capacitor with optimized high stress edge effect is carried out on the basis of completing the processes of N-type buried layer, P-type buried layer, epitaxial growth, N-well injection push-junction, P-well injection push-junction, field oxide layer growth, etc.

[0177] 1) Using the MOS transistor gate polycrystalline film layer as the lower plate polycrystalline film layer of the polycrystalline capacitor, and adopting the polycrystalline plate edge optimization technical solution described in Implementation 1.

[0178] If the analog BiCMOS integrated circuit process uses a gate polycrystalline sidewall structure, it is not necessary to specifically optimize the edge area of ​​the polycrystalline film layer of the lower plate of the polycrystalline capacitor.

[0179] 2) Depositing a polycrystalline film layer for the upper plate of the double polycrystalline capacitor, and completing doping, exposure, and etching to form the upper plate structure of the polycrystalline capacitor.

[0180] For a polycrystalline emitter Bipolar transistor, an external emitter polycrystalline film layer can be used as an upper plate of a polycrystalline capacitor, which simplifies the process steps and does not require special optimization of the edge region of the polycrystalline film layer of the upper plate of the polycrystalline capacitor.

[0181] The subsequent steps adopt the normal analog BiCMOS integrated circuit process scheme:

[0182] Embodiment 15:

[0183] The main contents of the high stress edge effect optimization integration method of the analog BiCMOS process are shown in Examples 1-14, wherein, for the pre-process of the self-aligned dual polycrystalline analog Bipolar integrated circuit process, the integrated production of the high stress edge effect optimization of the high linear dual polycrystalline capacitor is carried out on the basis of completing the processes of N-type buried layer, P-type buried layer, epitaxial growth, N-well injection push junction, P-well injection push junction, field oxide layer growth, etc.:

[0184] 1) Using the external base region polycrystalline layer as the polycrystalline film layer of the lower plate of the polycrystalline capacitor, and adopting the polycrystalline plate edge optimization technical solution described in Implementation 1.

[0185] 2) The external emitter polycrystalline film layer is used as the upper plate of the polycrystalline capacitor, and there is no need to specifically optimize the edge area of ​​the polycrystalline film layer of the upper plate of the polycrystalline capacitor.

[0186] The subsequent steps adopt the normal analog Bipolar integrated circuit process solution.

[0187] Embodiment 16:

[0188] A method for optimizing integration of high stress edge effect of simulated BiCMOS process mainly comprises the following steps:

[0189] 1) Forming N-type buried layer, P-type buried layer, and N-type epitaxial growth on the substrate

[0190] 2) Forming an N-type well, a P-type well and a vertical NPN bipolar transistor collector N+ implant on the epitaxial layer and completing the well push junction;

[0191] 3) completing P-type implantation of the base region of the vertical NPN bipolar transistor in the N-type well;

[0192] 4) depositing a silicon nitride film, and exposing and etching away the silicon nitride film layer outside the active device area, and using a thermal oxidation process to grow a field oxide layer of m angstroms;

[0193] 5) The field oxide layer area above the N-type well is deposited with a P1 angstrom polycrystalline film layer using low-pressure chemical vapor deposition, and N-type photolithography implantation doping is completed according to the performance requirements of the capacitor. This polycrystalline film layer can be used as the lower plate of a high-linear dual polycrystalline capacitor;

[0194] 6) growing an n angstrom thermal oxide layer using thermal oxidation process conditions;

[0195] 7) Using low pressure chemical vapor deposition to deposit the first layer of dielectric (dielectric constant ε1) of the d1 angstrom dual polycrystalline capacitor and exposure and etching process, the edge protection structure of the lower electrode of the dual polycrystalline capacitor is fabricated.

[0196] 8) Deposit the required capacitor dielectric film layer according to the parameter performance of the high linear dual polycrystalline capacitor, with a dielectric constant of ε2 and a film thickness of d2 angstroms. Use exposure and etching process to complete the capacitor dielectric layer structure;

[0197] 9) Complete the normal process steps such as sacrificial oxidation, channel injection, exposure etching, gate oxide oxidation, etc. before the gate polycrystalline deposition of the analog BiCMOS integrated circuit;

[0198] 10) using low pressure chemical vapor deposition to deposit a P2 angstrom MOS transistor gate polycrystalline film layer, and completing MOS transistor gate polycrystalline doping according to MOS device performance requirements;

[0199] 11) Next, complete the normal analog BiCMOS integrated circuit source, drain injection and emitter injection, annealing activation, dielectric layer deposition, reflow filling and flattening, contact hole etching, metal interconnection and other processes;

[0200] The method for forming the oxide layer of the polycrystalline film layer of the lower electrode of the double polycrystalline capacitor, the edge protection layer, and the capacitor dielectric layer is as follows:

[0201] 1) In the thermal oxidation process of the polycrystalline film layer of the lower electrode of the double polycrystalline capacitor, the main process temperature is ≤850°C and the main process time is ≤30min;

[0202] 2) In the edge protection layer of the polycrystalline film layer of the lower electrode of the double polycrystalline capacitor, a dielectric film layer with a thickness of d1 angstroms and a dielectric constant of ε1 is deposited by low-pressure chemical vapor deposition;

[0203] 3) In the production of the dielectric layer of the high linear dual polycrystalline capacitor, a dielectric film layer with a thickness of d2 angstroms and a dielectric constant of ε2 is deposited according to the capacitor performance requirements;

[0204] The edge protection film layer of the polycrystalline film layer of the upper plate of the high linearity dual polycrystalline capacitor adopts the same structure as the polycrystalline side protection structure of the gate of the MOS transistor in the normal analog BiCMOS integrated circuit process.

[0205] The double polycrystalline capacitor manufactured by the optimized integration method of high stress edge effect of the analog BiCMOS process mainly includes a substrate, an N-type buried layer, a P-type buried layer, an N-type epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer and a low dielectric constant filling film layer, a metal interconnect film layer, and a passivation layer;

[0206] The substrate is located at the bottom; the buried layer is located at the bottom of the epitaxial layer; and the well region is located on the surface of the epitaxial layer;

[0207] The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well;

[0208] The double polycrystalline capacitor polycrystalline film layer is located above the field oxide layer above the N-well;

[0209] The top surface and sidewall of the polycrystalline film layer are covered with different silicon dioxide and silicon nitride composite dielectric layers and a high dielectric constant capacitor dielectric layer.

[0210] The low dielectric coefficient filling film layer fills the area between silicon-metal, polysilicon-metal, field oxygen-metal and multi-layer metal.

[0211] Embodiment 17:

[0212] A method for optimizing the manufacturing of a high-stress edge effect of a high-linearity dual polycrystalline capacitor that can be integrated in an analog BiCMOS integrated circuit process mainly includes the following steps:

[0213] 1) Forming N-type buried layer, P-type buried layer, and N-type epitaxial growth on the substrate

[0214] 2) Forming an N-type well, a P-type well and a vertical NPN bipolar transistor collector N+ implant on the epitaxial layer and completing the well push junction;

[0215] 3) Complete P-type implantation of the base region of the vertical NPN Bipolar transistor in the N-type well;

[0216] 4) depositing a silicon nitride film, and exposing and etching away the silicon nitride film layer outside the active device area, and using a thermal oxidation process to grow a field oxide layer of m angstroms;

[0217] 5) Deposit a P1 angstrom polycrystalline film layer on the field oxide layer using low pressure chemical vapor deposition, and complete N-type photolithography implantation doping according to the capacitor performance requirements. The polycrystalline film layer can be used as the lower plate of a high linear dual polycrystalline capacitor;

[0218] A polycrystalline film layer of the lower plate of the double polycrystalline capacitor is deposited on the field oxide layer above the N-type well, and the doping oxidation enhancement effect is utilized to reduce the influence of parasitic capacitance and substrate noise and improve the performance of the polycrystalline capacitor device.

[0219] 6) growing an n angstrom thermal oxide layer using thermal oxidation process conditions;

[0220] The main process temperature of thermal oxidation is ≤850℃, and the main process time is ≤30min, which is conducive to process compatibility and reduces the impact on the main process devices of analog BiCMOS integrated circuits.

[0221] 7) Using low pressure chemical vapor deposition to deposit the first layer of dielectric (dielectric constant ε1) of the d1 angstrom dual polycrystalline capacitor and exposure and etching process, the edge protection structure of the lower electrode of the dual polycrystalline capacitor is fabricated.

[0222] 8) Deposit the required capacitor dielectric film layer according to the parameter performance of the high linear dual polycrystalline capacitor, with a dielectric constant of ε2 and a film thickness of d2 angstroms. Use exposure and etching process to complete the capacitor dielectric layer structure;

[0223] The capacitor dielectric film layer can be a high dielectric constant film layer to increase the unit capacitance of the dual polycrystalline capacitor.

[0224] Under the premise of ensuring the performance requirements of the polycrystalline capacitor, the capacitor dielectric film layer can be the same film layer as the dielectric film layer of the polycrystalline capacitor edge protection structure described in 7) to simplify the process steps.

[0225] 9) Complete the normal process steps such as sacrificial oxidation, channel injection, exposure etching, gate oxide oxidation, etc. before the gate polycrystalline deposition of the analog BiCMOS integrated circuit;

[0226] Especially for the integrated dual polycrystalline capacitor array circuit layout, the polycrystalline film layer of the polycrystalline capacitor bottom electrode with edge protection structure significantly improves Figure 5 The stress mismatch warping phenomenon of the polycrystalline film layer shown in the figure improves the matching degree and integration density of the integrated dual polycrystalline capacitor. The optimized structure is as follows Figure 6 shown.

[0227] 10) using low pressure chemical vapor deposition to deposit a P2 angstrom MOS transistor gate polycrystalline film layer, and completing MOS transistor gate polycrystalline doping according to MOS device performance requirements;

[0228] 11) Next, complete the normal analog BiCMOS integrated circuit MOS transistor source and drain injection and Bipolar transistor emitter injection, annealing activation, dielectric layer deposition, reflow filling and flattening, contact hole etching, metal interconnection and other processes;

[0229] Embodiment 18:

[0230] For the analog BiCMOS integrated circuit process described in Examples 1-17, integrated production of high-linearity dual polycrystalline capacitors with high stress edge effect optimization is carried out based on the completion of processes such as N-type buried layer, P-type buried layer, epitaxial growth, N-well injection push-junction, P-well injection push-junction, and field oxide layer growth.

[0231] 1) Using the MOS transistor gate polycrystalline film layer as the lower plate polycrystalline film layer of the polycrystalline capacitor, and adopting the polycrystalline plate edge optimization technical solution described in Implementation 1.

[0232] If the analog BiCMOS integrated circuit process adopts the gate polycrystalline sidewall structure, the gate polycrystalline sidewall structure can be improved to optimize the edge effect of the polycrystalline film layer of the lower plate of the polycrystalline capacitor

[0233] 2) Depositing a polycrystalline film layer for the upper plate of the double polycrystalline capacitor, and completing doping, exposure, and etching to form the upper plate structure of the polycrystalline capacitor.

[0234] For polycrystalline emitter Bipolar transistors, the external emitter polycrystalline film layer can be used as the upper plate of the polycrystalline capacitor to simplify the process steps. At the same time, the dielectric reflow filling after the emitter polycrystalline film layer is etched can be used to optimize the edge effect of the polycrystalline film layer on the upper plate of the polycrystalline capacitor.

[0235] The subsequent steps adopt the normal analog BiCMOS integrated circuit process scheme:

[0236] Embodiment 19:

[0237] For the analog BiCMOS integrated circuit process of the integrated self-aligned dual polycrystalline Bipolar transistor described in Examples 1-18, after completing the processes of N-type buried layer, P-type buried layer, epitaxial growth, N-well injection push-junction, P-well injection push-junction, field oxide layer growth, etc., the integrated production of high linearity dual polycrystalline capacitor with high stress edge effect optimization is carried out. :

[0238] 1) Using the external base region polycrystalline layer as the polycrystalline film layer of the lower plate of the polycrystalline capacitor, and adopting the polycrystalline plate edge optimization manufacturing method described in Implementation 17.

[0239] 2) The external emitter polycrystalline film layer is used as the upper plate of the polycrystalline capacitor, and the dielectric reflow filling after the emitter polycrystalline film layer is etched can be used to optimize the edge effect of the polycrystalline film layer on the upper plate of the polycrystalline capacitor.

[0240] The subsequent steps adopt the same process scheme of simulating BiCMOS integrated circuit in Example 17.

[0241] Embodiment 20:

[0242] An optimized manufacturing method for integrating high-linearity dual polycrystalline capacitors with high stress edge effects in an analog BiCMOS integrated circuit process as described in Example 1-19, the technical solution mainly comprises the following steps: 1) growing a field oxide layer above the N-type well of the analog BiCMOS integrated circuit; 2) depositing a polycrystalline film layer of the lower plate of the dual polycrystalline capacitor on the field oxide layer above the N-well by a low-pressure chemical deposition method; 3) growing an oxide film layer on the polycrystalline film layer of the lower electrode of the dual polycrystalline capacitor by a thermal oxygen oxidation method; 4) depositing an edge protection film layer and structure of the polycrystalline film layer of the lower plate of the polycrystalline capacitor; the optimized analog BiCMOS integrated circuit can integrate a high-linearity dual polycrystalline capacitor with high stress edge effects, which mainly includes a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a low dielectric constant filling film layer, a metal interconnect film layer, and a passivation layer. The present invention provides an optimized manufacturing method for high stress edge effect of integrated high linear dual polycrystalline capacitors in analog BiCMOS integrated circuit process, which improves the matching degree of integrated capacitors from ±0.1% mismatch to ±0.01% mismatch level of accurate matching, and can be applied to high-precision A / D and D / A converters with resolution above 14 bits. The optimization scheme proposed by the present invention reduces the stress mismatch and electric field concentration effect of polycrystalline capacitors, improves the uniformity of grain regrowth and impurity redistribution in polycrystalline thin layers, and at the same time, the optimization scheme improves the ability of high linear integrated dual polycrystalline capacitors to be applied to complex high-precision detection work in deep space, deep earth, deep sea and other working environments, and effectively improves the electrical performance stability, long-term reliability and market competitiveness of high linear integrated dual polycrystalline capacitors.

Claims

1. A method for optimizing integration of high stress edge effects in analog BiCMOS process, characterized in that: The following steps are involved: 1) Forming an N-type buried layer, a P-type buried layer, and an N-type epitaxial growth on the substrate; 2) Forming an N-type well and a P-type well on the epitaxial layer; forming a vertical NPN bipolar transistor collector N+ injection in the N-type well and completing the well push junction; 3) Complete the P-type implantation of the base region of the vertical NPN bipolar transistor in the epitaxial layer; 4) Deposit silicon nitride film, and expose and etch away the silicon nitride film outside the active device area, and use thermal oxidation process to grow m angstroms of field oxide; 5) Deposition on top of the field oxide layer on the surface of the N-type well P 1 angstrom polycrystalline film layer of the lower plate of the double polycrystalline capacitor, and complete N-type photolithography implantation doping; 6) Growth using wet oxygen process conditions n Angstrom thermal oxide layer; 7) Deposition d The first dielectric layer of the dual polycrystalline capacitor with a thickness of 1 angstrom is used, and the edge protection film layer of the lower electrode of the dual polycrystalline capacitor is completed by using an exposure and etching process; The edge protection film layer of the lower electrode of the double polycrystalline capacitor covers the side surface of the lower electrode plate of the double polycrystalline capacitor and a part of the top surface adjacent to the side surface; 8) Deposition d2 The double polycrystalline capacitor dielectric composite film layer of Angstrom is used, and the capacitor dielectric layer structure is completed by using exposure and etching process; A low-pressure chemical vapor deposition method is also used to deposit a polycrystalline film layer on the upper plate of a high-linear dual-polycrystalline capacitor and an edge protection film layer on the polycrystalline film layer on the upper plate; The edge protection film layer of the polycrystalline film layer (105) of the upper plate of the high linearity dual polycrystalline capacitor adopts the same structure as the MOS transistor gate polycrystalline side protection structure in the conventional analog CMOS or BiCMOS integrated circuit process; 9) Complete the conventional process before the gate poly deposition of analog BiCMOS integrated circuits; 10) Deposition P 2 angstrom MOS transistor gate polycrystalline film layer, and complete MOS transistor gate polycrystalline doping; 11) Complete the subsequent conventional processes of analog BiCMOS integrated circuits.

2. The analog BiCMOS process high stress edge effect optimization integration method according to claim 1, characterized in that: The method of depositing the polycrystalline film layer of the lower plate of the double polycrystalline capacitor, the first dielectric layer of the double polycrystalline capacitor, and the gate polycrystalline film layer of the MOS transistor includes a low-pressure chemical vapor deposition method.

3. The analog BiCMOS process high stress edge effect optimization integration method according to claim 1, characterized in that: The polycrystalline film layer of the lower electrode plate of the dual polycrystalline capacitor is used as the lower electrode plate of the high linearity dual polycrystalline capacitor; The polycrystalline film layer of the upper plate of the dual polycrystalline capacitor serves as the upper plate of the high linearity dual polycrystalline capacitor.

4. The analog BiCMOS process high stress edge effect optimization integration method according to claim 1, characterized in that: The dielectric constant of the first layer of the double polycrystalline capacitor is ε 1. The dielectric constant of the dual polycrystalline capacitor dielectric composite film layer is ε 2.

5. The analog BiCMOS process high stress edge effect optimization integration method according to claim 1, characterized in that: The conventional processes before gate poly deposition of analog BiCMOS integrated circuits include sacrificial oxidation, channel injection, exposure etching, and gate oxide oxidation.

6. The analog BiCMOS process high stress edge effect optimization integration method according to claim 1, characterized in that: The subsequent conventional processes of analog BiCMOS integrated circuits include source and drain implantation, emitter region implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

7. A high linearity dual polycrystalline capacitor based on the high stress edge effect optimization integration method of the analog BiCMOS process according to any one of claims 1 to 6, characterized in that: Including substrate, N-type buried layer, P-type buried layer, N-type epitaxial layer, N-type well, P-type well, field oxide layer, sacrificial oxide layer, gate oxide layer, polycrystalline thin film layer, silicon dioxide dielectric layer, silicon oxynitride dielectric layer, low dielectric constant filling film layer, metal interconnect film layer, passivation layer; The substrate is located at the bottom; The epitaxial layer is located on the substrate; The N-type buried layer and the P-type buried layer are located at the bottom of the epitaxial layer; The N-type well and the self-aligned P-type well are located on the surface of the epitaxial layer; The field oxide layer, the sacrificial oxide layer, and the gate oxide layer respectively cover different areas of the well; The polycrystalline film layer of the lower plate of the double polycrystalline capacitor is located above the field oxide layer above the N-well; The top surface and sidewall of the polycrystalline film layer of the lower plate of the double polycrystalline capacitor are covered with different silicon dioxide dielectric layers, silicon nitride composite dielectric layers, and high dielectric coefficient capacitor dielectric layers; The low dielectric constant filling film layer fills the area between silicon-metal, polysilicon-metal, field oxygen-metal and multi-layer metal.

8. The high linearity dual polycrystalline capacitor according to claim 7, characterized in that: A polycrystalline capacitor upper plate sidewall film layer is deposited on the sidewall of the polycrystalline film layer of the double polycrystalline capacitor upper plate.

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