Semiconductor packaging structure and its formation method

Abstract

An embodiment of the present application provides a semiconductor packaging structure and a method for forming the same, the packaging structure comprising: a first chip, the first chip comprising a first contact structure and a first through silicon via electrically connected to the first contact structure; the back side of the first chip having a groove, the groove exposing the first contact structure; a second chip, the second chip comprising a second contact structure; the first chip and the second chip being bonded to the second contact structure via the first contact structure to form the packaging structure having an air gap.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor packaging structure and a method for forming the same. Background Art

[0002] As people's requirements for electronic products develop in the direction of miniaturization and multifunctionality, packaging is also developing in the direction of high density and high integration, and the corresponding integrated circuit products are turning from two-dimensional to three-dimensional. At present, in the advanced packaging process of three-dimensional integrated circuit products, thermal compression bonding / non-conductive film (TCB-NCF) technology is usually used to achieve the stacking of multi-layer chips. Among them, the non-conductive film is used to release the stress between chips during the thermal compression bonding process, which is also the mainstream technical route for high-bandwidth memory (HBM) products. However, TCB-NCF technology has many shortcomings and deficiencies, such as the easy generation of holes during the NCF filling process; it is easy to cause poor welding of micro-bumps, etc., which affects the strength and airtightness of the packaging structure. Summary of the invention

[0003] In view of this, the present invention provides a semiconductor packaging structure and a method for forming the same.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor packaging structure, comprising: a first chip, the first chip comprising a first contact structure and a first through silicon via electrically connected to the first contact structure; the back side of the first chip having a groove, the groove exposing the first contact structure; a second chip, the second chip comprising a second contact structure; the first chip and the second chip are bonded to the second contact structure via the first contact structure to form the packaging structure having an air gap.

[0005] In some embodiments, the first contact structures and the second contact structures are arranged at intervals, and each of the first contact structures is correspondingly connected to one of the second contact structures.

[0006] In some embodiments, a barrier layer is disposed around a portion of the first TSV facing the first contact structure, and the barrier layer and a portion of the first substrate together constitute a sidewall structure of a portion of the first TSV, and the sidewall structure is spaced apart in the trench.

[0007] In some embodiments, the first contact structure is a first pad, and the second contact structure is one of a bump and a second pad.

[0008] In some embodiments, when the second contact structure is a second bonding pad, the spacer structure further covers the first contact structure, and the air gap is formed around the spacer structure.

[0009] In some embodiments, when the second contact structure is a bump, the air gap is formed around the spacer structure, the first contact structure and the bump.

[0010] In some embodiments, the top surface of the first substrate on the back side of the first chip except for the first substrate, the sidewall structure and the first contact structure exposed by the groove is covered with a protective layer, and the top surface of the air gap is flush with the top surface of the protective layer.

[0011] In some embodiments, when the second contact structure is a bump, a top surface of the protection layer is higher than a top surface of the spacer structure.

[0012] In some embodiments, the front side of the first chip further includes a third contact structure, and the third contact structure is electrically connected to a surface of the first through silicon via facing the front side of the first chip.

[0013] In some embodiments, the second chip is bonded to at least two of the first chips to form a stacked package structure.

[0014] In a second aspect, an embodiment of the present application also provides a method for forming a semiconductor packaging structure, comprising: forming a first chip, the first chip comprising a first contact structure and a first through silicon via electrically connected to the first contact structure; the back side of the first chip having a groove, the groove exposing the first contact structure; forming a second chip, the second chip comprising a second contact structure; bonding the first chip and the second chip through the first contact structure and the second contact structure to form the packaging structure having an air gap.

[0015] In some embodiments, the forming of the first chip includes: providing a first initial chip, the first initial chip including a first substrate structure and the first through-silicon via, the first through-silicon vias being arranged at intervals; etching a portion of the first initial substrate structure on the back side of the first initial chip to form an initial groove, the initial groove exposing a portion of the first through-silicon via; depositing an initial barrier layer, the initial barrier layer covering the first initial substrate structure and a portion of the first through-silicon via; etching the initial barrier layer to expose the top surface of the first through-silicon via toward the back side of the first initial chip; forming the first contact structure on the top surface of the first through-silicon via; etching the remaining initial barrier layer and a portion of the first initial substrate structure to form the groove.

[0016] In some embodiments, the forming of the second chip includes: providing a second initial chip, wherein the second initial chip includes a second substrate structure; depositing a second initial barrier layer on the front side of the second initial chip, the second initial barrier layer covering the second substrate structure; etching the second initial barrier layer to form an opening, and forming the second contact structure in the opening.

[0017] In some embodiments, the first chip and the second chip are hybrid bonded or micro-bump bonded through the first contact structure and the second contact structure to form the package structure with an air gap.

[0018] In some embodiments, a third initial barrier layer is formed on the front side of the first chip, the third initial barrier layer is etched to expose the surface of the first through silicon via facing the front side of the first chip, and a third contact structure is formed on the surface of the first through silicon via facing the front side of the first chip, and the third contact structure is electrically connected to the first through silicon via.

[0019] In some embodiments, the second chip is bonded to at least two of the first chips to form a stacked package structure.

[0020] In the embodiment of the present application, since the back side of the first chip has a groove, during the bonding process between the first chip and the second chip, the groove in the first chip can be used to release the stress during the bonding process, so that the bonding process can be performed without using a non-conductive film, thereby solving the problems of holes and poor welding that occur during the bonding process due to the use of a non-conductive film. At the same time, since the dielectric constant of the air gap is low, short circuits and crosstalk between silicon through vias can be effectively avoided. In addition, due to the presence of the air gap, the heat in the semiconductor packaging structure can be diffused to the groove air gap in time, so that the heat can be quickly dissipated, thereby improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 2B A schematic diagram of a semiconductor packaging structure provided by an embodiment of the present application;

[0022] Figure 2C for Figure 2A Schematic diagram of the structure obtained by cutting along EE;

[0023] Figure 2D for Figure 2A Enlarged view of area D in the middle;

[0024] Figure 3 A schematic diagram of a process for forming a semiconductor packaging structure provided in an embodiment of the present application;

[0025] FIG. 4A to FIG. 4IA schematic diagram of the structure of a first chip during the formation process provided in an embodiment of the present application;

[0026] FIG. 5A to FIG. 5D A schematic diagram of the structure of a second chip during the formation process provided in an embodiment of the present application;

[0027] FIG. 6A to FIG. 7 A schematic diagram of another semiconductor packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0029] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0030] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] The present application embodiment provides a semiconductor packaging structure, such as Figure 1A As shown, the packaging structure includes:

[0034] A first chip 10, the first chip 10 comprising a first contact structure 102 and a first through silicon via 103 electrically connected to the first contact structure 102;

[0035] The back side of the first chip 10 has a groove 104 , and the groove 104 exposes the first contact structure 102 ;

[0036] A second chip 20 , the second chip 20 comprising a second contact structure 202 ;

[0037] The first chip 10 and the second chip 20 are bonded to each other via the first contact structure 102 and the second contact structure 202 to form a packaging structure with an air gap.

[0038] Here, the first chip can be the bottom layer chip in the semiconductor package structure, or it can be the middle layer chip in the semiconductor package structure. In the case where the first chip is the bottom layer chip in the semiconductor package structure, the first chip can be used to form a logic chip in the semiconductor package structure; in the case where the first chip is the middle layer chip in the semiconductor package structure, the first chip can be used to form a core chip in the semiconductor package structure. Among them, the logic chip can be a chip configured to communicate with other core chips so as to access data from the core chip and store the data in the core chip. The logic chip may include, but is not limited to, a graphics processing unit (Graphic Processing Unit, GPU), a field programmable gate array (Field Programmable Gate Array, FPGA), an application-specific integrated circuit (Application-specific integrated circuit, ASIC), a central processing unit (Central Processing Unit, CPU) or other known electronic circuits used as processors. The core chip may include a dynamic random access memory (Dynamic Random Access Memory, DRAM) chip.

[0039] The first chip 10 includes a first substrate 101. The first substrate 101 may be a single-layer substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display; or a multi-layer substrate, such as a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate. Shallow trench isolation (STI) may also be formed in the single-layer or multi-layer first substrate to isolate a number of active areas in an array distribution or other distribution types in the first substrate. STI may be formed by forming a trench in the first substrate and then filling the trench with an isolation material layer. The material filled in STI may include silicon nitride or silicon oxide, and silicon oxide may be formed by thermal oxidation.

[0040] In some embodiments, the front side of the first substrate further includes a device layer (not shown in the figure). The device layer may include different types of active devices and / or passive devices according to the type of the first chip. For example, when the first chip is a flash memory, DRAM, static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), the device layer may include AND, OR, NOT gate logic gates, system large scale integrated circuits (LSIC) or micro-electro-mechanical systems (MEMS), etc.

[0041] The device layer may further include a wiring structure, which may electrically connect at least two devices, a device and a conductive structure in the first substrate, or a device and a first contact structure to achieve connection between devices and between the first chip and other chips.

[0042] The first silicon through via 103 is used to achieve connection between different chips. Usually, the first silicon through via is cylindrical and includes an insulating layer, a first isolation layer, a seed layer and a conductive layer. In some embodiments, the insulating layer is used to isolate the electrical conductivity between the filling metal and the first substrate and protect the first substrate from being damaged; the insulating layer material can be silicon oxide, silicon nitride and polymer, etc. Different insulating layer materials require different deposition techniques. For example, thermal oxidation technology (Thermal Oxidation) can be used to deposit silicon dioxide materials; Plasma Enhanced Chemical Vapor Deposition (PECVD) technology can be used to deposit silicon dioxide materials and silicon nitride materials; vacuum vapor deposition technology can be used to deposit paraxylene materials.

[0043] In some embodiments, the first isolation layer is used to prevent the diffusion of the conductive material subsequently filled in the first through silicon via; the material of the first isolation layer can be metal tantalum, tantalum nitride or titanium nitride, etc., and the first isolation layer can be formed by any suitable deposition process. The seed layer is used to provide a connection for the subsequent formation of a conductive layer in the first through silicon via. The material of the seed layer can be any conductive material, for example, tungsten, cobalt, copper, aluminum or any combination thereof.

[0044] In some embodiments, the material of the conductive layer can be any conductive metal, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof. The conductive material and the seed material can be the same or different. Generally speaking, the material of the conductive layer is copper metal. To form the copper conductive layer, a seed layer can be first deposited by physical vapor deposition (PVD) as a cathode for electroplating, and then a layer of copper is electroplated by electrochemical plating (ECP) to form a conductive layer.

[0045] The first contact structure 102 is electrically connected to the first through silicon via 103, and is used to realize the connection between the through silicon vias in different chips through the first contact structure. The shape of the first contact structure can be circular, elliptical or polygonal, etc. The material of the first contact structure can include but is not limited to an alloy formed by one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotubes.

[0046] The shape of the groove can be a long strip, a circular ring, a grid, etc., and the embodiment of the present application does not limit the shape of the groove. For example, when the shape of the groove is a circular ring, the first silicon via can be located inside the circular ring groove; when the shape of the groove is a grid type, the first silicon via can be located inside each grid in the grid-type groove. Among them, the groove may expose part of the first silicon via, or may not expose the first silicon via. As long as the first contact structure is exposed, the first contact structure can be bonded to the second contact structure. The groove is located on the back of the first chip, that is, the groove is away from the device layer in the first chip, so as to avoid damaging the device in the device layer during the formation of the groove, so as to facilitate the formation of the process.

[0047] In some embodiments, the groove may be located in the inner region of the first chip, that is, the outer region of the first chip has no groove. Therefore, the outer region may play a role in supporting the first chip and the second chip.

[0048] The second chip 20 may be the topmost chip in the semiconductor package structure. Since no other chips need to be connected to the second chip, no through silicon vias may be provided inside the second chip. The second chip 20 includes a second substrate structure 201. The structure of the second substrate structure 201 may be the same as that of the first substrate 101. The explanation of the second substrate may refer to the first substrate. In some embodiments, the front side of the second substrate may also include a device layer.

[0049] In some embodiments, Figure 1A As shown, the first contact structure 102 and the second contact structure 202 are arranged at intervals, and each first contact structure 102 is correspondingly connected to a second contact structure 202, so as to realize the connection between the first chip 10 and the second chip 20. The material of the second contact structure may include but is not limited to an alloy formed by one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotubes.

[0050] In some embodiments, the first contact structure is a first pad, and the second contact structure is a bump or a second pad. When the second contact structure is a bump, the packaging method of the first chip and the second chip is micro-bump bonding. When the second contact structure is a second pad, the packaging method of the first chip and the second chip is hybrid bonding.

[0051] In the embodiment of the present application, since the back side of the first chip has a groove, during the bonding process between the first chip and the second chip, the groove in the first chip can be used to release the stress during the bonding process, so that the bonding process can be performed without using a non-conductive film, thereby solving the problems of holes and poor welding that occur during the bonding process due to the use of a non-conductive film. At the same time, since the dielectric constant of the air gap is low, short circuits and crosstalk between silicon through vias can be effectively avoided. In addition, due to the presence of the air gap, the heat in the semiconductor packaging structure can be diffused to the groove air gap in time, so that the heat can be quickly dissipated, thereby improving the device performance.

[0052] In some embodiments, Figure 1B As shown, the front side of the first chip 10 further includes a third contact structure 303, and the third contact structure 303 is electrically connected to the surface of the first through silicon via 103 facing the front side of the first chip 10. The third contact structure 303 has the same material and structure as the second contact structure 202, and can be understood by referring to the second contact structure. The third contact structure 303 is used to connect other first chips.

[0053] In some embodiments, the second chip 20 is bonded to at least two first chips to form a stacked package structure. For example, two or more first chips may be bonded under the second chip 20 to form a multi-layer stacked package structure. Figure 1B The stacked package structure is shown in which the second chip 20 is bonded to two first chips 10 .

[0054] In some embodiments, the shape of the groove is a grid type, and the packaging structure formed is shown in FIG. Figure 2A (corresponding to the packaging method of micro-bump bonding) and Figure 2B (Corresponding to the hybrid bonding packaging method).

[0055] The first case (the second contact structure 202 is a bump, corresponding to the packaging method of micro-bump bonding):

[0056] like Figure 2A As shown, in some embodiments, a barrier layer 301a is provided around a portion of the first through silicon via 103 facing the first contact structure 102, and the barrier layer 301a and a portion of the first substrate 101 together constitute a sidewall structure 301 of the portion of the first through silicon via 103, and the sidewall structure 301 is arranged at intervals in the groove 104 to support the first through silicon via and protect the first through silicon via from the external environment, and an air gap is provided around the sidewall structure 301, which is beneficial to the heat diffusion in the stacked chip, thereby improving the device performance.

[0057] In some embodiments, the front side of the first substrate 101 and the front side of the second substrate structure 201 may further include a first protective layer 105 and a second protective layer 203, respectively. The materials of the first protective layer 105 and the second protective layer 203 may include silicon nitride, silicon oxide, etc., to prevent external substances such as water vapor from diffusing into the device layer in the first chip or the second chip, thereby affecting the performance of the device.

[0058] In some embodiments, the air gap 302 is formed around the spacer structure 301 , the first contact structure 102 and the bump 202 to release stress during the bonding process between the first chip 10 and the second chip 20 .

[0059] In some embodiments, the top surface of the first substrate 101 other than the first substrate 101, the spacer structure 301 and the first contact structure 102 exposed by the groove 104 on the back side of the first chip 10 is covered with a protective layer 106, and the top surface A of the air gap 302 is flush with the top surface B of the protective layer 106. The protective layer 106 may be a barrier layer 301a located on the top surface of the first substrate 101 other than the first substrate 101, the spacer structure 301 and the first contact structure 102 exposed by the groove 104 when the barrier layer 301a is formed.

[0060] In some embodiments, the top surface B of the protection layer 106 (the top surface of the first chip peripheral region protection layer) is higher than the top surface C of the spacer structure 301, so as to provide a certain space for the micro bumps when the micro bumps are bonded.

[0061] The second case (the second contact structure 202 is a second pad, corresponding to a hybrid bonding packaging method):

[0062] like Figure 2B As shown, compared to Figure 2A The side wall structure 301, Figure 2B The spacer structure 301 also covers the first contact structure 102 , and an air gap 302 is formed around the spacer structure 301 .

[0063] In some embodiments, the top surface of the remaining first substrate 101 except the first substrate 101, the sidewall structure 301 and the first contact structure 102 exposed by the groove 104 on the back side of the first chip 10 is covered with a protective layer 106, and the top surface A of the air gap 302 is flush with the top surface B of the protective layer 106, thereby facilitating the application in the hybrid bonding packaging method and improving the sealing of the hybrid bonding.

[0064] In some embodiments, the protective layer 106 may include a barrier layer 301a and a fourth barrier layer 1062. In general, after forming the first through silicon via, a first contact structure is formed on the back side of the first through silicon via, and the material of the first contact structure is a metal, such as tungsten, copper, etc., which is easy to diffuse to the first substrate and the sidewall of the first through silicon via, thereby affecting the insulation of the first substrate and the conductivity of the first through silicon via. Therefore, before forming the first contact structure, a barrier layer is first formed on the back side of the first substrate except the groove to protect the first through silicon via and the first substrate. Among them, a part of the barrier layer is used to form the sidewall structure, and a part is used to form the protective layer (see the explanation of the protective layer in the first case). The material of the barrier layer may include silicon nitride, silicon oxide, etc. The fourth barrier layer 1062 is used to form the first contact structure, that is, the first contact structure is formed in the fourth barrier layer 1062 having an opening. The material of the fourth barrier layer 1062 may also include silicon nitride, silicon oxide, etc.

[0065] In order to more clearly demonstrate the structure of the grid-type grooves, the packaging method of micro-bump bonding is taken as an example for explanation below. Figure 2C for Figure 2A It can be seen that the shape of the trench 104 is a grid type, the first silicon via 103 is located inside each sub-grid in the grid type trench 104, and there is a distance between the first silicon via 103 and the trench 104.

[0066] In some embodiments, in order to better release stress during the bonding process and facilitate bonding between the first contact structure and the second contact structure, the packaging method of micro-bump bonding is still used as an example to illustrate the requirements for the width of the sub-grooves in the grid-type grooves. Figure 2D ( Figure 2AAs shown in the enlarged view of the middle area D, the width b of each sub-groove 1041 in the groove can range from 5 to 10 microns (um), and the distance a between two adjacent sub-grooves 1041 can be greater than the width of the first contact structure 102 and the second contact structure 202.

[0067] The present application provides a method for forming a semiconductor packaging structure. Figure 3 As shown, the method includes the following steps S101 to S103:

[0068] Step S101: forming a first chip, wherein the first chip includes a first contact structure and a first through silicon via electrically connected to the first contact structure; a groove is provided on the back side of the first chip, wherein the groove exposes the first contact structure;

[0069] Here, the structure of the first chip can be seen in Figure 1A The embodiment of the present application does not limit the method for forming the first chip. The groove on the back side of the first chip can be formed by dry etching the back side of the first chip after forming the first contact structure and the first through silicon via.

[0070] Step S102: forming a second chip, wherein the second chip includes a second contact structure;

[0071] Here, the structure of the second chip can be seen in Figure 1A , the embodiment of the present application does not limit the method for forming the second chip.

[0072] Step S103: bonding the first chip and the second chip via the first contact structure and the second contact structure to form a packaging structure with an air gap.

[0073] Here, the implementation of step S103 can be achieved by hybrid bonding or micro-bump bonding to achieve mutual bonding between the first contact structure and the second contact structure to form a packaging structure with an air gap. In the packaging method of hybrid bonding or micro-bump bonding, the structures of the corresponding first chip and the second chip are also different, see Figure 2A and Figure 2B To understand.

[0074] In an embodiment of the present application, a packaging structure with an air gap is formed by bonding a first chip and a second chip having a groove on the back through a first contact structure and a second contact structure. Therefore, during the bonding process of the first chip and the second chip, the groove in the first chip can be used to release the stress in the bonding process, so that the bonding process can be performed without using a non-conductive film, thereby solving the problems of holes and poor welding that occur during the bonding process due to the use of a non-conductive film. At the same time, since the dielectric constant of the air gap is low, short circuits and crosstalk between silicon through vias can be effectively avoided. In addition, due to the presence of the air gap, the heat in the semiconductor packaging structure can be diffused to the groove air gap in time, so that the heat can be quickly dissipated, thereby improving the device performance.

[0075] For the convenience of description, the structures of the first chip, the second chip and the packaging structure are described below by taking the grid-shaped groove as an example.

[0076] In some embodiments, the implementation of step S101 “forming a first chip” may include the following steps S1011 to S1016:

[0077] Step S1011: providing a first initial chip, the first initial chip comprising a first initial substrate structure and first through silicon vias, the first through silicon vias being arranged at intervals;

[0078] like Figure 4A As shown, a first initial chip 10a is provided, which includes a first initial substrate structure 101a and a first through silicon via 103. The first through silicon via 103 does not penetrate the back side of the first initial substrate structure 101a, that is, there is a certain distance between the first through silicon via 103 and the back side of the first initial substrate structure 101a, and the first through silicon vias 103 are arranged at intervals.

[0079] In some embodiments, the first initial chip 10 a further includes a first protection layer 105 located on the front side of the first initial substrate structure 101 a .

[0080] Since the first through silicon via does not penetrate the back side of the first initial substrate structure, the provided first initial chip is a structure obtained before the backside via revealing process (Backside Via Reveal, BVR).

[0081] Step S1012: etching a portion of the first initial substrate structure on the back side of the first initial chip to form an initial trench, wherein the initial trench exposes a portion of the first through silicon via;

[0082] Here, the etching process may include a dry etching process or a wet etching process, which is not limited in the present embodiment. Depending on the different bonding methods for implementing the package, the implementation of step S1012 may include the following two methods:

[0083] The first method (corresponding to micro-bump bonding):

[0084] like Figure 4B As shown, a portion of the first initial substrate structure 101a on the back of the first initial chip 10a is etched to form an initial trench 104a, and the initial trench 104a exposes a portion of the first through silicon via 103. Since the initial trench 104a is located in the inner region of the first initial chip, that is, the edge region of the first initial chip is not etched, the edge region can be used to further support the first chip and the second chip.

[0085] The second method (corresponding to the case of mixed bonding):

[0086] like Figure 4C As shown, a portion of the first initial substrate structure 101a on the back of the first initial chip 10a is etched to form an initial trench 104a, and the initial trench 104a exposes a portion of the first through silicon via 103. The back of the etched first initial chip 10a is flat, which is conducive to improving the subsequent process yield.

[0087] In some embodiments, see Figure 4B and Figure 4C The bottom of the etched initial trench is a preset distance h1 from the top of the first through silicon via, wherein the preset distance is used to form an initial barrier layer on the first initial chip, so as to use the initial barrier layer to protect the first initial substrate and the first through silicon via from being damaged by the subsequently deposited metal. The preset distance can be set according to requirements.

[0088] Step S1013: depositing an initial barrier layer, wherein the initial barrier layer covers the first substrate structure and a portion of the first through silicon via;

[0089] Here, the initial barrier layer can be formed by any deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, a low-pressure chemical vapor deposition process, a molecular layer deposition process, a plasma enhanced vapor deposition process, etc.

[0090] Step S1014: etching the initial barrier layer to expose the top surface of the first through silicon via toward the back side of the first initial chip;

[0091] Here, for the case of micro-bump bonding, the implementation of step S1014 includes: etching the initial barrier layer 110 to expose the top surface of the first through silicon via 103 toward the back side of the first initial chip 10a, forming Figure 4D The structure shown.

[0092] In the case of hybrid bonding, the implementation of step S1014 may include: etching the initial barrier layer 110 to expose the top surface of the first through silicon via 103 facing the back side of the first initial chip 10a, forming Figure 4E The structure shown.

[0093] Step S1015: forming the first contact structure on the top surface of the first through silicon via;

[0094] Here, for the case of micro-bump bonding, after executing step S1015, the following Figure 4F The first contact structure 102 is located on the top surface of the first through silicon via 103 .

[0095] Correspondingly, the implementation of step S1015 may include the following steps S201 to S202:

[0096] Step S201: forming a first contact structure by electroplating on the initial barrier layer 110;

[0097] Step S202: Chemical mechanical polishing is performed on the first contact structure formed by electroplating to make its surface flush, so as to form Figure 4F The structure shown. ;

[0098] The material of the first contact layer may include, but is not limited to, an alloy formed by one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotubes.

[0099] For the case of hybrid bonding, the implementation of step S1015 may include the following steps S301 to S304:

[0100] Step S301: depositing a fourth initial barrier layer and a photoresist layer on the initial barrier layer 110 in sequence, wherein the material of the fourth initial barrier layer may include silicon oxide, silicon nitride, etc., which is not limited here;

[0101] Step S302: patterning the photoresist layer to form a photoresist layer having a first contact structure pattern, wherein a sub-pattern where the first contact structure is located in the first contact structure pattern is located above the first through silicon via;

[0102] Step S303: etching the fourth initial barrier layer using the first contact structure pattern as a mask to form an opening in the fourth initial barrier layer;

[0103] Step S304: depositing a metal layer in the first contact hole to form a first contact structure on the top surface of the first through silicon via. The final structure is located inside the fourth initial barrier layer 111, such as Figure 4G As shown. The process of depositing the metal layer may include electroplating, chemical vapor deposition, and physical vapor deposition, which are not limited here. The material of the metal layer may include, but is not limited to, an alloy formed by one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene, or carbon nanotubes.

[0104] In some embodiments, the first contact structure may be in the shape of a T. During implementation, a vertical structure in the T-shape may be formed in the fourth initial barrier layer, and then a horizontal structure in the T-shape may be formed in the fifth initial barrier layer, thereby obtaining the first contact structure.

[0105] Step S1016: etching the remaining initial barrier layer and a portion of the first initial substrate structure to form the trench.

[0106] The step S1016 can be implemented by using a dry etching process to etch the initial barrier layer and part of the first initial substrate structure with the first through silicon via as the center to form a grid-type groove. After the initial barrier layer is etched, a barrier layer is formed.

[0107] For micro-bump bonding, step S1016 is performed to form Figure 4H The structure shown in FIG. 1 is a structure in which the barrier layer 301a on the top surface of the first substrate 101 other than the first substrate 101, the sidewall structure 301 and the first contact structure 102 exposed by the groove 104 on the back side of the first chip 10 serves as a protective layer 106. The barrier layer 301a around the first through silicon via 103 and a part of the first substrate 101 together constitute a sidewall structure 301 of a part of the first through silicon via 103. The top surface of the protective layer 106 (the top surface of the protective layer in the edge area of ​​the first chip) is higher than the top surface of the sidewall structure 301.

[0108] Correspondingly, in some embodiments, the method further includes step S301: removing a portion of the top surface of the edge region protection layer so that the distance between the bottom of the groove and the top surface of the edge region protection layer meets a preset condition.

[0109] Here, step S301 can be implemented by chemical mechanical polishing to remove Figure 4H The top surface of the protective layer 106 in the edge area shown is so that the distance h2 between the bottom of the groove 104 and the top surface of the protective layer in the peripheral area meets the preset condition. Among them, the setting of h2 needs to be greater than the final height formed after the first contact structure and the second contact structure are bonded, so as to provide sufficient bonding space for the micro-bump when the micro-bump is bonded, and to ensure that after the first chip and the second chip are bonded, a packaging structure with good sealing is formed. In some embodiments, h2 can be greater than 30 microns.

[0110] For the case of mixed bonding, executing step S1016 can form Fig. 4I The structure shown in FIG. wherein the fourth initial barrier layer is etched to form a fourth barrier layer 1062. Compared to Figure 4H The side wall structure 301, Fig. 4IThe spacer structure 301 in the embodiment also covers the first contact structure 102. At this time, the protection layer 106 includes a barrier layer 301a and a fourth barrier layer 1062. The top surface of the protection layer 106 is flush with the top surface of the spacer structure 301.

[0111] In some embodiments, the implementation of step S102 “forming a second chip” may include the following steps S1021 to S1023:

[0112] Step S1021: providing a second initial chip, wherein the second initial chip includes a second substrate structure;

[0113] like Figure 5A As shown, the second initial chip 20 a includes a second substrate structure 201 .

[0114] In some embodiments, the second initial chip 20 a may further include a second protection layer 203 .

[0115] Step S1022: depositing a second initial barrier layer on the front side of the second initial chip, wherein the second initial barrier layer covers the second substrate structure;

[0116] Continue to refer Figure 5A , a second initial barrier layer 204 is deposited on the front side of the second initial chip 20 a and covers the second substrate structure 201 .

[0117] Step S1023: etching the second initial barrier layer to form an opening, and forming the second contact structure in the opening.

[0118] Here, since the second chip is used for bonding with the first chip, when the structure of the first chip is different, the structure of the second chip is also different.

[0119] like Figure 5B , the second initial barrier layer 204 is etched to form an opening 205, and a Figure 5C The second contact structure shown corresponds to a method for forming the second contact structure in a hybrid bonding packaging manner.

[0120] In the case of micro-bump bonding, Figure 5D As shown, after step S1023, the second initial barrier layer is removed to form a second contact structure in a micro-bump bonding packaging manner.

[0121] In some embodiments, Fig. 6A As shown, a third initial barrier layer 109 is formed on the front side of the first chip 10. The method further includes the following step S302:

[0122] The third initial barrier layer 109 is etched to expose the surface of the first through silicon via 103 facing the front direction of the first chip 10, and a third contact structure 303 is formed on the surface of the first through silicon via 103 facing the front direction of the first chip. The third contact structure is electrically connected to the first through silicon via 103, corresponding to the case where the packaging method is hybrid bonding.

[0123] In the case where the packaging method is micro-bump bonding, after performing the above step S302, the third initial barrier layer 109 is removed to form Figure 6B A third contact structure 303 is shown.

[0124] In some embodiments, the method further comprises:

[0125] like Figure 7 As shown, the second chip 20 is bonded to at least two first chips 10 to form a stacked package structure.

[0126] In some embodiments, the method further includes: forming a fusion layer on a peripheral area of ​​the back side of the first chip and a peripheral area of ​​the front side of the second chip.

[0127] Here, the fusion layer is used for further bonding during the bonding process between the first contact structure of the first chip and the second contact structure of the second chip. The material of the fusion layer may include silicon oxide or the like.

[0128] like Fig. 6A As shown (corresponding to the hybrid bonding packaging method), the fusion layer 401 is formed on the edge area of ​​the fourth barrier layer 1062 and the second initial barrier layer 204 .

[0129] like Figure 6B As shown (corresponding to the packaging method of micro-bump bonding), the fusion layer 401 is formed on the edge area of ​​the protection layer 106 and the second protection layer 203 .

[0130] Correspondingly, while performing step S103 for mutual bonding, the method further includes: performing melt bonding through the fusion layer in the edge region of the first chip and the fusion layer in the edge region of the second chip.

[0131] That is, the bonding between the first contact structure and the second contact structure is performed simultaneously with the bonding between the fusion layers. In some embodiments, the fusion process parameters may include: fusion temperature: 200 to 350 degrees Celsius (°C), fusion time: 1 to 2 hours. This embodiment of the application is not limited to this.

[0132] Since the bonding between the fusion layers is performed simultaneously with the bonding between the first contact structure and the second contact structure, the bonding strength and sealing between the first chip and the second chip can be further increased, thereby improving the reliability of the finally formed device.

[0133] In the embodiment of the present application, by forming a fusion layer on the edge area on the back side of the first chip and the edge area on the front side of the second chip, and further melt bonding of the fusion layer, the strength and sealing between the first chip and the second chip can be further increased, thereby improving the reliability of the final device.

[0134] The features disclosed in several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0135] The description of the semiconductor structure embodiment above is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the semiconductor structure embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0136] The above description is merely an exemplary embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor packaging structure, characterized in that: include: A first chip, wherein the first chip comprises a first contact structure and a first through silicon via electrically connected to the first contact structure; The back side of the first chip has a groove, and the groove exposes the first contact structure; a second chip, the second chip comprising a second contact structure; The first chip and the second chip are bonded via the first contact structure and the second contact structure to form the packaging structure having the air gap formed by the groove; The first contact structures and the second contact structures are arranged at intervals, and each of the first contact structures is correspondingly connected to one of the second contact structures; A barrier layer is disposed around a portion of the first through silicon via facing the first contact structure. The barrier layer and a portion of the first substrate together constitute a sidewall structure of a portion of the first through silicon via. The sidewall structure is disposed at intervals in the trench.

2. The packaging structure according to claim 1, characterized in that: The first contact structure is a first pad, and the second contact structure is a bump or a second pad.

3. The packaging structure according to claim 2, characterized in that: When the second contact structure is a second bonding pad, the sidewall structure also covers the first contact structure, and the air gap is formed around the sidewall structure.

4. The packaging structure according to claim 2, characterized in that: When the second contact structure is a bump, the air gap is formed around the spacer structure, the first contact structure and the bump.

5. The packaging structure according to claim 3 or 4, characterized in that: The top surface of the first substrate on the back side of the first chip except for the first substrate, the sidewall structure and the first contact structure exposed by the groove is covered with a protection layer, and the top surface of the air gap is flush with the top surface of the protection layer.

6. The packaging structure according to claim 5, characterized in that: When the second contact structure is a bump, a top surface of the protection layer is higher than a top surface of the spacer structure.

7. The packaging structure according to claim 1, characterized in that: The front side of the first chip further includes a third contact structure, and the third contact structure is electrically connected to a surface of the first through silicon via that faces the front side of the first chip.

8. The packaging structure according to claim 6, characterized in that: The second chip is bonded to at least two of the first chips to form a stacked package structure.

9. A method for forming a semiconductor packaging structure, characterized in that: include: forming a first chip, wherein the first chip includes a first contact structure and a first through silicon via electrically connected to the first contact structure; The back side of the first chip has a groove, and the groove exposes the first contact structure; forming a second chip, the second chip comprising a second contact structure; Bonding the first chip and the second chip through the first contact structure and the second contact structure to form the package structure having the air gap formed by the groove; The forming of the first chip comprises: Providing a first initial chip, wherein the first initial chip includes a first substrate structure and the first through silicon vias, wherein the first through silicon vias are arranged at intervals; Etching a portion of the first initial substrate structure on the back side of the first initial chip to form an initial trench, wherein the initial trench exposes a portion of the first through silicon via; Depositing an initial barrier layer, wherein the initial barrier layer covers the first initial substrate structure and a portion of the first through silicon via; Etching the initial barrier layer to expose the top surface of the first through silicon via toward the back side of the first initial chip; forming the first contact structure on a top surface of the first through silicon via; The remaining initial barrier layer and a portion of the first initial substrate structure are etched to form the trench.

10. The forming method according to claim 9, characterized in that: The forming of the second chip comprises: Providing a second initial chip, wherein the second initial chip includes a second substrate structure; Depositing a second initial barrier layer on the front side of the second initial chip, wherein the second initial barrier layer covers the second substrate structure; The second initial barrier layer is etched to form an opening, and the second contact structure is formed in the opening.

11. The forming method according to claim 10, characterized in that: The first chip and the second chip are hybrid bonded or micro-bump bonded through the first contact structure and the second contact structure to form the packaging structure with an air gap.

12. The forming method according to claim 9, characterized in that: A third initial barrier layer is formed on the front side of the first chip, and the third initial barrier layer is etched to expose the surface of the first through silicon via facing the front side of the first chip, and a third contact structure is formed on the surface of the first through silicon via facing the front side of the first chip, and the third contact structure is electrically connected to the first through silicon via.

13. The forming method according to claim 12, characterized in that: The second chip is bonded to at least two of the first chips to form a stacked package structure.

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