A timing optimization method, system, device and medium based on register region constraints

Abstract

The present invention discloses a timing optimization method, system, device and medium based on register area constraints, which relates to the technical field of integrated circuit physical design. The timing optimization method includes the following specific steps: S1, performing timing analysis on all paths to find out the violation path; S2, locating the register unit on the violation path to obtain the position coordinates of the register unit, wherein the register unit includes a first register and a second register; S3, creating layout area constraints for the first register and the second register; S4, completing timing optimization according to the layout area constraints. The present application solves the technical problem that there are limitations in the method of reducing line delay in timing repair. The key point of its technical solution is that by constraining the layout area of ​​the register unit, the length of the interconnection line of the timing violation path can be effectively reduced, which can not only reduce the line delay and repair the timing violation, but also reduce the signal transition time, thereby reducing the insertion of the buffer unit, and reducing the chip usage area and power consumption to a certain extent.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit physical design, and in particular to a timing optimization method, system, device and medium based on register region constraints. Background Art

[0002] In the physical design of digital chips, timing is one of the most critical indicators that designers need to ensure. Only when the layout and wiring of the chip meet the timing constraints can the data be correctly latched and transmitted, and the chip can achieve the correct logical function. Simply put, data processing and transmission can be understood as the data starting from the register and then being saved to the next-level register after a series of combination operations, waiting for further instructions from the system. The clock triggers the storage and output actions of the register, so the data signal needs to remain stable at the input end of the register before and after the arrival of the effective clock edge. These two periods of time are defined as setup time and hold time, respectively. In today's digital era, people's requirements for chip computing power have increased sharply, and the operating frequency of the chip is getting higher and higher, which means that the data signal must reach the input end of the next-level register through the combinational logic in a very short time, which poses new challenges to the timing design of the setup time. In such a context, whether the timing violations can be repaired quickly and effectively has become a decisive factor in the success of chip research and development.

[0003] The timing repair of the establishment time mainly starts from the perspective of reducing the data path delay. As we all know, the path delay is composed of unit delay and line delay. Reducing the unit delay can be achieved by replacing a unit with a smaller threshold voltage and a larger driving capability. This method can indeed play a certain role, but at the same time there are some disadvantages, such as the limited impact of changing the threshold voltage and driving capability on the unit delay, and the use of too many low threshold voltage units and large driving units may increase power consumption. Nowadays, under the advanced manufacturing process of nanometer level, the proportion of line delay in path delay is getting higher and higher, and the space for repairing timing violations by reducing unit delay is getting smaller and smaller. In the previous chip physical design, the line delay was mainly reduced by increasing the line width and using high-level routing, but this method has certain limitations at the expense of winding resources. How to reduce the line delay by reducing the length of the data path is the key problem that this application aims to solve, which is of great practical significance for the design of ultra-large-scale integrated circuits under advanced processes. Summary of the invention

[0004] The present application provides a timing optimization method, system, device and medium based on register region constraints, the technical purpose of which is to reduce line delay by reducing the length of the data path, thereby quickly and effectively repairing timing violations.

[0005] The above technical objectives of this application are achieved through the following technical solutions:

[0006] A timing optimization method based on register region constraints, comprising:

[0007] Step S1: Perform timing analysis on all paths to find out the violating paths;

[0008] Step S2: locating the register unit on the violation path to obtain the position coordinates of the register unit; wherein the register unit includes a first register and a second register;

[0009] Step S3: creating layout area constraints for the first register and the second register;

[0010] Step S4: completing timing optimization according to the layout area constraints;

[0011] Wherein, the step S3 comprises:

[0012] S31: Calculate the timing violation value S0 of the setup time on the violation path, and obtain the number and position information of the logic units on the violation path, and obtain i logic units between the first register and the second register, then the i logic units have a total of i+1 interconnection lines;

[0013] S32: Calculate the length of each interconnection line according to the location information of the logic unit and represent it as L0, L1, ..., L i , then the interconnect delay is expressed as: D j =k j *L j 2 , where j = 0, 1, ..., i, k j represents the delay coefficient of the jth interconnection line;

[0014] S33: The position coordinates of the first register and the second register are (x1, y1) and (x2, y2) respectively, and the total length of the interconnection line is approximately |x2-x1|+|y2-y1|, and the created layout area constraint is expressed as:

[0015]

[0016] Wherein, (x, y) represents the coordinates of the center point of the layout area constraint; W and H represent the width and height of the layout area constraint respectively, and the maximum integer values ​​W and H satisfying formula (2) are the size conditions for creating the layout constraint area; represents the reduction factor of the interconnect length;

[0017] The step S4 comprises:

[0018] Step S41: Performing timing analysis on the path after re-layout and routing under the layout area constraint, judging whether a new timing violation is generated, if so, proceeding to step S42, otherwise completing timing optimization;

[0019] Step S42: On the premise of satisfying equation (2), keep the coordinates (x, y) of the center point of equation (1) unchanged, take larger values ​​of W and H, expand the boundaries of the layout area constraints, obtain new layout area constraints, re-perform layout and routing based on the new layout area constraints, and iterate and optimize until the timing is met.

[0020] Furthermore, the step S1 includes: inputting the physical information file, timing library file and parasitic parameter library file of the design, the tool calculates the unit delay and line delay based on a specific timing model, and then calculates the setup time margin of each path at the maximum delay end angle according to the preset constraint file. If the setup time margin is negative, the path corresponding to the setup time margin is a violation path, outputting the violation path information, and finding the violation path in the timing report.

[0021] A timing optimization system based on register region constraints, the timing optimization system comprising:

[0022] The analysis unit performs timing analysis on all paths to find the violating paths;

[0023] A positioning unit, which locates the register unit on the violation path to obtain the position coordinates of the register unit; wherein the register unit includes a first register and a second register;

[0024] A creating unit, creating layout area constraints for the first register and the second register;

[0025] The optimization unit performs timing optimization according to the layout area constraints.

[0026] Furthermore, the creation unit is used to:

[0027] Calculate the timing violation value S0 of the setup time on the violation path, and obtain the number and position information of the logic units on the violation path to obtain i logic units between the first register and the second register, and the i logic units have a total of i+1 interconnection lines;

[0028] The length of each interconnection line is calculated according to the location information of the logic unit and represented as L0, L1, ..., L i , then the interconnect delay is expressed as: D j =k j *L j 2, where j = 0, 1, ..., i, k j represents the delay coefficient of the jth interconnection line;

[0029] The position coordinates of the first register and the second register are (x1, y1) and (x2, y2) respectively, and the total length of the interconnection line is approximately |x2-x1|+|y2-y1|, and the created layout area constraint is expressed as:

[0030]

[0031] Wherein, (x, y) represents the coordinates of the center point of the layout area constraint; W and H represent the width and height of the layout area constraint respectively, and the maximum integer values ​​W and H satisfying formula (2) are the size conditions for creating the layout constraint area; Represents the reduction factor of the interconnect length.

[0032] Furthermore, the optimization unit is used to:

[0033] Performing timing analysis on the path after re-layout and routing under the layout area constraint, judging whether a new timing violation is generated, if so, going to step S42, otherwise completing timing optimization;

[0034] Step S42: On the premise of satisfying equation (2), keep the coordinates (x, y) of the center point of equation (1) unchanged, take larger values ​​of W and H, expand the boundaries of the layout area constraints, obtain new layout area constraints, re-perform layout and routing based on the new layout area constraints, and iterate and optimize until the timing is met.

[0035] Furthermore, the analysis unit is used to: input the physical information file, timing library file and parasitic parameter library file of the design, the tool calculates the unit delay and line delay based on a specific timing model, and then calculates the setup time margin of each path at the maximum delay end angle according to the preset constraint file. If the setup time margin is negative, the path corresponding to the setup time margin is a violation path, outputs the violation path information, and finds the violation path in the timing report.

[0036] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of a timing optimization method when executing the computer program.

[0037] A computer storage medium stores a computer program, which implements the steps of a timing optimization method when executed by a processor.

[0038] The beneficial effect of the present application is that the present application can effectively reduce the length of the interconnection line of the timing violation path by constraining the layout area of ​​the register unit, which can not only reduce the line delay and solve the timing violation problem, but also reduce the signal transition time, thereby reducing the insertion of the buffer unit, and to a certain extent reducing the chip usage area and power consumption. In addition, for some low-frequency signals or non-critical paths whose timing is easy to meet, the present application can use the timing margin to solve the LVS violation or DRC violation. For example, when the unit density in a certain area is too high and the wiring resources are tight, the layout area constraints are used for the registers in the low-frequency clock domain or non-critical path in the area, and they are moved to the nearby area with relatively abundant wiring resources, which can effectively solve the LVS and DRC problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flowchart of a timing optimization method based on register region constraints in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of calculating the setup time margin of a timing violation path in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of register area constraints for a timing violation path in an embodiment of the present application;

[0042] Figure 4 This is a schematic diagram of the calculation of the setup time margin after timing optimization in an embodiment of the present application;

[0043] Figure 5 Schematic diagram of the calculation of the hold time margin after timing optimization in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The timing optimization method, system, device and medium based on register area constraints described in this application are applicable to any stage where timing violations occur after unit layout. The present invention is described in detail below in conjunction with the preferred embodiments. The detailed description should not be considered as a limitation of the present invention, but should be understood as a more detailed description of certain aspects, characteristics and implementation schemes of the present invention. It should be understood that the terms described in the present invention are only for describing specific implementation methods and are not intended to limit the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art in the field of the present invention.

[0045] like Figure 1 As shown, the timing optimization method based on register area constraints described in this application includes:

[0046] Step S1: Perform timing analysis on the timing violation to find the violation path.

[0047] In the embodiment of the present application, the scenario where setup time violation occurs after clock tree synthesis is taken as a specific analysis case.

[0048] In ICC2, input the physical information file, timing library file and parasitic parameter library file of the design. The tool calculates the cell delay and interconnection line delay based on the nonlinear delay model and the global wiring model, and then calculates the timing margin of each path according to the preset constraint file. Figure 2 As shown, observing the path from register DFF1 to register DFF2, at the maximum delay angle, the delay from DFF1 / CLK port to DFF2 / D port is 5.8ns, the delay of the clock launch path is 2ns, the delay of the clock capture path is 2.05ns, and the common path delay of the clock is 1.2ns. The setup time of DFF is 0.35ns. At the maximum delay process angle, the timing modification factor of the on-chip error is 0.95 of the early path and 1.05 of the late path. Therefore, the setup time margin of this path = 0.85*0.95+5-0.35-(0.8+6.2)*1.05 = -1.8925ns, resulting in a setup time violation, and the tool outputs the corresponding timing violation path report.

[0049] Step S2: Locate the register unit on the violation path to obtain the position coordinates of the register unit; wherein the register unit includes a first register and a second register.

[0050] Specifically, check the timing violation path report and locate the violation path in the graphical interface of the placement and routing tool according to the names of the starting point register and the ending point register of the violation path.

[0051] Step S3: creating layout area constraints for the first register and the second register.

[0052] Specifically, step S3 includes:

[0053] S31: Calculate the timing violation value S0 of the setup time on the violation path, and obtain the number and position information of the logic units on the violation path to obtain i logic units between the first register and the second register. The i logic units have a total of i+1 interconnection lines.

[0054] S32: Calculate the length of each interconnection line according to the location information of the logic unit and represent it as L0, L1, ..., L i , then the interconnect delay is expressed as: D j =k j *L j 2 , where j = 0, 1, ..., i, k jrepresents the delay coefficient of the jth interconnection line.

[0055] Delay coefficient k j Including factors such as the wiring level and the surrounding wiring environment, in the embodiment of the present application, it is assumed that the wiring environment before and after the timing optimization remains unchanged, that is, the delay coefficient remains unchanged.

[0056] S33: The position coordinates of the first register and the second register are (x1, y1) and (x2, y2) respectively. When the wiring is not too long, the total length of the interconnection line is approximately |x2-x1|+|y2-y1|.

[0057] The layout area constraint shape is usually set as a rectangle. Let the center point of the rectangle be (x, y), and the width and height be W and H respectively, satisfying W / H = |x2-x1| / |y2-y1|. When creating the layout area constraint, the most stringent case should be considered, that is, the two registers are located at the diagonal endpoints of the rectangle. In this case, the sum of the lengths of the interconnects is the largest and can be approximated as W+H. Therefore, the reduction factor of the length of the interconnects can be defined as A = (W+H) / (|x2-x1|+|y2-y1|). There are two key points that need to be met when creating the layout area constraint: (1) The delay reduced by reducing the length of the interconnects must be greater than the timing violation value of the current path; (2) The layout area constraint is selected in the middle of DFF1 and DFF2 to avoid setup time violations in the previous and next path.

[0058] Assume that the length of each interconnect line after timing optimization is L'0, L'1, ..., L' i , the corresponding delay sizes are D'0, D'1, ..., D' i , so L' j =A*L j , D' j =k j *L' j 2 =k j *(A*L j ) 2 =A 2 *D j , then the created layout area constraint is expressed as:

[0059]

[0060] Wherein, (x, y) represents the coordinates of the center point of the layout area constraint; W and H represent the width and height of the layout area constraint respectively, and the maximum integer values ​​W and H satisfying formula (2) are the size conditions for creating the layout constraint area; Represents the reduction factor of the interconnect length.

[0061] Formula (2) can be transformed into:

[0062]

[0063] Right now:

[0064] Right now: Then formula (2) means that the path delay reduced by timing optimization is greater than the timing violation value S0 of the violating path.

[0065] In the embodiment of the present application, it can be known from step S1 that the establishment time violation value S0=1.8925ns, the registers DFF1 and DFF2 are Figure 3 The positions before optimization are indicated by dotted lines. Their position coordinates are (920, 1000) and (1000, 1080). There are two logic gates between DFF1 and DFF2. The lengths of the three interconnects are L0 = 45um, L1 = 55um, and L2 = 50um. Under the process end angle of maximum delay, the corresponding line delay sizes reported are D0 = 0.6ns, D1 = 0.85ns, and D2 = 0.7ns. Therefore, |x2-x1| = 80, y2-y1| = 80, W = H, and the center point coordinates of the layout area constraint are (960, 1040). According to The inequality calculation shows that W<27.7, and the maximum integer value W=27 is taken. Therefore, a square layout area constraint with a side length of 27um is created at the point (960,1040).

[0066] Step S4: completing timing optimization according to the layout area constraints.

[0067] Specifically, step S4 includes:

[0068] Step S41: Perform timing analysis on the path after re-layout and routing under the layout area constraint, and determine whether a new timing violation is generated. If yes, go to step S42, otherwise, complete the timing optimization.

[0069] Step S42: Generally speaking, if a new timing problem occurs, it is usually because the above-mentioned layout area constraint pulls the two registers too close, and the setup time timing margin of the data path is insufficient, resulting in a setup time violation. Therefore, under the premise of satisfying equation (2), keep the center point coordinates (x, y) of equation (1) unchanged, take larger values ​​of W and H, expand the boundaries of the layout area constraint, obtain a new layout area constraint, re-perform layout and routing based on the new layout area constraint, and iterate and optimize until the timing is satisfied.

[0070] Specifically, Figure 4As shown in the figure, after the re-layout of the layout area constraints, the setup time margin of the original timing violation path becomes 0.3315ns. At the same time, the setup time margins of the previous and next stage paths are 1.009ns and 0.436ns respectively. Continue to check the hold time margin of the original timing violation path, as shown in the figure. Figure 5 As shown, after the registers are rearranged, the hold time margin of the original timing violation path changes from 1.668ns to 1.042ns, and no timing violation occurs. Therefore, it can be considered that the timing optimization solution is passed.

[0071] The timing optimization system based on register area constraints described in the present application includes an analysis unit, a positioning unit, a creation unit and an optimization unit. The analysis unit is used to perform timing analysis on the timing violation to find the violation path. The positioning unit is used to locate the register unit on the violation path to obtain the position coordinates of the register unit; wherein the register unit includes a first register and a second register. The creation unit is used to create the layout area constraints of the first register and the second register. The optimization unit is used to complete the timing optimization according to the layout area constraints.

[0072] The above are exemplary embodiments of the present application, and the protection scope of the present application is defined by the claims and their equivalents.

Claims

1. A timing optimization method based on register area constraints, characterized in that: include: Step S1: Perform timing analysis on all paths to find out the violating paths; Step S2: locating the register unit on the violation path to obtain the position coordinates of the register unit; wherein the register unit includes a first register and a second register; Step S3: creating layout area constraints for the first register and the second register; Step S4: completing timing optimization according to the layout area constraints; Wherein, the step S3 comprises: S31: Calculate the timing violation value S0 of the setup time on the violation path, and obtain the number and position information of the logic units on the violation path, and obtain i logic units between the first register and the second register, then the i logic units have a total of i+1 interconnection lines; S32: Calculate the length of each interconnection line according to the location information of the logic unit and represent it as L0, L1, ..., L i , then the interconnect delay is expressed as: D j =k j *L j 2 , where j = 0, 1, ..., i, k j represents the delay coefficient of the jth interconnection line; S33: The position coordinates of the first register and the second register are (x1, y1) and (x2, y2) respectively, and the total length of the interconnection line is approximately |x2-x1|+|y2-y1|, and the created layout area constraint is expressed as: Wherein, (x, y) represents the coordinates of the center point of the layout area constraint; W and H represent the width and height of the layout area constraint respectively, and the maximum integer values ​​W and H satisfying formula (2) are the size conditions for creating the layout constraint area; represents the reduction factor of the interconnect length; The step S4 comprises: Step S41: Performing timing analysis on the path after re-layout and routing under the layout area constraint, judging whether a new timing violation is generated, if so, proceeding to step S42, otherwise completing timing optimization; Step S42: On the premise of satisfying equation (2), keep the coordinates (x, y) of the center point of equation (1) unchanged, take larger values ​​of W and H, expand the boundaries of the layout area constraints, obtain new layout area constraints, re-perform layout and routing based on the new layout area constraints, and iterate and optimize until the timing is met.

2. The timing optimization method according to claim 1, characterized in that: The step S1 includes: inputting the physical information file, timing library file and parasitic parameter library file of the design, the tool calculates the unit delay and line delay based on a specific timing model, and then calculates the setup time margin of each path under the maximum delay end angle according to the preset constraint file. If the setup time margin is negative, the path corresponding to the setup time margin is a violation path, outputting the violation path information, and finding the violation path in the timing report.

3. A timing optimization system based on register region constraints, the timing optimization system is used to implement the timing optimization method according to any one of claims 1-2, characterized in that: The timing optimization system includes: The analysis unit performs timing analysis on all paths to find violating paths; A positioning unit, which locates the register unit on the violation path to obtain the position coordinates of the register unit; wherein the register unit includes a first register and a second register; A creating unit, creating layout area constraints for the first register and the second register; The optimization unit performs timing optimization according to the layout area constraints.

4. The timing optimization system according to claim 3, characterized in that: The creation unit is used for: Calculate the timing violation value S0 of the setup time on the violation path, and obtain the number and position information of the logic units on the violation path to obtain i logic units between the first register and the second register, and the i logic units have a total of i+1 interconnection lines; The length of each interconnection line is calculated according to the location information of the logic unit and represented as L0, L1, ..., L i , then the interconnect delay is expressed as: D j =k j *L j 2 , where j = 0, 1, ..., i, k j represents the delay coefficient of the jth interconnection line; The position coordinates of the first register and the second register are (x1, y1) and (x2, y2) respectively, and the total length of the interconnection line is approximately |x2-x1|+|y2-y1|, and the created layout area constraint is expressed as: Wherein, (x, y) represents the coordinates of the center point of the layout area constraint; W and H represent the width and height of the layout area constraint respectively, and the maximum integer values ​​W and H satisfying formula (2) are the size conditions for creating the layout constraint area; Represents the reduction factor of the interconnect length.

5. The timing optimization system according to claim 3, characterized in that: The optimization unit is used to: Performing timing analysis on the path after re-layout and routing under the layout area constraint, judging whether a new timing violation is generated, if so, going to step S42, otherwise completing timing optimization; Step S42: On the premise of satisfying equation (2), keep the coordinates (x, y) of the center point of equation (1) unchanged, take larger values ​​of W and H, expand the boundaries of the layout area constraints, obtain new layout area constraints, re-perform layout and routing based on the new layout area constraints, and iterate and optimize until the timing is met.

6. The timing optimization system according to claim 3, characterized in that: The analysis unit is used to: input the physical information file, timing library file and parasitic parameter library file of the design. The tool calculates the unit delay and line delay based on a specific timing model, and then calculates the setup time margin of each path under the maximum delay end angle according to the preset constraint file. If the setup time margin is negative, the path corresponding to the setup time margin is a violation path, outputs the violation path information, and finds the violation path in the timing report.

7. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the timing optimization method as described in any one of claims 1-2 are implemented.

8. A computer storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the timing optimization method as described in any one of claims 1-2 are implemented.

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