RC oscillator circuit and monolithic integrated chip

Abstract

The present invention provides an RC oscillator circuit and a monolithic integrated chip, the RC oscillator circuit comprises an oscillation module, a bias current generating module and a delay replica module; the oscillation module is used to generate a first clock signal and a second clock signal which are inversely phased to each other; the bias current generating module provides a first charging current and a second charging current to the oscillation module; the delay replica module generates a first delay signal at the falling edge of the first clock signal or the rising edge of the second clock signal, and generates a second delay signal at the rising edge of the first clock signal or the falling edge of the second clock signal; the bias current generating module amplifies the first charging current to twice the original value within the pulse width of the first delay signal, and maintains the same value at other times; and amplifies the second charging current to twice the original value within the pulse width of the second delay signal, and maintains the same value at other times. The present invention can eliminate the influence of the delay error of the comparator and improve the accuracy of the clock frequency.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an RC oscillator circuit and a monolithic integrated chip. Background Art

[0002] In low-power communication applications, such as the Internet of Things and Bluetooth communications, a resistor-capacitor RC oscillator is usually used instead of a crystal oscillator as the clock source in the system sleep state. In order to ensure the accuracy of sleep timing, such applications usually have high requirements for the frequency accuracy of the RC oscillator.

[0003] See also Figure 8 , Figure 8 An RC oscillator circuit provided by the prior art has the following working principle: a first capacitor in a first charge-discharge module is charged with a fixed current Io1, and a voltage Vcap1 at both ends of the first capacitor is increased after the first capacitor is charged. A first comparator is used to compare Vcap1 with a reference voltage Vref1. When Vcap1 is greater than the reference voltage Vref1, the output of the first comparator is flipped, triggering the clock CLK signal and CLKN signal output by the control logic module to flip, and the CLKN signal is an inverted signal of the CLK signal; the flipped CLK signal controls the first capacitor to start discharging, and at the same time, the CLKN signal controls the second capacitor in the second charge-discharge module to start charging. A fixed current Io2 is used to charge the second capacitor, and a voltage Vcap2 at both ends of the second capacitor is increased after the second capacitor is charged. A second comparator is used to compare Vcap2 with a reference voltage Vref2. When Vcap2 is greater than the reference voltage Vref2, the output of the second comparator is flipped, triggering the clock CLK signal and CLKN signal to flip again, and the flipped CLK signal controls the first capacitor to start charging, and the CLKN signal controls the second capacitor to start discharging, and so on. The clock output signal CLK or CLKN of a specific frequency is obtained.

[0004] Theoretically, the period of the clock signal of the above circuit should be equal to the charging time of the first capacitor plus the charging time of the second capacitor, but due to the comparison delay error of the comparator, the clock period is actually equal to the sum of the charging time of the first capacitor, the comparison delay td1 of the first comparator, the charging time of the second capacitor and the comparison delay td2 of the second comparator.

[0005] How to eliminate the comparison delay error introduced by the comparator to improve the accuracy of the clock frequency is a problem that is expected to be solved. Summary of the invention

[0006] One of the purposes of the present invention is to overcome the deficiencies in the prior art and to provide an RC oscillator circuit.

[0007] The technical solution provided by the present invention is as follows:

[0008] An RC oscillator circuit comprises: an oscillation module, a bias current generating module and a delay replica module;

[0009] The oscillation module is used to generate a first clock signal CLK and / or a second clock signal CLKN, the first clock signal and the second clock signal are mutually inverted signals;

[0010] A bias current generating module, connected to the oscillation module, and configured to provide the oscillation module with a first charging current and a second charging current;

[0011] A delay replication module, connected to the oscillation module, for receiving the first clock signal and / or the second clock signal, generating a first delay signal VDP with a pulse width equal to the delay time of the comparator at a falling edge of the first clock signal or a rising edge of the second clock signal, and generating a second delay signal VDN with a pulse width equal to the delay time of the comparator at a rising edge of the first clock signal or a falling edge of the second clock signal;

[0012] The bias current generating module is connected to the delay replica module, and is also used to receive the first delay signal VDP and the second delay signal VDN, and amplify the first charging current to twice its original value within the pulse width of the first delay signal VDP, and keep it unchanged at other times; and amplify the second charging current to twice its original value within the pulse width of the second delay signal VDN, and keep it unchanged at other times.

[0013] In some embodiments, the delay replica module includes a switch, a third comparator, and a first logic circuit;

[0014] The two input ends of the switching switch are respectively connected to the third reference voltage and the fourth reference voltage, the two output ends are respectively connected to the positive and negative input ends of the third comparator, and the control end is connected to the first clock signal and / or the second clock signal; the output end of the third comparator is connected to the first logic circuit, the first logic circuit receives the first clock signal and / or the second clock signal, and outputs a first delay signal VDP and a second delay signal VDN.

[0015] In some embodiments, the bias current generating module includes:

[0016] A reference current generating unit, used for generating a reference current;

[0017] The charging current forming unit is connected to the reference current generating unit and is used to generate 4 mirror currents of the reference current, and the second mirror current is connected in series with the first switch and then connected in parallel with the first mirror current to form a first charging current; the control end of the first switch is connected to the first delay signal VDP; the fourth mirror current is connected in series with the second switch and then connected in parallel with the third mirror current to form a second charging current; the control end of the second switch is connected to the second delay signal VDN.

[0018] In some embodiments, the reference current generating unit includes a current source, one end of which is grounded;

[0019] The charging current forming unit includes: a 17th transistor, an 18th transistor, a 21st transistor, a 22nd transistor, a 23rd transistor, a 24th transistor, and a 25th transistor;

[0020] The sources of the 17th transistor, the 18th transistor, the 21st transistor, the 22nd transistor and the 23rd transistor are connected to the power supply voltage VDD;

[0021] The drain of the 17th transistor is connected to the gate and the other end of the current source;

[0022] The gates of the 17th transistor, the 18th transistor, the 21st transistor, the 22nd transistor and the 23rd transistor are connected;

[0023] The drain of the 21st transistor is connected to the drain of the 24th transistor, the source of the 24th transistor is connected to the drain of the 18th transistor; the gate of the 24th transistor is connected to the first delay signal VDP;

[0024] The drain of the 23rd transistor is connected to the drain of the 25th transistor, the source of the 25th transistor is connected to the drain of the 22nd transistor; and the gate of the 25th transistor is connected to the second delay signal VDN.

[0025] In some embodiments, the oscillation module includes a first capacitor, a second capacitor, a first comparator, a second comparator, a third switch, a fourth switch, a fifth switch, an eighth switch, and a control logic unit;

[0026] One end of the first capacitor is grounded, and the other end is connected to one end of the fifth switch; the other end of the fifth switch is connected to an input end of the first comparator; the other input end of the first comparator is connected to the first reference voltage, and the output end is connected to the control logic unit;

[0027] One end of the second capacitor is grounded, and the other end is connected to one end of the eighth switch; the other end of the eighth switch is connected to an input end of the second comparator; the other input end of the second comparator is connected to the second reference voltage, and the output end is connected to the control logic unit;

[0028] The control logic unit outputs a first clock signal CLK and a second clock signal CLKN;

[0029] The third switch is connected in parallel with the first capacitor, and the control end of the third switch is connected to the first clock signal; the fourth switch is connected in parallel with the second capacitor, and the control end of the fourth switch is connected to the second clock signal; the control end of the fifth switch is connected to the second clock signal, and the control end of the eighth switch is connected to the first clock signal.

[0030] In some embodiments, the oscillation module includes a first capacitor, a second capacitor, a first comparator, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch and a control logic unit;

[0031] One end of the first capacitor is grounded, and the other end is connected to one end of a fifth switch, the other end of the fifth switch is connected to an input end of the first comparator and one end of a sixth switch, and the other end of the sixth switch is connected to a reference voltage;

[0032] One end of the second capacitor is grounded, and the other end is connected to one end of the eighth switch, the other end of the eighth switch is connected to the other input end of the first comparator and one end of the seventh switch, and the other end of the seventh switch is connected to the reference voltage;

[0033] The output end of the first comparator is connected to the control logic unit, and the control logic unit outputs a first clock signal CLK and a second clock signal CLKN;

[0034] The control end of the fifth switch is connected to the second clock signal, the control end of the sixth switch is connected to the first clock signal, the control end of the seventh switch is connected to the second clock signal, and the control end of the eighth switch is connected to the first clock signal.

[0035] In some embodiments, it also includes:

[0036] The reference voltage generating module is connected to the bias current generating module and the oscillation module, and is used for generating a reference voltage according to the reference current.

[0037] In some embodiments, the first capacitor and / or the second capacitor adopts an adjustable capacitor array.

[0038] In some embodiments, the reference current generating unit includes a current source in a self-biasing structure.

[0039] The present invention also provides a monolithic integrated chip, comprising the RC oscillator circuit described in any of the aforementioned embodiments, wherein the RC oscillator circuit provides a clock signal to a clock using circuit in the monolithic integrated chip.

[0040] The RC oscillator circuit and the monolithic integrated chip provided by the present invention can at least bring the following beneficial effects:

[0041] 1. The present invention adds a delay replication module to replicate the delay of the comparator, and changes the charging speed in the subsequent charging process to compensate for the delay of the comparator, thereby avoiding the error caused by the delay of the comparator on the frequency and improving the accuracy of the clock frequency; and the delay replication module is suitable for various temperatures, avoiding the influence of the comparator delay error on the clock frequency at various temperatures.

[0042] 2. The present invention utilizes the same reference current to generate charging current and reference voltage, and the error of the reference voltage can be offset by the error of the charging current, thereby further improving the accuracy of the clock frequency.

[0043] 3. The present invention uses capacitors and resistors with low temperature coefficients to avoid the capacitance and resistance values ​​being affected by temperature, thereby further reducing the impact of temperature drift on the clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of an RC oscillator circuit.

[0045] Figure 1 It is a structural schematic diagram of an embodiment of an RC oscillator circuit of the present invention;

[0046] Figure 2 is a schematic structural diagram of an embodiment of an oscillation module of the present invention;

[0047] Figure 3 yes Figure 2 A schematic structural diagram of an embodiment of a first charge and discharge circuit;

[0048] Figure 4 yes Figure 2 A schematic structural diagram of an embodiment of a second charge and discharge circuit;

[0049] Figure 5 is a schematic structural diagram of another embodiment of an oscillation module of the present invention;

[0050] Figure 6 is a circuit diagram of an embodiment of the present invention in which a bias current generating module and an oscillating module are combined;

[0051] Figure 7 yes Figure 6 Timing diagram of each signal in;

[0052] Figure 8 It is a structural schematic diagram of an existing RC oscillation circuit;

[0053] Fig. 9 is a schematic structural diagram of an embodiment of a monolithic integrated chip of the present invention;

[0054] Fig.10 is a timing diagram for generating a first delay signal VDP and a second delay signal VDN;

[0055] Fig.11 It is a structural diagram of an embodiment of a bias current generating module. DETAILED DESCRIPTION

[0056] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0057] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0058] One embodiment of the present invention, as Figure 1-Figure 4 As shown, an RC oscillator circuit 20 includes:

[0059] The oscillation module 100 , the bias current generation module 200 and the delay replication module 300 .

[0060] The oscillation module is used to generate a first clock signal CLK and / or a second clock signal CLKN, and the first clock signal and the second clock signal are inverted signals to each other.

[0061] like Figure 2 As shown, the oscillation module includes a first charge and discharge circuit 110, a second charge and discharge circuit 120, a first comparator, a second comparator and a control logic unit 130. The first charge and discharge circuit is connected to an input end of the first comparator, the other input end of the first comparator is connected to the first reference voltage Vref1, and the output end is connected to the control logic unit 130. The second charge and discharge circuit is connected to an input end of the second comparator, the other input end of the second comparator is connected to the second reference voltage Vref2, and the output end is connected to the control logic unit 130. The control logic unit 130 outputs a first clock signal CLK and a second clock signal CLKN. The control logic unit outputs a first control signal Ctrl1 to the first charge and discharge circuit, and outputs a second control signal Ctrl2 to the second charge and discharge circuit. Ctrl1 and Ctrl2 can be the first clock signal CLK and / or the second clock signal CLKN.

[0062] like Figure 3As shown, the first charge and discharge circuit 110 includes a first capacitor C1, a third switch M20, and a fifth switch M19. One end of the first capacitor is grounded GND, and the other end is connected to one end of the fifth switch, the other end of the fifth switch is connected to an input end of the first comparator, and the control end of the fifth switch is connected to the second clock signal CLKN. The third switch is connected in parallel with the first capacitor, and the control end of the third switch is connected to the first clock signal CLK.

[0063] like Figure 4 As shown, the second charge and discharge circuit includes a second capacitor C2, a fourth switch M29, and an eighth switch M28. One end of the second capacitor is grounded, and the other end is connected to one end of the eighth switch, the other end of the eighth switch is connected to an input end of the second comparator, and the control end of the eighth switch is connected to the first clock signal CLK. The fourth switch is connected in parallel with the second capacitor, and the control end of the fourth switch is connected to the second clock signal CLKN.

[0064] The connection point VP is the first voltage node of the oscillation module, and the connection point VN is the second voltage node of the oscillation module. The first comparator compares the voltage at the VP point with the first reference voltage Vref1, and the second comparator compares the voltage at the VN point with the second reference voltage Vref2. When it is detected that the voltage at the VP point is greater than the first reference voltage, the first comparator notifies the control logic unit 130 to trigger the first clock signal CLK and the second clock signal CLKN to flip, and at the same time trigger the switching of the charging and discharging states of the first capacitor and the second capacitor; when it is detected that the voltage at the VN point is greater than the second reference voltage, the second comparator notifies the control logic unit 130 to trigger the first clock signal CLK and the second clock signal CLKN to flip, and at the same time trigger the switching of the charging and discharging states of the first capacitor and the second capacitor.

[0065] The bias current generating module provides the first charging current Io1 and the second charging current Io2 to the oscillating module. Io1 charges the first capacitor through the fifth switch M19, and Io2 charges the second capacitor through the eighth switch M28.

[0066] The delay replication module 300 receives the third control signal Ctrl3 generated by the oscillation module 100, and generates a first delay signal VDP and a second delay signal VDN according to the third control signal Ctrl3. The third control signal Ctrl3 may be a first clock CLK signal and / or a second clock CLKN signal. The delay replication module generates a first delay signal VDP with a pulse width equal to the delay time of the comparator at the falling edge of the first clock signal or the rising edge of the second clock signal, and generates a second delay signal VDN with a pulse width equal to the delay time of the comparator at the rising edge of the first clock signal or the falling edge of the second clock signal.

[0067] The bias current generating module 200 is connected to the delay replica module, receives the first delay signal VDP and the second delay signal VDN, and controls the magnitude of the first charging current Io1 according to the first delay signal VDP, and controls the magnitude of the second charging current Io2 according to the second delay signal VDN.

[0068] The delay replica module 300 includes a switch 310 , a third comparator and a first logic circuit 320 .

[0069] The two input ends of the switch are respectively connected to the third reference voltage Vref3 and the fourth reference voltage Vref4, the two output ends are respectively connected to the positive and negative input ends of the third comparator, and the control end is connected to the third control signal Ctrl3. The output end of the third comparator is connected to the first logic circuit. The first logic circuit generates a first delay signal VDP and a second delay signal VDN according to the third control signal Ctrl3 and the output signal of the third comparator.

[0070] There is a fixed voltage difference between Vref3 and Vref4, and it is greater than the minimum comparison voltage of the third comparator. The third control signal Ctrl3 controls the switching of Vref3 and Vref4. For example, assuming that Vref4 is greater than Vref3, the third control signal Ctrl3 is a clock CLK signal. When the CLK signal is at a low level, Vref4 is connected to the negative input of the third comparator, and Vref3 is connected to the positive input of the third comparator. The output signal P3 of the third comparator is low level. When the CLK signal is at a high level, Vref3 switches from the positive input of the third comparator to the negative input, and Vref4 switches from the negative input to the positive input, which will stimulate the output signal P3 of the third comparator to become a high level. In this comparison process, the third comparator also has a delay time td3, that is, the signal P3 is delayed by td3 to flip, and the output signal of the third comparator and the third control signal Ctrl3 are used to generate VDP and VDN through the first logic circuit 320. Specifically, assuming that the third control signal Ctrl3 is a clock CLK signal, such as Fig.10 As shown, a pulse signal with a continuous pulse width equal to the delay time of the third comparator is generated at each falling edge of the CLK signal. , a pulse signal with a continuous pulse width equal to the delay time of the third comparator is generated at each rising edge of the CLK signal .

[0071] The magnitude of the first charging current Io1 is controlled according to the first delay signal VDP, specifically including: within the pulse width of the first delay signal VDP, the first charging current Io1 is amplified to 2 times of the original value, and restored to 1 times of the original value at other times. In this way, the charging speed of the first capacitor can be doubled within the delay time of the third comparator.

[0072] The second charging current Io2 is controlled according to the second delay signal VDN, specifically including: within the pulse width of the second delay signal VDN, the second charging current Io2 is amplified to 2 times of the original value, and restored to 1 times of the original value at other times. In this way, the charging speed of the second capacitor can be doubled within the delay time of the third comparator.

[0073] The bias current generating module 200 includes a reference current generating unit 210 and a charging current forming unit 220. Fig.11 As shown, the reference current generating unit is used to generate the reference current I1. The charging current forming unit includes a mirror circuit, a first switch and a second switch. The mirror circuit is connected to the reference current generating unit and is used to generate 4 mirror currents of the reference current; the second mirror current I3 is connected in series with the first switch and then connected in parallel with the first mirror current I2 to form the first charging current Io1; the control end of the first switch is connected to the first delay signal VDP; the fourth mirror current I5 is connected in series with the second switch and then connected in parallel with the third mirror current I4 to form the second charging current Io2; the control end of the second switch is connected to the second delay signal VDN.

[0074] Since they are in the same circuit, the delay time td3 of the third comparator is almost identical to the delay time td1 of the first comparator and the delay time td2 of the second comparator, and are also affected by the process variation in the same way.

[0075] Figure 8 The clock period of the RC oscillator circuit shown (without the delayed replica module 300) is:

[0076] ;

[0077] Wherein, c1 is the capacitance value of the first capacitor, c2 is the capacitance value of the second capacitor, Io1 is the first charging current; and Io2 is the second charging current.

[0078] After including the delayed replication module, such as Figure 1 , Figure 2 The clock period of the RC oscillator circuit shown is:

[0079] =The charging time of the first capacitor at 2 times of Io1 + The charging time of the first capacitor at Io1 + td1 + The charging time of the second capacitor at 2 times of Io2 + The charging time of the second capacitor at Io2 + td2

[0080] .

[0081] in, is the voltage raised by charging the first capacitor according to the current Io1 during the delay time of the first comparator, The voltage raised by the second capacitor during the delay time of the second comparator by charging the second capacitor according to the current Io2.

[0082] It can be seen that by doubling the charging speed of the capacitor within the delay time of the third comparator, the delay time introduced by the first comparator and the second comparator is compensated, and the generated clock signal period is no longer related to the delay time of the comparator.

[0083] At different temperatures, even if the delay time of the comparator changes, the change of the third comparator is the same as that of the first comparator and the second comparator. The third comparator can still accurately copy the comparison delay at the current temperature for compensation, so the generated clock signal period will not change with temperature.

[0084] In this embodiment, the delay of the comparator is copied by introducing a delay replication module, and the delay of the comparator is compensated by changing the charging speed in the subsequent charging process, thereby avoiding the error of the clock frequency caused by the delay of the comparator and improving the frequency accuracy of the clock signal generated by the RC oscillation circuit.

[0085] In the RC oscillator system, the current consumed by the comparator accounts for a relatively high proportion of the entire system. Thanks to the improvement of the RC oscillator circuit in this embodiment, the clock cycle does not include the delay error component of the comparator, so an extremely low-power comparator design can be used to reduce the power consumption of the entire system.

[0086] In one embodiment, it further includes: a reference voltage generating module, connected to the bias current generating module and the oscillation module, and configured to generate a first reference voltage and a second reference voltage according to a reference current.

[0087] The clock error sources of the RC oscillator circuit also include charging current and reference voltage errors, which cannot be avoided by system calibration. This embodiment generates charging current and reference voltage based on the same reference current, and can offset the charging current error and reference voltage error. If the charging current is too high, the charging speed will be faster, making the charging cycle shorter, but at the same time the reference voltage will also be too high, making the charging cycle longer. The two offset each other, and the clock cycle remains unchanged. Conversely, the charging current is too low.

[0088] Through the above measures, the charging current error can be offset by the reference voltage error, so the accuracy requirement of the reference current can be reduced. On this basis, the reference current generating unit can adopt a current source with a self-bias structure. The self-bias structure is a circuit design method for generating a stable bias current in an integrated circuit. It does not require an external bias voltage, but establishes the required bias conditions through certain parameters of the circuit itself. It can simplify circuit design, reduce the number of components, and reduce costs.

[0089] In one embodiment, the reference voltage generating module is further configured to generate a third reference voltage Vref3 and a fourth reference voltage Vref4 according to the reference current.

[0090] In one embodiment, the first capacitor and / or the second capacitor adopts an adjustable capacitor array.

[0091] In one embodiment, the first capacitor and the second capacitor are capacitors with low temperature coefficients, which can reduce the influence of temperature on the capacitance value and the influence of temperature on the clock frequency.

[0092] This makes it convenient to calibrate the clock frequency to the target frequency by adjusting the capacitor value during the factory stage or the product power-on self-calibration stage.

[0093] Another embodiment of the present invention, as Figure 1 , Figure 5-Figure 6 As shown, an RC oscillator circuit 20 includes:

[0094] The oscillation module 100 , the bias current generation module 200 and the delay replication module 300 .

[0095] The oscillation module is used to generate a first clock signal CLK and / or a second clock signal CLKN, and the first clock signal and the second clock signal are inverted signals to each other.

[0096] like Figure 5 As shown, the oscillation module includes a charge and discharge circuit 111, a first comparator and a control logic unit 112. An implementation of the charge and discharge circuit 111 is as follows: Figure 6 As shown, it includes a first capacitor C1, a second capacitor C2, a third switch M20, a fourth switch M29, a fifth switch M19, a sixth switch M26, a seventh switch M27 and an eighth switch M28. Figure 6 The third switch to the eighth switch use MOS tubes, and other equivalent transistors may also be used.

[0097] One end of the first capacitor C1 is grounded GND, and the other end is connected to one end of the fifth switch M19. The other end of the fifth switch M19 is connected to an input end of the first comparator and one end of the sixth switch M26. The other end of the sixth switch M26 is connected to the reference voltage VREF.

[0098] One end of the second capacitor C2 is grounded, and the other end is connected to one end of the eighth switch M28. The other end of the eighth switch M28 is connected to the other input end of the first comparator and one end of the seventh switch M27. The other end of the seventh switch M27 is connected to the reference voltage VREF.

[0099] The output end of the first comparator is connected to the control logic unit, and the control logic unit outputs the first clock signal CLK and the second clock signal CLKN. The control end of the fifth switch M19 is connected to the second clock signal, the control end of the sixth switch M26 is connected to the first clock signal, the control end of the eighth switch M28 is connected to the first clock signal, and the control end of the seventh switch M27 is connected to the second clock signal.

[0100] The bias current generating module 200 is used to provide the oscillation module with a first charging current Io1 and a second charging current Io2, wherein Io1 is used to charge the first capacitor and Io2 is used to charge the second capacitor.

[0101] The delay replication module 300 receives the third control signal Ctrl3 generated by the oscillation module 100, and generates a first delay signal VDP and a second delay signal VDN according to the third control signal Ctrl3. The third control signal Ctrl3 is the first clock CLK signal and / or the second clock CLKN signal. The delay replication module generates a first delay signal VDP with a pulse width equal to the delay time of the comparator at the falling edge of the first clock signal or the rising edge of the second clock signal, and generates a second delay signal VDN with a pulse width equal to the delay time of the comparator at the rising edge of the first clock signal or the falling edge of the second clock signal.

[0102] The specific structure of the delayed replication module 300 is the same as that of the previous embodiment and will not be repeated here.

[0103] The bias current generating module 200 is connected to the delay replica module, receives the first delay signal VDP and the second delay signal VDN, and controls the magnitude of the first charging current Io1 according to the first delay signal VDP, and controls the magnitude of the second charging current Io2 according to the second delay signal VDN. Specifically, it includes: within the pulse width of the first delay signal VDP, the first charging current Io1 is amplified to 2 times of the original value, and restored to 1 times of the original value at other times. In this way, the charging speed of the first capacitor can be doubled within the delay time of the third comparator. Within the pulse width of the second delay signal VDN, the second charging current Io2 is amplified to 2 times of the original value, and restored to 1 times of the original value at other times. In this way, the charging speed of the second capacitor can be doubled within the delay time of the third comparator.

[0104] The bias current generating module includes a reference current generating unit and a charging current forming unit. The reference current generating unit is used to generate a reference current. The charging current forming unit is connected to the reference current generating unit and is used to generate 4 mirror currents of the reference current, and the second mirror current is connected in series with the first switch and then connected in parallel with the first mirror current to form a first charging current; the control end of the first switch is connected to the first delay signal VDP; the fourth mirror current is connected in series with the second switch and then connected in parallel with the third mirror current to form a second charging current; the control end of the second switch is connected to the second delay signal VDN.

[0105] like Figure 6 As shown, a specific circuit of the bias current generating module 200 includes:

[0106] The reference current generating unit 210 includes a current source, one end of which is grounded GND, and the other end of which is connected to the charging current forming unit. The current source is used to provide a reference current I1.

[0107] The charging current forming unit includes: a 17th transistor M17, an 18th transistor M18, a 21st transistor M21, a 22nd transistor M22, a 23rd transistor M23, a 24th transistor M24, and a 25th transistor M25. The 24th transistor M24 is a first switch, and the 25th transistor M25 is a second switch.

[0108] The sources of the 17th transistor M17, the 18th transistor M18, the 21st transistor M21, the 22nd transistor M22 and the 23rd transistor M23 are connected to the power supply voltage VDD; the drain of the 17th transistor M17 is connected to the gate and the other end of the current source; the gates of the 17th transistor M17, the 18th transistor M18, the 21st transistor M21, the 22nd transistor M22 and the 23rd transistor M23 are connected. This part constitutes a current mirror circuit, through which 4 mirror currents of the reference current are generated, the first mirror current is I2 in the figure, the second mirror current is I3, the third mirror current is I4, and the fourth mirror current is I5.

[0109] The drain of the 21st transistor M21 is connected to the drain of the 24th transistor M24 (ie, the first switch), the source of the 24th transistor M24 is connected to the drain of the 18th transistor M18; the gate of the 24th transistor M24 (ie, the control end of the first switch) is connected to the first delay signal VDP.

[0110] The drain of the 23rd transistor M23 is connected to the drain of the 25th transistor M25 (ie, the second switch), the source of the 25th transistor M25 is connected to the drain of the 22nd transistor M22; the gate of the 25th transistor M25 (ie, the control terminal of the second switch) is connected to the second delay signal VDN.

[0111] against Figure 6 The specific circuit shown has the following working principle:

[0112] In the first half of the oscillation cycle, CLK is high, M26 is turned on, VP is shorted with VREF, M20 is turned on, capacitor C1 is discharged to GND, M28 is turned on, capacitor C2 is charged, and in the early stage of C2 charging, due to the effect of the delay replication module, VDN is high, M25 is turned on, and I4 is equal to I5. Capacitor C2 is charged with twice I4, and the maintenance time is the delay time of the comparator, thereby compensating for the delay time of the comparator. After the compensation time is over, capacitor C2 is charged with one times the normal I4 until it exceeds VP, CLK flips to a low level, and CL KN flips to high level, M27 turns on, VN and VREF are short-circuited, M29 turns on, capacitor C2 discharges to GND, M19 turns on, capacitor C1 is charged, in the early stage of capacitor C1 charging, due to the effect of the delay replication module, VDP is high level, M24 turns on, and I2 and I3 are equal. Capacitor C1 is charged with twice I2, and the maintenance time is the delay time of the comparator, so as to compensate for the delay time of the comparator. After the compensation time, capacitor C1 is charged with one times the normal I2 until it exceeds VN, CLK flips to high level, and oscillation is formed in a continuous cycle. The timing diagram is as follows Figure 7 shown.

[0113] In the RC oscillator system, the current consumed by the comparator accounts for a relatively high proportion of the entire system. Compared with the previous embodiment, this embodiment uses one less comparator, further reducing the power consumption of the system.

[0114] In one embodiment, it further includes:

[0115] The reference voltage generating module is connected to the bias current generating module and the oscillation module, and is used for generating a first reference voltage according to the reference current.

[0116] like Figure 6 As shown, the reference voltage generating module 400 includes a resistor R3 and a third capacitor C3 connected in parallel, one end of the resistor R3 is grounded, and the other end is connected to the reference voltage VREF. The third capacitor C3 plays a role in stabilizing the voltage VREF.

[0117] Figure 6 In the circuit, when CLK is low and CLKN is high, M27 is turned on, and the reference voltage VREF is generated according to the mirror current I4 of the reference current; when CLK is high and CLKN is low, M26 is turned on, and VREF is generated according to the mirror current I2 of the reference current. In this way, the charging current error and the reference voltage error can be offset each other, and the clock frequency accuracy of the RC oscillator circuit can be improved.

[0118] Figure 6The clock cycle of the circuit is:

[0119] .

[0120] Where r3 is the resistance value of resistor R3, c1 is the capacitance value of the first capacitor, and c2 is the capacitance value of the second capacitor. From the above formula, it can be seen that if the reference current is too large, I2 and I4 will also be too large, VP and VN will also be too high, and the reference voltage VREF will also be too high, so they will cancel each other out. It has nothing to do with the charging current, only with R3, C1 and C2.

[0121] Through the above measures, the charging current error can be offset by the reference voltage error, so the accuracy requirement of the reference current can be reduced. On this basis, the reference current generating unit can adopt a current source with a self-bias structure.

[0122] In one embodiment, the reference voltage generating module is further configured to generate a third reference voltage Vref3 and a fourth reference voltage Vref4 according to the reference current.

[0123] In one embodiment, the first capacitor and / or the second capacitor adopts an adjustable capacitor array.

[0124] This makes it convenient to calibrate the clock frequency to the target frequency by adjusting the capacitor value during the factory stage or the product power-on self-calibration stage.

[0125] In one embodiment, the first capacitor and the second capacitor are capacitors with low temperature coefficients, and the resistor is a resistor with low temperature coefficients, so as to reduce the influence of temperature on the capacitance and resistance values ​​and the influence of temperature on the clock frequency.

[0126] One embodiment of the present invention, as Fig. 9 As shown, a monolithic integrated chip 10 includes an RC oscillator circuit 20 according to any of the aforementioned embodiments. The RC oscillator circuit 20 provides a clock signal to a clock using circuit in the chip 10 .

[0127] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. An RC oscillator circuit, characterized in that: It includes an oscillation module, a bias current generation module and a delay replication module; The oscillation module is used to generate a first clock signal CLK and / or a second clock signal CLKN, wherein the first clock signal and the second clock signal are inverted signals to each other; The bias current generating module is connected to the oscillating module and is used to provide the oscillating module with a first charging current and a second charging current; The delay replication module is connected to the oscillation module, and is used to receive the first clock signal and / or the second clock signal, generate a first delay signal VDP with a pulse width equal to the delay time of the comparator at the falling edge of the first clock signal or the rising edge of the second clock signal, and generate a second delay signal VDN with a pulse width equal to the delay time of the comparator at the rising edge of the first clock signal or the falling edge of the second clock signal; The bias current generating module is connected to the delay replica module, and is further used to receive the first delay signal VDP and the second delay signal VDN, and amplify the first charging current to twice the original value within the pulse width of the first delay signal VDP, and keep it unchanged at other times; Within the pulse width of the second delay signal VDN, the second charging current is amplified to twice its original value, and remains unchanged at other times; The delay replication module includes a switch, a third comparator and a first logic circuit; The two input ends of the switching switch are respectively connected to the third reference voltage and the fourth reference voltage, the two output ends are respectively connected to the positive and negative input ends of the third comparator, and the control end is connected to the first clock signal and / or the second clock signal; the output end of the third comparator is connected to the first logic circuit, the first logic circuit receives the first clock signal and / or the second clock signal, and outputs the first delay signal VDP and the second delay signal VDN; there is a fixed voltage difference between the third reference voltage and the fourth reference voltage.

2. The RC oscillator circuit according to claim 1, characterized in that: The first logic circuit comprises: The second clock signal is ANDed with the output signal of the third comparator to obtain the first delay signal VDP; The first clock signal and the output signal of the third comparator are ANDed together to obtain the second delay signal VDN.

3. The RC oscillator circuit according to claim 1, characterized in that: The bias current generating module comprises: A reference current generating unit, used for generating a reference current; A charging current forming unit is connected to the reference current generating unit, and is used to generate four mirror currents of the reference current, and the second mirror current is connected in series with the first switch and then connected in parallel with the first mirror current to form the first charging current; the control end of the first switch is connected to the first delay signal VDP; the fourth mirror current is connected in series with the second switch and then connected in parallel with the third mirror current to form the second charging current; the control end of the second switch is connected to the second delay signal VDN.

4. The RC oscillator circuit according to claim 3, characterized in that: The reference current generating unit comprises a current source, one end of which is grounded; The charging current forming unit includes: a 17th transistor, an 18th transistor, a 21st transistor, a 22nd transistor, a 23rd transistor, a 24th transistor, and a 25th transistor; Sources of the 17th transistor, the 18th transistor, the 21st transistor, the 22nd transistor and the 23rd transistor are connected to a power supply voltage VDD; The drain and gate of the 17th transistor are connected to the other end of the current source; The gates of the 17th transistor, the 18th transistor, the 21st transistor, the 22nd transistor and the 23rd transistor are connected; The drain of the 21st transistor is connected to the drain of the 24th transistor, the source of the 24th transistor is connected to the drain of the 18th transistor; the gate of the 24th transistor is connected to the first delay signal VDP; The drain of the 23rd transistor is connected to the drain of the 25th transistor, the source of the 25th transistor is connected to the drain of the 22nd transistor; and the gate of the 25th transistor is connected to the second delay signal VDN.

5. The RC oscillator circuit according to claim 3, characterized in that: The oscillation module includes a first capacitor, a second capacitor, a first comparator, a second comparator, a third switch, a fourth switch, a fifth switch, an eighth switch and a control logic unit; One end of the first capacitor is grounded, and the other end is connected to one end of the fifth switch; the other end of the fifth switch is connected to an input end of the first comparator; the other input end of the first comparator is connected to a first reference voltage, and the output end is connected to the control logic unit; One end of the second capacitor is grounded, and the other end is connected to one end of the eighth switch; the other end of the eighth switch is connected to an input end of the second comparator; the other input end of the second comparator is connected to a second reference voltage, and the output end is connected to the control logic unit; The control logic unit outputs the first clock signal CLK and the second clock signal CLKN; The third switch is connected in parallel with the first capacitor, and the control end of the third switch is connected to the first clock signal; the fourth switch is connected in parallel with the second capacitor, and the control end of the fourth switch is connected to the second clock signal; the control end of the fifth switch is connected to the second clock signal, and the control end of the eighth switch is connected to the first clock signal.

6. The RC oscillator circuit according to claim 3, characterized in that: The oscillation module includes a first capacitor, a second capacitor, a first comparator, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch and a control logic unit; One end of the first capacitor is grounded, and the other end is connected to one end of the fifth switch, the other end of the fifth switch is connected to an input end of the first comparator and one end of the sixth switch, and the other end of the sixth switch is connected to a reference voltage; One end of the second capacitor is grounded, and the other end is connected to one end of the eighth switch, the other end of the eighth switch is connected to the other input end of the first comparator and one end of the seventh switch, and the other end of the seventh switch is connected to a reference voltage; The output end of the first comparator is connected to the control logic unit, and the control logic unit outputs the first clock signal CLK and the second clock signal CLKN; The control end of the fifth switch is connected to the second clock signal, the control end of the sixth switch is connected to the first clock signal, the control end of the seventh switch is connected to the second clock signal, and the control end of the eighth switch is connected to the first clock signal.

7. The RC oscillator circuit according to claim 5 or 6, characterized in that: Also includes: The reference voltage generating module is connected to the bias current generating module and the oscillating module, and is used to generate a first reference voltage and a second reference voltage, or a reference voltage according to the reference current.

8. The RC oscillator circuit according to claim 5 or 6, characterized in that: The first capacitor and / or the second capacitor adopts an adjustable capacitor array.

9. The RC oscillator circuit according to claim 3, characterized in that: The reference current generating unit includes a current source with a self-bias structure.

10. A monolithic integrated chip, characterized in that: The RC oscillator circuit comprises the RC oscillator circuit according to any one of claims 1 to 9, wherein the RC oscillator circuit provides a clock signal to a clock using circuit in the monolithic integrated chip.

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