Trench MOS device and method for preparing the same

Abstract

The present application discloses a trench MOS device and a method for preparing the trench MOS device. The trench MOS device comprises a gate trench structure penetrating a source region and extending into a drift layer, the gate trench structure comprises a gate dielectric layer and a gate, the gate dielectric layer comprises a first region and a second region, the first region and the second region respectively have a first thickness and a second thickness in a first direction, and the second thickness is greater than the first thickness; a rectifying structure is located on a side of the drift layer away from a substrate, the rectifying structure comprises a semiconductor material region and a drift layer region, the drift layer region comprises a portion of the drift layer in contact with the semiconductor material region, and the semiconductor material region and the drift layer have different doping types, so as to solve the problems of increased size and poor reliability caused by the use of an external reverse-parallel diode in the MOS device in the related art.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a trench MOS device and a method for preparing the trench MOS device. Background Art

[0002] Silicon-based IGBTs dominate high-voltage and high-current scenarios, but they cannot withstand high-frequency conditions and have high power consumption. SiC's high-voltage and high-temperature resistance allows it to cover the voltage resistance level of silicon-based IGBTs with only simpler MOSFET devices, while avoiding its high energy consumption disadvantages. Under the same environment, silicon carbide-based MOSFETs reduce energy losses by 66% compared to silicon-based IGBTs of the same specifications, mainly due to a significant reduction in switching losses. In the new energy vehicle industry, SiC can be used to drive and control inverters, on-board chargers, and fast charging piles for motors. In photovoltaic power generation, leading photovoltaic inverter companies have currently adopted SiC power devices to replace silicon devices.

[0003] SiC MOSFET mainly acts as an electronic switch in power electronic systems. When MOSFET is in the off state, there will be a reverse leakage current between the drain and the source. If a diode is not added in reverse parallel, this leakage current may cause damage to other devices in the circuit. In addition, when SiC MOSFET is used for rectification of AC circuits, since MOSFET can only be turned on under forward voltage, an anti-parallel diode is required to provide a conduction channel under reverse voltage to achieve current rectification. Therefore, it is usually necessary to connect a diode in reverse parallel to the SiC MOSFET body to improve the performance of the SiC MOSFET body diode, thereby improving the working efficiency of the SiC MOSFET. However, the external anti-parallel diode will increase the circuit footprint, increase the device packaging cost, and introduce parasitic capacitance and parasitic inductance, resulting in problems such as slow response speed of the reverse diode and poor reliability.

[0004] In traditional trench-gate MOSFET devices, the electric field concentration at the corners of the gate oxide layer causes the gate dielectric layer to break down, causing the device to break down at a voltage lower than the rated breakdown voltage, seriously affecting the forward blocking characteristics and long-term reliability of the device. Summary of the invention

[0005] The present application provides a trench MOS device and a method for preparing the trench MOS device, so as to solve the problems of increased size and poor reliability caused by the use of external reverse-parallel diodes in the MOS device in the related art.

[0006] According to one aspect of the present application, a trench MOS device is provided, comprising a substrate and a drift layer and a source region arranged on the substrate, the trench MOS device further comprising: a gate trench structure, the gate trench structure penetrates the source region and extends into the drift layer, the gate trench structure comprises a gate dielectric layer and a gate, the gate comprises a first side surface and a second side surface arranged opposite to each other, the gate dielectric layer comprises a first region and a second region, the first region contacts the first side surface, the second region contacts the second side surface, the first region and the second region respectively have a first thickness and a second thickness in a first direction, the second thickness is greater than the first thickness, and the first direction is a direction perpendicular to the first side surface; a rectifying structure, the rectifying structure is located on a side of the drift layer away from the substrate, the rectifying structure contacts the second region, the rectifying structure comprises a semiconductor material region and a drift layer region, the drift layer region comprises a portion of the drift layer in contact with the semiconductor material region, and the semiconductor material region and the drift layer have different doping types.

[0007] Optionally, the semiconductor material region includes a doped polysilicon material, and the doping concentration of the polysilicon material is 10 19 / cm 3 ~10 20 / cm 3 .

[0008] Optionally, the first thickness is 0.03 μm to 0.08 μm, and the second thickness is 0.4 μm to 0.8 μm.

[0009] Optionally, the gate dielectric layer further includes a third region, the third region contacts the bottom surface of the gate, the third region has a third thickness in a second direction, the third thickness is 0.03 μm to 0.08 μm, and the second direction is a direction perpendicular to the bottom surface of the gate.

[0010] Optionally, the trench MOS device also includes: a shielding region, the shielding region is located in the drift layer, the shielding region includes a first shielding region and a second shielding region, the first shielding region is in contact with at least the first region, the second shielding region is in contact with at least the second region and the semiconductor material region, and the doping type of the shielding region is different from the doping type of the drift layer.

[0011] Optionally, the trench MOS device further includes: an extension layer, the extension layer being located between the source region and the drift layer and contacting the first region and the first shielding region respectively, the extension layer and the drift layer having the same doping type, and the doping concentration of the extension layer being greater than the doping concentration of the drift layer.

[0012] According to another aspect of the present application, a method for preparing a trench MOS device is provided, comprising: providing a substrate; sequentially forming a stacked drift layer and a source region on the substrate; forming a gate trench structure, wherein the gate trench structure penetrates the source region and extends into the drift layer, wherein the gate trench structure comprises a gate dielectric layer and a gate, wherein the gate comprises a first side surface and a second side surface that are oppositely arranged, wherein the gate dielectric layer comprises a first region and a second region, wherein the first region contacts the first side surface, wherein the second region contacts the second side surface, wherein the first region and the second region respectively have a first thickness and a second thickness in a first direction, wherein the second thickness is greater than the first thickness, and wherein the first direction is a direction perpendicular to the first side surface; and forming a rectifying structure, wherein the rectifying structure is located on a side of the drift layer away from the substrate, wherein the rectifying structure contacts the second region, wherein the rectifying structure comprises a semiconductor material region and a drift layer region, wherein the drift layer region comprises a portion of the drift layer that contacts the semiconductor material region, and wherein the semiconductor material region and the drift layer have different doping types.

[0013] Optionally, the steps of forming the gate trench structure include: using an etching process to form a first trench that penetrates the source region and extends to the drift layer; using an oxidation process to oxidize the trench bottom surface and the first trench side and the second trench side that are relatively arranged of the first trench to form a first sub-gate dielectric layer, and the area of ​​the first trench other than the first sub-gate dielectric layer is the second trench; using a deposition process to fill the second trench with gate material to form a first sub-gate; using an etching process to etch the area of ​​the first sub-gate close to the second side of the first trench to form a third trench, and the remaining first sub-gate is the gate; using a deposition process to fill the third trench with insulating material to form a second sub-gate dielectric layer, and the first sub-gate dielectric layer and the second sub-gate dielectric layer constitute the gate dielectric layer.

[0014] Optionally, the step of forming the rectifying structure includes: using an etching process to form a fourth groove in the area of ​​the drift layer that contacts the second area, the fourth groove exposing a surface of the second area that is away from the second side surface; and using a deposition process to fill the fourth groove with doped polysilicon material, the polysilicon material having a different doping type from the drift layer.

[0015] Optionally, the preparation method also includes: forming an extension layer on the drift layer, the extension layer having the same doping type as the drift layer; using an ion implantation process to form a first doping region and a second doping region spaced apart in the drift layer, and forming a third doping region and a fourth doping region spaced apart in the extension layer, the first doping region contacts the third doping region and constitutes a first shielding region, the second doping region contacts the fourth doping region and constitutes a second shielding region, the first shielding region and the second shielding region constitute a shielding region, the doping type of the shielding region is different from the doping type of the drift layer, and after forming the gate trench structure, the first shielding region at least contacts the first region, and the second shielding region at least contacts the second region and the semiconductor material region.

[0016] By applying the technical solution of the present application, a trench MOS device is provided, in which the rectifying structure includes semiconductor material regions of different doping types and a drift layer, which can form a heterojunction Schottky diode structure, that is, a heterojunction SBD (Schottky Barrier Diode, SBD for short) diode integrated inside the MOS device can effectively improve the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode, and at the same time, the internally integrated heterojunction SBD replaces the external anti-parallel diode, which can improve the switching efficiency and the surge resistance of the body diode without increasing the cell size of the MOS device and reducing the packaging cost of the device, improve the reverse recovery characteristics of the device, and enhance the reliability of the MOS device. In addition, in the rectifying structure formed on one side of the gate trench structure, the contact area between the semiconductor material region and the drift layer region is increased, and under the condition of large current conduction of the device, the resistance of the device is reduced and the on-voltage of the device is reduced. In addition, the width of the second region in the first direction of the gate trench structure is greater than the width of the first region. The above-mentioned gate trench structure has an irregular and single-sided conductive structure. The insulating pressure-bearing layer with a certain thickness located on the side wall of the gate in the trench increases the voltage resistance of the trench, realizes protection of the gate, and improves the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A schematic diagram of a trench MOS device in the prior art is shown;

[0019] Figure 2 is a schematic cross-sectional structure diagram of a trench MOS device according to an embodiment of the present application;

[0020] Figure 3 is a schematic cross-sectional structure diagram of another trench MOS device according to an embodiment of the present application;

[0021] Figure 4 is a schematic cross-sectional structure diagram of another trench MOS device according to an embodiment of the present application;

[0022] Figure 5 A flow chart of a method for preparing a trench MOS device provided according to an embodiment of the present application is shown;

[0023] Figure 6 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in a method for preparing a trench MOS device provided in an embodiment of the present application is shown;

[0024] Figure 7 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in another method for preparing a trench MOS device provided in an embodiment of the present application is shown.

[0025] The above drawings include the following reference numerals:

[0026] 10. substrate; 20. drift layer; 30. source region; 301. first heavily doped region; 302. second heavily doped region; 303. doped region; 40. gate trench structure; 41. gate dielectric layer; 411. first region; 412. second region; 413. third region; 414. first sub-gate dielectric layer; 415. second sub-gate dielectric layer; 42. gate; 421. first side surface; 422. second side surface; 423. first sub-gate; 431. first trench; 4311. first trench side surface; 4312. Side of the second groove; 432, second groove; 433, third groove; 434, fourth groove; 50, rectifying structure; 51, semiconductor material region; 52, drift layer region; 61, first conductive layer; 62, second conductive layer; 63, third conductive layer; 64, fourth conductive layer; 70, dielectric layer; 80, shielding region; 81, first shielding region; 82, second shielding region; 83, first doped region; 84, second doped region; 85, third doped region; 86, fourth doped region; 90, extension layer. DETAILED DESCRIPTION

[0027] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] As described in the background art, in the trench MOS device in the prior art, such as Figure 1 As shown, the trench MOS device includes a substrate 10 and a drift layer 20 and a source region 30 stacked in sequence on one side of the substrate 10, the source region 30 includes a first heavily doped region 301, a second heavily doped region 302 and a doping region 303, the first heavily doped region 301 and the second heavily doped region 302 are located on the side of the doping region 303 away from the substrate 10, the trench MOS device also includes a gate trench structure 40 that penetrates the source region 30 and extends into the drift layer 20, and the gate trench structure 40 is in contact with the second heavily doped region 302 and the doping region 303, the gate trench structure 40 includes a gate dielectric layer 41 and a gate 42, and the gate dielectric layer 41 is located at the bottom and side of the gate 42. When the MOS device is in the cut-off state, there will be a reverse leakage current between the drain and the source, which will cause damage to other devices in the circuit. Therefore, when the MOS device is used for rectification of an AC circuit, an anti-parallel diode is required to provide a conduction channel under a reverse voltage to achieve current rectification. However, the external anti-parallel diode will increase the circuit footprint, increase the device packaging cost, and introduce parasitic capacitance and parasitic inductance, resulting in a slow response speed of the reverse diode, poor reliability, and other problems. In order to solve the above problems, the present application provides a trench MOS device and a method for preparing a trench MOS device.

[0031] According to one aspect of the present application, a trench MOS device is provided, such as Figure 2As shown, the trench MOS device includes a substrate 10 and a drift layer 20 and a source region 30 arranged on the substrate 10. The trench MOS device also includes: a gate trench structure 40, the gate trench structure 40 penetrates the source region 30 and extends into the drift layer 20, the gate trench structure 40 includes a gate dielectric layer 41 and a gate 42, the gate 42 includes a first side surface 421 and a second side surface 422 arranged opposite to each other, the gate dielectric layer 41 includes a first region 411 and a second region 412, the first region 411 contacts the first side surface 421, the second region 412 contacts the second side surface 422, and the first region 411 contacts the first side surface 421. 1 and the second region 412 have a first thickness and a second thickness in a first direction A respectively, the second thickness is greater than the first thickness, and the first direction A is a direction perpendicular to the first side surface 421; a rectifying structure 50, the rectifying structure 50 is located on a side of the drift layer 20 away from the substrate 10, the rectifying structure 50 is in contact with the second region 412, the rectifying structure 50 includes a semiconductor material region 51 and a drift layer region 52, the drift layer region 52 includes a portion of the drift layer 20 in contact with the semiconductor material region 51, and the semiconductor material region 51 and the drift layer 20 have different doping types. The above-mentioned trench MOS device includes a rectifying structure including semiconductor material regions of different doping types and a drift layer, which can form a heterojunction Schottky diode structure, that is, a heterojunction SBD (Schottky Barrier Diode, SBD for short) diode integrated inside the MOS device, which can effectively improve the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode. At the same time, the internally integrated heterojunction SBD replaces the external anti-parallel diode, which can improve the switching efficiency and the surge resistance of the body diode without increasing the cell size of the MOS device and reducing the packaging cost of the device, improve the reverse recovery characteristics of the device, and enhance the reliability of the MOS device. In addition, in the rectifying structure formed on one side of the gate trench structure, the contact area between the semiconductor material region and the drift layer region is increased, and under the condition of large current conduction of the device, the resistance of the device is reduced and the on-voltage of the device is reduced. In addition, the width of the second region in the first direction of the gate trench structure is greater than the width of the first region. The above-mentioned gate trench structure has an irregular and single-sided conductive structure. The insulating pressure-bearing layer with a certain thickness located on the side wall of the gate in the trench increases the voltage resistance of the trench, realizes protection of the gate, and improves the reliability of the device.

[0032] Specifically, the materials of the substrate 10 and the drift layer 20 include silicon carbide, silicon, quartz, silicon nitride, gallium nitride, gallium oxide, aluminum oxide, aluminum nitride and the like. Personnel skilled in the art may make reasonable selections based on actual needs, and no specific limitation is imposed.

[0033] Among them, Figure 2As shown, the source region 30 includes a first heavily doped region 301, a second heavily doped region 302 and a doped region 303, wherein the doped region 303 is located on the side of the drift layer 20 away from the substrate 10, the doped region 303 is in contact with the first region 411 of the gate dielectric layer 41, the first heavily doped region 301 and the second heavily doped region 302 are located side by side on the side of the doped region 303 away from the substrate 10, wherein the second heavily doped region 302 is in contact with the first region 411 of the gate dielectric layer 41. A channel is formed when the MOS device is turned on, and current regulation of the MOS device is achieved by controlling the gate voltage.

[0034] In some optional embodiments, the substrate 10 and the drift layer 20 have the same doping type, and the doping concentration of the drift layer is 10 15 / cm 3 ~10 16 / cm 3 , wherein the doping concentration of the substrate is higher than the doping concentration of the drift layer, and the highly doped substrate layer 101 can reduce the on-resistance of the MOSFET device, thereby improving the performance of the device. In addition, the drift layer plays the role of bearing the main breakdown voltage. Those skilled in the art can adjust the thickness of the drift layer to meet the breakdown voltage of the product. For example, when the thickness of the drift layer is 9μm~11μm, the breakdown voltage of the MOS device is 1200V, and when the thickness of the drift layer is 5μm~7μm, the breakdown voltage of the MOS device is reduced to 650V.

[0035] In an optional embodiment, the semiconductor material region 51 includes a doped polysilicon material, and the doping concentration of the polysilicon material is 10 19 / cm 3 ~10 20 / cm 3 .

[0036] Specifically, polysilicon is a polycrystalline material composed of small crystals. The arrangement of silicon atoms in polysilicon is non-directional, and there are multiple randomly arranged small grains. This special structure makes polysilicon have the properties of both metal and semiconductor, that is, it has good conductivity and can also achieve specific electrical functions through doping. In trench MOS devices, the doped polysilicon and the drift layer have different doping types. Because polysilicon has metallic properties, the doped polysilicon and the drift layer form a heterojunction Schottky diode structure, which realizes the integration of SBD in MOS devices, reduces the resistance of the rectification structure, reduces the forward turn-on voltage drop of the diode structure without increasing the width of the SiC MOSFET cell, and shortens the reverse recovery time of the diode structure.

[0037] In addition, since the SBD is a Schottky barrier withstanding voltage, its withstand voltage is usually lower than that of the PN junction, so the middle SBD needs to be protected to improve the reverse withstand voltage of the device; a gate dielectric layer with a second thickness is formed on one side of the SBD, and the second thickness is greater than the first thickness, that is, the thickness of the second region of the gate dielectric layer in contact with the SBD in the gate dielectric layer is increased, and the withstand voltage of the second region is improved, so that the electric field peak on the surface of the SBD is moved to the inside of the device, thereby protecting the SBD.

[0038] In an optional implementation, the first thickness is 0.03 μm to 0.08 μm, and the second thickness is 0.4 μm to 0.8 μm.

[0039] Specifically, the gate dielectric layer 41 in the gate trench structure 40 has an asymmetric and unilaterally conductive structure, wherein the first region 411 of the gate dielectric layer 41 contacts the source region 30 and has a relatively thin first thickness, which plays a role in controlling the current to form a charge channel. The second region 412 of the gate dielectric layer 41 contacts the rectifying structure 50 and has a relatively thick second thickness, which plays a role in increasing the withstand voltage performance of the trench, realizing protection of the gate 42 and the rectifying structure 50, and improving the reliability of the device.

[0040] In an optional embodiment, if Figure 2 As shown, the gate dielectric layer 41 also includes a third region 413 , which contacts the bottom surface of the gate 42 , and has a third thickness in the second direction B, which is 0.03 μm to 0.08 μm. The second direction B is perpendicular to the bottom surface of the gate 42 .

[0041] Specifically, the thickness of the third region 413 is 0.03 μm to 0.08 μm, which can play a role in isolating the circuit and protecting the bottom of the gate trench structure. The material of the gate dielectric layer 41 including the third region 413 includes an insulating material, and further, can include an oxidized insulating material and / or a high-k dielectric material, wherein the oxidized insulating material includes but is not limited to any one or more of silicon oxide, aluminum oxide (Al2O3), titanium oxide (TiO2), germanium oxide (GeO2), gallium oxide (Ga2O3), and indium tin oxide (In2O5Sn). The high-k dielectric material can be selected from one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3 and BaSrTiO. The high-k dielectric material can further improve the withstand voltage reliability of the bottom of the trench and avoid the risk of breakdown at the bottom of the gate trench structure 40. Those skilled in the art can make reasonable selections according to actual needs, and this application does not make specific restrictions.

[0042] In an optional embodiment, if Figure 3As shown, the trench MOS device further includes: a shielding region 80, the shielding region 80 is located in the drift layer 20, the shielding region 80 includes a first shielding region 81 and a second shielding region 82, the first shielding region 81 is in contact with at least the first region 411, the second shielding region 82 is in contact with at least the second region 412 and the semiconductor material region 51, the doping type of the shielding region 80 is different from the doping type of the drift layer 20, and in addition, Figure 3 The other structural positions shown in Figure 2 The structural position relationship is the same as in , and will not be repeated here.

[0043] Specifically, the shielding area and the drift layer have different doping types, so the shielding area and the drift layer can form a PN connection structure. Under the action of the external electric field, the shielding area can form an electric field barrier, that is, when an electric field is formed in the shielding area, the charge will move along the conductive path of the material, which has a counteracting effect on the energy of the electric field, so that the electric field in the internal area is weakened. The shielding area is formed at the corner of the gate trench structure, which can reduce the electric field strength at the bottom and corner of the gate trench structure and enhance the anti-breakthrough property of the MOS device. In addition, the shielding area includes a first shielding area and a second shielding area, and the first shielding area and the second shielding area are respectively located at the two corners of the gate trench structure, that is, two electric field shielding areas are formed at the bottom of the trench gate, which can play a role in dispersing the charge, thereby reducing the local electric field, further improving the anti-breakthrough property of the MOS device, and thus improving the device reliability.

[0044] In an optional embodiment, the doping concentration of the shielding region is 5×10 18 / cm 3 ~1.5×10 19 / cm 3 , that is, the shielding area has a higher doping concentration. By forming an electric field shielding area with a high doping concentration at the corner of the gate trench structure, the anti-breakthrough capability of the MOS device is further enhanced and the stability of the device is improved.

[0045] In some optional embodiments, such as Figure 4 As shown, the trench MOS device further includes: an extension layer 90, the extension layer 90 is located between the source region 30 and the drift layer 20, and is in contact with the first region 411 and the first shielding region 81 respectively, the extension layer 90 and the drift layer 20 have the same doping type, and the doping concentration of the extension layer 90 is greater than the doping concentration of the drift layer 20, and in addition, Figure 4 The other structural positions shown in Figure 2 The structural position relationship is the same as in , and will not be repeated here.

[0046] Specifically, the shielding area plays a role in reducing the electric field strength at the bottom of the gate trench structure and improving the stability of the device, but the shielding area will increase the on-resistance of the MOS device. Among them, an extension layer is added between the offset region and the source region, the doping concentration of the extension layer is greater than the doping concentration of the drift layer, and the extension layer is in contact with the shielding area to adjust the on-resistance of the MOS device. Among them, the extension layer and the drift layer constitute an epitaxial variable doping structure, that is, a doping gradient is formed between the extension layer and the drift layer, which slows down the transition barrier of the carrier, promotes the movement of the carrier, reduces the forward on-resistance of the device, increases the withstand voltage of the device, and improves the reliability and stability of the device. At the same time, the electric field distribution in the diode structure can be optimized, the performance of the device can be improved, and the efficiency and performance indicators of the device can be improved.

[0047] In some specific embodiments, the materials of the extension layer include silicon carbide, silicon, quartz, silicon nitride, gallium nitride, gallium oxide, aluminum oxide, aluminum nitride and the like. Personnel in the art can make reasonable selections according to actual needs, and no specific limitation is made without application. The doping concentration of the extension layer is 10 16 / cm 3 ~10 17 / cm 3 By designing the doping concentration of the extension layer and the drift layer, the electric field can be precisely controlled, thereby improving the performance and characteristics of the device.

[0048] In addition, if Figure 1 As shown, the trench MOS device in the prior art also includes a first conductive layer 61, a second conductive layer 62, a third conductive layer 63, a fourth conductive layer 64 and a dielectric layer 70, wherein the first conductive layer 61 is located on the side of the source region 30 facing away from the substrate 10, the second conductive layer 62 is located on the side of the gate 42 facing away from the substrate 10, and a dielectric layer 70 is provided on the second conductive layer 62, and the dielectric layer 70 is respectively in contact with the first conductive layer 61, the second conductive layer 62, the gate trench structure 40 and a portion of the source region 30; the third conductive layer 63 is provided on the side of the first conductive layer 61 and the dielectric layer 70 facing away from the substrate 10, and the fourth conductive layer 64 is provided on the side of the substrate 10 facing away from the drift layer 20.

[0049] In some optional embodiments of the present application, such as Figures 2 to 4As shown, the trench MOS device also includes: a first conductive layer 61, a second conductive layer 62, a third conductive layer 63, a fourth conductive layer 64 and a dielectric layer 70, wherein the first conductive layer 61 is located on the side of the source region 30 away from the substrate 10, the second conductive layer 62 is located on the side of the gate 42 away from the substrate 10, the dielectric layer 70 is located on the side of the second conductive layer 62 away from the substrate 10, the dielectric layer 70 is respectively in contact with the gate trench structure 40, a portion of the source region 30, the first conductive layer 61 and the second conductive layer 62, the third conductive layer 63 is located on the side of the dielectric layer 70 away from the substrate 10, the third conductive layer 63 is respectively in contact with the rectifying structure 50, the first conductive layer 61 and the dielectric layer 70, and the fourth conductive layer 64 is located on the side of the substrate away from the drift layer 20.

[0050] Specifically, the first conductive layer 61, the second conductive layer 62, the third conductive layer 63, and the fourth conductive layer 64 include conductive materials, and the conductive materials include but are not limited to alloy materials composed of any one or more of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0051] According to another aspect of the present application, a method for preparing a trench MOS device is provided, such as Figure 5 As shown, the above preparation method comprises:

[0052] Step S101: providing a substrate;

[0053] Step S102: forming a stacked drift layer and a source region in sequence on a substrate;

[0054] Step S103: forming a gate trench structure, the gate trench structure penetrates the source region and extends into the drift layer, the gate trench structure includes a gate dielectric layer and a gate, the gate includes a first side surface and a second side surface that are oppositely arranged, the gate dielectric layer includes a first region and a second region, the first region contacts the first side surface, the second region contacts the second side surface, the first region and the second region have a first thickness and a second thickness in a first direction respectively, the second thickness is greater than the first thickness, and the first direction is a direction perpendicular to the first side surface;

[0055] Step S104: forming a rectifying structure, wherein the rectifying structure is located on a side of the drift layer facing away from the substrate, the rectifying structure is in contact with the second region, the rectifying structure includes a semiconductor material region and a drift layer region, the drift layer region includes a portion of the drift layer in contact with the semiconductor material region, and the semiconductor material region and the drift layer have different doping types.

[0056] By adopting the above-mentioned preparation method of the embodiment of the present application, on the basis of the traditional trench MOS device, an etching and deposition process is added to form a semiconductor material region including different doping types and a drift layer, so as to form a heterojunction Schottky diode structure, that is, a heterojunction SBD (Schottky Barrier Diode, referred to as SBD) diode integrated inside the MOS device can be realized, which can effectively improve the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode. At the same time, the internally integrated heterojunction SBD replaces the external anti-parallel diode, which can improve the switching efficiency and the surge resistance of the body diode without increasing the cell size of the MOS device and reducing the packaging cost of the device, improve the reverse recovery characteristics of the device, and enhance the reliability of the MOS device. In addition, in the gate trench structure, the width of the second region in the first direction is greater than the width of the first region, and the above-mentioned gate trench structure has an irregular and unilaterally conductive structure. The pressure-bearing layer with a certain thickness and insulation located on the side wall of the gate in the trench increases the voltage resistance of the trench, realizes the protection of the gate, and improves the reliability of the device.

[0057] The following will describe in more detail the exemplary embodiments of the method for preparing the trench MOS device provided by the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0058] First, if Figure 6 (a) and Figure 7 As shown in (a), step S101 is performed: providing a substrate 10.

[0059] Specifically, the materials of the substrate 10 include silicon carbide, silicon, quartz, silicon nitride, gallium nitride, gallium oxide, aluminum oxide, aluminum nitride and the like. Personnel skilled in the art may make reasonable selections based on actual needs, and no specific limitation is imposed on the application.

[0060] Exemplarily, the substrate includes a doped SiC substrate having a resistivity of 0.016 Ωcm to 0.024 Ωcm, so as to form a Schottky contact at the source, reduce the forward voltage drop of the diode structure, and increase the breakdown voltage.

[0061] After providing the substrate, as Figure 6 (a) to Figure 6 (b) and Figure 7 (a) to Figure 7 As shown in (c), step S102 is performed: a drift layer 20 and a source region 30 are stacked in sequence on the substrate.

[0062] Specifically, Figure 6 As shown in (a) and 7 (a), the drift layer 20 can be an epitaxial layer having the same doping type as the substrate 10, and the doping concentration of the drift layer 20 is 10 15 / cm 3 ~10 16 / cm 3 , and the doping concentration of the drift layer 20 is lower than the doping concentration of the substrate, and bears the main breakdown voltage in the MOS device. In addition, those skilled in the art can adjust the thickness of the drift layer 20 to meet the breakdown voltage of the product. For example, when the thickness of the drift layer 20 is 9μm~11μm, the breakdown voltage of the MOS device is 1200V, and when the thickness of the drift layer 20 is 5μm~7μm, the breakdown voltage of the MOS device is reduced to 650V.

[0063] In some optional embodiments, the process of forming a drift layer includes but is not limited to a deposition process and an epitaxial growth process. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control and the activation rate is relatively fixed, so it is easy to achieve the target doping distribution. It is not only suitable for silicon-based power devices, but also can avoid the difficulty of injection doping of silicon carbide power devices and improve the efficiency of its terminal structure. The deposition process is relatively mature, simple to operate and has low cost. The deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). Physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, and chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), and laser-induced chemical vapor deposition (LCVD). Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0064] In some optional embodiments, such as Figure 6 (b) and Figure 7 As shown in (c), the steps of forming the source region 30 include: first, forming a doped region 303 on the side of the drift layer 20 away from the substrate 10, as shown in FIG. Figure 6 (b), or a doped region 303 is formed on the side of the extension layer 90 away from the substrate 10, as shown in Figure 7 (c); then, a first heavily doped region 301 and a second heavily doped region 302 are formed on the side of the doped region 303 facing away from the substrate 10 .

[0065] Specifically, the source region 30 may include a first heavily doped region 301, a second heavily doped region 302, and a doping region 303, wherein the first heavily doped region 301 and the doping region 303 have the same doping type, and the first heavily doped region 301 and the second heavily doped region 302 have different doping types, and the doping concentration of the first heavily doped region is greater than the doping concentration of the doping region. For example, the doping concentration of the doping region 303 is 5×10 18 / cm 3 ~1.5×10 19 / cm 3 The implantation depth is 0.7 μm to 0.8 μm, and the doping concentration of the first heavily doped region 301 is 5×10 18 / cm 3 ~1.5×10 19 / cm 3 The implantation depth is 0.2 μm to 0.3 μm, and the doping concentration of the second heavily doped region 302 is 10 19 / cm 3 ~10 20 / cm 3 The injection depth is 0.2μm~0.3μm. Those skilled in the art can make a reasonable selection according to actual needs, and no specific limitation is made without application.

[0066] In some optional embodiments, the process of forming the source region includes but is not limited to an ion implantation process and a diffusion process, wherein the ion implantation process is to inject a high-energy ion beam into a semiconductor material, and is a process in which ions collide with semiconductor atoms and embed ions into semiconductor crystals. The ion implantation process can accurately control the concentration and depth, and ion doping can be achieved at a lower temperature. The ion implantation equipment is expensive and the cost is high. The diffusion process is a process in which impurity atoms are allowed to diffuse freely along the thermal gradient of the crystal while maintaining thermal equilibrium in the semiconductor through high temperature or chemical reaction to achieve doping. The diffusion process does not require expensive equipment, requires higher control temperature and time conditions, and cannot accurately control the distribution and concentration of impurity atoms. Those skilled in the art can make reasonable selections based on actual needs, and no specific restrictions are made without application.

[0067] After forming the drift layer and source region, as Figure 6 (c) to Figure 6 (g) and Figure 7 (d) to Figure 7As shown in (h), step S103 is performed: a gate trench structure 40 is formed. The gate trench structure 40 penetrates the source region 30 and extends into the drift layer 20 .

[0068] Specifically, the steps of forming the gate trench structure 40 may include: Figure 6 As shown in (c), a first trench 431 penetrating the source region 30 and extending to the drift layer 20 is formed by an etching process, or as shown in Figure 7 As shown in (c), an etching process is used to form a first trench 431 penetrating the source region 30, the extension layer 90 and extending to the drift layer 20, the first shielding region 81 and the second shielding region 82; Figure 6 (d) and Figure 7 As shown in (e), the bottom surface of the first trench 431 and the first trench side surface 4311 and the second trench side surface 4312 disposed opposite to each other are oxidized by an oxidation process to form a first sub-gate dielectric layer 414, and the area of ​​the first trench 431 except the first sub-gate dielectric layer 414 is the second trench 432; Figure 6 (e) and Figure 7 As shown in (f), a gate material is filled in the second trench 432 by a deposition process to form a first sub-gate 423; Figure 6 (f) and Figure 7 As shown in (g), an etching process is used to etch the area of ​​the first sub-gate 423 close to the second trench side 4312 of the first trench 431 to form a third trench 433, and the remaining first sub-gate 423 is the gate 42; Figure 6 (g) and Figure 7 As shown in (h), an insulating material is filled in the third trench 433 by a deposition process to form a second sub-gate dielectric layer 415 . The first sub-gate dielectric layer 414 and the second sub-gate dielectric layer 415 constitute a gate dielectric layer 41 .

[0069] Specifically, the above etching process includes but is not limited to dry etching and wet etching, wherein dry etching includes physical etching, chemical etching and chemical-physical etching, and physical etching includes ion beam etching, plasma etching, reactive ion etching and the like.

[0070] Exemplarily, the etching width of the first trench 431 is 0.15 μm-1.3 μm, the etching depth is 0.8 μm-1.5 μm, and the thickness of the first sub-gate dielectric layer 414 is 0.03 μm-0.08 μm.

[0071] In some optional embodiments, the gate material includes a doped polysilicon material, the doping type of the gate is different from the doping type of the drift layer, and the doping concentration of the gate material is 10 19 / cm 3 ~10 20 / cm 3Doped polysilicon material has high electrical conductivity and can withstand large current and voltage. In addition, polysilicon material has good stability and compatibility. Using doped polysilicon material as gate material can improve the conductivity and stability of MOS devices.

[0072] Specifically, the second sub-gate dielectric layer can contact the second side of the gate, that is, the second sub-gate dielectric layer is a part of the second region of the gate dielectric layer, and the first region of the gate dielectric layer contacts the first side of the gate, wherein the first thickness is 0.03μm~0.08μm, and the second thickness is 0.4μm~0.8μm.

[0073] After forming the gate trench structure, as Figure 6 (h) to Figure 6 (i) and 7(i) to Figure 7 As shown in (j), step S104 is performed: a rectifying structure 50 is formed. The rectifying structure 50 is located on a side of the drift layer 20 away from the substrate 10 , and the rectifying structure 50 is in contact with the second region 412 .

[0074] Specifically, the steps of forming the above-mentioned rectifying structure 50 may include: Figure 6 (h) and Figure 7 As shown in (i), a fourth trench 434 is formed in the region of the drift layer 20 that contacts the second region 412 by an etching process, and the fourth trench 434 exposes the surface of the second region 412 that is away from the second side surface 422; Figure 6 (i) and Figure 7 As shown in (j), a deposition process is used to fill the fourth trench 434 with doped polysilicon material to form a semiconductor material region 51 . The semiconductor material region 51 and the drift layer region 52 have different doping types.

[0075] Among them, polysilicon has the properties of both metal and semiconductor, that is, it has good conductivity and can also achieve specific electrical functions through doping. In trench MOS devices, the doped polysilicon and the drift layer have different doping types, and their doping concentration is 10 19 / cm 3 ~10 20 / cm 3 Because polysilicon has metallic properties, the doped polysilicon and the drift layer form a heterojunction Schottky diode structure, which enables the integration of SBD in MOS devices, reduces the resistance of the rectification structure, and reduces the forward turn-on voltage drop of the diode structure without increasing the cell width of the SiC MOSFET, and shortens the reverse recovery time of the diode structure.

[0076] In some optional embodiments, the above preparation method in the examples of the present application further comprises: Figure 7 (a) to Figure 7As shown in (b), an extension layer 90 is formed on the drift layer 20, and the extension layer 90 has the same doping type as the drift layer 20; an ion implantation process is used to form a first doping region 83 and a second doping region 84 spaced apart in the drift layer 20, and a third doping region 85 and a fourth doping region 86 spaced apart in the extension layer 90, the first doping region 83 contacts the third doping region 85 and constitutes a first shielding region 81, the second doping region 84 contacts the fourth doping region 86 and constitutes a second shielding region 82, the first shielding region 81 and the second shielding region 82 constitute a shielding region 80, and the doping type of the shielding region 80 is different from the doping type of the drift layer 20. Figure 7 As shown in (j), after the gate trench structure 40 is formed, the first shielding region 81 at least contacts the first region, and the second shielding region 82 at least contacts the second region and the semiconductor material region 51 .

[0077] Specifically, the process of forming the shielding region may include but is not limited to an ion implantation process. The shielding region and the drift layer have different doping types. The shielding region has a higher doping concentration, which is 5×10 18 / cm 3 ~1.5×10 19 / cm 3 , the injection depth is 0.9~1.8μm. Therefore, the shielding area and the drift layer can form a PN connection structure. Under the action of the external electric field, the shielding area can form an electric field barrier, that is, when an electric field is formed in the shielding area, the charge will move along the conductive path of the material, which will have a counteracting effect on the energy of the electric field, and weaken the electric field in the internal area. The shielding area is formed at the corner of the gate trench structure, which can reduce the electric field strength at the bottom and corner of the gate trench structure and enhance the anti-breakthrough property of the MOS device. In addition, the shielding area includes a first shielding area and a second shielding area, and the first shielding area and the second shielding area are respectively located at the two corners of the gate trench structure, that is, two electric field shielding areas are formed at the bottom of the trench gate, which can disperse the charge, thereby reducing the local electric field, further improving the anti-breakthrough property of the MOS device, and thus improving the device reliability.

[0078] In addition, the shielding area can reduce the electric field strength at the bottom of the trench and improve the stability of the device, but the shielding area will increase the on-resistance of the MOS device. An extension layer is added between the offset area and the source area, the doping concentration of the extension layer is greater than the doping concentration of the drift layer, and the extension layer is in contact with the shielding area to adjust the on-resistance of the MOS device. The extension layer and the drift layer constitute an epitaxial variable doping structure, that is, a doping gradient is formed between the extension layer and the drift layer, which slows down the transition barrier of the carrier, promotes the movement of the carrier, reduces the forward on-resistance of the device, increases the withstand voltage of the device, and improves the reliability and stability of the device. At the same time, the electric field distribution in the diode structure can be optimized, the performance of the device can be improved, and the efficiency and performance indicators of the device can be improved.

[0079] In some specific embodiments, the materials of the extension layer include silicon carbide, silicon, quartz, silicon nitride, gallium nitride, gallium oxide, aluminum oxide, aluminum nitride and the like. Personnel in the art can make reasonable selections according to actual needs, and no specific limitation is made without application. The doping concentration of the extension layer is 10 16 / cm 3 ~10 17 / cm 3 By designing the doping concentration of the extension layer and the drift layer, the electric field can be precisely controlled, thereby improving the performance and characteristics of the device.

[0080] Specifically, the process of forming the above extension layer may include but is not limited to a deposition process and an epitaxial growth process.

[0081] In some optional embodiments, the above preparation method in the examples of the present application further comprises: Figure 6 (j) and Figure 7 As shown in (k), a deposition process is used to deposit a conductive material on the side of the source region 30 away from the substrate 10 to form a first conductive layer 61; a deposition process is used to deposit a conductive material on the side of the gate 42 away from the substrate 10 to form a second conductive layer 62; a deposition process is used to deposit an insulating material on the first conductive layer 61 to form a dielectric layer 70, and the dielectric layer is respectively in contact with the gate trench structure 40, the first conductive layer 61, the second conductive layer 62, a portion of the source region 30 and a portion of the semiconductor material region 51; a deposition process is used to deposit a conductive material on the side of the dielectric layer 70 away from the substrate 10 to form a third conductive layer 63, and the third conductive layer 63 is respectively in contact with the second conductive layer 62 and the semiconductor material region 51; a deposition process is used to deposit a conductive material on the side of the substrate 10 away from the drift layer 20 to form a fourth conductive layer 64.

[0082] Specifically, the first conductive layer can serve as the gate electrode of the MOS device to control the charge density in the source channel, thereby controlling the current of the MOS device; the second conductive layer contacts the first heavily doped region and the second heavily doped region of the source region, and forms an ohmic contact in the contact region, which can reduce the on-current of the MOS device; the third conductive layer and the fourth conductive layer serve as the source electrode and the drain electrode of the MOS device, respectively, and play the role of current input and output of the MOS device.

[0083] Among them, the conductive material includes but is not limited to alloy materials composed of any one or more of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0084] The diode structure formed by the method for preparing the diode structure of the present application will be described below in conjunction with an embodiment.

[0085] Example 1

[0086] The method for preparing a trench MOS device provided in this embodiment includes the following steps: Figure 6 As shown:

[0087] Provide an N-type SiC substrate 10, whose resistivity is 0.02Ωcm, such as Figure 6 (a) as shown;

[0088] An N-type SiC drift layer 20 is formed on an N-type SiC substrate 10 by using an epitaxial growth process. The doping concentration of the N-type SiC drift layer 20 is 10 15 / cm 3 ,like Figure 6 (a) as shown;

[0089] Aluminum ions are implanted into the N-type SiC drift layer 20 by an ion implantation process to form a P-type doping region 303. The ion implantation concentration of the P-type doping region 303 is 10 17 / cm 3 , the implantation depth is 0.7 μm, such as Figure 6 (b) as shown;

[0090] Aluminum ions are implanted into the P-type doping region 303 by an ion implantation process to form a P-type first heavily doped region 301. The ion implantation concentration of the P-type first heavily doped region 301 is 10 19 / cm 3 , the implantation depth is 0.2 μm, such as Figure 6 (b) as shown;

[0091] Nitrogen ions are implanted into the P-type doping region 303 by an ion implantation process to form an N-type second heavily doped region 302. The ion implantation concentration of the N-type second heavily doped region 302 is 1019 / cm 3 , the implantation depth is 0.2 μm, wherein the P-type doping region 303, the P-type first heavily doped region 301 and the N-type second heavily doped region 302 constitute the source region 30, such as Figure 6 (b) as shown;

[0092] The first trench 431 penetrating the source region 30 and extending to the N-type SiC drift layer 20 is formed by etching. The first trench 431 has a depth of 1.3 μm and a width of 0.8 μm. Figure 6 (c) as shown;

[0093] The bottom surface of the first trench 431 and the first trench side surface 4311 and the second trench side surface 4312 disposed opposite to each other are oxidized by an oxidation process to form a first sub-gate dielectric layer 414. The thickness of the first sub-gate dielectric layer 414 is 0.05 μm. The area of ​​the first trench except the first sub-gate dielectric layer 414 is the second trench 432. Figure 6 (d) as shown;

[0094] The N-type polysilicon material is filled in the second trench 432 by a deposition process to form a first sub-gate 423, wherein the doping element of the N-type polysilicon material is nitrogen, and the doping concentration is 10 19 / cm 3 ,like Figure 6 (e) as shown;

[0095] The area of ​​the first sub-gate near the second trench side 4312 is etched by an etching process to form a third trench 433, and the remaining first sub-gate is the gate 42. Figure 6 (f) as shown;

[0096] A silicon oxide material is filled in the third trench 433 by a deposition process to form a second sub-gate dielectric layer 415. The first sub-gate dielectric layer 414 and the second sub-gate dielectric layer 415 constitute a gate dielectric layer 41. Figure 6 (g) as shown;

[0097] A fourth trench 434 is formed in the region of the N-type SiC drift layer 20 that contacts the second region by an etching process. The fourth trench 434 exposes a portion of the surface of the second region 412 of the gate dielectric layer 41 that is away from the second side surface 422 of the gate 42. Figure 6 (h) as shown;

[0098] The fourth trench 434 is filled with a P-type polysilicon material by a deposition process. The doping element of the P-type polysilicon material is boron atoms, and the doping concentration is 10 19 / cm 3 , forming a P-type semiconductor material region 51, such as Figure 6 (i) as shown;

[0099] A metal nickel material is deposited on the source region 30 by a deposition process to form a first conductive layer 61. Figure 6 (j) as shown;

[0100] A metal aluminum material is deposited on the gate 42 by a deposition process to form a second conductive layer 62. Figure 6 (j) as shown;

[0101] A silicon oxide material is deposited on the first conductive layer 61 by a deposition process to form a dielectric layer 70. The dielectric layer 70 is in contact with the gate trench structure 40, a portion of the source region 30 and a portion of the P-type semiconductor material region 51, respectively. Figure 6 (j) as shown;

[0102] A metal aluminum material is deposited on the dielectric layer 70, the second conductive layer 62 and the P-type semiconductor material region 51 by a deposition process to form a third conductive layer 63. Figure 6 (j) as shown;

[0103] A metal aluminum material is deposited on the side of the N-type SiC substrate 10 away from the N-type SiC drift layer 20 by a deposition process to form a fourth conductive layer 64. Figure 6 (j) shown.

[0104] Example 2

[0105] The method for preparing a trench MOS device provided in this embodiment includes the following steps: Figure 7 As shown:

[0106] Provide an N-type SiC substrate 10, whose resistivity is 0.02Ωcm, such as Figure 7 (a) as shown;

[0107] An N-type SiC drift layer 20 is formed on an N-type SiC substrate 10 by using an epitaxial growth process. The doping concentration of the N-type SiC drift layer 20 is 10 15 / cm 3 ~10 16 / cm 3 ,like Figure 7 (a) as shown;

[0108] An N-type SiC extension layer 90 is formed on the N-type SiC drift layer 20 by using an epitaxial growth process. The doping concentration of the N-type SiC extension layer 90 is 10 17 / cm 3 , with a thickness of 1.1 μm, such as Figure 7 (a) as shown;

[0109] Aluminum ions are implanted into the N-type SiC drift layer 20 and the N-type SiC extension layer 90 by using an ion implantation process to form a P-type first doped region 83 and a P-type second doped region 84 arranged at intervals in the N-type SiC drift layer 20, and a P-type third doped region 85 and a P-type fourth doped region 86 arranged at intervals in the N-type SiC extension layer 90. The P-type first doped region 83 contacts the P-type third doped region 85 and constitutes a P-type first shielding region 81. The P-type second doped region 84 contacts the P-type fourth doped region 86 and constitutes a P-type second shielding region 82. The P-type first shielding region 81 and the P-type second shielding region 82 constitute a P-type shielding region 80. The aluminum ion implantation concentration of the P-type shielding region 80 is 10 19 / cm 3 , the implantation depth is 1.5 μm, such as Figure 7 (b) as shown;

[0110] Aluminum ions are implanted into the N-type SiC extension layer 90 by an ion implantation process to form a P-type doping region 303. The ion implantation concentration of the P-type doping region 303 is 10 17 / cm 3 , the implantation depth is 0.7 μm, such as Figure 7 (c) as shown;

[0111] Aluminum ions are implanted into the P-type doping region 303 by an ion implantation process to form a P-type first heavily doped region 301. The ion implantation concentration of the P-type first heavily doped region 301 is 10 19 / cm 3 , the implantation depth is 0.2 μm, such as Figure 7 (c) as shown;

[0112] Nitrogen ions are implanted into the P-type doping region 303 by an ion implantation process to form an N-type second heavily doped region 302. The ion implantation concentration of the N-type second heavily doped region 302 is 10 19 / cm 3 , the implantation depth is 0.2 μm, wherein the P-type doping region 303, the P-type first heavily doped region 301 and the N-type second heavily doped region 302 constitute the source region 30, such as Figure 7 (c) as shown;

[0113] An etching process is used to form a first trench 431 penetrating the source region 30 and the N-type SiC extension layer 90 and extending to the N-type SiC drift layer 20, the P-type first shielding region 81 and the P-type second shielding region 82, respectively. The first trench 431 has a depth of 1.3 μm and a width of 0.8 μm. Figure 7 (d) as shown;

[0114] The bottom surface of the first trench 431 and the first trench side surface 4311 and the second trench side surface 4312 disposed opposite to each other are oxidized by an oxidation process to form a first sub-gate dielectric layer 414. The thickness of the first sub-gate dielectric layer 414 is 0.05 μm. The area of ​​the first trench except the first sub-gate dielectric layer 414 is the second trench 432. Figure 7 (e) as shown;

[0115] The N-type polysilicon material is filled in the second trench 432 by a deposition process to form a first sub-gate 423, wherein the doping element of the N-type polysilicon material is nitrogen, and the doping concentration is 10 19 / cm 3 ,like Figure 7 (f) as shown;

[0116] The area of ​​the first sub-gate near the second trench side 4312 is etched by an etching process to form a third trench 433, and the remaining first sub-gate is the gate 42. Figure 7 (g) as shown;

[0117] A silicon oxide material is filled in the third trench 433 by a deposition process to form a second sub-gate dielectric layer 415. The first sub-gate dielectric layer 414 and the second sub-gate dielectric layer 415 constitute a gate dielectric layer 41. Figure 7 (h) as shown;

[0118] A fourth trench 434 is formed in the N-type SiC drift layer 20 in the region contacting the second region by an etching process. The fourth trench 434 extends into the second shielding region 82. The fourth trench 434 exposes a portion of the surface of the second region 412 of the gate dielectric layer 41 away from the second side surface 422 of the gate 42. Figure 7 (i) as shown;

[0119] The fourth trench 434 is filled with a P-type polysilicon material by a deposition process. The doping element of the P-type polysilicon material is boron atoms, and the doping concentration is 10 19 / cm 3 , forming a P-type semiconductor material region 51, such as Figure 7 (j) as shown;

[0120] A metal nickel material is deposited on the source region 30 by a deposition process to form a first conductive layer 61. Figure 7 (k) as shown;

[0121] A metal aluminum material is deposited on the gate 42 by a deposition process to form a second conductive layer 62. Figure 7 (k) as shown;

[0122] A silicon oxide material is deposited on the first conductive layer 61 by a deposition process to form a dielectric layer 70. The dielectric layer 70 is in contact with the gate trench structure 40, a portion of the source region 30 and a portion of the P-type semiconductor material region 51, respectively. Figure 7 (k) as shown;

[0123] A metal aluminum material is deposited on the dielectric layer 70, the second conductive layer 62 and the P-type semiconductor material region 51 by a deposition process to form a third conductive layer 63. Figure 7 (k) as shown;

[0124] A metal aluminum material is deposited on the side of the N-type SiC substrate 10 away from the N-type SiC drift layer 20 by a deposition process to form a fourth conductive layer 64. Figure 7 (k) shown.

[0125] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0126] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A trench MOS device, characterized in that: The trench MOS device comprises a substrate and a drift layer and a source region arranged on the substrate, and the trench MOS device further comprises: a gate trench structure, wherein the gate trench structure penetrates the source region and extends into the drift layer, the gate trench structure comprises a gate dielectric layer and a gate, the gate comprises a first side surface and a second side surface arranged opposite to each other, the gate dielectric layer comprises a first region and a second region, the first region contacts the first side surface, the second region contacts the second side surface, the first region and the second region respectively have a first thickness and a second thickness in a first direction, the second thickness is greater than the first thickness, and the first direction is a direction perpendicular to the first side surface; A rectifying structure, wherein the rectifying structure is located on a side of the drift layer away from the substrate, the rectifying structure is in contact with the second region, the rectifying structure comprises a semiconductor material region and a drift layer region, the drift layer region comprises a portion of the drift layer in contact with the semiconductor material region, the semiconductor material region and the drift layer region have different doping types, the semiconductor material region is in contact with the second region, the semiconductor material region comprises doped polysilicon material, and the semiconductor material and the drift layer region constitute a heterojunction Schottky diode.

2. The trench MOS device according to claim 1, characterized in that: The doping concentration of the polysilicon material is 10 19 / cm 3 ~10 20 / cm 3 .

3. The trench MOS device according to claim 1, characterized in that: The first thickness is 0.03 μm to 0.08 μm, and the second thickness is 0.4 μm to 0.8 μm.

4. The trench MOS device according to claim 1, characterized in that: The gate dielectric layer also includes a third region, the third region contacts the bottom surface of the gate, the third region has a third thickness in a second direction, the third thickness is 0.03 μm to 0.08 μm, and the second direction is a direction perpendicular to the bottom surface of the gate.

5. The trench MOS device according to claim 1, characterized in that: Also includes: A shielding region, wherein the shielding region is located in the drift layer, the shielding region comprises a first shielding region and a second shielding region, the first shielding region at least contacts the first region, the second shielding region at least contacts the second region and the semiconductor material region, and the doping type of the shielding region is different from the doping type of the drift layer.

6. The trench MOS device according to claim 5, characterized in that: Also includes: An extension layer is located between the source region and the drift layer and is in contact with the first region and the first shielding region respectively. The extension layer and the drift layer have the same doping type, and the doping concentration of the extension layer is greater than the doping concentration of the drift layer.

7. A method for preparing a trench MOS device, characterized in that: Used to prepare the trench MOS device according to any one of claims 1 to 6, the preparation method comprising: providing a substrate; forming a stacked drift layer and a source region in sequence on the substrate; forming a gate trench structure, wherein the gate trench structure penetrates the source region and extends into the drift layer, the gate trench structure comprises a gate dielectric layer and a gate, the gate comprises a first side surface and a second side surface arranged opposite to each other, the gate dielectric layer comprises a first region and a second region, the first region contacts the first side surface, the second region contacts the second side surface, the first region and the second region respectively have a first thickness and a second thickness in a first direction, the second thickness is greater than the first thickness, and the first direction is a direction perpendicular to the first side surface; A rectifying structure is formed, wherein the rectifying structure is located on a side of the drift layer away from the substrate, the rectifying structure is in contact with the second region, the rectifying structure includes a semiconductor material region and a drift layer region, the drift layer region includes a portion of the drift layer in contact with the semiconductor material region, the semiconductor material region and the drift layer have different doping types, the semiconductor material region includes doped polysilicon material, and the semiconductor material and the drift layer region constitute a heterojunction Schottky diode.

8. The preparation method according to claim 7, characterized in that: The step of forming the gate trench structure comprises: Forming a first trench penetrating the source region and extending to the drift layer by an etching process; The first trench bottom surface and the first trench side surface and the second trench side surface disposed opposite to each other are oxidized by an oxidation process to form a first sub-gate dielectric layer, and the area of ​​the first trench except the first sub-gate dielectric layer is a second trench; Filling the second trench with a gate material using a deposition process to form a first sub-gate; Etching the area of ​​the first sub-gate close to the second side surface of the first trench by an etching process to form a third trench, and the remaining first sub-gate is the gate; An insulating material is filled in the third trench by a deposition process to form a second sub-gate dielectric layer, and the first sub-gate dielectric layer and the second sub-gate dielectric layer constitute the gate dielectric layer.

9. The preparation method according to claim 7, characterized in that: The steps of forming the rectifying structure include: forming a fourth trench in a region of the drift layer in contact with the second region by an etching process, wherein the fourth trench exposes a surface of the second region away from the second side surface; A doped polysilicon material is filled in the fourth trench by a deposition process, wherein the polysilicon material and the drift layer have different doping types.

10. The preparation method according to claim 7, characterized in that: Also includes: forming an extension layer on the drift layer, wherein the extension layer and the drift layer have the same doping type; An ion implantation process is used to form a first doped region and a second doped region spaced apart in the drift layer, and a third doped region and a fourth doped region spaced apart in the extension layer, the first doped region contacts the third doped region and constitutes a first shielding region, the second doped region contacts the fourth doped region and constitutes a second shielding region, the first shielding region and the second shielding region constitute a shielding region, the doping type of the shielding region is different from the doping type of the drift layer, and after the gate trench structure is formed, the first shielding region at least contacts the first region, and the second shielding region at least contacts the second region and the semiconductor material region.

Images