Micro-LED epitaxial wafer and preparation method thereof, Micro-LED

Abstract

The present invention discloses a Micro-LED epitaxial wafer and a preparation method thereof, and a Micro-LED, which relates to the field of semiconductor optoelectronic devices. The Micro-LED epitaxial wafer includes a substrate, a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, a hole transport layer, and a P-type semiconductor layer in sequence; the hole transport layer includes Al2O3, Al2O3, Al2O4, Al2O5, Al2O6, Al2O7, Al2O8, Al2O9, Al2O9, Al2O1, Al2O1, Al2O3, Al2O4, Al2O6, Al2O7, Al2O8, Al2O9 ...8, Al2O9, Al2O8, Al2O9, Al2O8, Al2O9, Al2O8, Al2O9, Al2 α Ga 1‑α N layer, B β Ga 1‑β N layer and AlN layer; the P-type semiconductor layer includes a P-type In layer sequentially stacked on the hole transport layer x Ga 1‑x N layer, P type Al y Ga 1‑y N layer, P-type GaN layer and Ta2O5 layer. The implementation of the present invention can improve the light efficiency of Micro-LED at low current density and improve its display effect.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices, and in particular to a Micro-LED epitaxial wafer and a preparation method thereof, and a Micro-LED. Background Art

[0002] Micro-LED generally refers to chips with a size of less than 100μm. It has excellent performance and low power consumption. It is the latest and best application technology in the foreseeable multi-display scenarios at the current stage. However, due to its small size, Micro-LED has higher requirements than ordinary LED chips in terms of stress, defect control, wavelength control, etc. The operating current density of Micro-LED used for display is generally 0.1~2A / cm 2 One of the main reasons for the low luminous efficiency at such a small current density is that the number of holes in the multi-quantum well layer is small, and the matching degree between holes and electrons is low, which reduces the luminous efficiency. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a Micro-LED epitaxial wafer and a preparation method thereof, which can improve the luminous efficiency under low current density.

[0004] Another technical problem to be solved by the present invention is to provide a Micro-LED.

[0005] In order to solve the above problems, the present invention discloses a Micro-LED epitaxial wafer, which includes a substrate, a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, a hole transport layer and a P-type semiconductor layer stacked on the substrate in sequence;

[0006] Wherein, the hole transport layer comprises Al2O3 sequentially stacked on the multi-quantum well layer. α Ga 1-α N layer, B β Ga 1-β N layer and AlN layer;

[0007] The P-type semiconductor layer includes a P-type In layer sequentially stacked on the hole transport layer. x Ga 1-x N layer, P type Al y Ga 1-y N layer, P-type GaN layer and Ta2O5 layer.

[0008] As an improvement of the above technical solution, the Al α Ga 1-α The thickness of the N layer is 5 nm to 10 nm, and the value of α is in the range of 0.08 to 0.2; and / or

[0009] The Bβ Ga 1-β The thickness of the N layer is 5nm~15nm, and the value range of β is 0.02~0.1; and / or

[0010] The thickness of the AlN layer is 2nm-5nm.

[0011] As an improvement of the above technical solution, the P-type In x Ga 1-x The doping concentration of the N layer is 8×10 19 cm -3 ~1×10 21 cm -3 , thickness is 50nm~100nm, and the value range of x is 0.01~0.1; and / or

[0012] The P-type Al y Ga 1-y The doping concentration of the N layer is 1×10 19 cm -3 ~1×10 20 cm -3 , thickness is 30nm~50nm; the value range of y is 0.03~0.15; and / or

[0013] The doping concentration of the P-type GaN layer is 1×10 19 cm -3 ~1×10 20 cm -3 , with a thickness of 50nm to 100nm; and / or

[0014] The thickness of the Ta2O5 layer is 5nm~25nm.

[0015] As an improvement of the above technical solution, the Ta2O5 layer is a β-Ta2O5 layer; and / or

[0016] The B β Ga 1-β The N layer is doped with Mg, and its doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 .

[0017] As an improvement of the above technical solution, the thickness of the AlN layer is less than 8 nm; and / or

[0018] The thickness of the Ta2O5 layer is ≤30nm.

[0019] As an improvement of the above technical solution, the multi-quantum well layer is a periodic structure, the number of periods is 3 to 8, and each period includes sequentially stacked InGaN quantum well layers and GaN quantum barrier layers;

[0020] The thickness of the InGaN quantum well layer is 2nm-4nm, and the thickness of the GaN quantum barrier layer is 5nm-10nm.

[0021] Correspondingly, the present invention also discloses a method for preparing a Micro-LED epitaxial wafer, which is used to prepare the above-mentioned Micro-LED epitaxial wafer, and comprises:

[0022] Providing a substrate, and sequentially growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, a hole transport layer and a P-type semiconductor layer on the substrate;

[0023] Wherein, the hole transport layer comprises Al2O3 sequentially stacked on the multi-quantum well layer. α Ga 1-α N layer, B β Ga 1-β N layer and AlN layer;

[0024] The P-type semiconductor layer includes a P-type In layer sequentially stacked on the hole transport layer. x Ga 1-x N layer, P type Al y Ga 1-y N layer, P-type GaN layer and Ta2O5 layer.

[0025] As an improvement of the above technical solution, the Al α Ga 1-α The growth temperature of the N layer is 900°C to 1000°C, and the growth pressure is 100 torr to 500 torr; and / or

[0026] The B β Ga 1-β The growth temperature of the N layer is 900°C to 1000°C, and the growth pressure is 100 torr to 500 torr; and / or

[0027] The AlN layer is grown at a temperature of 1000° C. to 1200° C. and a pressure of 100 torr to 500 torr; and / or

[0028] The P-type x Ga 1-x The growth temperature of the N layer is 800°C to 900°C and the growth pressure is 100 torr to 500 torr; and / or

[0029] The P-type Al y Ga 1-yThe growth temperature of the N layer is 900℃~1000℃, and the growth pressure is 100torr~500torr;

[0030] The growth temperature of the P-type GaN layer is 900° C. to 1000° C., and the growth pressure is 100 torr to 500 torr; and / or

[0031] The growth temperature of the Ta2O5 layer is 650°C to 900°C, and the growth pressure is 10torr to 100torr.

[0032] As an improvement of the above technical solution, the growth temperature of the Ta2O5 layer is 800°C~900°C, and the growth pressure is 10torr~100torr;

[0033] After the growth of the Ta2O5 layer is completed, annealing is performed at 900°C to 950°C for 10min to 30min in air or oxygen atmosphere.

[0034] Correspondingly, the present invention also discloses a Micro-LED, which includes the above-mentioned Micro-LED epitaxial wafer.

[0035] The implementation of the present invention has the following beneficial effects:

[0036] In the Micro-LED epitaxial wafer in one embodiment of the present invention, the hole transport layer includes Al α Ga 1-α N layer, B β Ga 1-β N layer and AlN layer; one, Al α Ga 1-α N layer, B β Ga 1-β The N layer forms a structure that gathers negative polarization charges, effectively promoting the transport of holes in the hole transport layer and improving the efficiency of hole injection into the multi-quantum well layer. β Ga 1-β The N layer and the AlN layer are aggregated at the interface, which accelerates the holes to a certain extent, making it easier for them to tunnel through the hole input layer, thereby effectively improving the matching degree of electrons and holes in the multi-quantum well layer, and greatly improving the luminous efficiency of Micro-LED at low current density. In addition, in one embodiment of the present invention, the P-type semiconductor layer includes a P-type In layer stacked on the hole transport layer. x Ga 1-x N layer, P type Al y Ga 1-yN layer, P-type GaN layer and Ta2O5 layer. First, the bandgap width of the Ta2O5 layer is about 4.4eV, which can form a local electric field with the P-type GaN layer, shorten the hole transmission distance, and improve the efficiency of hole injection from the electrode to the P-type semiconductor layer, thereby improving the efficiency of injection into the multi-quantum well layer. Second, the P-type In x Ga 1-x N layer, P type Al y Ga 1-y The heterojunction structure composed of the N layer and the P-type GaN layer can greatly accelerate holes, so that holes are more effectively injected from the P-type semiconductor layer into the multi-quantum well layer. In short, based on the hole transport layer and the P-type semiconductor layer in this embodiment, the efficiency of hole injection into the multi-quantum well layer is greatly improved, the balance of electrons and holes in the multi-quantum well layer is optimized, the luminous efficiency of Micro-LED at low current density is improved, and the display effect of the display device based on it is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic structural diagram of a Micro-LED epitaxial wafer in one embodiment of the present invention;

[0038] Figure 2 It is a flow chart of a method for preparing a Micro-LED epitaxial wafer in one embodiment of the present invention.

[0039] Among them, 100 is a substrate, 200 is a buffer layer, 300 is an undoped GaN layer, 400 is an N-type GaN layer, 500 is a multi-quantum well layer, 510 is a quantum well layer, 520 is a quantum barrier layer, 600 is a hole transport layer, 610 is an Al α Ga 1-α N layer, 620 for B β Ga 1-β N layer, 630 is AlN layer, 700 is P-type semiconductor layer, 710 is P-type In x Ga 1-x N layer, 720 is P-type Al y Ga 1-y N layer, 730 is a P-type GaN layer, and 740 is a Ta2O5 layer. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0041] See also Figure 1 The present invention discloses a Micro-LED epitaxial wafer, which includes a substrate 100, a buffer layer 200, a non-doped GaN layer 300, an N-type GaN layer 400, a multi-quantum well layer 500, a hole transport layer 600 and a P-type semiconductor layer 700 stacked on the substrate 100 in sequence.

[0042] The hole transport layer 600 includes Al2O3 sequentially stacked on the multi-quantum well layer 500. α Ga 1-α N layer 610, B β Ga 1-β N layer 620 and AlN layer 630; Based on the hole transport layer 600, Al α Ga 1-α N layer 610, B β Ga 1-β The N layer 620 forms a structure that gathers negative polarization charges, which effectively promotes the transport of holes in the hole transport layer 600 and improves the efficiency of hole injection into the multi-quantum well layer 500. Furthermore, by introducing the AlN layer 630, the hole injection into the B β Ga 1-β Aggregation occurs at the interface of the N layer 620 and the AlN layer 630, which accelerates the holes to a certain extent, making it easier for them to tunnel through the hole input layer, thereby effectively improving the matching degree of electrons and holes in the multi-quantum well layer 500, and greatly improving the luminous efficiency of Micro-LED at low current density.

[0043] Among them, Al α Ga 1-α The thickness of the N layer 610 is 5 nm to 15 nm, and is exemplarily 6 nm, 8 nm, 10 nm, 12 nm or 14 nm, but is not limited thereto, and is preferably 5 nm to 10 nm.

[0044] Among them, Al α Ga 1-α The proportion of Al component in N layer 610 (i.e., α) is 0.05-0.2. If α>0.2, holes will be blocked, reducing the probability of holes entering multi-quantum well layer 500. If α<0.05, the interface polarization positive charge is small, and it is difficult to effectively accelerate holes. Exemplarily, α is 0.08, 0.11, 0.14, 0.16 or 0.18, but not limited thereto. Preferably, it is 0.08-0.2.

[0045] Among them, B β Ga 1-β The thickness of the N layer 620 is 5 nm to 20 nm, exemplarily 8 nm, 10 nm, 12 nm, 14 nm, 16 nm or 18 nm, but not limited thereto, preferably 5 nm to 15 nm.

[0046] Among them, B β Ga 1-βThe proportion of the B component in the N layer 620 (ie, β) is 0.02-0.12, exemplarily 0.04, 0.06, 0.1 or 0.11, but not limited thereto, preferably 0.02-0.1.

[0047] The thickness of the AlN layer 630 is less than 8 nm to prevent it from causing hole blocking. Preferably, in one embodiment, the thickness of the AlN layer 630 is 2 nm to 6 nm, and is exemplarily 3 nm, 4 nm, 5 nm or 5.5 nm, but is not limited thereto. Preferably, it is 2 nm to 5 nm.

[0048] The P-type semiconductor layer 700 includes a P-type In layer sequentially stacked on the hole transport layer 600. x Ga 1-x N layer 710, P type Al y Ga 1-y N layer 720, P-type GaN layer 730 and Ta2O5 layer 740. Based on the above-mentioned P-type semiconductor layer 700, a local electric field is formed between the Ta2O5 layer 740 and the P-type GaN layer 730, which reduces the hole transmission distance and improves the hole injection efficiency. x Ga 1-x N layer 710, P type Al y Ga 1-y The heterojunction structure formed by the N layer 720 and the P-type GaN layer 730 can greatly accelerate holes and improve the hole injection efficiency.

[0049] Among them, P-type In x Ga 1-x The thickness of the N layer 710 is 50 nm to 150 nm, exemplarily 50 nm, 65 nm, 80 nm, 95 nm, 110 nm or 135 nm, but not limited thereto, preferably 50 nm to 100 nm.

[0050] P-type In x Ga 1-x The ratio of In component in N layer 710 (i.e., x) is 0.01-0.12. By introducing In, the activation energy of Mg can be increased and the hole concentration can be increased. However, if the ratio of In component is too high, the crystal quality of P-type semiconductor layer 700 will be reduced and the light absorption will be increased. Exemplarily, x is 0.02, 0.04, 0.06, 0.08 or 0.11, but not limited thereto. Preferably, it is 0.01-0.1.

[0051] P-type In x Ga 1-x The P-type doping element in the N layer 710 is Mg or Be, preferably Mg. x Ga 1-x The doping concentration of the N layer 710 is 5×1019 cm -3 ~1×10 21 cm -3 , exemplarily 7×10 19 cm -3 , 3×10 20 cm -3 , 5×10 20 cm -3 or 9×10 20 cm -3 , but not limited to this. Preferably 8×10 19 cm -3 ~1×10 21 cm -3 .

[0052] Among them, P-type Al y Ga 1-y The thickness of the N layer 720 is 20 nm to 50 nm, exemplarily 24 nm, 28 nm, 33 nm, 40 nm or 45 nm, but not limited thereto, preferably 30 nm to 50 nm.

[0053] P-type Al y Ga 1-y The ratio of Al component in the N layer 720 (ie, y) is 0.03-0.2, exemplarily 0.05, 0.1, 0.15 or 0.18, but not limited thereto, preferably 0.03-0.15.

[0054] P-type Al y Ga 1-y The P-type doping element in the N layer 720 is Mg or Be, preferably Mg. y Ga 1-y The doping concentration of the N layer 720 is 5×10 18 cm -3 ~1×10 20 cm -3 , exemplarily 7×10 18 cm -3 , 1×10 19 cm -3 , 6×10 19 cm -3 or 8×10 19 cm -3 , but not limited thereto. Preferably 1×10 19 cm -3 ~1×10 20 cm -3 .

[0055] The thickness of the P-type GaN layer 730 is 30 nm to 150 nm, exemplarily 50 nm, 70 nm, 90 nm, 110 nm or 130 nm, but not limited thereto, preferably 50 nm to 100 nm.

[0056] The doping concentration of the P-type GaN layer 730 is 1×10 19 cm -3 ~1×10 21 cm -3， An example is 3×10 19 cm -3、 5×10 19 cm -3 , 8×10 19 cm -3 , 3×10 20 cm -3 , 5×10 20 cm -3 or 9×10 20 cm -3 , but not limited thereto. Preferably 1×10 19 cm -3 ~1×10 20 cm -3 .

[0057] The thickness of the Ta2O5 layer 740 is ≤30nm to prevent it from affecting the ohmic contact between the P-type semiconductor layer 700 and the subsequently formed electrode. Preferably, in one embodiment, the thickness of the Ta2O5 layer 740 is 5nm to 25nm, and is exemplarily 8nm, 11nm, 14nm, 17nm, 20nm or 23nm, but is not limited thereto.

[0058] The substrate 100 is a sapphire substrate or a silicon substrate, but is not limited thereto.

[0059] The buffer layer 200 is an AlN layer or an AlGaN layer, but is not limited thereto. The buffer layer 200 has a thickness of 30 nm to 80 nm.

[0060] The thickness of the non-doped GaN layer 300 is 1 μm-3 μm.

[0061] The doping element of the N-type GaN layer 400 is Si, but not limited thereto. The doping concentration of Si in the N-type GaN layer 400 is 1×10 18 cm -3 ~5×10 19 cm -3 , and its thickness is 1μm~5μm.

[0062] Among them, the multi-quantum well layer 500 is a periodic structure with a period number of 3 to 8, and each period includes InGaN quantum well layers and GaN quantum barrier layers stacked in sequence. Among them, the proportion of In component in the InGaN quantum well layer is 0.1 to 0.2, and its In component proportion is low, and the compressive stress between it and the GaN quantum barrier layer is small, and the polarization electric field formed is weak, which is conducive to improving the luminous efficiency. The thickness of the InGaN quantum well layer is 2nm to 4nm, and the thickness of the GaN quantum barrier layer is 5nm to 10nm. By reducing the structure of the GaN quantum barrier layer, the vertical resistance can be reduced, the non-radiative recombination in the etched area can be reduced, and the luminous efficiency can be improved.

[0063] Preferably, in one embodiment of the present invention, the Ta2O5 layer 740 is a β-Ta2O5 layer 740, which has a smaller lattice mismatch with the P-type GaN layer 730, can reduce interface defects and improve luminous efficiency.

[0064] Preferably, in one embodiment of the present invention, B β Ga 1-β The N layer 620 is doped with Mg, and the doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 , which can serve as a hole source to provide some holes, thereby improving the luminescence efficiency.

[0065] Accordingly, see Figure 2 The present invention also provides a method for preparing a Micro-LED epitaxial wafer, which is used to prepare the above-mentioned Micro-LED epitaxial wafer, and specifically comprises the following steps:

[0066] S1: providing a substrate;

[0067] S2: sequentially growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, a hole transport layer and a P-type semiconductor layer on the substrate;

[0068] Specifically, in some embodiments of the present invention, step S2 includes:

[0069] S21: growing a buffer layer on the substrate;

[0070] The buffer layer may be grown by PVD, MOCVD, MBE or VPE, but is not limited thereto.

[0071] Preferably, in one embodiment of the present invention, an AlN layer is grown by PVD as a buffer layer.

[0072] S22: growing a non-doped GaN layer on the buffer layer;

[0073] Specifically, in one embodiment of the present invention, the undoped GaN layer is grown by MOCVD, the growth temperature is 1000° C. to 1200° C., and the growth pressure is 100 torr to 500 torr.

[0074] S23: growing an N-type GaN layer on the non-doped GaN layer;

[0075] Specifically, in one embodiment of the present invention, MOCVD is used to grow the N-type GaN layer, the growth temperature is 1100° C. to 1200° C., and the growth pressure is 100 torr to 500 torr.

[0076] S24: growing a multi-quantum well layer on the N-type GaN layer;

[0077] Specifically, in one embodiment, an InGaN quantum well layer and a GaN quantum barrier layer are periodically grown on an N-type GaN layer by MOCVD until a multi-quantum well layer is obtained.

[0078] The growth temperature of the InGaN quantum well layer is 740°C to 820°C, and the growth pressure is 100 torr to 300 torr. The growth temperature of the GaN quantum barrier layer is 800°C to 900°C, and the growth pressure is 100 torr to 300 torr.

[0079] S25: growing a hole transport layer on the multi-quantum well layer;

[0080] Specifically, in one embodiment, Al is grown in sequence by MOCVD. α Ga 1-α N layer, B β Ga 1-β N layer and AlN layer, that is, the hole transport layer is obtained. α Ga 1-α The growth temperature of the N layer is 900℃~1000℃, and the growth pressure is 100torr~500torr; B β Ga 1-β The growth temperature of the N layer is 900°C~1000°C, and the growth pressure is 100torr~500torr; the growth temperature of the AlN layer is 1000°C~1200°C, and the growth pressure is 100torr~500torr.

[0081] S26: growing a P-type semiconductor layer on the hole transport layer;

[0082] Specifically, in one embodiment of the present invention, MOCVD is used to sequentially grow P-type In x Ga 1-x N layer, P type Al y Ga 1-yN layer, P-type GaN layer and Ta2O5 layer until a P-type semiconductor layer is obtained. x Ga 1-x The growth temperature of the N layer is 800℃~900℃, and the growth pressure is 100torr~500torr; P-type Al y Ga 1-y The growth temperature of the N layer is 900℃~1000℃, and the growth pressure is 100torr~500torr; the growth temperature of the P-type GaN layer is 900℃~1000℃, and the growth pressure is 100torr~500torr; the growth temperature of the Ta2O5 layer is 650℃~900℃, and the growth pressure is 10torr~100torr.

[0083] Preferably, in one embodiment, the growth temperature of the Ta2O5 layer is 800°C to 900°C, and the growth pressure is 10 torr to 100 torr; based on this growth condition, a β-Ta2O5 layer can be obtained. Further preferably, after the growth of the Ta2O5 layer is completed, annealing is performed at 900°C to 950°C in an air or oxygen atmosphere for 10 min to 30 min. Based on the annealing treatment, the crystal quality of the β-Ta2O5 layer can be further improved, and its blocking effect on electrons can be improved.

[0084] The present invention will be further described below with specific embodiments:

[0085] Example 1

[0086] The present embodiment provides a Micro-LED epitaxial wafer, which includes a substrate, a buffer layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well layer, a hole transport layer and a P-type semiconductor layer stacked in sequence on the substrate.

[0087] The substrate is a sapphire substrate, the buffer layer is an AlN layer with a thickness of 50 nm, and the thickness of the undoped GaN layer is 1.5 μm. The Si doping concentration in the N-type GaN layer is 8.5×10 18 cm -3 , and its thickness is 3μm. The multi-quantum well layer includes alternately stacked InGaN quantum well layers and GaN quantum barrier layers, and its period number is 8. Among them, the In component in the InGaN quantum well layer accounts for 0.15, its thickness is 3nm, and the thickness of the GaN quantum barrier layer is 8nm.

[0088] The hole transport layer includes Al2O3 layer stacked on the multi-quantum well layer. α Ga 1-α N layer (α=0.07), B β Ga 1-β N layer (β=0.05) and AlN layer; Al α Ga1-α The thickness of the N layer is 10 nm, and the B β Ga 1-β The thickness of the N layer is 12 nm, and the thickness of the AlN layer is 3 nm.

[0089] The P-type semiconductor layer includes a P-type In layer stacked on the hole transport layer. x Ga 1-x N layer (x=0.05), P-type Al y Ga 1-y N layer (y=0.12), P-type GaN layer and Ta2O5 layer. x Ga 1-x The Mg doping concentration in the N layer is 5×10 20 cm -3 , its thickness is 70nm; P-type Al y Ga 1-y The Mg doping concentration in the N layer is 5×10 19 cm -3 , its thickness is 40nm; the Mg doping concentration in the P-type GaN layer is 8×10 19 cm -3 cm -3 The Ta2O5 layer is a δ-Ta2O5 layer, and its thickness is 20nm.

[0090] The method for preparing the Micro-LED epitaxial wafer in this embodiment includes the following steps:

[0091] (1) Providing a substrate;

[0092] (2) growing a buffer layer on the substrate;

[0093] Specifically, an AlN layer is grown by PVD to serve as a buffer layer.

[0094] (3) growing a non-doped GaN layer on the buffer layer;

[0095] Specifically, the non-doped GaN layer is grown by MOCVD, with a growth temperature of 1100° C. and a growth pressure of 300 torr.

[0096] (4) growing an N-type GaN layer on the undoped GaN layer;

[0097] Specifically, MOCVD is used to grow the N-type GaN layer, with a growth temperature of 1150° C. and a growth pressure of 300 torr.

[0098] (5) Growing a multi-quantum well layer on the N-type GaN layer;

[0099] Specifically, InGaN quantum well layers and GaN quantum barrier layers are alternately grown on the N-type GaN layer by MOCVD until a multi-quantum well layer is obtained. The growth temperature of the InGaN quantum well layer is 780°C and the growth pressure is 200 torr. The growth temperature of the GaN quantum barrier layer is 880°C and the growth pressure is 200 torr.

[0100] (6) growing a hole transport layer on the multi-quantum well layer;

[0101] Specifically, Al was grown sequentially by MOCVD. α Ga 1-α N layer, B β Ga 1-β N layer and AlN layer, that is, the hole transport layer is obtained. α Ga 1-α The growth temperature of the N layer is 940℃ and the growth pressure is 300torr; β Ga 1-β The growth temperature of the N layer is 950°C and the growth pressure is 300 torr; the growth temperature of the AlN layer is 1100°C and the growth pressure is 300 torr.

[0102] (7) growing a P-type semiconductor layer on the hole transport layer;

[0103] Specifically, P-type In is grown in sequence by MOCVD. x Ga 1-x N layer, P type Al y Ga 1-y N layer, P-type GaN layer and Ta2O5 layer until a P-type semiconductor layer is obtained. x Ga 1-x The growth temperature of the N layer is 820℃ and the growth pressure is 300torr; the P-type Al y Ga 1-y The growth temperature of the N layer is 980°C and the growth pressure is 300 torr; the growth temperature of the P-type GaN layer is 920°C and the growth pressure is 300 torr; the growth temperature of the Ta2O5 layer is 720°C and the growth pressure is 20 torr.

[0104] Example 2

[0105] This embodiment provides a Micro-LED epitaxial wafer, which is different from the embodiment 1 in that:

[0106] B β Ga 1-β The N layer is doped with Mg, and its doping concentration is 2×10 18 cm -3 .

[0107] The rest are the same as in Example 1.

[0108] Example 3

[0109] This embodiment provides a Micro-LED epitaxial wafer, which is different from Embodiment 2 in that:

[0110] The Ta2O5 layer is a β-Ta2O5 layer; its growth temperature is 820°C and its growth pressure is 10 torr.

[0111] The rest are the same as in Example 2.

[0112] Example 4

[0113] This embodiment provides a Micro-LED epitaxial wafer, which is different from the embodiment 3 in that:

[0114] After the Ta2O5 layer is grown, it is annealed at 920°C for 20 minutes in an oxygen atmosphere.

[0115] The rest is the same as Example 3.

[0116] Comparative Example 1

[0117] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0118] The hole input layer is replaced by an electron blocking layer, and the electron blocking layer is Al 0.4 Ga 0.6 N layer, with a thickness of 30nm; its growth temperature is 1120℃ and the growth pressure is 300torr.

[0119] The P-type semiconductor layer is a P-type GaN layer with a thickness of 200 nm and a doping concentration of 3×10 20 cm -3 , the growth temperature is 950℃ and the growth pressure is 300torr.

[0120] The rest are the same as in Example 1.

[0121] Comparative Example 2

[0122] This comparative example provides a Micro-LED epitaxial wafer, which differs from comparative example 1 in that:

[0123] No electron blocking layer is included.

[0124] The rest are the same as Comparative Example 1.

[0125] Comparative Example 3

[0126] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0127] The hole input layer is replaced by an electron blocking layer, and the electron blocking layer is Al 0.4 Ga 0.6 N layer, with a thickness of 30nm; its growth temperature is 1120℃ and the growth pressure is 300torr.

[0128] The rest are the same as in Example 1.

[0129] Comparative Example 4

[0130] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0131] The P-type semiconductor layer is a P-type GaN layer with a thickness of 200 nm and a doping concentration of 3×10 20 cm -3 , the growth temperature is 950℃ and the growth pressure is 300torr.

[0132] The rest are the same as in Example 1.

[0133] Comparative Example 5

[0134] This comparative example provides an epitaxial structure, which differs from Example 1 in that:

[0135] The hole transport layer is not included, and accordingly, the preparation method does not include the step of preparing the layer.

[0136] The rest are the same as in Example 1.

[0137] The epitaxial structures obtained in Examples 1 to 4 and Comparative Examples 1 to 5 were prepared into Micro-LEDs with a size of 50 μm×50 μm and a horizontal structure, and the 2 , 1A / cm 2 The luminous power was tested at a current density of , and the luminous power improvement rate was calculated based on the data of comparative example 1. The specific results are shown in the following table:

[0138]

[0139] It can be seen from the table that when the Micro-LED epitaxial wafer in the present invention is used, the luminous efficiency at low current density can be effectively improved.

[0140] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A Micro-LED epitaxial wafer, characterized in that: It includes a substrate, a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, a hole transport layer and a P-type semiconductor layer stacked in sequence on the substrate; Wherein, the hole transport layer comprises Al2O3 sequentially stacked on the multi-quantum well layer. α Ga 1-α N layer, B β Ga 1-β N layer and AlN layer; the Al α Ga 1-α The thickness of the N layer is 5nm~10nm, and the value range of α is 0.08~0.2; β Ga 1-β The thickness of the N layer is 5nm~15nm, and the value range of β is 0.02~0.1; the thickness of the AlN layer is 2nm~5nm; The P-type semiconductor layer includes a P-type In layer sequentially stacked on the hole transport layer. x Ga 1-x N layer, P type Al y Ga 1-y N layer, P-type GaN layer and Ta2O5 layer; the P-type In x Ga 1-x The doping concentration of the N layer is 8×10 19 cm -3 ~1×10 21 cm -3 , the thickness is 50nm~100nm, the value range of x is 0.01~0.1; the P-type Al y Ga 1-y The doping concentration of the N layer is 1×10 19 cm -3 ~1×10 20 cm -3 , with a thickness of 30nm~50nm; the value range of y is 0.03~0.15; the doping concentration of the P-type GaN layer is 1×10 19 cm -3 ~1×10 20 cm -3 , with a thickness of 50nm~100nm; the thickness of the Ta2O5 layer is 5nm~25nm.

2. The Micro-LED epitaxial wafer according to claim 1, characterized in that: The Ta2O5 layer is a β-Ta2O5 layer; and / or B β Ga 1-β The N layer is doped with Mg, and its doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 .

3. The Micro-LED epitaxial wafer according to claim 1, wherein: The multi-quantum well layer is a periodic structure, the number of periods is 3 to 8, and each period includes an InGaN quantum well layer and a GaN quantum barrier layer stacked in sequence; The thickness of the InGaN quantum well layer is 2nm-4nm, and the thickness of the GaN quantum barrier layer is 5nm-10nm.

4. A method for preparing a Micro-LED epitaxial wafer, for preparing the Micro-LED epitaxial wafer as claimed in any one of claims 1 to 3, characterized in that: include: Providing a substrate, and sequentially growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, a hole transport layer and a P-type semiconductor layer on the substrate; Wherein, the hole transport layer comprises Al2O3 sequentially stacked on the multi-quantum well layer. α Ga 1-α N layer, B β Ga 1-β N layer and AlN layer; The P-type semiconductor layer includes a P-type In layer sequentially stacked on the hole transport layer. x Ga 1-x N layer, P type Al y Ga 1-y N layer, P-type GaN layer and Ta2O5 layer.

5. The method for preparing a Micro-LED epitaxial wafer according to claim 4, wherein: The Al α Ga 1-α The growth temperature of the N layer is 900°C to 1000°C, and the growth pressure is 100 torr to 500 torr; and / or B β Ga 1-β The growth temperature of the N layer is 900°C to 1000°C, and the growth pressure is 100 torr to 500 torr; and / or The AlN layer is grown at a temperature of 1000° C. to 1200° C. and a pressure of 100 torr to 500 torr; and / or The P-type x Ga 1-x The growth temperature of the N layer is 800°C to 900°C and the growth pressure is 100 torr to 500 torr; and / or The P-type Al y Ga 1-y The growth temperature of the N layer is 900℃~1000℃, and the growth pressure is 100torr~500torr; The growth temperature of the P-type GaN layer is 900° C. to 1000° C., and the growth pressure is 100 torr to 500 torr; and / or The growth temperature of the Ta2O5 layer is 650°C to 900°C, and the growth pressure is 10torr to 100torr.

6. The method for preparing a Micro-LED epitaxial wafer according to claim 4, characterized in that: The growth temperature of the Ta2O5 layer is 800°C to 900°C, and the growth pressure is 10torr to 100torr; After the growth of the Ta2O5 layer is completed, annealing is performed at 900°C to 950°C for 10min to 30min in air or oxygen atmosphere.

7. A Micro-LED, characterized in that: Comprising the Micro-LED epitaxial wafer as described in any one of claims 1 to 3.

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