Electrostatic discharge test equipment and test method

Abstract

The invention discloses an electrostatic discharge test device and a test method, and belongs to the field of test. The electrostatic discharge test equipment provided by the invention comprises a port configuration unit, a control unit, a measurement unit and an electrostatic discharge generator, the port configuration unit is provided with an input end connected with a target pin of the chip to be tested, a first output end connected with the measuring unit, a second output end connected with the electrostatic discharge generator and a control end connected with the control unit; the control unit is used for outputting a first configuration signal or a second configuration signal to the port configuration unit, so that the port configuration unit controls a target pin of the to-be-tested chip to be electrically connected with the measurement unit or the electrostatic discharge generator. The port configuration unit is used for configuring the connection relation between the target pin of the to-be-tested chip and the measuring unit or the electrostatic discharge generator, electrostatic discharge testing and electric signal testing integration can be achieved, frequent insertion and extraction of the target pin of the to-be-tested chip are not needed, and the testing efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of testing, and specifically to an electrostatic discharge testing device and a testing method. Background Art

[0002] During the chip production, assembly, testing, storage, and transportation process, static electricity may accumulate in the chip. When these charged chips are touched, a discharge path will be formed, causing the chip to be instantly damaged by static discharge. Since the instantaneous voltage of static electricity is usually very high, this damage is destructive and permanent, and will cause the circuit to burn directly. Therefore, during the chip design and manufacturing process, it is very important to perform electrostatic discharge (ESD) testing on the chip to determine the chip's anti-static performance and then prevent static damage in a targeted manner.

[0003] In the related art, ESD equipment is generally used in combination with an IV (current-voltage) tester to perform an electrostatic discharge test on the chip to be tested. Specifically, the electrostatic discharge test process of the chip to be tested in the related art is generally as follows: the first step is to manually connect the pin to be tested of the chip to be tested with the IV tester, and use the IV tester to test the IV curve of the chip to be tested to obtain an initial IV test result; the second step is to disconnect the pin to be tested of the chip to be tested from the IV tester, and then manually connect the pin to be tested of the chip to be tested with the ESD device, and use the ESD device to perform an electrostatic discharge test on the chip to be tested; the third step is to disconnect the pin to be tested of the chip to be tested from the ESD device, and then manually connect the pin to be tested of the chip to be tested with the IV tester, and use the IV tester to test the IV curve of the chip to be tested to obtain the IV test result after electrostatic discharge (the above three steps need to be repeated and executed multiple times until all the pins to be tested of the chip to be tested are tested); finally, by comparing the IV test results obtained before and after the electrostatic discharge test, it is determined whether the chip to be tested has passed the electrostatic discharge test. The greater the difference between the IV test results obtained before and after the electrostatic discharge test, the worse the anti-static performance of the chip to be tested.

[0004] However, there is a problem of low test efficiency of electrostatic discharge test in the related art. Specifically, since the related art needs to use ESD equipment and IV tester in conjunction, it is necessary to manually disconnect the tested pin of the chip under test from the ESD equipment and then manually connect it to the IV tester for IV curve testing, or it is necessary to manually disconnect the tested pin of the chip under test from the IV tester and then manually connect it to the ESD equipment for electrostatic discharge testing, and the above steps need to be repeated many times until all the pins of the chip under test are tested, which makes the steps of manually connecting / disconnecting the tested pins of the chip under test with the ESD equipment and the IV tester respectively very cumbersome, and it is necessary to frequently plug and unplug the tested pins of the chip under test, resulting in low efficiency of electrostatic discharge testing. Summary of the invention

[0005] The embodiments of the present application provide an electrostatic discharge testing device and a testing method, which can solve the problem of low testing efficiency of electrostatic discharge testing in related technologies.

[0006] In a first aspect, an embodiment of the present application provides an electrostatic discharge testing device, comprising:

[0007] A port configuration unit, a control unit, a measuring unit connected to the control unit, and an electrostatic discharge generator connected to the control unit;

[0008] The port configuration unit has an input end, a first output end, a second output end and a control end; the input end of the port configuration unit is connected to the target pin of the chip to be tested; the first output end of the port configuration unit is connected to the measuring unit; the second output end of the port configuration unit is connected to the electrostatic discharge generator; the control end of the port configuration unit is connected to the control unit;

[0009] The control unit is used to output a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the measurement unit;

[0010] The control unit is used to output a second configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the electrostatic discharge generator;

[0011] The measuring unit is used to test the electrical signal of the chip to be tested;

[0012] The electrostatic discharge generator is used to perform an electrostatic discharge test on the chip to be tested.

[0013] In a second aspect, an embodiment of the present application provides an electrostatic discharge testing method, which is applied to the electrostatic discharge testing device as described in the first aspect, comprising:

[0014] The control unit outputs a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the measurement unit; when the target pin of the chip to be tested is electrically connected to the measurement unit, the control unit outputs a first test signal to the measurement unit, so that the measurement unit tests the electrical signal of the chip to be tested and obtains a first test result;

[0015] The control unit outputs a second configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip under test to be electrically connected to the electrostatic discharge generator; when the target pin of the chip under test is electrically connected to the electrostatic discharge generator, the control unit outputs a second test signal to the electrostatic discharge generator, so that the electrostatic discharge generator performs an electrostatic discharge test on the chip under test under specified test conditions;

[0016] After the electrostatic discharge test is performed on the chip under test, the control unit outputs a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip under test to be electrically connected to the measurement unit; when the target pin of the chip under test is electrically connected to the measurement unit, the control unit again outputs the first test signal to the measurement unit, so that the measurement unit again tests the electrical signal of the chip under test to obtain a second test result;

[0017] Based on the first test result and the second test result, it is determined whether the chip to be tested passes the electrostatic discharge test under specified test conditions.

[0018] In an embodiment of the present application, an electrostatic discharge test device includes a port configuration unit, a control unit, a measuring unit connected to the control unit, and an electrostatic discharge generator connected to the control unit; the port configuration unit has an input end, a first output end, a second output end, and a control end; the input end of the port configuration unit is connected to the target pin of the chip to be tested; the first output end of the port configuration unit is connected to the measuring unit; the second output end of the port configuration unit is connected to the electrostatic discharge generator; the control end of the port configuration unit is connected to the control unit; the port configuration unit is used to configure the connection relationship between the target pin of the chip to be tested and the measuring unit and the electrostatic discharge generator; the control unit is used to output a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the measuring unit; the control unit is used to output a second configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the electrostatic discharge generator; the measuring unit is used to test the electrical signal of the chip to be tested; and the electrostatic discharge generator is used to perform an electrostatic discharge test on the chip to be tested. In this way, when it is necessary to test the electrical signal of the chip to be tested, the port configuration unit can control the target pin of the chip to be tested to be electrically connected to the measurement unit, so that the measurement unit can be used to test the electrical signal. When it is necessary to perform an electrostatic discharge test on the chip to be tested, the port configuration unit can control the target pin of the chip to be tested to be electrically connected to the electrostatic discharge generator, so that the electrostatic discharge generator can be used to perform the electrostatic discharge test. Compared with the related technology, the electrostatic discharge testing equipment can realize the integration of electrostatic discharge testing and electrical signal testing. Moreover, since the port configuration unit is used to configure the connection relationship between the target pin of the chip to be tested and the measurement unit and the electrostatic discharge generator, there is no need to frequently plug and unplug the target pin of the chip to be tested, thereby improving the testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic structural diagram of an electrostatic discharge testing device provided in an embodiment of the present application;

[0020] Figure 2 A schematic structural diagram of another electrostatic discharge testing device provided in an embodiment of the present application;

[0021] Figure 3 A schematic structural diagram of another electrostatic discharge testing device provided in an embodiment of the present application;

[0022] Figure 4 A partial schematic structural diagram of an electrostatic discharge testing device provided in an embodiment of the present application;

[0023] Figure 5A partial schematic structural diagram of another electrostatic discharge testing device provided in an embodiment of the present application;

[0024] Figure 6 A schematic structural diagram of another electrostatic discharge testing device provided in an embodiment of the present application;

[0025] Figure 7 A partial schematic structural diagram of another electrostatic discharge testing device provided in an embodiment of the present application;

[0026] Figure 8 A schematic structural diagram of another electrostatic discharge testing device provided in an embodiment of the present application;

[0027] Fig. 9 A partial schematic structural diagram of another electrostatic discharge testing device provided in an embodiment of the present application;

[0028] Fig.10 A partial schematic structural diagram of another electrostatic discharge testing device provided in an embodiment of the present application;

[0029] Fig.11 A partial schematic structural diagram of another electrostatic discharge testing device provided in an embodiment of the present application;

[0030] Fig.12 A schematic flow chart of an electrostatic discharge testing method provided in an embodiment of the present application;

[0031] Fig.13 A schematic diagram of a test interface for an electrostatic discharge test provided in an embodiment of the present application;

[0032] Fig.14 A schematic flowchart of another electrostatic discharge testing method provided in an embodiment of the present application.

[0033] Description of reference numerals:

[0034] 100-electrostatic discharge test equipment; 110-port configuration unit; 120-control unit; 130-measurement unit; 1301-measurement module; 1302-switching module; 140-electrostatic discharge generator; DUT_PIN-target pin of the chip to be tested; DUT_PIN1-first target pin; DUT_PIN i-i-th target pin; DUT_PIN N-N-th target pin; Floating-floating state; IV_P-positive port of the measurement unit; IV_N-negative port of the measurement unit; ESD_P-positive discharge port of the electrostatic discharge generator; ESD_N-reverse discharge port of the electrostatic discharge generator; 1101-first relay; 1102-second relay; 1103-third relay; 1104-fourth relay; K5-fifth relay; K6-sixth relay; DAC-digital-to-analog converter; U1-first amplifier; U2-second amplifier; U3-third amplifier; R1-first resistor; ADC-analog-to-digital converter. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0036] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0037] As described in the background art, in the related art, the steps of manually connecting / disconnecting the pins of the chip to be tested with the ESD device and the IV tester are very cumbersome, resulting in low efficiency of electrostatic discharge testing.

[0038] Based on this, in order to solve the problem of low efficiency of electrostatic discharge testing in related technologies, an electrostatic discharge testing device provided in an embodiment of the present application includes: a port configuration unit, a control unit, a measuring unit and an electrostatic discharge generator; the port configuration unit has an input end connected to a target pin of a chip to be tested, a first output end connected to a measuring unit, a second output end connected to an electrostatic discharge generator and a control end connected to the control unit; the control unit is used to output a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the measuring unit; the control unit is used to output a second configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the electrostatic discharge generator; the measuring unit is used to test the electrical signal of the chip to be tested; and the electrostatic discharge generator is used to perform an electrostatic discharge test on the chip to be tested.

[0039] The electrostatic discharge test equipment provided in the embodiments of the present application can be independently used for electrostatic discharge testing of devices under test (DUT) such as chips under test, electronic components under test, circuits under test, electronic equipment under test, etc. The present application does not impose any specific restrictions on the type of device under test. Specifically, taking the test device as an example of a chip to be tested, since the electrostatic discharge test device has a measurement unit for testing the electrical signal of the chip to be tested, an electrostatic discharge generator for performing electrostatic discharge testing on the chip to be tested, and a port configuration unit for configuring the connection relationship between the target pin of the chip to be tested and the measurement unit and the electrostatic discharge generator, when it is necessary to test the electrical signal of the chip to be tested, the port configuration unit can control the target pin of the chip to be tested to be electrically connected to the measurement unit, so as to use the measurement unit to test the electrical signal, and when it is necessary to perform an electrostatic discharge test on the chip to be tested, the port configuration unit can control the target pin of the chip to be tested to be electrically connected to the electrostatic discharge generator, so as to use the electrostatic discharge generator to perform an electrostatic discharge test. Compared with the related art, the electrostatic discharge test device can realize the integration of electrostatic discharge testing and electrical signal testing, and there is no need to frequently plug and unplug the target pin of the chip to be tested, thereby improving the test efficiency.

[0040] The electrostatic discharge testing device and the testing method provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0041] Figure 1 A schematic structural diagram of an electrostatic discharge testing device provided in an embodiment of the present application.

[0042] like Figure 1 As shown, the electrostatic discharge testing device 100 provided in the embodiment of the present application may include:

[0043] A port configuration unit 110, a control unit 120, a measurement unit 130 connected to the control unit, and an electrostatic discharge generator 140 connected to the control unit;

[0044] The port configuration unit 110 has an input end, a first output end, a second output end and a control end; the input end of the port configuration unit 110 is connected to the target pin DUT_PIN of the chip to be tested; the first output end of the port configuration unit 110 is connected to the measuring unit 130; the second output end of the port configuration unit 110 is connected to the electrostatic discharge generator 140; the control end of the port configuration unit 110 is connected to the control unit 120;

[0045] The control unit 120 may be configured to output a first configuration signal to the port configuration unit 110, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test to be electrically connected to the measurement unit 130;

[0046] The control unit 120 may also be used to output a second configuration signal to the port configuration unit 110, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test to be electrically connected to the electrostatic discharge generator 140;

[0047] The measuring unit 130 may be used to test the electrical signal of the chip to be tested;

[0048] The electrostatic discharge generator 140 can be used to perform an electrostatic discharge test on the chip to be tested.

[0049] In the embodiment of the present application, the port configuration unit 110 can be used to configure the connection relationship between the target pin DUT_PIN of the chip under test and the measurement unit 130 and the electrostatic discharge generator 140. For example, in the case where the control unit 120 outputs a first configuration signal to the port configuration unit 110, the port configuration unit 110 can control the target pin DUT_PIN of the chip under test to be electrically connected to the measurement unit 130 according to the first configuration signal; in the case where the control unit 120 outputs a second configuration signal to the port configuration unit 110, the port configuration unit 110 can control the target pin DUT_PIN of the chip under test to be electrically connected to the electrostatic discharge generator 140 according to the second configuration signal.

[0050] In the embodiment of the present application, the control unit 120 can be a main control MCU (Microcontroller Unit), or a CPU (Central Processing Unit), or a processor or controller of other architectures. The present application does not limit the specific type of the control unit 120.

[0051] In an embodiment of the present application, the measuring unit 130 can be used to measure the volt-ampere characteristics of the chip to be tested. The electrical signal of the chip to be tested can be a voltage signal or a current signal. For example, the voltage is tested under a set current, or the current is tested under a set voltage. The present application does not impose any specific restrictions on this.

[0052] In the embodiment of the present application, the electrostatic discharge generator 140 may provide a forward discharge port / reverse discharge port for electrostatic discharge testing of the chip to be tested.

[0053] In the embodiment of the present application, when it is necessary to test the electrical signal of the chip under test, the port configuration unit 110 can control the target pin DUT_PIN of the chip under test to be electrically connected to the measurement unit 130, so as to use the measurement unit 130 to test the electrical signal of the chip under test.

[0054] In the embodiment of the present application, when an electrostatic discharge test is required for the chip under test, the port configuration unit 110 can control the target pin DUT_PIN of the chip under test to be electrically connected to the electrostatic discharge generator 140 to facilitate the electrostatic discharge test using the electrostatic discharge generator 140.

[0055] In the embodiment of the present application, the electrostatic discharge testing device 100 can be used to check whether the chip under test can work normally when subjected to external electrostatic discharge. In other words, the electrostatic discharge testing device 100 can be used to detect the anti-static performance of the chip under test.

[0056] In the embodiment of the present application, the output of the electrostatic discharge generator 140 can be forward discharge or reverse discharge, the discharge direction of forward discharge / reverse discharge can be switched, and the discharge voltage is bipolar and highly accurate and continuously adjustable.

[0057] In the embodiment of the present application, the detection principle of the electrostatic discharge testing equipment 100 can be: using the measuring unit 130 to test the IV curve of the chip under test before the electrostatic discharge test; using the electrostatic discharge generator 140 to perform an electrostatic discharge test on the chip under test; and again using the measuring unit 130 to test the IV curve of the chip under test after the electrostatic discharge test, by comparing the changes in the test results of the IV curve of the chip under test before and after the electrostatic discharge test, it is determined whether the anti-static performance of the chip under test is qualified.

[0058] It can be understood that, compared with the related art, the electrostatic discharge testing device 100 can realize the integration of electrostatic discharge testing and electrical signal testing, and because the present solution adopts the port configuration unit 110 to configure the connection relationship between the target pin DUT_PIN of the chip to be tested and the measurement unit 130 and the electrostatic discharge generator 140, there is no need to frequently plug and unplug the target pin DUT_PIN of the chip to be tested, thereby improving the test efficiency.

[0059] According to an embodiment of the present application, an electrostatic discharge test device is provided, comprising a port configuration unit, a control unit, a measuring unit connected to the control unit, and an electrostatic discharge generator connected to the control unit; the port configuration unit has an input end, a first output end, a second output end, and a control end; the input end of the port configuration unit is connected to a target pin of a chip to be tested; the first output end of the port configuration unit is connected to the measuring unit; the second output end of the port configuration unit is connected to the electrostatic discharge generator; the control end of the port configuration unit is connected to the control unit; the port configuration unit is used to configure the connection relationship between the target pin of the chip to be tested and the measuring unit and the electrostatic discharge generator; the control unit is used to output a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the measuring unit; the control unit is used to output a second configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the electrostatic discharge generator; the measuring unit is used to test the electrical signal of the chip to be tested; and the electrostatic discharge generator is used to perform an electrostatic discharge test on the chip to be tested. In this way, when it is necessary to test the electrical signal of the chip to be tested, the port configuration unit can control the target pin of the chip to be tested to be electrically connected to the measurement unit, so that the measurement unit can be used to test the electrical signal. When it is necessary to perform an electrostatic discharge test on the chip to be tested, the port configuration unit can control the target pin of the chip to be tested to be electrically connected to the electrostatic discharge generator, so that the electrostatic discharge generator can be used to perform the electrostatic discharge test. Compared with the related technology, the electrostatic discharge testing equipment can realize the integration of electrostatic discharge testing and electrical signal testing. Moreover, since the port configuration unit is used to configure the connection relationship between the target pin of the chip to be tested and the measurement unit and the electrostatic discharge generator, there is no need to frequently plug and unplug the target pin of the chip to be tested, thereby improving the testing efficiency.

[0060] In a specific embodiment, after the control unit 120 outputs a first configuration signal to the port configuration unit 110, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test to be electrically connected to the measurement unit 130 according to the first configuration signal, when the target pin DUT_PIN of the chip under test is electrically connected to the measurement unit 130, the control unit 120 can be used to output a first test signal to the measurement unit 130, so that the measurement unit 130 tests the electrical signal of the chip under test.

[0061] After the control unit 120 outputs the second configuration signal to the port configuration unit 110, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test to be electrically connected to the electrostatic discharge generator 140 according to the second configuration signal, when the target pin DUT_PIN of the chip under test is electrically connected to the electrostatic discharge generator 140, the control unit 120 is used to output a second test signal to the electrostatic discharge generator 140, so that the electrostatic discharge generator 140 performs an electrostatic discharge test on the chip under test.

[0062] In this way, compared with related technologies, there is no need to use ESD equipment and combine it with an IV tester to perform electrostatic discharge testing on the chip to be tested. The electrostatic discharge testing equipment can integrate electrostatic discharge testing and electrical signal testing. The electrostatic discharge testing equipment has higher integration and more comprehensive functions.

[0063] In a specific embodiment, since the chip to be tested generally includes multiple pins, multiple pins may need to be tested. Thus, the embodiment of the present application can set multiple port configuration units 110 on the electrostatic discharge test equipment 100 to facilitate one-to-one connection of multiple pins of the chip to be tested with multiple port configuration units of the electrostatic discharge test equipment. Subsequently, multiple pins of the chip to be tested can be tested without frequent plugging and unplugging of each pin of the chip to be tested, thereby improving the test efficiency.

[0064] For example, the port configuration unit 110 includes N, and the input end of each port configuration unit 110 in the N port configuration units 110 is connected to each target pin of the chip to be tested in a one-to-one correspondence, and N is a positive integer. Among them, N can be any positive integer such as 1, 2, 3 or 4, and this application does not make any specific limitation.

[0065] Of course, in practical applications, the number of port configuration units of the electrostatic discharge test equipment can be greater than or equal to the number of pins of the chip to be tested, or can be less than the number of pins of the chip to be tested, and this application does not impose any restrictions on this. The following is an example in which the number of port configuration units of the electrostatic discharge test equipment is equal to the number of pins of the chip to be tested.

[0066] like Figure 2 As shown, in the electrostatic discharge testing device 100 provided in the embodiment of the present application, the port configuration unit 110 may include N units, for example, the port configuration unit 110 may include a first port configuration unit...an i-th port configuration unit...an N-th port configuration unit.

[0067] The target pins DUT_PIN of the chip under test may also include N numbers. For example, the target pins DUT_PIN of the chip under test include a first target pin ... an i-th target pin ... an N-th target pin;

[0068] The input end of the first port configuration unit is connected to the first target pin of the chip under test...the input end of the i-th port configuration unit is connected to the i-th target pin of the chip under test...the input end of the N-th port configuration unit is connected to the N-th target pin of the chip under test.

[0069] Wherein, i is a positive integer greater than 1 and less than N, and N is a positive integer greater than 1.

[0070] In this way, the multiple pins of the chip to be tested are connected one-to-one with the multiple port configuration units of the electrostatic discharge test equipment, and the multiple pins of the chip to be tested can be tested subsequently without frequently plugging and unplugging the pins of the chip to be tested, thereby improving the test efficiency.

[0071] The principle of testing each pin of the chip to be tested according to the embodiment of the present application is described in detail below.

[0072] In the embodiment of the present application, each pin of the chip under test can be tested in sequence. Specifically, the control unit 120 can also be used to output a third configuration signal to the port configuration unit 110, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test to be in a floating state.

[0073] It can be understood that the measuring unit 130 / electrostatic discharge generator 140 can only test the target pin DUT_PIN of the chip under test that is electrically connected to it, but cannot test the target pin DUT_PIN of the chip under test that is not connected to it. In this case, the control unit 120 outputs the third configuration signal to the port configuration unit 110, so that the port configuration unit 110 controls some target pins of the chip under test to be in a floating state, thereby avoiding multiple target pins being connected to the measuring unit 130 / electrostatic discharge generator 140 at the same time, which causes the test accuracy to deteriorate.

[0074] For example, when the target pins DUT_PIN of the chip to be tested include a first target pin ... an i-th target pin ... an N-th target pin, the process of sequentially testing each pin of the chip to be tested is as follows:

[0075] In the first step, the control unit 120 outputs a first configuration signal to the first port configuration unit 110, so that the first port configuration unit 110 controls the first target pin DUT_PIN 1 to be electrically connected to the measuring unit 130 according to the first configuration signal, and the control unit 120 then outputs a first test signal to the measuring unit 130, so that the measuring unit 130 tests the electrical signal of the chip under test; or, the control unit 120 outputs a second configuration signal to the first port configuration unit 110, so that the first port configuration unit 110 controls the first target pin DUT_PIN 1 to be electrically connected to the electrostatic discharge generator 140 according to the second configuration signal, and the control unit 120 then outputs a second test signal to the electrostatic discharge generator 140, so that the electrostatic discharge generator 140 performs an electrostatic discharge test on the chip under test via the first target pin DUT_PIN 1 of the chip under test; and the other port configuration units except the first port configuration unit all control the corresponding target pins to be in a floating state.

[0076] In the second step, the control unit 120 outputs a first configuration signal to the second port configuration unit 110, so that the second port configuration unit 110 controls the second target pin DUT_PIN 2 to be electrically connected to the measuring unit 130 according to the first configuration signal, and the control unit 120 then outputs a first test signal to the measuring unit 130, so that the measuring unit 130 tests the electrical signal of the chip under test; or, the control unit 120 outputs a second configuration signal to the second port configuration unit 110, so that the second port configuration unit 110 controls the second target pin DUT_PIN 2 to be electrically connected to the electrostatic discharge generator 140 according to the second configuration signal, and the control unit 120 then outputs a second test signal to the electrostatic discharge generator 140, so that the electrostatic discharge generator 140 performs an electrostatic discharge test on the chip under test via the second target pin DUT_PIN 2 of the chip under test. Except for the second port configuration unit, all other port configuration units control the corresponding target pins to be in a floating state.

[0077] By analogy, in the Nth step, the control unit 120 outputs a first configuration signal to the Nth port configuration unit 110, so that the Nth port configuration unit 110 controls the Nth target pin DUT_PIN N to be electrically connected to the measurement unit 130 according to the first configuration signal, and the control unit 120 then outputs a first test signal to the measurement unit 130, so that the measurement unit 130 tests the electrical signal of the chip under test; or, the control unit 120 outputs a second configuration signal to the Nth port configuration unit 110, so that the Nth port configuration unit 110 controls the Nth target pin DUT_PIN N to be electrically connected to the electrostatic discharge generator 140 according to the second configuration signal, and the control unit 120 then outputs a second test signal to the electrostatic discharge generator 140, so that the electrostatic discharge generator 140 performs an electrostatic discharge test on the chip under test via the Nth target pin DUT_PIN N of the chip under test. Except for the Nth port configuration unit, the other port configuration units all control the corresponding target pins to be in a floating state.

[0078] In this way, when the multiple pins DUT_PIN of the chip to be tested are connected one-to-one with the multiple port configuration units 110 of the electrostatic discharge testing equipment, by setting the control unit 120 to output the third configuration signal to the port configuration unit 110 so that the port configuration unit 110 controls some target pins of the chip to be tested to be in a floating state, it can be ensured that each pin of the chip to be tested is tested sequentially (orderly).

[0079] In practical applications, the port configuration unit 110 may include five working modes (corresponding to the third configuration signal, the fourth configuration signal, the fifth configuration signal, the sixth configuration signal and the seventh configuration signal output by the control unit described below).

[0080] like Figure 3 As shown, taking the first port configuration unit 110 as an example, the control unit 120 can be used to output a third configuration signal to the port configuration unit 110, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test to be in a floating state (corresponding to Figure 3 Floating port in the middle);

[0081] With respect to the connection relationship between the target pin DUT_PIN and the measurement unit 130, the first configuration signal may include at least one of a fourth configuration signal and a fifth configuration signal;

[0082] The control unit 120 may be configured to output a fourth configuration signal to the port configuration unit, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test and the positive port (corresponding to Figure 3 IV_P port) electrical connection;

[0083] The control unit 120 may be configured to output a fifth configuration signal to the port configuration unit, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test and the negative port (corresponding to Figure 3 IV_N port) electrical connection;

[0084] With respect to the connection relationship between the target pin and the electrostatic discharge generator, the second configuration signal includes at least one of a sixth configuration signal and a seventh configuration signal;

[0085] The control unit 120 can be used to output a sixth configuration signal to the port configuration unit, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test and the forward discharge port (corresponding to Figure 3 ESD_P port) electrical connection;

[0086] The control unit 120 can be used to output the seventh configuration signal to the port configuration unit, so that the port configuration unit 110 controls the target pin DUT_PIN of the chip under test and the reverse discharge port (corresponding to Figure 3 ESD_N port) is electrically connected.

[0087] It can be understood that the first port configuration unit...the i-th port configuration unit...the N-th port configuration unit can all implement the five working modes described above, which will not be described in detail here.

[0088] Accordingly, if Figure 4 As shown, the port configuration unit can be a relay component; the relay component has five switching modes;

[0089] The relay component is used to switch the target pin of the chip to be tested to a floating state (corresponding to the third configuration signal output by the control unit) in the first switching mode. Figure 4 Floating port in the middle);

[0090] The relay component is used to switch the target pin DUT_PIN of the chip under test to the positive port (corresponding to the positive port of the measuring unit) of the measuring unit according to the fourth configuration signal output by the control unit in the second switching mode. Figure 4 IV_P port) electrical connection;

[0091] The relay assembly is used to switch the target pin DUT_PIN of the chip under test to the negative terminal (corresponding to the negative terminal of the measuring unit) of the measuring unit according to the fifth configuration signal output by the control unit in the third switching mode. Figure 4 IV_N port) electrical connection;

[0092] The relay assembly is used to switch the target pin DUT_PIN of the chip under test to the forward discharge port (corresponding to the forward discharge port) of the electrostatic discharge generator according to the sixth configuration signal output by the control unit in the fourth switching mode. Figure 4 ESD_P port) electrical connection;

[0093] The relay assembly is used to switch the target pin DUT_PIN of the chip under test to the reverse discharge port (corresponding to the reverse discharge port) of the electrostatic discharge generator according to the seventh configuration signal output by the control unit in the fifth switching mode. Figure 4 ESD_N port) is electrically connected.

[0094] The relay assembly may include at least one relay, and the present application does not impose any specific restrictions on the specific type of the relay assembly. Exemplarily, the port configuration unit may be composed of a relay with five output channels, or the port configuration unit may be composed of a relay with four output channels and a relay with two output channels, or the port configuration unit may be composed of four relays with two output channels, and the present application does not impose any specific restrictions on the type and quantity of the relays in the port configuration unit.

[0095] In practical applications, the control end of the relay component can be connected to the control unit, and the relay component receives various configuration signals output by the control unit through its control end. Since the control end and the output end of the relay are electrically separated, the safety of the port configuration unit is improved.

[0096] The following is an example in which the port configuration unit consists of four relays with two output channels.

[0097] For example, Figure 5 As shown, the port configuration unit 110 is a relay component, and the relay component includes a first relay 1101, a second relay 1102, a third relay 1103 and a fourth relay 1104;

[0098] Among them, the switch contact of the first relay 1101 is connected to the target pin DUT_PIN of the chip to be tested, the first connection end of the first relay 1101 is connected to the switch contact of the second relay 1102, the first connection end of the second relay 1102 is connected to the forward discharge port ESD_P of the electrostatic discharge generator, and the second connection end of the second relay 1102 is connected to the reverse discharge port ESD_N of the electrostatic discharge generator;

[0099] The second connection end of the first relay 1101 is connected to the switch contact of the third relay 1103, the first connection end of the third relay 1102 is in a floating state (corresponding to Floating in the figure), and the second connection end of the third relay 1103 is connected to the switch contact of the fourth relay 1104;

[0100] The first connection end of the fourth relay 1104 is connected to the positive terminal IV_P of the measuring unit, and the second connection end of the fourth relay 1104 is connected to the negative terminal IV_N of the measuring unit.

[0101] exist Figure 5 In the embodiment, the third configuration signal output by the control unit 120 is used to adjust the switch contact of the first relay 1101 to be connected to the second connection end, and the switch contact of the third relay 1103 is connected to the first connection end, thereby realizing the port configuration function, which can make the target pin DUT_PIN of the chip under test to be in a floating state.

[0102] exist Figure 5 In the embodiment, the fourth configuration signal output by the control unit 120 is used to adjust the switch contact of the first relay 1101 to be connected to the second connection terminal, the switch contact of the third relay 1103 to be connected to the second connection terminal, and the switch contact of the fourth relay 1104 to be connected to the first connection terminal, thereby realizing the port configuration function, which can connect the target pin DUT_PIN of the chip under test to the IV_P port of the measurement unit.

[0103] exist Figure 5 In the embodiment, the fifth configuration signal output by the control unit 120 is used to adjust the switch contact of the first relay 1101 to be connected to the second connection terminal, the switch contact of the third relay 1103 to be connected to the second connection terminal, and the switch contact of the fourth relay 1104 to be connected to the second connection terminal, thereby realizing the port configuration function, and enabling the target pin DUT_PIN of the chip to be tested to be connected to the IV_N port of the measurement unit.

[0104] exist Figure 5 In the embodiment, the sixth configuration signal output by the control unit 120 is used to adjust the switch contact of the first relay 1101 to be connected to the first connection end, and the switch contact of the second relay 1102 to be connected to the first connection end, thereby realizing the port configuration function, which can connect the target pin DUT_PIN of the chip under test to the ESD_P port of the electrostatic discharge generator.

[0105] exist Figure 5In the embodiment, the seventh configuration signal output by the control unit 120 is used to adjust the switch contact of the first relay 1101 to be connected to the first connection end, and the switch contact of the second relay 1102 to be connected to the second connection end, thereby realizing the port configuration function, which can connect the target pin DUT_PIN of the chip under test to the ESD_N port of the electrostatic discharge generator.

[0106] In addition, if Figure 3 As shown, in the embodiment of the present application, the third configuration signal, the fourth configuration signal, the fifth configuration signal, the sixth configuration signal or the seventh configuration signal and other configuration signals may be signals generated by the control unit 120 itself, or may be signals received by the control unit 120 (when connected to the host computer through the "control & communication terminal") from the host computer, and the present application does not limit this. Among them, the host computer may be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc., and the non-mobile electronic device may be a server, a network attached storage (NAS), a personal computer (PC), etc., and the embodiment of the present application does not specifically limit this.

[0107] In addition, in the embodiment of the present application, after the electrostatic discharge generator 140 is used to perform an electrostatic discharge test on the chip under test via the target pin DUT_PIN of the chip under test, it is difficult to directly determine whether the chip under test has passed the electrostatic discharge test, and it is also necessary to combine the measurement unit 130 to perform auxiliary judgment on the range of change of the volt-ampere characteristics of the chip under test before and after the electrostatic discharge test.

[0108] In an embodiment of the present application, the measuring unit 130 can be used to measure the volt-ampere characteristics of the chip to be tested, such as testing the voltage under a set current, or testing the current under a set voltage. The present application does not limit the specific testing method.

[0109] For example, the first test signal may include a voltage test signal or a current test signal, and accordingly, the measuring unit 130 may have a voltage measurement function and / or a current measurement function. Figure 7 or Fig. 9In the embodiment, the first test signal may be a voltage test signal, and the control unit 120 is used to output the voltage test signal to the measuring unit 130, so that the measuring unit 130 tests the voltage of the chip under test when determining the preset current of the target pin of the chip under test. Fig.10 or Fig.11 In the embodiment, the first test signal may be a current test signal, and the control unit 120 is used to output the current test signal to the measuring unit 130, so that the measuring unit 130 tests the current of the chip to be tested when determining the preset voltage of the target pin of the chip to be tested.

[0110] Two different volt-ampere characteristic testing methods are described below in conjunction with the specific structure of the measuring unit 130 .

[0111] In a specific embodiment, Figure 6 As shown, in the embodiment of the present application, the measuring unit 130 includes a measuring module 1301 , and the measuring module 1301 is connected to the port configuration unit 110 .

[0112] For example, Figure 7 As shown, the measuring module 1301 may include: a digital-to-analog converter DAC, a first amplifier U1, a second amplifier U2, a third amplifier U3, a first resistor R1 and an analog-to-digital converter ADC;

[0113] The output end of the digital-to-analog converter DAC is connected to the first input end of the first amplifier U1, the second input end of the first amplifier U1 is connected to the output end of the second amplifier U2, the output end of the first amplifier U1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the positive terminal IV_P of the voltage measuring unit, and the negative terminal IV_N of the voltage measuring unit is grounded;

[0114] A first input terminal of the second amplifier U2 is connected to one end of the first resistor R1, and a second input terminal of the second amplifier U2 is connected to the other end of the first resistor R1;

[0115] The first input end of the third amplifier U3 is connected to the positive port IV_P of the voltage measurement unit, the second input end of the third amplifier U3 is connected to the output end of the third amplifier U3, and the output end of the third amplifier U3 is connected to the analog-to-digital converter ADC.

[0116] In the embodiments of the present application, Figure 7The measurement module 1301 shown can be directly used to test the voltage of the chip to be tested when the preset current of the target pin of the chip to be tested is determined. Specifically, in the measurement module 1301, the digital-to-analog converter DAC can be connected to the control unit 120 (not shown in the figure), and the voltage test signal output by the control unit 120 can carry the voltage value information of the first target analog voltage signal V0, and the voltage value V0 of the first target analog voltage signal is calculated by multiplying the preset current i0, the resistance value of the first resistor R1, and the amplification factor A of the second amplifier U2;

[0117] The digital-to-analog converter DAC is used to output a first target analog voltage signal V0;

[0118] The analog-to-digital converter ADC is used to collect a first target voltage V1 as the voltage of the chip to be tested;

[0119] The analog-to-digital converter ADC can be connected to the control unit 120, and the analog-to-digital converter ADC can be used to output the collected first target voltage V1 to the control unit 120, so that the control unit 120 uses the collected first target voltage V1 as the voltage of the chip under test (ie, the test result).

[0120] It can be understood that the digital-to-analog converter DAC is used to convert a digital signal into an analog voltage signal.

[0121] When the reference voltage of the digital-to-analog converter DAC is VREF+, the digital signal input by the control unit 120 is linearly converted into an analog voltage output through the digital-to-analog converter DAC, and the adjustable range of the analog voltage value is 0 to VREF+.

[0122] The second amplifier U2 is used to amplify the current to improve the detection accuracy.

[0123] Among them, the third amplifier U3 forms a follower circuit. The follower circuit can be understood as the output signal follows the input signal, with the same amplitude and phase, and can be regarded as a common-mode amplifier with an amplification factor of 1. The follower circuit has the following advantages: 1. Isolation: The operational amplifier has high input impedance and low output impedance. It shows high impedance to the upper side and low impedance to the lower side. It is often in the middle stage, which can isolate the front and rear circuits and eliminate the influence between them. 2. Impedance matching and improved load carrying capacity: Due to the low impedance of the output program, it can easily achieve matching with the subsequent circuit through a series resistor.

[0124] In the embodiments of the present application, Figure 7The test principle of the voltage of the chip to be tested by the measurement module 1301 shown can be: since the preset current i0, the resistance value of the first resistor R1 and the amplification factor A of the second amplifier U2 are all known, the control unit 120 can calculate the voltage V0 required to be applied to the digital-to-analog converter DAC by the formula V0=i0*R1*A. After that, the digital-to-analog converter DAC outputs the voltage V0, and the current across R1 is the same as the current across IV_P and IV_N. At this time, only the output voltage of the third amplifier U3 needs to be tested to obtain the voltage across the load. Among them, the two ends of the load can be understood as a pair of pins of the chip to be tested connected to the positive port and the negative port of the measurement unit 130. Among them, the analog-to-digital converter ADC can collect the output voltage of the third amplifier U3 (i.e., the first target voltage V1).

[0125] In this way, the measuring module 1301 can test the voltage of the chip under test when determining the preset current i0 of the target pin of the chip under test.

[0126] In practical applications, in order to improve the space utilization of the electrostatic discharge testing equipment 110, the embodiment of the present application can improve the integration of the measuring unit 130, and add a switching module 1302 in the measuring unit 130. The connection relationship of the components in the measuring module 1301 is changed by the switching module 1302, so that the measuring module 1301 can not only test the voltage of the chip to be tested, but also test the current of the chip to be tested.

[0127] For example, Figure 8 As shown, in addition to the measuring module 1301, the measuring unit 130 may further include a switching module 1302, the switching module 1302 is connected to the measuring module 1301, and the switching module 1302 is connected to the control unit 120;

[0128] The first test signal output by the control unit 120 may include a voltage test signal or a current test signal;

[0129] When the control unit 120 outputs a voltage test signal to the measuring unit 130, the switching module 1302 is in a first working state; when the switching module 1302 is in the first working state, the measuring module is used to test the voltage of the chip under test while determining a preset current of a target pin of the chip under test;

[0130] When the control unit 120 outputs a current test signal to the measuring unit 130, the switching module 1302 is in the second working state; when the switching module 1302 is in the second working state, the measuring module 1301 tests the current of the chip to be tested while determining the preset voltage of the target pin of the chip to be tested.

[0131] In this way, Figure 7 On the basis of the measurement module 1301 shown, by adding a switching module 1302, the measurement unit 130 can realize the integration of voltage measurement function and current measurement function, and its components can be reused, thereby improving the integration of the measurement unit, thereby improving the space utilization of the electrostatic discharge test equipment 110, and also expanding the application scope of the measurement unit 130.

[0132] In a specific embodiment, Fig. 9 or Fig.10 In the embodiment, the switching module 1302 includes a fifth relay K5 and a sixth relay K6;

[0133] The second input terminal of the first amplifier U1 is connected to the switch contact of the fifth relay K5, the first connection terminal of the fifth relay K5 is connected to the output terminal of the second amplifier U2, and the second connection terminal of the fifth relay K5 is connected to the positive terminal IV_P of the measuring unit;

[0134] The switch contact of the sixth relay K6 is connected to the first input terminal of the third amplifier U3, the output terminal of the second amplifier U2 is connected to the first connection terminal of the sixth relay K6, and the second connection terminal of the sixth relay K6 is connected to the positive terminal IV_P of the measuring unit.

[0135] like Fig. 9 As shown, when the switching module 1302 is in the first working state, the control unit 120 is used to control the switch contact of the fifth relay K5 to be connected to the first connection end, and the switch contact of the sixth relay K6 to be connected to the second connection end; the measuring unit 130 is used to test the voltage of the chip to be tested.

[0136] Or, if Fig.10 As shown, when the switching module 1302 is in the second working state, the control unit 120 is used to control the switch contact of the fifth relay K5 to be connected to the second connection end, and the switch contact of the sixth relay K6 to be connected to the first connection end; the measuring unit 130 is used to test the current of the chip to be tested.

[0137] Based on this, comparison Fig. 9 and Fig.10 It can be seen that when the switch contact of the fifth relay K5 is switched from the first connection end to the second connection end, and the switch contact of the sixth relay K6 is switched from the second connection end to the first connection end, the function of the measuring unit 130 can be switched from the voltage measurement function to the current measurement function. Alternatively, when the switch contact of the fifth relay K5 is switched from the second connection end to the first connection end, and the switch contact of the sixth relay K6 is switched from the first connection end to the second connection end, the function of the measuring unit 130 can be switched from the current measurement function to the voltage measurement function.

[0138] Of course, in addition to the fifth relay and the sixth relay, the present application may also adopt other structures to form a switching module, and the present application does not limit the specific structure of the switching module.

[0139] In the embodiments of the present application, Figure 8 The measurement unit 130 shown can have two test modes: testing voltage when current is set; or testing current when voltage is set. The embodiment of the present application can select which test mode to adopt according to the actual working requirements of the chip to be tested, and the present application does not impose specific restrictions on this. The principle of the measurement unit 130 testing voltage when current is set and the principle of testing current when voltage is set are described in detail below.

[0140] like Fig. 9 As shown, when the switching module 1302 is in the first working state and the measuring unit 130 tests the voltage under the set current, the digital-to-analog converter DAC is used to output a first target analog voltage signal, and the voltage value of the first target analog voltage signal is obtained by multiplying the preset current, the resistance value of the first resistor R1 and the amplification factor of the second amplifier U2; the analog-to-digital converter ADC is used to collect the first target voltage; and the control unit 120 is used to use the first target voltage as the voltage of the chip to be tested under the preset current condition.

[0141] Understandably, Fig. 9 The principle of the measurement unit 130 testing the voltage of the chip to be tested can be referred to in the above Figure 7 The principle of the measurement module 1301 testing the voltage of the chip to be tested is not described in detail here.

[0142] In addition, if Fig.10 As shown, when the switching module 1302 is in the second working state and the measuring unit 130 tests the current under the condition of setting the voltage, the digital-to-analog converter DAC is used to output the second target analog voltage signal, and the voltage value of the second target analog voltage signal is obtained based on the preset voltage; the analog-to-digital converter ADC is used to collect the second target voltage, and the second target voltage is used to characterize the product of the current of the chip to be tested, the resistance value of the first resistor R1, and the amplification factor of the second amplifier U2;

[0143] The control unit 120 is used to determine the current of the chip under test under a preset voltage condition based on the second target voltage collected by the analog-to-digital converter ADC, the resistance value of the first resistor R1, and the amplification factor of the second amplifier U2.

[0144] For example, in Fig.10In the measurement unit 130 shown, the digital-to-analog converter DAC may be connected to the control unit 120, and the current test signal output by the control unit 120 may carry voltage value information of the second target analog voltage signal, where the voltage value of the second target analog voltage signal is obtained based on the preset voltage;

[0145] The digital-to-analog converter DAC may be used to output a second target analog voltage signal;

[0146] The analog-to-digital converter ADC may be used to collect a second target voltage V2, where the second target voltage V2 is used to represent the product of the current i of the chip under test, the resistance value of the first resistor R1, and the amplification factor A of the second amplifier;

[0147] The control unit 120 is configured to determine the current i of the chip under test based on the second target voltage V2 acquired by the analog-to-digital converter ADC, the resistance value R1 of the first resistor, and the amplification factor A of the second amplifier.

[0148] In the embodiment of the present application, the principle of the test current of the measuring unit 130 can be: a preset fixed voltage (i.e., the second target analog voltage signal) is output through the digital-to-analog converter DAC, and the set fixed voltage is applied to IV_P through the negative feedback loop formed by the U1 amplifier. At this time, the current flowing through R1 is equivalent to the load current at both ends of IV_P and IV_N. U2 is an instrument amplifier, and its output end is connected to the U3 amplifier to form a follower circuit. The final output voltage V2 is measured by the ADC. According to the calculation formula V2=i*R1*A of this circuit, combined with the known amplification factor (A) of U2 and the value of R1, the IV_P and IV_N load current i can be obtained. Among them, the load can be understood as the chip to be tested.

[0149] The second amplifier U2 is used to amplify the current to improve the detection accuracy.

[0150] Among them, the U3 amplifier forms a follower circuit. The follower circuit can be understood as the output signal follows the input signal, with the same amplitude and phase, and can be regarded as a common-mode amplifier with an amplification factor of 1. The follower circuit has the following advantages: 1. Isolation: The op amp input has high impedance, the output has low impedance, it shows high impedance to the upper side, and low impedance to the lower side, and is often in the middle stage, which can isolate the front and rear circuits and eliminate the influence between them. 2. Impedance matching, improving load carrying capacity: Due to the low impedance of the output program, it can easily achieve matching with the subsequent circuit through a series resistor.

[0151] In this way, the measuring unit 130 tests the current i of the chip under test while determining the preset voltage of the target pin of the chip under test.

[0152] In another specific embodiment, when the measuring unit 130 tests the current under the condition of setting the voltage, the measuring unit 130 may also be composed of other structures. Fig.11 As shown, in the embodiment of the present application, the measuring unit 130 may include: a digital-to-analog converter DAC, a first amplifier U1, a second amplifier U2, a third amplifier U3, a first resistor R1 and an analog-to-digital converter ADC;

[0153] The output end of the digital-to-analog converter DAC is connected to the first input end of the first amplifier U1, the second input end of the first amplifier U1 is connected to the positive port IV_P of the voltage measuring unit, the output end of the first amplifier U1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the positive port IV_P of the voltage measuring unit, and the negative port IV_N of the voltage measuring unit is grounded;

[0154] A first input end of a second amplifier U2 is connected to one end of the first resistor R1, a second input end of the second amplifier U2 is connected to the other end of the first resistor R1, and an output end of the second amplifier U2 is connected to a first input end of the third amplifier U3;

[0155] The second input end of the third amplifier U3 is connected to the output end of the third amplifier U3 , and the output end of the third amplifier U3 is connected to the analog-to-digital converter ADC.

[0156] Understandably, Fig.11 The principle of the measurement unit 130 for testing the current of the chip to be tested can be referred to in the above Fig.10 The principle of the measuring unit 130 testing the current of the chip under test is not described here in detail. In this way, the measuring unit 130 tests the current i of the chip under test when determining the preset voltage of the target pin of the chip under test.

[0157] Based on the same concept as the above-mentioned electrostatic discharge testing equipment embodiment, the embodiment of the present application also provides an electrostatic discharge testing method.

[0158] like Fig.12 As shown, the present application provides an electrostatic discharge testing method, which is applied to the electrostatic discharge testing device provided in any of the above embodiments, and may include:

[0159] Step 1210: The control unit outputs a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip under test to be electrically connected to the measurement unit; when the target pin of the chip under test is electrically connected to the measurement unit, the control unit outputs a first test signal to the measurement unit, so that the measurement unit tests the electrical signal of the chip under test to obtain a first test result;

[0160] Step 1220: the control unit outputs a second configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip under test to be electrically connected to the electrostatic discharge generator; when the target pin of the chip under test is electrically connected to the electrostatic discharge generator, the control unit outputs a second test signal to the electrostatic discharge generator, so that the electrostatic discharge generator performs an electrostatic discharge test on the chip under test under specified test conditions;

[0161] Step 1230: After performing an electrostatic discharge test on the chip under test, the control unit outputs a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip under test to be electrically connected to the measurement unit; when the target pin of the chip under test is electrically connected to the measurement unit, the control unit again outputs the first test signal to the measurement unit, so that the measurement unit again tests the electrical signal of the chip under test to obtain a second test result;

[0162] Step 1240: Based on the first test result and the second test result, determine whether the chip under test passes the electrostatic discharge test under specified test conditions.

[0163] The first test result is obtained before the electrostatic discharge test is performed on the chip to be tested, and the second test result is obtained after the electrostatic discharge test is performed on the chip to be tested. The electrical signal of the chip to be tested can be voltage or current. When the first test result is a voltage result, the second test result is also a voltage result. When the first test result is a current result, the second test result is also a current result. In this way, the test dimensions of the first test result and the second test result are the same, which facilitates the subsequent determination of whether the chip to be tested passes the electrostatic discharge test based on the degree of difference between the first test result and the second test result.

[0164] In the embodiment of the present application, Figure 3 The electrostatic discharge test equipment shown in the figure is used as an example to illustrate the Figure 3In the present invention, the control unit 120 can be packaged into a chip, and the other parts in the electrostatic discharge test device can be circuit parts set on the PCB board. The electrostatic discharge test device 100 can be connected to a personal computer through the "control & communication terminal" and configured and used through the test software in the personal computer. Alternatively, the electrostatic discharge test device 100 can be used to directly load the test software into the control unit 120, and only the electrostatic discharge test device 100 is used for testing, and this application does not make specific restrictions on this.

[0165] exist Figure 3 In the present invention, each port configuration unit of the electrostatic discharge test equipment is connected to each pin of the chip one by one, and then the electrostatic discharge test equipment can test each pin of a chip in turn. Fig.13 A schematic diagram of a test interface displayed by a display component of a personal computer or electrostatic discharge test equipment, such as Fig.13 As shown, the user can set the port name and port type of each port configuration unit, and then connect each port configuration unit to each pin of the chip to be tested one by one.

[0166] exist Figure 3 In the embodiment, port configuration units 1 to N are connected to target pins 1 to N of the chip to be tested respectively and one by one. The connection relationship of the target pins can be controlled by the control unit, and each target pin can be selected to be connected to an electrostatic discharge generator, a measurement unit or floating.

[0167] Among them, the target pin DUT_PIN is not connected to any signal in the floating state.

[0168] The electrostatic discharge generator 140 is mainly used to generate electrostatic pulses that meet the standards, and the control unit 120 can configure the specified test conditions and control the triggering of the electrostatic discharge test through the communication port.

[0169] The ESD generator 140 connects to a pair of target pins DUT_PIN of the chip under test at one time through its forward discharge port ESD_P and reverse discharge port ESD_N. When the ESD generator 140 performs an ESD test on the connected pair of target pins DUT_PIN, the remaining target pins of the chip under test are in a floating state.

[0170] Among them, the measuring unit 130 is mainly used to measure the load current by adding a set voltage, or to test the load voltage by adding a set current. The control unit 130 can control the execution of the corresponding electrical signal test, and determine whether the chip under test passes the electrostatic discharge test through the test value.

[0171] The measuring unit 130 connects to a pair of target pins DUT_PIN of the chip under test through its positive port IV_P and negative port IV_N at one time. When the measuring unit 130 tests the current or voltage of the connected pair of target pins DUT_PIN, the other target pins of the chip under test are in a floating state.

[0172] In this way, when it is necessary to test the electrical signal of the chip to be tested, the port configuration unit can control the target pin of the chip to be tested to be electrically connected to the measurement unit, so that the measurement unit can be used to test the electrical signal. When it is necessary to perform an electrostatic discharge test on the chip to be tested, the port configuration unit can control the target pin of the chip to be tested to be electrically connected to the electrostatic discharge generator, so that the electrostatic discharge test can be performed using the electrostatic discharge generator. Compared with the related technology, the electrostatic discharge testing equipment can realize the integration of electrostatic discharge testing and electrical signal testing. Moreover, since the port configuration unit is used to configure the connection relationship between the target pin of the chip to be tested and the measurement unit and the electrostatic discharge generator, there is no need to frequently plug and unplug the target pin of the chip to be tested, thereby improving the testing efficiency.

[0173] In a specific embodiment, in the above step 1240, determining whether the chip under test passes the electrostatic discharge test under specified test conditions based on the first test result and the second test result includes:

[0174] When the absolute value of the difference between the first test result and the second test result is less than or equal to a first critical value, or the ratio between the first test result and the second test result is less than or equal to a second critical value, it is determined that the chip under test passes the electrostatic discharge test under the specified test conditions;

[0175] When the absolute value of the difference between the first test result and the second test result is greater than a first critical value, or the ratio between the first test result and the second test result is greater than a second critical value, it is determined that the chip under test fails the electrostatic discharge test under specified test conditions.

[0176] Among them, the first critical value / the second critical value can be set according to actual needs, and this application does not make any specific limitations on this.

[0177] In step 1220, the specified test condition may include at least one of a test voltage value, an electrostatic discharge test mode, and a test direction.

[0178] The test voltage value represents the electrostatic pulse voltage value generated by the electrostatic discharge generator.

[0179] The electrostatic discharge test mode may include a human body electrostatic discharge mode or a machine electrostatic discharge mode.

[0180] The test direction may include forward discharge or reverse discharge.

[0181] In practical applications, in scenarios where multiple consecutive tests are required, the specified test conditions may also include a test voltage starting value, a test voltage interval, and a test number, etc., which are not specifically limited in this application. Fig.13 As shown, the test voltage interval can be expressed as an ESD voltage test step, and the voltage starting value and the number of tests are not shown in the figure.

[0182] Based on this, in another specific embodiment, after step 1240, the electrostatic discharge test provided by the embodiment of the present application may further include:

[0183] When it is determined that the chip under test passes the electrostatic discharge test under the specified test condition of the first test voltage value, the first test voltage value is replaced with a second test voltage value;

[0184] When the designated test condition is a second test voltage value, an electrostatic discharge test is performed on the chip to be tested, and an electrical signal of the chip to be tested is tested to obtain a third test result;

[0185] Based on the first test result and the third test result, it is determined whether the chip under test passes the electrostatic discharge test when the specified test condition is a second test voltage value.

[0186] The second test voltage value is greater than the first test voltage value. The difference between the second test voltage value and the first test voltage value may be a preset test voltage interval.

[0187] In this way, if the electrostatic discharge test is passed under the current electrostatic pulse voltage value test conditions, it is necessary to further increase the test voltage value to repeatedly perform the electrostatic discharge test and IV judgment until the electrostatic discharge test fails. The maximum value of the multiple electrostatic pulse voltage values ​​that pass the electrostatic discharge test is determined as the anti-static voltage value of the chip to be tested.

[0188] In practical applications, such as Fig.14 As shown, the embodiment of the present application provides an electrostatic discharge test method, which can test each pin of a chip to be tested in sequence. The test process may include:

[0189] Place the chip and name the port: Select the chip to be tested, place the chip, and define the chip pin name and pin type in the test software. The pin types include: negative power pin, positive power pin, and non-power pin.

[0190] Port configuration DUT connection, test IV initial value (traversal): Select the negative power pin and connect it to the IV_P port through the port configuration unit, then select any other pins to connect to the IV_N port, and configure the remaining pins to float, switch the test unit to the set current test voltage mode (generally based on the test voltage at 1uA current), and test and record the voltage values ​​respectively. Similarly, connect the positive power pin to the IV_N port through the port configuration unit, then select any other pins to connect to the IV_P port, and test and record the voltage values. The voltage values ​​recorded here are all the initial values ​​before recording the electrostatic discharge test, which are used as the standard for judging voltage changes.

[0191] Configure the ESD generator: Configure the ESD pulse test conditions, such as the ESD test mode (human or machine mode), the number of tests and intervals, the test direction (forward or reverse), and the test voltage starting value, through the communication port between the control unit and the ESD generator.

[0192] Port configuration DUT connection, electrostatic test trigger (traversal): Test trigger refers to controlling the charging and discharging behavior of the ESD generator through the control unit, which is used for electrostatic discharge testing of the chip to be tested.

[0193] Among them, the ESD test standard includes three test connection methods: any pin to the negative power supply, any pin to the positive power supply, and any pin among non-power pins to the remaining non-power pins.

[0194] Among them, any pin to the negative power supply can be understood as: select the negative power supply pin and connect it to the ESD_N port through the port configuration unit, then select any pin to connect to the ESD_P port, and the remaining pins are configured to float, and the test trigger is controlled to complete the test.

[0195] Among them, any pin to the positive power supply can be understood as: select the positive power supply pin and connect it to the ESD_P port through the port configuration unit, then select any pin to connect to the ESD_N port, and configure the remaining pins to float, and control the test trigger to complete the test.

[0196] Among them, any pin among the non-power pins can be understood as: select any non-power pin and connect it to the ESD_P port through the port configuration unit, and then select the remaining non-power pins to be configured as the ESD_N port, and the positive and negative power pins are configured as floating, and the control test trigger completes the test.

[0197] Test IV judgment: The control method is the same as the IV test initial value. The test records all values ​​and determines whether the corresponding value exceeds ±30% compared with the initial value. If the changes are all within the range, it is determined that the chip under test has passed the electrostatic discharge test. If any value exceeds the range, it is determined that the chip under test has failed the electrostatic discharge test.

[0198] Increase the trigger value: If the electrostatic discharge test is passed under the current electrostatic pulse voltage value, it is necessary to further increase the test voltage value to repeatedly perform the electrostatic discharge test and IV judgment until the electrostatic discharge test fails. Then the anti-static voltage value of the chip to be tested can be recorded.

[0199] In the embodiment of the present application, for each pair of pins of the chip to be tested, generally after the initial IV test, ESD test and IV test, combined with the change of IV test results before and after the ESD test, it is determined whether the chip to be tested has passed the electrostatic discharge test. In the case of passing the electrostatic discharge test, the test voltage value of the ESD test can be further increased, and the ESD test and IV determination are repeated until it is determined that the ESD test cannot be passed, so as to determine the antistatic voltage value of the chip to be tested.

[0200] In this way, when switching from ESD testing to IV testing, or vice versa, there is no need to frequently plug and unplug chip pins. Only the port configuration unit needs to reconfigure the connection relationship of the chip pins, thereby improving test efficiency.

[0201] In addition, when testing all the pins of the chip to be tested, the port configuration unit configures a pair of pins to be connected to the test unit / ESD generator, and configures the remaining chip pins to be floating. Then, the test of a pair of pins is completed at a time, and the test of all the pins of the chip to be tested is completed in sequence. This process does not require frequent plugging and unplugging of chip pins, which improves the test efficiency.

[0202] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0203] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0204] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. An electrostatic discharge test device, characterized in that: include: A port configuration unit (110), a control unit (120), a measurement unit (130) connected to the control unit, and an electrostatic discharge generator (140) connected to the control unit; The port configuration unit (110) has an input end, a first output end, a second output end and a control end; the input end of the port configuration unit (110) is connected to a target pin of a chip to be tested; the first output end of the port configuration unit (110) is connected to the measurement unit (130); the second output end of the port configuration unit (110) is connected to the electrostatic discharge generator (140); and the control end of the port configuration unit (110) is connected to the control unit (120); The control unit (120) is used to output a first configuration signal to the port configuration unit (110), so that the port configuration unit (110) controls the target pin of the chip to be tested to be electrically connected to the measurement unit (130); The control unit (120) is used to output a second configuration signal to the port configuration unit (110), so that the port configuration unit (110) controls the target pin of the chip to be tested to be electrically connected to the electrostatic discharge generator (140); The measuring unit (130) is used to test the electrical signal of the chip to be tested; The electrostatic discharge generator (140) is used to perform an electrostatic discharge test on the chip to be tested.

2. The electrostatic discharge testing device according to claim 1, characterized in that: When the target pin of the chip to be tested is electrically connected to the measuring unit (130), the control unit (120) is used to output a first test signal to the measuring unit (130), so that the measuring unit (130) tests the electrical signal of the chip to be tested; When the target pin of the chip to be tested is electrically connected to the electrostatic discharge generator (140), the control unit (120) is used to output a second test signal to the electrostatic discharge generator (140), so that the electrostatic discharge generator (140) performs an electrostatic discharge test on the chip to be tested.

3. The electrostatic discharge testing device according to claim 1, characterized in that: The port configuration units (110) include N port configuration units (110), and the input end of each port configuration unit (110) in the N port configuration units (110) is connected to each target pin of the chip to be tested in a one-to-one correspondence, and N is a positive integer greater than 1.

4. The electrostatic discharge testing device according to any one of claims 1 to 3, characterized in that: The control unit (120) is further used to output a third configuration signal to the port configuration unit (110), so that the port configuration unit (110) controls the target pin of the chip to be tested to be in a floating state; The first configuration signal includes at least one of a fourth configuration signal and a fifth configuration signal; The control unit (120) is used to output a fourth configuration signal to the port configuration unit (110), so that the port configuration unit (110) controls the target pin of the chip to be tested to be electrically connected to the positive port (IV_P) of the measurement unit; The control unit (120) is used to output a fifth configuration signal to the port configuration unit (110), so that the port configuration unit (110) controls the target pin of the chip to be tested to be electrically connected to the negative port (IV_N) of the measurement unit; The second configuration signal includes at least one of a sixth configuration signal and a seventh configuration signal; The control unit (120) is used to output a sixth configuration signal to the port configuration unit (110), so that the port configuration unit (110) controls the target pin of the chip to be tested to be electrically connected to the forward discharge port (ESD_P) of the electrostatic discharge generator; The control unit (120) is used to output a seventh configuration signal to the port configuration unit (110), so that the port configuration unit (110) controls the target pin of the chip to be tested to be electrically connected to the reverse discharge port (ESD_N) of the electrostatic discharge generator.

5. The electrostatic discharge testing device according to any one of claims 1 to 3, characterized in that: The port configuration unit (110) is a relay component; The relay assembly has five switching modes; The relay component is used to switch the target pin of the chip to be tested to a floating state according to a third configuration signal output by the control unit in the first switching mode; The relay assembly is used to switch the target pin of the chip to be tested to be electrically connected to the positive port of the measuring unit according to a fourth configuration signal output by the control unit in the second switching mode; The relay assembly is used to switch the target pin of the chip to be tested to be electrically connected to the negative port of the measuring unit according to the fifth configuration signal output by the control unit in the third switching mode; The relay assembly is used to switch the target pin of the chip under test to be electrically connected to the forward discharge port of the electrostatic discharge generator according to the sixth configuration signal output by the control unit in the fourth switching mode; The relay component is used to switch the target pin of the chip under test to be electrically connected to the reverse discharge port of the electrostatic discharge generator according to the seventh configuration signal output by the control unit in the fifth switching mode.

6. The electrostatic discharge testing device according to claim 5, characterized in that: The relay assembly comprises a first relay (1101), a second relay (1102), a third relay (1103) and a fourth relay (1104); The switch contact of the first relay (1101) is connected to the target pin (DUT_PIN) of the chip under test, the first connection end of the first relay (1101) is connected to the switch contact of the second relay (1102), the first connection end of the second relay (1102) is connected to the forward discharge port (ESD_P) of the electrostatic discharge generator, and the second connection end of the second relay (1102) is connected to the reverse discharge port (ESD_N) of the electrostatic discharge generator; The second connection end of the first relay (1101) is connected to the switch contact of the third relay (1103), the first connection end of the third relay (1103) is in a floating state, and the second connection end of the third relay (1103) is connected to the switch contact of the fourth relay (1104); The first connection end of the fourth relay (1104) is connected to the positive terminal (IV_P) of the measuring unit, and the second connection end of the fourth relay (1104) is connected to the negative terminal (IV_N) of the measuring unit.

7. The electrostatic discharge testing device according to any one of claims 1 to 3, characterized in that: The measuring unit (130) comprises a measuring module (1301), the measuring module (1301) is connected to the port configuration unit (110), and the measuring module (1301) comprises a digital-to-analog converter (DAC), a first amplifier (U1), a second amplifier (U2), a third amplifier (U3), a first resistor (R1) and an analog-to-digital converter (ADC); The output end of the digital-to-analog converter (DAC) is connected to the first input end of the first amplifier (U1), the second input end of the first amplifier (U1) is connected to the output end of the second amplifier (U2), the output end of the first amplifier (U1) is connected to one end of the first resistor (R1), the other end of the first resistor (R1) is connected to the positive port (IV_P) of the measuring unit, and the negative port (IV_N) of the measuring unit is grounded; A first input end of the second amplifier (U2) is connected to one end of the first resistor (R1), and a second input end of the second amplifier (U2) is connected to the other end of the first resistor (R1); The first input end of the third amplifier (U3) is connected to the positive port (IV_P) of the measuring unit, the second input end of the third amplifier (U3) is connected to the output end of the third amplifier (U3), and the output end of the third amplifier (U3) is connected to the analog-to-digital converter (ADC).

8. The electrostatic discharge testing device according to claim 7, characterized in that: The measuring unit (130) further comprises a switching module (1302), wherein the switching module (1302) is connected to the measuring module (1301), and the switching module (1302) is connected to the control unit (120); The first test signal output by the control unit (120) includes a voltage test signal or a current test signal; When the control unit (120) outputs a voltage test signal to the measuring unit (130), the switching module (1302) is in a first working state; when the switching module (1302) is in the first working state, the measuring module is used to test the voltage of the chip under test while determining a preset current of a target pin of the chip under test; When the control unit (120) outputs a current test signal to the measuring unit (130), the switching module (1302) is in a second working state; when the switching module (1302) is in the second working state, the measuring module (1301) tests the current of the chip to be tested while determining a preset voltage of a target pin of the chip to be tested.

9. The electrostatic discharge testing device according to claim 8, characterized in that: The switching module (1302) includes a fifth relay (K5) and a sixth relay (K6); The second input end of the first amplifier (U1) is connected to the switch contact of the fifth relay (K5), the first connection end of the fifth relay (K5) is connected to the output end of the second amplifier (U2), and the second connection end of the fifth relay (K5) is connected to the positive terminal (IV_P) of the measuring unit; The switch contact of the sixth relay (K6) is connected to the first input end of the third amplifier (U3), the output end of the second amplifier (U2) is connected to the first connection end of the sixth relay (K6), and the second connection end of the sixth relay (K6) is connected to the positive port (IV_P) of the measuring unit.

10. The electrostatic discharge testing device according to claim 9, characterized in that: When the switching module (1302) is in a first working state, the control unit (120) is used to control the switch contact of the fifth relay (K5) to be connected to the first connection end, and the switch contact of the sixth relay (K6) to be connected to the second connection end; the measuring unit (130) is used to test the voltage of the chip to be tested; Alternatively, when the switching module (1302) is in the second working state, the control unit (120) is used to control the switch contact of the fifth relay (K5) to be connected to the second connection end, and the switch contact of the sixth relay (K6) to be connected to the first connection end; and the measuring unit (130) is used to test the current of the chip to be tested.

11. The electrostatic discharge testing device according to claim 9, characterized in that: When the switching module is in a first working state: the digital-to-analog converter (DAC) is used to output a first target analog voltage signal, the voltage value of the first target analog voltage signal is calculated by multiplying a preset current, the resistance value of the first resistor (R1) and the amplification factor of the second amplifier (U2); the analog-to-digital converter (ADC) is used to collect the first target voltage; The control unit (120) is used to use the first target voltage as the voltage of the chip to be tested under a preset current condition.

12. The electrostatic discharge testing device according to claim 9, characterized in that: When the switching module is in the second working state: the digital-to-analog converter (DAC) is used to output a second target analog voltage signal, and the voltage value of the second target analog voltage signal is obtained based on the preset voltage; The analog-to-digital converter (ADC) is used to collect a second target voltage, and the second target voltage is used to represent the product of the current of the chip to be tested, the resistance value of the first resistor (R1), and the amplification factor of the second amplifier (U2); The control unit (120) is used to determine the current of the chip to be tested under preset voltage conditions based on the second target voltage collected by the analog-to-digital converter (ADC), the resistance value of the first resistor (R1), and the amplification factor of the second amplifier (U2).

13. An electrostatic discharge testing method, applied to the electrostatic discharge testing device according to any one of claims 1 to 12, characterized in that: include: The control unit outputs a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip to be tested to be electrically connected to the measurement unit; when the target pin of the chip to be tested is electrically connected to the measurement unit, the control unit outputs a first test signal to the measurement unit, so that the measurement unit tests the electrical signal of the chip to be tested and obtains a first test result; The control unit outputs a second configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip under test to be electrically connected to the electrostatic discharge generator; when the target pin of the chip under test is electrically connected to the electrostatic discharge generator, the control unit outputs a second test signal to the electrostatic discharge generator, so that the electrostatic discharge generator performs an electrostatic discharge test on the chip under test under specified test conditions; After the electrostatic discharge test is performed on the chip under test, the control unit outputs a first configuration signal to the port configuration unit, so that the port configuration unit controls the target pin of the chip under test to be electrically connected to the measurement unit; when the target pin of the chip under test is electrically connected to the measurement unit, the control unit again outputs the first test signal to the measurement unit, so that the measurement unit again tests the electrical signal of the chip under test to obtain a second test result; Based on the first test result and the second test result, it is determined whether the chip to be tested passes the electrostatic discharge test under specified test conditions.

14. The electrostatic discharge testing device according to claim 13, characterized in that: Determining whether the chip under test passes the electrostatic discharge test under specified test conditions based on the first test result and the second test result includes: When the absolute value of the difference between the first test result and the second test result is less than or equal to a first critical value, or the ratio between the first test result and the second test result is less than or equal to a second critical value, it is determined that the chip under test passes the electrostatic discharge test under the specified test conditions; When the absolute value of the difference between the first test result and the second test result is greater than a first critical value, or the ratio between the first test result and the second test result is greater than a second critical value, it is determined that the chip under test fails the electrostatic discharge test under specified test conditions.

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