Metal structure of power device and manufacturing method thereof

Abstract

The invention discloses a metal structure of a power device, which is formed on the surface of a bottom layer structure, and at least in a first region, the metal structure comprises a first superposed structure formed by superposing n layers of metal sub-layers, and n is an integer greater than or equal to 2. And the structure of the edge region of the first superposition structure comprises that each metal sub-layer is provided with an etching step. The etching step of the (k + 1) th metal sub-layer is positioned on the outer side of the etching step of the kth metal sub-layer; the height of the etching step of each metal sub-layer is determined by the thickness of each metal sub-layer; and the etching step of the kth metal sub-layer is covered by the (k + 1) th metal sub-layer, and a deposition step of the (k + 1) th metal sub-layer is formed at the top of the etching step of the kth metal sub-layer. The invention further discloses a manufacturing method of the metal structure of the power device. According to the invention, the thickness of the metal structure can be increased, so that the parasitic resistance of metal interconnection can be reduced, and the junction temperature of the device can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a metal structure of a power device; the present invention also relates to a method for manufacturing the metal structure of a power device. Background Art

[0002] like Figure 1 , which is a schematic structural diagram of a metal structure of an existing power device; the metal structure of the existing power device is formed on the surface of the underlying structure 101 .

[0003] The power device is formed in the underlying structure 101 , and the electrodes of the power device are formed by a metal structure.

[0004] Power devices usually adopt a vertical structure with three pins, namely the gate, source and drain. The drain is led out through the back of the chip, and the front is the gate and source of the chip, so the source and gate are formed by metal structures. The higher the current that the power device needs to withstand, the more primitive cells it needs to connect in parallel. The metal connection of the device is to connect the source and gate of these primitive cells together in the chip. Current power devices usually use a layer of thick metal. Figure 1 In the figure, the gate electrode is composed of a metal pattern 9a, and the source electrode is composed of a metal pattern 9b. The metal structure includes metal patterns 9a and 9b, and the metal patterns 9a and 9b are formed by patterning and etching the same metal layer. Usually, it is hoped that the thickness of the metal layer of the metal structure is thicker, but the thickness of the metal layer is usually 3μm to 5μm, and it becomes very difficult to further increase its thickness in terms of process. Because the thicker the metal layer, the more difficult it is to control the deposition process and etching process of the metal layer. Therefore, due to the limitations of the deposition process and etching process of the metal layer, the thickness of the metal layer cannot be further increased, and can only be 3μm to 5μm.

[0005] like Figure 1 As shown, the power device includes an active region. The primitive cell of the power device, i.e., the device unit structure, is formed in the active region. The power device includes a trench MOSFET, an SGT MOSFET, and an IGBT. The power device is further described below using an N-type trench MOSFET as an example. The power device includes:

[0006] The semiconductor substrate 1 is a heavily N-type doped semiconductor substrate 1, and the semiconductor substrate 1 includes a silicon substrate. Generally, the semiconductor substrate 1 will be used as a drain region after being thinned, so the lower the resistivity of the semiconductor substrate 1, the better. Currently, the resistivity of the silicon substrate can be less than 1 mΩ*cm, and the thickness of the silicon substrate can be less than 50 μm.

[0007] A drift region 2 composed of an N-type epitaxial layer is formed on the front surface of the semiconductor substrate 3 .

[0008] A P-type doped channel region 3 is formed on the surface of the drift region 2 .

[0009] The trench gate includes a gate dielectric layer 4 and a gate conductive material layer 5 formed on the inner surface of the gate trench. The gate trench passes through the channel region 3 vertically.

[0010] The source region 6 is self-aligned to the surface of the channel region 3 formed on both sides of the trench gate in the active region.

[0011] A dielectric layer 8 is also formed on the front surface of the semiconductor substrate 3 .

[0012] Corresponding through holes 7 are formed on the top of the source region 6 and the gate conductive material layer 5 . The bottom of the through hole 7 on the top of the source region 6 is also in contact with the channel region 3 .

[0013] A P+ contact region is usually formed at the bottom of the through hole 7 to form a better ohmic contact between the through hole 7 and the channel region 3 at the bottom. The implanted impurity in the P+ contact region is usually BF2, the implanted energy is usually 15-40keV, and the dose is usually 1e14-5e15cm -3 between.

[0014] The source region 6 contacts the metal pattern 9a of the top metal structure through the through hole 7, and the metal pattern 9a serves as the source metal of the power device.

[0015] in and Figure 1 At different cross sections, the gate conductive material layer 5 will contact the metal pattern 9b through the through hole 7 (not shown) at the top, and the metal pattern 9b serves as the gate metal of the power device. The metal pattern 9b is located in the gate lead-out region.

[0016] The gate metal brings together the gate conductive material layer 5 of all the primitive cells through metal wiring, and connects to the outside world through the opening on the gate metal; the source metal brings together the source region 6 of all the primitive cells through metal wiring, and connects to the outside world through the opening on the source metal. The dielectric layer 8 is used to isolate the metal from the silicon below. Summary of the invention

[0017] The technical problem to be solved by the present invention is to provide a metal structure of a power device, which can increase the thickness of the metal structure, thereby reducing the parasitic resistance of the metal interconnection and the junction temperature of the device. To this end, the present invention also provides a method for manufacturing the metal structure of a power device.

[0018] To solve the above technical problems, the metal structure of the power device provided by the present invention is formed on the surface of the underlying structure; at least in the first area, the metal structure includes a first superimposed structure formed by the superposition of n metal sublayers, where n is an integer greater than or equal to 2.

[0019] The structure of the edge region of the first stacked structure includes:

[0020] Each of the metal sub-layers has an etching step.

[0021] The etching step of the k+1th metal sublayer is located outside the etching step of the kth metal sublayer, the height of the etching step of the kth metal sublayer is determined by the thickness of the kth metal sublayer, and the height of the etching step of the k+1th metal sublayer is determined by the thickness of the k+1th metal sublayer, 1≤k≤n-1;

[0022] The etching step of the k-th metal sub-layer is covered by the k+1-th metal sub-layer and a deposition step of the k+1-th metal sub-layer is formed on the top of the etching step of the k-th metal sub-layer.

[0023] A further improvement is that when k is greater than or equal to 2, the etching step of the kth metal sublayer has a deposition step inside, and a deposition step of the k+1th metal sublayer is formed on the top of the deposition step of the kth metal sublayer.

[0024] Further improvements include:

[0025] In the second region, the metal structure is a second stacked structure formed by stacking m layers of the metal sub-layers, where m is an integer greater than or equal to 1 and less than or equal to n.

[0026] When m is less than n, the metal sublayers of each layer of the second stacked structure are respectively the (n-m+1)th metal sublayer to the nth metal sublayer.

[0027] A further improvement is that the thickness of each metal sublayer is less than or equal to the maximum thickness of the metal process.

[0028] The thickness inside the edge region of the first stacked structure is greater than the maximum thickness of the metal process.

[0029] A further improvement is that the material of each metal sub-layer includes AlSiCu.

[0030] A further improvement is that the thickness of each metal sublayer is 3 microns to 5 microns.

[0031] A further improvement is that the thickness of each metal sublayer is 4 microns.

[0032] A further improvement is that the distance between the etching step of the k+1th metal sublayer and the etching step of the kth metal sublayer is greater than 10 microns or greater than twice the thickness of the kth metal sublayer.

[0033] A further improvement is that, within the edge region of the first stacked structure, a stress relief groove is formed in a selected region of a portion of the metal sublayer.

[0034] A further improvement is that the underlying structure includes a power device formed on a semiconductor substrate, and the power device includes an active region.

[0035] The first region is located in a partial region, the entire region of the active region, or extends to the outside of the active region.

[0036] The second region is located in an electrode lead-out region outside the active region.

[0037] A further improvement is that the power device includes a trench MOSFET, a SGT MOSFET, and an IGBT.

[0038] The power device is a vertical power device or a lateral power device.

[0039] The power device includes a super junction device.

[0040] The material of the semiconductor substrate includes silicon, SiC or GaN.

[0041] To solve the above technical problems, in the method for manufacturing a metal structure of a power device provided by the present invention, the metal structure is formed on the surface of the underlying structure; at least in the first region, the metal structure includes a first stacked structure formed by stacking n metal sublayers, where n is an integer greater than or equal to 2;

[0042] In the first region, the process for forming the metal sub-layers of any two adjacent layers includes:

[0043] A k-th metal deposition process is performed to form a k-th metal sublayer, where 1≤k≤n-1.

[0044] The kth metal patterning etching process is performed to pattern the kth metal sublayer, and an etching step is formed at the edge of the kth metal sublayer; the height of the etching step of the kth metal sublayer is determined by the thickness of the kth metal sublayer.

[0045] A k+1th metal deposition process is performed to form a k+1th metal sublayer, wherein the k+1th metal sublayer completely covers the kth metal sublayer and extends to the outside of the kth metal sublayer, the etching step of the kth metal sublayer is covered by the k+1th metal sublayer and a deposition step of the k+1th metal sublayer is formed on the top of the etching step of the kth metal sublayer.

[0046] A k+1th metal patterning etching process is performed to pattern the k+1th metal sublayer, and an etching step is formed at the edge of the k+1th metal sublayer; in the edge area of ​​the first stacked structure, the etching step of the k+1th metal sublayer is located outside the etching step of the kth metal sublayer; the height of the etching step of the k+1th metal sublayer is determined by the thickness of the k+1th metal sublayer.

[0047] A further improvement is that when k is greater than or equal to 2, the etching step of the kth metal sublayer has a deposition step inside, and a deposition step of the k+1th metal sublayer is formed on the top of the deposition step of the kth metal sublayer.

[0048] Further improvements include:

[0049] In the second region, the metal structure is a second stacked structure formed by stacking m layers of the metal sub-layers, where m is an integer greater than or equal to 1 and less than or equal to n.

[0050] When m is less than n, the metal sublayers of each layer of the second stacked structure are respectively the (n-m+1)th metal sublayer to the nth metal sublayer.

[0051] When 1≤k≤(nm), in the k-th metal patterning etching process, the k-th metal sub-layer in the second region is removed.

[0052] When (n-m+1)≤k≤n, in the k-th metal patterning etching process, a pattern of the k-th metal sub-layer is simultaneously formed in the second region.

[0053] A further improvement is that the thickness of each metal sublayer is less than or equal to the maximum thickness of the metal process.

[0054] The thickness inside the edge region of the first stacked structure is greater than the maximum thickness of the metal process.

[0055] A further improvement is that the material of each metal sub-layer includes AlSiCu.

[0056] A further improvement is that the thickness of each metal sublayer is 3 microns to 5 microns.

[0057] A further improvement is that the distance between the etching step of the k+1th metal sublayer and the etching step of the kth metal sublayer is greater than 10 microns or greater than twice the thickness of the kth metal sublayer.

[0058] Further improvements include:

[0059] When the metal patterning etching process is performed on the selected one or more metal sub-layers, a stress relief groove is formed in a selected area inside the edge area of ​​the first stacked structure.

[0060] A further improvement is that the underlying structure includes a power device formed on a semiconductor substrate, and the power device includes an active region.

[0061] The first region is located in a partial region, the entire region of the active region, or extends to the outside of the active region.

[0062] The second region is located in an electrode lead-out region outside the active region.

[0063] The metal structure of the present invention is formed by stacking multiple metal sublayers. At the same time, at least in the first area, which is usually an area where a thicker metal layer is required, such as an active area of ​​a power device, the stacking relationship between the metal sublayers is a stacking in which the upper metal sublayer completely covers the etching step of the lower metal sublayer. In this way, the etching step height of each metal sublayer is only determined by the thickness of the metal sublayer itself. Relative to the maximum thickness of the first stacking structure formed by the stacking of the metal sublayers of the metal structure, the thickness of each metal sublayer is relatively thin, so the deposition process and etching process of each metal sublayer are easy to implement. A thicker metal structure can be obtained by cyclically performing the deposition and etching processes of the metal sublayers for multiple times. Therefore, the present invention breaks through the limitation of metal processes such as metal deposition and etching processes on the thickness of the metal, and finally increases the thickness of the metal structure. The thicker the metal structure, the smaller the resistance, so the parasitic resistance of the metal interconnection can be reduced; at the same time, the thicker the metal structure, the better the thermal conductivity effect. Therefore, in the present invention, when the metal structure is used as the top metal, it can also form a heat sink, which can reduce the junction temperature of the device during pulse current.

[0064] The multi-layer metal sub-layer structure of the present invention can also realize the process independence of each metal sub-layer, so that stress relief slots can be formed in the selected metal sub-layer, which can reduce stress.

[0065] The metal structure of the present invention can be realized by adjusting the number of cycles of the deposition process and the etching process, so the present invention has the advantages of low process difficulty and wide application range. For example, the metal structure of the present invention can be used as a top metal layer and is applicable to various power devices. It can also be applicable to chips in which power devices and driver ICs are integrated together. According to device type, various power devices include trench MOSFET, SGT MOSFET, IGBT; according to current direction, the power devices include vertical power devices or lateral power devices; according to whether a super junction structure is set in the drift region, the power devices include super junction devices; according to the material of the semiconductor substrate, the power devices include silicon-based, SiC-based or GaN-based devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0067] Figure 1 It is a schematic diagram of the metal structure of an existing power device;

[0068] Figure 2 is a schematic structural diagram of a metal structure of a power device according to a first embodiment of the present invention;

[0069] Figure 3 is a schematic structural diagram of a metal structure of a power device according to a second embodiment of the present invention;

[0070] Figure 4 is a schematic structural diagram of a metal structure of a power device according to a third embodiment of the present invention;

[0071] Figure 5A It is a schematic diagram of the device structure after the first metal deposition process is completed in the method for manufacturing the metal structure of the power device according to the embodiment of the present invention;

[0072] Figure 5B It is a schematic diagram of the device structure after the first metal patterning etching process is completed in the method for manufacturing the metal structure of the power device according to the embodiment of the present invention. DETAILED DESCRIPTION

[0073] like Figure 2 , which is a schematic structural diagram of the metal structure of the power device of the first embodiment of the present invention; the metal structure of the power device of the first embodiment of the present invention is formed on the surface of the underlying structure 201; at least in the first region 202a, the metal structure includes a first superimposed structure 203a formed by the superposition of n metal sublayers, where n is an integer greater than or equal to 2.

[0074] The structure of the edge region of the first stacked structure 203a includes:

[0075] Each metal sub-layer has an etching step.

[0076] The etching step of the k+1th metal sublayer is located outside the etching step of the kth metal sublayer, the height of the etching step of the kth metal sublayer is determined by the thickness of the kth metal sublayer, and the height of the etching step of the k+1th metal sublayer is determined by the thickness of the k+1th metal sublayer, 1≤k≤n-1;

[0077] The etching step of the k-th metal sub-layer is covered by the k+1-th metal sub-layer and a deposition step 205 of the k+1-th metal sub-layer is formed on the top of the etching step of the k-th metal sub-layer.

[0078] In the first embodiment of the present invention, Figure 2 As shown, n is 2, and there are two metal sublayers, namely the first metal sublayer 2031 and the second metal sublayer 2032. The etching steps of the first metal sublayer 2031 are marked with a mark 2041, and the etching steps of the second metal sublayer 2032 are marked with a mark 2042.

[0079] In the first embodiment of the present invention, it further includes:

[0080] In the second region 202b, the metal structure is a second stacked structure 203b formed by stacking m metal sub-layers, where m is an integer greater than or equal to 1 and less than or equal to n.

[0081] When m is less than n, the metal sub-layers of the second stacked structure 203b are respectively the (n-m+1)th metal sub-layer to the nth metal sub-layer.

[0082] like Figure 2 As shown, in the first embodiment of the present invention, m is equal to 1, so the second stacked structure 203 b only includes the second metal sub-layer 2032 .

[0083] In the first embodiment of the present invention, the thickness of each metal sublayer is less than or equal to the maximum thickness of the metal process. In the present application, the maximum thickness of the metal process refers to the maximum metal thickness that can be achieved by a single deposition and a single etching of the metal. Generally, the maximum thickness of the metal process is less than 5 microns. If the metal thickness that can be achieved by a single deposition and a single etching is increased to more than the maximum thickness of the metal process, it is difficult to achieve in terms of technology.

[0084] The thickness inside the edge region of the first stacked structure 203a is greater than the maximum thickness of the metal process. Figure 2 As shown, although the various thicknesses of the first metal sublayer 2031 and the second metal sublayer 2032 are respectively less than the maximum thickness of the metal process, the superimposed thickness of the two is greater than the maximum thickness of the metal process. Therefore, the first embodiment of the present invention can realize a metal structure with a thickness greater than the maximum thickness of the metal process by using the existing metal deposition and etching processes.

[0085] In some embodiments, the material of each metal sub-layer includes AlSiCu. In other embodiments, the material of each metal sub-layer can also be set to different metal materials as needed.

[0086] In some embodiments, the thickness of each metal sub-layer is 3 microns to 5 microns. Preferably, the thickness of each metal sub-layer is 4 microns.

[0087] In some embodiments, the distance between the etching step of the k+1th metal sublayer and the etching step of the kth metal sublayer is greater than 10 microns or greater than twice the thickness of the kth metal sublayer. Figure 2 As shown in d101, d101 is the distance between the etching step 2041 and the etching step 2042.

[0088] In some embodiments, a stress relief groove is formed in a selected area of ​​a portion of the metal sub-layer inside an edge region of the first stacked structure 203 a .

[0089] In the first embodiment of the present invention, the underlying structure 201 includes a power device formed on a semiconductor substrate 301 , and the power device includes an active region.

[0090] The first region 202a is located in the entire region of the active region. In other embodiments, the first region 202a may be located in a partial region of the active region or extend outside the active region.

[0091] The second region 202b is located in the electrode extraction region outside the active region.

[0092] Power devices include trench MOSFET, SGT MOSFET, IGBT.

[0093] The power device is a vertical power device or a lateral power device.

[0094] Power devices include super junction devices.

[0095] The material of the semiconductor substrate 301 includes silicon, SiC or GaN.

[0096] Figure 2 In the first embodiment of the present invention shown, the power device is described by taking a trench MOSFET as an example. The power device is also a vertical power device. The material of the semiconductor substrate 301 is silicon, and no super junction structure is set in the drift region, so it is not a super junction device.

[0097] like Figure 2 As shown, taking N-type devices as an example, the power devices include:

[0098] The N-type heavily doped semiconductor substrate 301 is usually used as a drain region after being thinned.

[0099] A drift region 302 composed of an N-type epitaxial layer is formed on the front surface of the semiconductor substrate 303 .

[0100] A P-type doped channel region 303 is formed on the surface of the drift region 302 .

[0101] The trench gate includes a gate dielectric layer 304 and a gate conductive material layer 305 formed on the inner surface of the gate trench. In some embodiments, the gate dielectric layer 304 is a gate oxide layer, and the gate conductive material layer 305 is a polysilicon gate. The gate trench passes through the channel region 303 vertically.

[0102] The source region 306 is self-aligned to the surface of the channel region 303 formed on both sides of the trench gate in the active region.

[0103] A dielectric layer 308 is also formed on the front surface of the semiconductor substrate 303 .

[0104] A corresponding through hole 307 is formed on the top of the source region 306 and the gate conductive material layer 305 . The bottom of the through hole 307 on the top of the source region 306 is also in contact with the channel region 303 .

[0105] The source region 306 contacts the first stacked structure 203 a in the top metal structure through the through hole 307 , and the first stacked structure 203 a serves as the source metal of the power device.

[0106] in and Figure 2 At different cross sections, the gate conductive material layer 305 contacts the second stacked structure 203b through the through hole 307 (not shown) at the top, and the second stacked structure 203b serves as the gate metal of the power device. The second region 202b serves as a gate lead-out region.

[0107] The metal structure of the first embodiment of the present invention is formed by stacking multiple metal sublayers. At the same time, at least in the first area 202a, usually the first area 202a is an area where a thicker metal layer is required, such as the active area of ​​a power device. The stacking relationship between the metal sublayers is a stacking in which the upper metal sublayer completely covers the etching step of the lower metal sublayer. In this way, the height of the etching step of each metal sublayer is only determined by the thickness of the metal sublayer itself. Compared with the maximum thickness of the first stacked structure 203a formed by the stacking of the metal sublayers of the metal structure, the thickness of each metal sublayer is thinner, so each The deposition process and etching process of the metal sublayer are easy to implement. A thicker metal structure can be obtained by cyclically performing the deposition and etching processes of the metal sublayer for multiple times. Therefore, the first embodiment of the present invention breaks through the limitations of metal processes such as metal deposition and etching processes on the thickness of the metal, and finally increases the thickness of the metal structure. The thicker the metal structure, the smaller the resistance, so the parasitic resistance of the metal interconnection can be reduced; at the same time, the thicker the metal structure, the better the thermal conductivity. Therefore, in the first embodiment of the present invention, when the metal structure is used as the top metal, it can also form a heat sink, which can reduce the junction temperature of the device during pulse current.

[0108] The multi-layer metal sub-layer structure of the first embodiment of the present invention can also realize independent process of each metal sub-layer, so that stress relief slots can be formed in the selected metal sub-layer, which can reduce stress.

[0109] The metal structure of the first embodiment of the present invention can be realized by adjusting the number of cycles of the deposition process and the etching process, so the first embodiment of the present invention has the advantages of low process difficulty and wide application range. For example, the metal structure of the present invention can be used as a top metal layer and is applicable to various power devices. It can also be applicable to chips in which power devices and driver ICs are integrated together. According to device type, various power devices include trench MOSFET, SGT MOSFET, IGBT; according to current direction, power devices include vertical power devices or lateral power devices; according to whether a super junction structure is set in the drift region, power devices include super junction devices; according to the material of the semiconductor substrate 301, power devices include silicon-based, SiC-based or GaN-based devices.

[0110] like Figure 3 , which is a schematic diagram of the metal structure of a power device according to a second embodiment of the present invention; and Figure 2 The difference between the power device of the first embodiment of the present invention shown is that in the power device of the second embodiment of the present invention, the number of metal sublayers of the second stacking structure 203b is the same as that of the first stacking structure 203a, that is, both are composed of a first metal sublayer 2031 and a second metal sublayer 2032 stacked together.

[0111] like Figure 4 , which is a schematic structural diagram of a metal structure of a power device according to a third embodiment of the present invention; and Figure 2 The difference between the power device of the first embodiment of the present invention shown is that in the power device of the third embodiment of the present invention, the first stacking structure 203a is formed by stacking three metal sublayers, that is, a third metal sublayer 2033 is added on the basis of the first metal sublayer 2031 and the second metal sublayer 2032.

[0112] In the third embodiment of the present invention, when k is greater than or equal to 2, the etching step of the k-th metal sub-layer has a deposition step 205 inside, and a deposition step 205 of the k+1-th metal sub-layer is formed on the top of the deposition step 205 of the k-th metal sub-layer. Figure 4 As shown, the second metal sub-layer 2032 has one deposition step 205 , and the third metal sub-layer 2033 has two deposition steps 205 .

[0113] In the method for manufacturing the metal structure of the power device according to the embodiment of the present invention, the metal structure is formed on the surface of the underlying structure 201; at least in the first region 202a, the metal structure includes a first stacked structure 203a formed by stacking n metal sublayers, where n is an integer greater than or equal to 2;

[0114] In the first region 202a, the process for forming any two adjacent metal sub-layers includes:

[0115] Perform the kth metal deposition process to form the kth metal sublayer, 1≤k≤n-1. Figure 5A , is a schematic diagram of the device structure after the first metal deposition process is completed in the method for manufacturing the metal structure of the power device according to an embodiment of the present invention; after the first metal deposition process is completed, a first metal sublayer 2031 is formed.

[0116] The kth metal patterning etching process is performed to pattern the kth metal sublayer, and an etching step is formed at the edge of the kth metal sublayer; the height of the etching step of the kth metal sublayer is determined by the thickness of the kth metal sublayer. Figure 5B , which is a schematic diagram of the device structure after the first metal patterning etching process is completed in the method for manufacturing the metal structure of the power device according to the embodiment of the present invention; the first metal sub-layer 2031 is patterned after the kth metal patterning etching process is completed. Figure 5B As shown, the etching step 2041 of the first metal sub-layer 2031 is a step formed by an etching process, namely, a first metal patterning etching process.

[0117] The k+1th metal deposition process is performed to form the k+1th metal sublayer, the k+1th metal sublayer completely covers the kth metal sublayer and extends to the outside of the kth metal sublayer, the etching step of the kth metal sublayer is covered by the k+1th metal sublayer and a deposition step 205 of the k+1th metal sublayer is formed on the top of the etching step of the kth metal sublayer. Figure 2 As shown, Figure 2 FIG. 2 shows a deposition step 205 of the second metal sub-layer 2032 . The deposition step 205 is formed by the bottom etching step 2041 being transferred upward during the deposition process.

[0118] The k+1th metal patterning etching process is performed to pattern the k+1th metal sublayer, and an etching step is formed at the edge of the k+1th metal sublayer; in the edge area of ​​the first stacking structure 203a, the etching step of the k+1th metal sublayer is located outside the etching step of the kth metal sublayer; the height of the etching step of the k+1th metal sublayer is determined by the thickness of the k+1th metal sublayer.

[0119] When k is greater than or equal to 2, a deposition step 205 is provided inside the etching step of the k-th metal sublayer, and a deposition step 205 of the k+1-th metal sublayer is formed on top of the deposition step 205 of the k-th metal sublayer.

[0120] Also includes:

[0121] In the second region 202b, the metal structure is a second stacked structure 203b formed by stacking m metal sub-layers, where m is an integer greater than or equal to 1 and less than or equal to n.

[0122] When m is less than n, the metal sub-layers of the second stacked structure 203b are respectively the (n-m+1)th metal sub-layer to the nth metal sub-layer.

[0123] When 1≤k≤(nm), in the k-th metal patterning etching process, the k-th metal sub-layer in the second region 202b is removed.

[0124] When (n-m+1)≤k≤n, during the k-th metal patterning etching process, a pattern of the k-th metal sub-layer is simultaneously formed in the second region 202b.

[0125] The thickness of each metal sub-layer is less than or equal to the maximum thickness of the metal process.

[0126] The thickness inside the edge region of the first stacked structure 203 a is greater than the maximum thickness of the metal process.

[0127] The material of the layer metal sublayer includes AlSiCu.

[0128] The thickness of each metal sub-layer is 3 microns to 5 microns.

[0129] The distance between the etching step of the k+1th metal sub-layer and the etching step of the kth metal sub-layer is greater than 10 micrometers or greater than twice the thickness of the kth metal sub-layer.

[0130] Also includes:

[0131] When the metal patterning etching process is performed on the selected one or more metal sub-layers, a stress relief groove is also formed in a selected area inside the edge area of ​​the first stacking structure 203a.

[0132] The underlying structure 201 includes a power device formed on a semiconductor substrate 301 , wherein the power device includes an active region.

[0133] The first region 202 a is located in a partial region, the entire region, or extends to the outside of the active region.

[0134] The second region 202b is located in the electrode extraction region outside the active region.

[0135] like Figure 2 As shown, taking N-type devices as an example, the power devices include:

[0136] The N-type heavily doped semiconductor substrate 301 is usually used as a drain region after being thinned.

[0137] A drift region 302 composed of an N-type epitaxial layer is formed on the front surface of the semiconductor substrate 303 .

[0138] A P-type doped channel region 303 is formed on the surface of the drift region 302 .

[0139] The trench gate includes a gate dielectric layer 304 and a gate conductive material layer 305 formed on the inner surface of the gate trench. In some embodiments, the gate dielectric layer 304 is a gate oxide layer, and the gate conductive material layer 305 is a polysilicon gate. The gate trench passes through the channel region 303 vertically.

[0140] The source region 306 is self-aligned to the surface of the channel region 303 formed on both sides of the trench gate in the active region.

[0141] A dielectric layer 308 is also formed on the front surface of the semiconductor substrate 303 .

[0142] A corresponding through hole 307 is formed on the top of the source region 306 and the gate conductive material layer 305 . The bottom of the through hole 307 on the top of the source region 306 is also in contact with the channel region 303 .

[0143] The source region 306 contacts the first stacked structure 203 a in the top metal structure through the through hole 307 , and the first stacked structure 203 a serves as the source metal of the power device.

[0144] in and Figure 2 At different cross sections, the gate conductive material layer 305 contacts the second stacked structure 203b through the through hole 307 (not shown) at the top, and the second stacked structure 203b serves as the gate metal of the power device. The second region 202b serves as a gate lead-out region.

[0145] The metal structures of the power devices of the first to third embodiments of the present invention can be formed by the manufacturing method of the metal structure of the power device of the embodiment of the present invention. In the first embodiment of the present invention, Metal1, i.e., the first metal sublayer 2031, is only above the active area, and there is no Metal1 on the gate bus and the gate pad. This is because the parasitic resistance of the active area has a great influence on the on-resistance of the device. By increasing the metal thickness above the active area, the on-resistance can be reduced. In addition, the heat of the device is mainly below the active area. By increasing the metal thickness above the active area, it is also helpful to reduce the junction temperature of the device.

[0146] The graphic structure of the second metal sublayer 2032 can be obtained by depositing Metal2, i.e., the second metal sublayer 2032, and etching Metal2. The second metal sublayer 2032 is usually AlSiCu, and the thickness is usually 3 to 5 μm; preferably 4 μm. Where Metal1 is present, Metal2 completely covers Metal1, and the covering distance is preferably greater than 10 μm, or at least greater than 2 times the thickness of Metal1; where Metal1 is present, the overall metal thickness is increased to 8 μm; therefore, the first embodiment of the present invention achieves an increase in metal thickness, overcoming the defect that the existing metal thickness is limited by the metal formation process.

[0147] The advantages of the structure of the first embodiment of the present invention are:

[0148] 1. The thickness of the top metal increases above the active area, which has the greatest impact on on-resistance and heat dissipation.

[0149] 2. Compared with the solution where the top metal layer is directly 8 μm, the height difference is too large, which will increase the difficulty of step coverage of the subsequent passivation layer and polyimide. In the first embodiment of the present invention, the height difference of the top metal layer is reduced, which also reduces the difficulty of step coverage of the passivation layer and polyimide.

[0150] In some embodiments, in order to increase chip utilization and improve the area ratio of the active area, Metal1 cannot cover all primitive cell areas in some locations, which is also acceptable; Metal2 will also cover them later; in this way, both the Gate Bus and the Gate Pad only use Metal2.

[0151] In some embodiments, if the gate resistance needs to be further reduced, the following method may be used:

[0152] Another benefit of using this patent is that, for traditional power devices, if only one layer of top thick metal is used, that is, one metal sub-layer is used, it is difficult to make a slot design to reduce stress, because this will cause some primitives to be unable to connect through Metal1. However, with the top metal design of the embodiment of the present invention, since the top metal is formed by a mask of two layers of Metal, a slot design can be used in Metal1 or Metal2, or in both Metal1 and Metal2.

[0153] Figure 2 and Figure 3In the two embodiments of the present invention shown, the thick top metal is achieved by two times of metal deposit and etching. In other embodiments, it can also be achieved by three times of metal deposit and etching;

[0154] As above Figure 4 As shown, the gate metal (Gate Metal) is composed of Metal3, ie, the third metal sublayer 2033; the source metal (Source Metal) is composed of Metal1, Metal2, and Metal3.

[0155] Readers of this application can also implement more Metal Deposit and Etching according to the content of this application.

[0156] The structure of the present application is not only suitable for traditional vertical power devices, but also for lateral power devices, such as LDMOS; it provides a solution for increasing the thickness of the top metal; it is also suitable for third-generation power semiconductor devices such as SiC / GaN.

[0157] In the case of integrating power devices and driver ICs, if a thick top metal is required, the technical solution of the embodiment of the present application can also be used to achieve this.

[0158] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A metal structure of a power device, Features: A metal structure is formed on the surface of the underlying structure; at least in the first region, the metal structure comprises a first stacked structure formed by stacking n metal sublayers, where n is an integer greater than or equal to 2; The structure of the edge region of the first stacked structure includes: Each metal sublayer has an etching step; The etching step of the k+1th metal sublayer is located outside the etching step of the kth metal sublayer, the height of the etching step of the kth metal sublayer is determined by the thickness of the kth metal sublayer, and the height of the etching step of the k+1th metal sublayer is determined by the thickness of the k+1th metal sublayer, 1≤k≤n-1; The etching step of the k-th metal sub-layer is covered by the k+1-th metal sub-layer and a deposition step of the k+1-th metal sub-layer is formed on the top of the etching step of the k-th metal sub-layer.

2. The metal structure of the power device according to claim 1, Features: When k is greater than or equal to 2, a deposition step is provided inside the etching step of the k-th metal sublayer, and a deposition step of the k+1-th metal sublayer is formed on the top of the deposition step of the k-th metal sublayer.

3. The metal structure of the power device according to claim 2, It is characterized in that Also includes: In the second region, the metal structure is a second stacked structure formed by stacking m layers of the metal sub-layers, where m is an integer greater than or equal to 1 and less than or equal to n; When m is less than n, the metal sublayers of each layer of the second stacked structure are respectively the (n-m+1)th metal sublayer to the nth metal sublayer.

4. The metal structure of a power device according to claim 2 or 3, Features: The thickness of the metal sublayer of each layer is less than or equal to the maximum thickness of the metal process; The thickness inside the edge region of the first stacked structure is greater than the maximum thickness of the metal process.

5. The metal structure of a power device according to claim 4, Features: The material of each metal sub-layer includes AlSiCu.

6. The metal structure of the power device according to claim 5, Features: The thickness of each metal sublayer is 3 micrometers to 5 micrometers.

7. The metal structure of a power device according to claim 6, Features: The thickness of each metal sublayer is 4 microns.

8. The metal structure of a power device according to claim 4, Features: The distance between the etching step of the k+1th metal sublayer and the etching step of the kth metal sublayer is greater than 10 micrometers or greater than twice the thickness of the kth metal sublayer.

9. The metal structure of a power device according to claim 4, Features: A stress relief groove (Slot) is formed in a selected area of ​​a portion of the metal sub-layer inside an edge area of ​​the first stacked structure.

10. The metal structure of a power device according to claim 3, Features: The underlying structure includes a power device formed on a semiconductor substrate, the power device including an active region; The first region is located in a partial region, the entire region of the active region, or extends to the outside of the active region; The second region is located in an electrode lead-out region outside the active region.

11. The metal structure of a power device according to claim 10, Features: The power devices include trench MOSFET, SGT MOSFET, IGBT; The power device is a vertical power device or a lateral power device; The power device comprises a super junction device; The material of the semiconductor substrate includes silicon, SiC or GaN.

12. A method for manufacturing a metal structure of a power device, It is characterized in that A metal structure is formed on the surface of the underlying structure; at least in the first region, the metal structure comprises a first stacked structure formed by stacking n metal sublayers, where n is an integer greater than or equal to 2; In the first region, the process for forming the metal sub-layers of any two adjacent layers includes: Performing a k-th metal deposition process to form a k-th metal sublayer, 1≤k≤n-1; Performing a k-th metal patterning etching process to pattern the k-th metal sublayer, forming an etching step at the edge of the k-th metal sublayer; the height of the etching step of the k-th metal sublayer is determined by the thickness of the k-th metal sublayer; Performing a k+1th metal deposition process to form a k+1th metal sublayer, wherein the k+1th metal sublayer completely covers the kth metal sublayer and extends to the outside of the kth metal sublayer, the etching step of the kth metal sublayer is covered by the k+1th metal sublayer and a deposition step of the k+1th metal sublayer is formed on the top of the etching step of the kth metal sublayer; A k+1th metal patterning etching process is performed to pattern the k+1th metal sublayer, and an etching step is formed at the edge of the k+1th metal sublayer; in the edge area of ​​the first stacked structure, the etching step of the k+1th metal sublayer is located outside the etching step of the kth metal sublayer; the height of the etching step of the k+1th metal sublayer is determined by the thickness of the k+1th metal sublayer.

13. The method for manufacturing a metal structure of a power device according to claim 12, Features: When k is greater than or equal to 2, a deposition step is provided inside the etching step of the k-th metal sublayer, and a deposition step of the k+1-th metal sublayer is formed on the top of the deposition step of the k-th metal sublayer.

14. The method for manufacturing a metal structure of a power device according to claim 13, It is characterized in that Also includes: In the second region, the metal structure is a second stacked structure formed by stacking m layers of the metal sub-layers, where m is an integer greater than or equal to 1 and less than or equal to n; When m is less than n, the metal sublayers of each layer of the second stacked structure are respectively the (n-m+1)th metal sublayer to the nth metal sublayer; When 1≤k≤(nm), in the k-th metal patterning etching process, the k-th metal sublayer in the second region is removed; When (n-m+1)≤k≤n, in the k-th metal patterning etching process, a pattern of the k-th metal sub-layer is simultaneously formed in the second region.

15. The method for manufacturing a metal structure of a power device according to claim 13 or 14, Features: The thickness of the metal sublayer of each layer is less than or equal to the maximum thickness of the metal process; The thickness inside the edge region of the first stacked structure is greater than the maximum thickness of the metal process.

16. The method for manufacturing a metal structure of a power device according to claim 15, Features: The material of each metal sub-layer includes AlSiCu.

17. The method for manufacturing a metal structure of a power device according to claim 16, Features: The thickness of each metal sublayer is 3 micrometers to 5 micrometers.

18. The method for manufacturing a metal structure of a power device according to claim 15, Features: The distance between the etching step of the k+1th metal sublayer and the etching step of the kth metal sublayer is greater than 10 micrometers or greater than twice the thickness of the kth metal sublayer.

19. The method for manufacturing a metal structure of a power device according to claim 4, Features: Also includes: When the metal patterning etching process is performed on the selected one or more metal sub-layers, a stress relief groove is formed in a selected area inside the edge area of ​​the first stacked structure.

20. The method for manufacturing a metal structure of a power device according to claim 14, Features: The underlying structure includes a power device formed on a semiconductor substrate, the power device including an active region; The first region is located in a partial region, the entire region of the active region, or extends to the outside of the active region; The second region is located in an electrode lead-out region outside the active region.

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