Germanium-silicon heterojunction npn type bipolar transistor and preparation method thereof
By inserting the inner sidewall of the p-type heavily doped polysilicon emitter region into the germanium-silicon heterojunction npn bipolar transistor, the contradiction between doping and diffusion in the base region is resolved, parasitic resistance is reduced, and high-frequency performance and RF noise performance are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON TECH INNOVATION CENT(BEIJING) CORP
- Filing Date
- 2025-12-17
- Publication Date
- 2026-05-01
AI Technical Summary
In existing germanium-silicon heterojunction npn bipolar transistors, there is a contradiction between doping and diffusion in the base region, resulting in high parasitic resistance and affecting the high-frequency performance and radio frequency noise performance of the device.
A p-type heavily doped polycrystalline silicon emitter inner wall is inserted between the n-type heavily doped polycrystalline silicon emitter region and the L-shaped silicon oxide inner wall. By utilizing the difference in work function of the p-type heavily doped polycrystalline silicon, the hole accumulation state of the connecting base region is increased, and the parasitic resistance is reduced.
It effectively reduces the parasitic resistance of the connection base region, increases fmax, and lowers the RF noise figure, thereby improving RF power gain and noise performance.
Smart Images
Figure CN121968609A_ABST
Abstract
Description
Germanium-silicon heterojunction npn bipolar transistor and its fabrication method Technical Field
[0001] This application relates to the field of semiconductor device and integrated circuit process design and manufacturing, specifically to a germanium-silicon heterojunction npn bipolar transistor and its fabrication method. Background Technology
[0002] A key process step of a germanium-silicon heterojunction npn bipolar transistor is to simultaneously grow an intrinsic inner base region located below the region surrounded by the inner sidewall of silicon nitride and a connection base region located below the polysilicon layer cantilever and the inner sidewall of silicon nitride in the outer base region by using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method.
[0003] The epitaxial base region, the core intrinsic region of the device obtained through selective epitaxial growth, roughly comprises a silicon buffer layer, a germanium-silicon-carbon layer, and a silicon capping layer in the order of growth. The buffer and capping layers are undoped. Even the germanium-silicon-carbon layer, when subdivided, includes several epitaxial layers, with only the innermost layer being boron-doped. This ensures that the final base region is sufficiently thin to minimize the carrier density over time, thus maximizing the device's cutoff frequency f. T .
[0004] However, since the connecting base region is grown simultaneously with the inner base region, the doping situation of the connecting base region during the growth process is roughly similar to that of the inner base region. That is, only the innermost layer is boron-doped, while the other layers are undoped. Although some boron impurities can diffuse from the heavily doped outer polysilicon layer during growth and subsequent thermal processes, in order to ensure the final ultra-thin inner base region, the diffusion of boron impurities during growth and subsequent thermal processes must be minimized. In other words, there are contradictory requirements for boron doping and diffusion in the inner base region and the connecting base region. Therefore, under the premise of ensuring the requirements of the intrinsic inner base region, the boron doping and diffusion of the connecting base region grown simultaneously cannot be fully optimized independently. This inevitably results in a considerable portion of the final connecting base region having relatively low doping concentration, that is, areas with high resistance. The high resistance of the connecting base region will inevitably lead to the inability to sufficiently reduce the parasitic base region resistance of the entire device.
[0005] As a representative of high-performance silicon-based radio frequency semiconductor devices, the germanium-silicon bipolar transistor, even with structural and process optimizations including the intrinsic region of the base region, achieves very high f-values. T However, if the base region parasitic resistance, one of the most important parasitic parameters, cannot be sufficiently reduced, the final device performance will be significantly compromised, not only in terms of its relationship with f. T Another performance metric that is equally or even more important is the highest oscillation frequency f.max The base region parasitic resistance is not small enough, so it cannot be fully improved, thus failing to guarantee that the device can obtain a sufficiently high RF power gain under high frequency operating conditions. Moreover, a high base region parasitic resistance will directly cause the deterioration of RF noise performance.
[0006] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention
[0007] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a germanium-silicon heterojunction npn bipolar transistor and a method for fabricating the same.
[0008] This application provides a germanium-silicon heterojunction npn bipolar transistor, including:
[0009] p-type lightly doped silicon substrate;
[0010] An n-type heavily doped silicon buried collector region is formed on the substrate;
[0011] An n-type lightly doped silicon epitaxial collector region is formed on the buried layer collector region;
[0012] The SiC region is formed in the silicon epitaxial collector region by SiC ion implantation process;
[0013] A field region silicon oxide layer is formed on the buried layer current collector region and located on the side of the silicon epitaxial current collector region;
[0014] p-type in-situ doped germanium silicon-carbon epitaxial base region is formed on the SiC region;
[0015] A connection base region is formed on the SiC region and the silicon epitaxial collector region;
[0016] A base-collector region isolation silicon oxide layer is formed on the silicon epitaxial collector region and the field region silicon oxide layer;
[0017] L-shaped silicon oxide inner walls are formed on the germanium-silicon-carbon epitaxial inner base region and the connecting base region, and the bottom of the L-shaped silicon oxide inner walls encloses a window region.
[0018] The inner sidewall of the p-type heavily doped polycrystalline silicon emitter region is formed on the inner side of the L-shaped silicon oxide inner sidewall;
[0019] A single-crystal emitter region is formed on the inner base region of the germanium-silicon-carbon epitaxial layer and located below the window region;
[0020] p-type heavily doped polycrystalline silicon outer base region is formed on the base region-collector region isolation silicon oxide layer and the connecting base region and located on the side of the inner wall of the L-shaped silicon oxide;
[0021] An emitter-base isolation silicon oxide layer is formed on the outer base region of the polycrystalline silicon and located on the side of the inner wall of the L-shaped silicon oxide.
[0022] An n-type heavily doped polysilicon emitter region is formed inside and above the window region and the inner sidewall of the polysilicon emitter region, and extends outward to the emitter-base region isolation silicon oxide layer.
[0023] In some embodiments, it also includes:
[0024] A silicon oxide outer wall is formed on the outer side of the base-collector region isolation silicon oxide layer, the polysilicon outer base region, the emitter region-base region isolation silicon oxide layer, and the polysilicon emitter region.
[0025] In some embodiments, the upper surfaces of the field region silicon oxide layer and the silicon epitaxial collector region are flush;
[0026] The upper surfaces of the connecting base region, the germanium-silicon-carbon epitaxial inner base region, and the base region-collector region isolation silicon oxide layer are flush.
[0027] In some embodiments, it also includes:
[0028] The emitter is connected to the polycrystalline silicon emitter region;
[0029] The base is connected to the outer base region of the polycrystalline silicon.
[0030] The collector electrode is electrically connected to the buried layer current collection region;
[0031] The substrate electrode is electrically connected to the substrate.
[0032] In some embodiments, the emitter includes an emitter silicide electrode formed on the polysilicon emitter region;
[0033] The base includes a base silicide electrode formed on the exposed upper surface of the polycrystalline silicon outer base region.
[0034] In some embodiments, heavy doping refers to impurity concentrations of 10. 19 cm -3 The above refers to light doping, which means an impurity concentration of 10. 16 cm -3 the following.
[0035] This application also provides a method for fabricating a germanium-silicon heterojunction npn bipolar transistor, including:
[0036] An npn bipolar transistor basic structure is provided, the npn bipolar transistor basic structure includes a p-type lightly doped silicon substrate, an n-type heavily doped silicon buried collector region formed on the substrate, and an n-type lightly doped silicon epitaxial collector region and a field region silicon oxide layer formed on the buried collector region, wherein the field region silicon oxide layer is located on the side of the silicon epitaxial collector region;
[0037] A base-collector region isolation silicon oxide layer, a p-type heavily doped outer base region polycrystalline silicon layer, an emitter-base region isolation silicon oxide layer, and a first silicon nitride layer are deposited sequentially.
[0038] Photolithography is performed on the collector region window. The first silicon nitride layer, the emitter-base region isolation silicon oxide layer and the outer base region polysilicon layer are sequentially etched using photoresist as a mask until the base region-collector region isolation silicon oxide layer is exposed, forming the collector region window.
[0039] SiC ion implantation is performed through the collector region window to form a SiC region in the area of the silicon epitaxial collector region opposite the collector region window, and then the photoresist is removed.
[0040] First, a second silicon nitride layer is deposited, and then the silicon nitride is etched anisotropically to form an inner wall of silicon nitride inside the window of the collector region.
[0041] Using the remaining silicon nitride layer and the inner wall of the silicon nitride as a mask, the exposed base-collector region isolation silicon oxide layer is wet-etched away, and the base-collector region isolation silicon oxide layer is further etched laterally, so that a part of the silicon epitaxial collector region is exposed.
[0042] Using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method, a germanium-silicon-carbon epitaxial inner base region located below the region surrounded by the silicon nitride inner sidewall, a cantilever of the polycrystalline silicon layer in the outer base region, and a connection base region located below the silicon nitride inner sidewall are simultaneously grown.
[0043] The remaining silicon nitride layer and the inner wall of the silicon nitride are removed by wet etching;
[0044] Deposit silicon oxide isolation layer;
[0045] First, a p-type in-situ heavily doped emitter region inner sidewall polysilicon layer is deposited, and then the emitter region inner sidewall polysilicon layer is anisotropically dry etched to form the p-type heavily doped polysilicon emitter region inner sidewall.
[0046] Using the inner wall of the polycrystalline silicon emitter region as a mask, the exposed silicon oxide isolation layer is etched away by wet etching to form an L-shaped silicon oxide inner wall, wherein the bottom of the L-shaped silicon oxide inner wall forms a window area.
[0047] Deposit an n-type heavily doped emitter polysilicon layer;
[0048] Photolithography is performed on the polycrystalline silicon emitter region, and the n-type heavily doped emitter region polycrystalline silicon layer and the emitter region-base region isolation silicon oxide layer are sequentially etched using photoresist as a mask to form the n-type heavily doped polycrystalline silicon emitter region. Then the photoresist is removed.
[0049] Photolithography is performed on the polysilicon outer base region, and the polysilicon layer of the outer base region and the base-collector isolation silicon oxide layer are etched using photoresist as a mask to form a p-type heavily doped polysilicon outer base region. Then the photoresist is removed.
[0050] Rapid thermal annealing is performed to allow impurities in the polycrystalline silicon emitter region to diffuse into the germanium-silicon-carbon epitaxial inner base region, forming an n-type heavily doped single-crystal emitter region.
[0051] In some embodiments, after forming the p-type heavily doped polysilicon substrate region and then removing the photoresist, and before performing rapid thermal annealing, the method further includes:
[0052] Deposit a silicon oxide layer on the outer wall;
[0053] After the rapid thermal annealing, the method further includes:
[0054] The outer wall silicon oxide layer is etched using anisotropic dry etching to form a silicon oxide outer wall.
[0055] In some embodiments, the method further includes:
[0056] An emitter, a base, a collector, and a substrate are formed, such that the emitter is connected to the polysilicon emitter region, the base is connected to the polysilicon outer base region, the collector is electrically connected to the buried layer collector region, and the substrate is electrically connected to the substrate.
[0057] In some embodiments, forming the emitter and base includes:
[0058] Emitter silicide electrodes and base silicide electrodes are formed by silicide reaction between refractory metal and the exposed polycrystalline silicon emitter region and polycrystalline silicon base region, which are self-aligned and isolated by the outer wall of the silicon oxide.
[0059] The germanium-silicon heterojunction npn bipolar transistor and its fabrication method provided in this application embodiment insert a p-type heavily doped polycrystalline silicon emitter inner wall between the n-type heavily doped polycrystalline silicon emitter region and the L-shaped silicon oxide inner wall (also known as the L-shaped silicon oxide isolation layer). The technical effect is that, since the work function of p-type heavily doped polycrystalline silicon is almost one electron volt larger than that of the corresponding n-type heavily doped polycrystalline silicon, the inserted p-type heavily doped polycrystalline silicon emitter inner wall can cause or enhance the hole accumulation state of the adjacent p-type connection base region below the L-shaped silicon oxide inner wall, thereby increasing the hole concentration in the corresponding region and effectively reducing the parasitic resistance of the corresponding connection base region. Reducing the parasitic resistance of the connection base region can reduce the parasitic base region resistance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor in this embodiment, which not only reduces the parasitic base region resistance of the bipolar transistor at a given ff... T Increase f under the condition max Furthermore, it can effectively reduce the radio frequency noise figure, ultimately achieving the goal of improving the overall device performance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor as a radio frequency device, including radio frequency power and noise. Attached Figure Description
[0060] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:
[0061] Figure 1 is a schematic flowchart of a method for fabricating a germanium-silicon heterojunction npn bipolar transistor according to an embodiment of this application.
[0062] Figures 2 to 16 are schematic diagrams of the semiconductor structures obtained by each key process step in the fabrication method of a germanium-silicon heterojunction npn bipolar transistor provided in the embodiments of this application.
[0063] [Attached image labels]
[0064] A. Current collection area window;
[0065] 1. Substrate;
[0066] 2. Buried layer current collection area;
[0067] 3. Silicon epitaxial collector region;
[0068] 4. Silica layer in the field area;
[0069] 5. Base-collector region isolation silicon oxide layer;
[0070] 6. Polycrystalline silicon layer in the outer base region;
[0071] 6a. Polycrystalline silicon outer base region;
[0072] 7. Emitter-base isolation silicon oxide layer;
[0073] 8. First silicon nitride layer;
[0074] 9. Photoresist;
[0075] 9a. Window area;
[0076] 10. SIC Zone;
[0077] 11. Germanium-silicon-carbon epitaxial inner base region;
[0078] 12. Connect the base region;
[0079] 13. Silicon oxide insulating layer;
[0080] 13a. L-shaped silica inner wall;
[0081] 14. Emitter region polycrystalline silicon layer;
[0082] 14a. Polycrystalline silicon emitter region;
[0083] 15. Single-crystal emitter region;
[0084] 16. Emitter silicide electrode;
[0085] 17. Base silicide electrode;
[0086] 18. Silicon oxide layer on the outer wall;
[0087] 18a. Silica outer wall;
[0088] 19. Silicon nitride inner wall;
[0089] 20. The remaining silicon nitride layer;
[0090] 21. Inner sidewall of the polycrystalline silicon emitter region. Detailed Implementation
[0091] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0092] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, indicating how the principles of this application can be adopted. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, embodiments of this application include many changes, modifications, and equivalents.
[0093] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0094] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0095] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a germanium-silicon heterojunction npn bipolar transistor and a method for fabricating the same.
[0096] Figure 1 is a schematic flowchart illustrating a method for fabricating a germanium-silicon heterojunction npn bipolar transistor according to an embodiment of this application. As shown in Figure 1, the method for fabricating a germanium-silicon heterojunction npn bipolar transistor according to an embodiment of this application includes:
[0097] S1. Provide an npn bipolar transistor basic structure, the npn bipolar transistor basic structure including a p-type lightly doped silicon substrate 1, an n-type heavily doped silicon buried collector region 2 formed on the substrate 1, and an n-type lightly doped silicon epitaxial collector region 3 and a field region silicon oxide layer 4 formed on the buried collector region 2, wherein the field region silicon oxide layer 4 is located on the side of the silicon epitaxial collector region 3;
[0098] In step S1, the basic structure of the npn bipolar transistor is shown in Figure 2.
[0099] S2, sequentially deposit the base region-collector region isolation silicon oxide layer 5, the p-type heavily doped outer base region polycrystalline silicon layer 6, the emitter region-base region isolation silicon oxide layer 7, and the first silicon nitride layer 8;
[0100] In step S2, referring to Figure 3, a base-collector isolation silicon oxide layer 5, a p-type heavily doped outer base region polysilicon layer 6, an emitter-base isolation silicon oxide layer 7, and a first silicon nitride layer 8 are sequentially deposited on the npn-type bipolar transistor basic structure. Specifically, the p-type heavily doped outer base region polysilicon layer 6 can be a p-type in-situ boron heavily doped outer base region polysilicon layer 6.
[0101] S3. Perform photolithography on the collector region window. Using photoresist 9 as a mask, sequentially etch the first silicon nitride layer 8, the emitter-base region isolation silicon oxide layer 7, and the outer base region polysilicon layer 6 until the base region-collector region isolation silicon oxide layer 5 is exposed, forming the collector region window A.
[0102] In step S3, referring to Figure 4, photolithography is performed on the collector region window to form a photoresist 9 on the first silicon nitride layer 8, and a window region 9a is formed on the photoresist 9. Referring to Figure 5, the first silicon nitride layer 8, the emitter-base region isolation silicon oxide layer 7, and the outer base region polysilicon layer 6 are sequentially etched using the photoresist 9 as a mask to expose the base region-collector region isolation silicon oxide layer 5 and form the collector region window A.
[0103] S4. Perform SIC ion implantation through the collector region window A to form an SIC region 10 in the area of the silicon epitaxial collector region 3 opposite to the collector region window A, and then remove the photoresist 9.
[0104] In step S4, referring to Figure 5, before removing the photoresist 9 after etching, n-type ion implantation (SIC ion implantation) is performed on the exposed base-collector region isolation silicon oxide layer 5 to form a selectively implanted collector region (SIC) in the region directly opposite collector region window A in the lightly doped silicon epitaxial collector region 3, i.e., the SIC region 10. Then, the photoresist 9 is removed.
[0105] S5. First, deposit the second silicon nitride layer, then anisotropically dry etch the silicon nitride to form a silicon nitride inner wall 19 inside the collector region window A.
[0106] In step S5, referring to Figure 6, a second silicon nitride layer is first deposited, and then anisotropic dry etching is used to form an inner sidewall 19 of silicon nitride at the edge of the collector window A.
[0107] S6. Using the remaining silicon nitride layer 20 and the inner wall 19 of the silicon nitride as a mask, wet etching is used to remove the exposed base-collector region isolation silicon oxide layer 5, and the base-collector region isolation silicon oxide layer 5 is further etched laterally, so that a part of the silicon epitaxial collector region 3 is exposed.
[0108] In step S6, referring to Figure 7, the exposed base-collector region isolation silicon oxide layer 5 is wet-etched away using the remaining silicon nitride layer 20 and silicon nitride inner sidewall 19 as a mask, and the base-collector region isolation silicon oxide layer 5 is further etched laterally, so that a part of the silicon epitaxial collector region 3 is exposed.
[0109] S7. Using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method, a germanium-silicon-carbon epitaxial inner base region 11 located below the region surrounded by the silicon nitride inner sidewall 19 and a cantilever of the polycrystalline silicon layer 6 in the outer base region and a connecting base region 12 located below the silicon nitride inner sidewall 19 are simultaneously grown.
[0110] In step S7, referring to Figure 8, the germanium-silicon-carbon epitaxial inner base region 11 (intrinsic inner base region) and the cantilever of the polysilicon layer 6 in the outer base region and the connecting base region 12 under the silicon nitride inner wall 19 are simultaneously grown by the p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method.
[0111] S8. Wet etching removes the remaining silicon nitride layer 20 and the silicon nitride inner wall 19;
[0112] In step S8, referring to Figure 9, the remaining silicon nitride layer 20 and the silicon nitride inner wall 19 are removed by wet etching.
[0113] S9, Deposited silicon oxide isolation layer 13;
[0114] In step S9, as shown in Figure 10, a thin silicon oxide isolation layer 13 is deposited.
[0115] S10. First, deposit a p-type in-situ heavily doped emitter region inner sidewall polysilicon layer, and then anisotropically dry etch the emitter region inner sidewall polysilicon layer to form p-type heavily doped polysilicon emitter region inner sidewall 21.
[0116] In step S10, referring to Figure 10, a p-type in-situ heavily doped emitter region inner sidewall polysilicon layer is first deposited, and then anisotropic dry etching is used to form the p-type heavily doped polysilicon emitter region inner sidewall 21.
[0117] S11. Using the inner sidewall 21 of the polycrystalline silicon emitter region as a mask, wet etching is used to remove the exposed silicon oxide isolation layer 13 to form an L-shaped silicon oxide inner sidewall 13a, wherein the bottom of the L-shaped silicon oxide inner sidewall 13a forms a window area.
[0118] In step S11, referring to Figures 10 and 11, the exposed silicon oxide isolation layer 13 is wet-etched away using the inner sidewall 21 of the polycrystalline silicon emitter region as a mask to form an L-shaped silicon oxide inner sidewall 13a (also referred to as an L-shaped silicon oxide isolation layer). The bottom of the L-shaped silicon oxide inner sidewall 13a forms a window area.
[0119] S12, depositing an n-type heavily doped emitter region polysilicon layer 14;
[0120] In step S12, referring to Figure 11, an n-type in-situ heavily doped emitter region polysilicon layer 14 is deposited.
[0121] S13. Perform polysilicon emitter region photolithography, and sequentially etch the n-type heavily doped emitter region polysilicon layer 14 and the emitter region-base region isolation silicon oxide layer 7 using photoresist as a mask to form the n-type heavily doped polysilicon emitter region 14a, and then remove the photoresist.
[0122] In step S13, referring to Figures 11 and 12, polysilicon emitter region photolithography is performed, and the exposed n-type in-situ heavily doped emitter region polysilicon layer 14 and the underlying emitter-base region isolation silicon oxide layer 7 are sequentially etched away using photoresist as a mask to form n-type heavily doped polysilicon emitter region 14a. Then the photoresist is removed.
[0123] S14. Perform photolithography on the polysilicon outer base region, and use photoresist as a mask to etch the polysilicon layer 6 of the outer base region and the base region-collector region isolation silicon oxide layer 5 to form a p-type heavily doped polysilicon outer base region 6a, and then remove the photoresist.
[0124] In step S14, referring to Figures 12 and 13, polysilicon outer substrate photolithography is performed, and the exposed outer substrate polysilicon layer 6 and the underlying base-collector isolation silicon oxide layer 5 are sequentially etched away using photoresist as a mask to form a p-type heavily doped polysilicon outer substrate region 6a. Then the photoresist is removed.
[0125] S15. Perform rapid thermal annealing to allow impurities in the polycrystalline silicon emitter region 14a to diffuse into the germanium-silicon-carbon epitaxial inner base region 11 to form an n-type heavily doped single crystal emitter region 15.
[0126] In step S15, referring to Figure 14, rapid thermal annealing (RTA) is performed. On the one hand, this allows impurities in the polycrystalline silicon emitter region 14a to diffuse into the germanium-silicon-carbon epitaxial inner base region 11 to form an n-type heavily doped single crystal emitter region 15. On the other hand, it activates the impurities.
[0127] The method for fabricating a germanium-silicon heterojunction npn bipolar transistor provided in this application involves inserting a p-type heavily doped polycrystalline silicon emitter inner wall 21 between the n-type heavily doped polycrystalline silicon emitter region 14a and the L-shaped silicon oxide inner sidewall 13a (also referred to as the L-shaped silicon oxide isolation layer). The technical effect is that, since the work function of p-type heavily doped polycrystalline silicon is almost one electron volt larger than that of the corresponding n-type heavily doped polycrystalline silicon, the inserted p-type heavily doped polycrystalline silicon emitter inner wall 21 can cause or enhance the hole accumulation state of the adjacent p-type connection base region 12 below the L-shaped silicon oxide inner sidewall 13a, thereby increasing the hole concentration in the corresponding region and effectively reducing the parasitic resistance of the corresponding connection base region 12. Reducing the parasitic resistance of the connection base region 12 can reduce the parasitic base region resistance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor in this embodiment, which not only reduces the parasitic base region resistance of the bipolar transistor at a given ff T Increase f under the condition maxFurthermore, it can effectively reduce the radio frequency noise figure, ultimately achieving the goal of improving the overall device performance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor as a radio frequency device, including radio frequency power and noise.
[0128] In some embodiments, after step S14 and before step S15, the method further includes:
[0129] S15-0, deposited outer wall silicon oxide layer 18.
[0130] In step S15-0, referring to Figure 14, an outer wall silicon oxide layer 18 is deposited.
[0131] In some embodiments, after depositing the outer wall silicon oxide layer 18 and performing rapid thermal annealing, the method further includes:
[0132] S16. The outer wall silicon oxide layer 18 is etched using anisotropic dry etching to form a silicon oxide outer wall 18a.
[0133] In step S18, referring to Figure 15, the outer wall silicon oxide layer 18 is etched anisotropically to form the silicon oxide outer wall 18a.
[0134] In some embodiments, after step S16 described above, the method further includes:
[0135] S17. An emitter, a base, a collector, and a substrate are formed, such that the emitter is connected to the polysilicon emitter region 14a, the base is connected to the polysilicon outer base region 6a, the collector is electrically connected to the buried layer collector region 2, and the substrate is electrically connected to the substrate 1.
[0136] In some embodiments, the formation of the emitter and base includes: forming an emitter silicide electrode 16 and a base silicide electrode 17 by silicide reaction of a refractory metal with the exposed polycrystalline silicon emitter region 14a and the polycrystalline silicon base region 6a, which are self-aligned and isolated by the silicon oxide outer wall 18a.
[0137] Specifically, as shown in Figure 16, a low-resistance metal silicide layer is formed by self-aligning a silicide reaction between a refractory metal and exposed monocrystalline and polycrystalline silicon, thereby forming an emitter silicide electrode 16 and a base silicide electrode 17, respectively.
[0138] Finally, the germanium-silicon heterojunction npn bipolar transistor can also be fabricated using back-end metallization processes in this field. It should be noted that, considering that this application does not impose any restrictions on the collector and substrate lead-out methods, or the number and relative positions of the emitter, base, collector, and substrate electrodes of the germanium-silicon heterojunction npn bipolar transistor, the electrode lead-out methods of the collector and substrate regions and all electrode configurations are not fully illustrated in the specification and related process flow diagrams of this application. However, all of these can be implemented using common techniques in this field.
[0139] Based on the same inventive concept, this application also provides a germanium-silicon heterojunction npn bipolar transistor.
[0140] Figure 16 is a schematic diagram of a germanium-silicon heterojunction npn bipolar transistor provided in an embodiment of this application. As shown in Figure 16, the germanium-silicon heterojunction npn bipolar transistor 001 provided in an embodiment of this application includes:
[0141] p-type lightly doped silicon substrate 1;
[0142] n-type heavily doped silicon buried layer collector region 2 is formed on the substrate 1;
[0143] n-type lightly doped silicon epitaxial collector region 3 is formed on the buried layer collector region 2;
[0144] The SIC region 10 is formed in the silicon epitaxial collector region 3 by the SIC ion implantation process;
[0145] A field region silicon oxide layer 4 is formed on the buried layer current collector region 2 and located on the side of the silicon epitaxial current collector region 3;
[0146] p-type in-situ doped germanium silicon-carbon epitaxial base region 11 is formed on the SiC region 10;
[0147] A connecting base region 12 is formed on the SiC region 10 and the silicon epitaxial collector region 3;
[0148] A base region-collector region isolation silicon oxide layer 5 is formed on the silicon epitaxial collector region 3 and the field region silicon oxide layer 4;
[0149] L-shaped silicon oxide inner sidewall 13a is formed on the germanium-silicon-carbon epitaxial inner base region 11 and the connecting base region 12, and the bottom of the L-shaped silicon oxide inner sidewall 13a forms a window region.
[0150] The inner sidewall 21 of the p-type heavily doped polycrystalline silicon emitter region is formed on the inner side of the L-shaped silicon oxide inner sidewall 13a.
[0151] A single-crystal emitter region 15 is formed on the germanium-silicon-carbon epitaxial inner base region 11 and located below the window region;
[0152] p-type heavily doped polycrystalline silicon outer base region 6a is formed on the base region-collector region isolation silicon oxide layer 5 and the connecting base region 12 and is located on the side of the L-shaped silicon oxide inner sidewall 13a;
[0153] An emitter-base isolation silicon oxide layer 7 is formed on the outer base region 6a of the polysilicon and is located on the side of the inner sidewall 13a of the L-shaped silicon oxide.
[0154] The n-type heavily doped polysilicon emitter region 14a is formed inside and above the window region and the inner sidewall 21 of the polysilicon emitter region, and extends outward to the emitter-base region isolation silicon oxide layer 7.
[0155] The germanium-silicon heterojunction npn bipolar transistor provided in this application embodiment inserts a p-type heavily doped polysilicon emitter inner wall 21 between the n-type heavily doped polysilicon emitter region 14a and the L-shaped silicon oxide inner wall 13a (also referred to as the L-shaped silicon oxide isolation layer). The technical effect is that, since the work function of p-type heavily doped polysilicon is almost one electron volt larger than that of the corresponding n-type heavily doped polysilicon, the inserted p-type heavily doped polysilicon emitter inner wall 21 can cause or enhance the hole accumulation state of the adjacent p-type connection base region 12 below the L-shaped silicon oxide inner wall 13a, thereby increasing the hole concentration in the corresponding region and effectively reducing the parasitic resistance of the corresponding connection base region 12. Reducing the parasitic resistance of the connection base region 12 can reduce the parasitic base region resistance of the dual polysilicon self-aligned germanium-silicon heterojunction npn bipolar transistor in this embodiment, which can not only reduce the parasitic base region resistance of the connected base region 12 under a given f... T Increase f under the condition max Furthermore, it can effectively reduce the radio frequency noise figure, ultimately achieving the goal of improving the overall device performance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor as a radio frequency device, including radio frequency power and noise.
[0156] In some embodiments, it also includes:
[0157] The silicon oxide outer wall 18a is formed on the outer side of the base region-collector region isolation silicon oxide layer 5, the polysilicon outer base region 6a, the emitter region-base region isolation silicon oxide layer 7, and the polysilicon emitter region 14a.
[0158] In some embodiments, the upper surfaces of the field region silicon oxide layer 4 and the silicon epitaxial collector region 3 are flush; the upper surfaces of the connecting base region 12, the germanium-silicon-carbon epitaxial inner base region 11, and the base region-collector region isolation silicon oxide layer 5 are flush.
[0159] In some embodiments, it also includes:
[0160] The emitter is connected to the polycrystalline silicon emitter region 14a;
[0161] The base is connected to the polycrystalline silicon outer base region 6a;
[0162] The collector electrode is electrically connected to the buried layer collector region 2.
[0163] The substrate electrode is electrically connected to the substrate 1.
[0164] In some embodiments, the emitter includes an emitter silicide electrode 16, which is formed on the polysilicon emitter region 14a;
[0165] The base includes a base silicide electrode 17, which is formed on the exposed upper surface of the polysilicon outer base region 6a.
[0166] In some embodiments, heavy doping refers to impurity concentrations of 10. 19 cm -3 The above refers to light doping, which means an impurity concentration of 10. 16 cm -3 the following.
[0167] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The terms "upper," "lower," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and for simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0168] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments in this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0169] This application uses specific embodiments to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A germanium-silicon heterojunction npn-type bipolar transistor, characterized in that, include: p-type lightly doped silicon substrate; n-type heavily doped silicon buried collector region formed on the substrate; n-type lightly doped silicon epitaxial collector region formed on the buried collector region; A SiC region is formed in the silicon epitaxial collector region using a SiC ion implantation process; a field region silicon oxide layer is formed on the buried collector region and located on the side of the silicon epitaxial collector region; a p-type in-situ doped germanium-silicon-carbon epitaxial base region is formed on the SiC region; a connecting base region is formed on the SiC region and the silicon epitaxial collector region; a base-collector region isolation silicon oxide layer is formed on the silicon epitaxial collector region and the field region silicon oxide layer; an L-shaped silicon oxide inner sidewall is formed on the germanium-silicon-carbon epitaxial base region and the connecting base region, the bottom of the L-shaped silicon oxide inner sidewall forming a window region; and a p-type heavily doped polycrystalline silicon emitter region. An inner sidewall is formed on the inner side of the L-shaped silicon oxide inner sidewall; a single-crystal emitter region is formed on the germanium-silicon-carbon epitaxial inner base region and located below the window region; a p-type heavily doped polycrystalline silicon outer base region is formed on the base-collector region isolation silicon oxide layer and the connecting base region and located on the side of the L-shaped silicon oxide inner sidewall; an emitter region-base region isolation silicon oxide layer is formed on the polycrystalline silicon outer base region and located on the side of the L-shaped silicon oxide inner sidewall; an n-type heavily doped polycrystalline silicon emitter region is formed inside and above the window region and the polycrystalline silicon emitter region inner sidewall, and extends outward to the emitter region-base region isolation silicon oxide layer.
2. The germanium-silicon heterojunction npn bipolar transistor according to claim 1, characterized in that, Also includes: A silicon oxide outer wall is formed on the outer side of the base-collector region isolation silicon oxide layer, the polysilicon outer base region, the emitter region-base region isolation silicon oxide layer, and the polysilicon emitter region.
3. The germanium-silicon heterojunction npn bipolar transistor according to claim 1 or 2, characterized in that, The upper surfaces of the field region silicon oxide layer and the silicon epitaxial collector region are flush; the upper surfaces of the connecting base region, the germanium-silicon-carbon epitaxial inner base region, and the base region-collector region isolation silicon oxide layer are flush.
4. The germanium-silicon heterojunction npn bipolar transistor according to claim 1, characterized in that, Also includes: The emitter is connected to the polysilicon emitter region; the base is connected to the polysilicon outer base region; the collector is electrically connected to the buried layer collector region; and the substrate is electrically connected to the substrate.
5. The germanium-silicon heterojunction npn bipolar transistor according to claim 4, characterized in that, The emitter includes an emitter silicide electrode formed on the polycrystalline silicon emitter region; the base includes a base silicide electrode formed on the exposed upper surface of the polycrystalline silicon outer base region.
6. The germanium-silicon heterojunction npn bipolar transistor according to claim 1, characterized in that, The term "heavy doping" refers to an impurity concentration of 10. 19 cm -3 The above refers to light doping, which means an impurity concentration of 10. 16 cm -3 the following.
7. A method for fabricating a germanium-silicon heterojunction npn-type bipolar transistor, characterized in that, include: A basic structure for an npn bipolar transistor is provided, comprising a p-type lightly doped silicon substrate, an n-type heavily doped silicon buried collector region formed on the substrate, and an n-type lightly doped silicon epitaxial collector region and a field region silicon oxide layer formed on the buried collector region, wherein the field region silicon oxide layer is located on the side of the silicon epitaxial collector region; a base-collector region isolation silicon oxide layer, a p-type heavily doped outer base region polysilicon layer, an emitter-base region isolation silicon oxide layer, and a first silicon nitride layer are sequentially deposited; a collector region window photolithography is performed, and the first silicon nitride layer, the emitter-base region isolation silicon oxide layer, and the outer base region polysilicon layer are sequentially etched using photoresist as a mask. The photoresist is then removed. A second silicon nitride layer is deposited, followed by anisotropic dry etching to form a silicon nitride inner wall inside the collector window. Using the remaining silicon nitride layer and the inner wall as a mask, the exposed base-collector isolation silicon oxide layer is wet-etched away, and the lateral etching continues, exposing a portion of the silicon epitaxial collector region. Finally, p-type in-situ doped germanium-silicon-carbon selective etching is performed. A selective epitaxial growth method is used to simultaneously grow a germanium-silicon-carbon epitaxial inner base region located below the region surrounded by the silicon nitride inner sidewall, and a cantilever of the polysilicon layer in the outer base region and a connecting base region below the silicon nitride inner sidewall; wet etching is used to remove the remaining silicon nitride layer and silicon nitride inner sidewall; a silicon oxide isolation layer is deposited; first, a p-type in-situ heavily doped emitter region inner sidewall polysilicon layer is deposited, and then the emitter region inner sidewall polysilicon layer is anisotropically dry etched to form a p-type heavily doped polysilicon emitter region inner sidewall; using the polysilicon emitter region inner sidewall as a mask, wet etching is used to remove the exposed silicon oxide isolation layer to form an L-shaped silicon oxide inner sidewall, wherein the L-shaped silicon oxide inner sidewall... The bottom of the sidewalls forms a window area; an n-type heavily doped emitter polysilicon layer is deposited; polysilicon emitter photolithography is performed, and the n-type heavily doped emitter polysilicon layer and the emitter-base isolation silicon oxide layer are sequentially etched using photoresist as a mask to form an n-type heavily doped polysilicon emitter region, and then the photoresist is removed; polysilicon outer base region photolithography is performed, and the outer base region polysilicon layer and the base-collector isolation silicon oxide layer are etched using photoresist as a mask to form a p-type heavily doped polysilicon outer base region, and then the photoresist is removed; rapid thermal annealing is performed, causing impurities in the polysilicon emitter region to diffuse into the germanium-silicon-carbon epitaxial inner base region to form an n-type heavily doped single crystal emitter region.
8. The method according to claim 7, characterized in that, After forming the p-type heavily doped polycrystalline silicon outer base region and then removing the photoresist, before performing rapid thermal annealing, the method further includes: depositing an outer wall silicon oxide layer; after performing rapid thermal annealing, the method further includes: anisotropically dry etching the outer wall silicon oxide layer to form a silicon oxide outer wall.
9. The method according to claim 8, characterized in that, The method further includes: forming an emitter, a base, a collector, and a substrate, wherein the emitter is connected to the polysilicon emitter region, the base is connected to the polysilicon outer base region, the collector is electrically connected to the buried layer collector region, and the substrate is electrically connected to the substrate.
10. The method according to claim 9, characterized in that, The formation of the emitter and base includes: forming emitter silicide electrodes and base silicide electrodes by silicide reaction between a refractory metal and the exposed polycrystalline silicon emitter region and polycrystalline silicon base region that are self-aligned and isolated by the outer wall of the silicon oxide.