Image sensor and electronic device

Abstract

The invention discloses an image sensor and electronic equipment. The image sensor comprises an SPAD pixel array, the SPAD pixel array comprises SPAD pixels arranged in multiple rows and multiple columns, each SPAD pixel comprises an SPAD and a register, the registers are electrically connected with the SPAD, the output end of the register of the ith SPAD pixel in the same column of SPAD pixels is electrically connected with the input end of the register of the (i + a) th SPAD pixel, and the output end of the register of the (i + a) th SPAD pixel in the same column of SPAD pixels is electrically connected with the input end of the register of the (i + a) th SPAD pixel. The output end of the last-stage register in the multiple cascade registers in the same column of SPAD pixels is connected with the input end of the column scanning circuit, and a is larger than or equal to 1. The registers of the SPAD pixels are cascaded, a counter is not needed, and the problem that a large number of SPAD pixels cannot be integrated in a unit chip area to improve the effective resolution of CI S due to the fact that the SPAD pixels are too large in size in the prior art can be solved.

Description

Technical Field

[0001] The present application belongs to the field of image technology, and specifically relates to an image sensor and an electronic device. Background Art

[0002] Single-Photon Avalanche Diode (SPAD) has higher sensitivity than the pinned photodiode (PPD) in conventional complementary metal oxide semiconductor (CMOS) image sensors (CIS). Each photon (Photon) shining on the SPAD will stimulate a corresponding electrical signal, which will form a square wave pulse signal after rectification, and then output as a SPAD pixel signal after counting. In recent years, researchers have begun to study the use of SPAD to replace PPD as the SPAD pixel photosensitive element of ordinary visible light RGB camera CIS, in order to make full use of the ultra-high sensitivity of SPAD single photon sensing level and exert imaging capabilities beyond the human eye in polar night scenes.

[0003] However, in the related art, each SPAD pixel needs to include a counter, and the structure of the counter is relatively complex, which causes the SPAD pixel size to be too large, resulting in the inability to integrate a large number of SPAD pixels per unit chip area to improve the effective resolution of the CIS. Summary of the invention

[0004] The present application aims to provide an image sensor and an electronic device that can solve the problem in the prior art that the SPAD pixel size is too large, resulting in an inability to integrate a large number of SPAD pixels per unit chip area to improve the effective resolution of the CIS.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application proposes an image sensor, comprising a SPAD pixel array, the SPAD pixel array comprising SPAD pixels arranged in multiple rows and columns, the SPAD pixels comprising a SPAD and a register, the register being electrically connected to the SPAD, and the output end of the register of the i-th SPAD pixel in the same column of SPAD pixels being electrically connected to the input end of the register of the i+a-th SPAD pixel, the output end of the last stage register of multiple cascade registers in the same column of SPAD pixels being connected to the input end of the column scanning circuit, where a is greater than or equal to 1.

[0007] In a second aspect, an embodiment of the present application proposes an electronic device, including a central processing unit and an image sensor as described in the embodiment of the first aspect.

[0008] In an embodiment of the present application, a SPAD pixel includes a SPAD and a register, the register is electrically connected to the SPAD, and the registers of multiple SPAD pixels in the same column are cascaded to form a shift register, and the signal generated by the SPAD photosensitivity can be transferred pixel by pixel through the cascaded registers, and the signal is output to the column scanning circuit by the last-level register; in the embodiment of the present application, the design method of cascading the registers of SPAD pixels in the same column can process and output the light signal captured by the SPAD device at a high speed and effectively, thereby improving the pixel operation energy efficiency; and the SPAD pixel does not include a complex counter and the clock control circuit required by the counter, which simplifies the circuit structure of the SPAD pixel and reduces the unit area occupied by a single SPAD pixel, which is conducive to integrating a larger number of SPAD pixels within a unit chip area to improve the effective resolution of the CIS; and the SPAD pixel does not include a complex counter, which simplifies the composition and complexity of the circuit on the chip, can provide space for more auxiliary modules, and also makes it possible to have the same chip size as the logic layer and the pixel layer.

[0009] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0011] Figure 1 It is a circuit diagram and working principle diagram of a CIS chip of a SPAD in the related art;

[0012] Figure 2 It is a schematic diagram of the architecture of an image sensor in the related art;

[0013] Figure 3 It is a structural schematic diagram of a counter in the related art;

[0014] Figure 4 is a structural schematic diagram of an image sensor according to an embodiment of the present application;

[0015] Figure 5 is another structural schematic diagram of an image sensor according to an embodiment of the present application;

[0016] Figure 6 is another structural schematic diagram of an image sensor according to an embodiment of the present application;

[0017] Figure 7 is another structural schematic diagram of an image sensor according to an embodiment of the present application;

[0018] Figure 8 is a structural schematic diagram of a column scanning circuit in an image sensor according to an embodiment of the present application;

[0019] Fig. 9 is a structural schematic diagram of a clock and control circuit in an image sensor according to an embodiment of the present application;

[0020] Fig.10 is another structural schematic diagram of an image sensor according to an embodiment of the present application;

[0021] Fig.11 It is a structural schematic diagram of an electronic device according to an embodiment of the present application.

[0022] Description of reference numerals:

[0023] 1. SPAD pixel; 11. SPAD; 12. register; 13. first switch device; 14. shaping circuit; 15. selector;

[0024] 21. Selection signal line; 22. Clock signal line; 23. Control signal line;

[0025] 3. Column scanning circuit; 31. Gating circuit; 32. First demultiplexer;

[0026] 4. Clock and control circuit; 41. Counter; 42. First clock circuit; 43. Second clock circuit; 44. Second demultiplexer;

[0027] 5. Signal processing circuit, 6. Port circuit;

[0028] 01. Pixel layer; 02. Logic layer. DETAILED DESCRIPTION

[0029] Embodiments of the present invention will be described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0030] The term "first" or "second" in the specification and claims of the present application may include one or more of the features explicitly or implicitly. In the description of the present invention, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0031] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] At present, single photon avalanche transistors (SPADs) are widely used in direct time-of-flight (dToF) image sensor CIS chips. The circuit structure and working principle of SPAD pixels in related technologies are as follows: Figure 1 shown.

[0033] There is no structural difference between SPAD and PPD used in conventional CIS pixels. It is the higher bias voltage (VDD-VSS) that makes PPD work in the avalanche region. SPAD has higher sensitivity than PPD. Every photon shining on SPAD will stimulate a corresponding electrical signal. Figure 1 In the typical SPAD pixel structure shown, the SPAD receives a photon and pulls down the Vc voltage (called SPAD quenching (Quench)), and then the charging clock jumps to pull up the Vc voltage (called SPAD charging = (Re-Charge)) so that the waveform of Vc is a pulse signal, which is rectified by the inverter (NOT gate, also called non-gate) to form a square wave pulse signal Vp. The PMOS transistor switch connected to the power supply voltage VDD is equivalent to a variable resistor, which mainly controls the size of the pulse signal flowing through the SPAD to prevent the Vc signal from being too large or too small. The Vp signal is connected to a counter (Counter). In theory, the counter will count once for each photon received by the SPAD. If N photons reach the SPAD, the counter will count N times.

[0034] The SPAD pixel circuit architecture of the CMOS single-photon image sensor based on SPAD devices has undergone significant changes compared to the current mainstream CMOS image sensor based on PPD pixels. Figure 2 As shown in Figure 1, each SPAD pixel circuit must integrate a corresponding digital counter, so the SPAD pixel is too large and difficult to shrink. For example, a typical SPAD pixel internal n-bit digital counter circuit design is shown in Figure 1. Figure 3 As shown in the figure, in order to output n-bit (S1 S2 … Sn) digital counts, N D flip-flops need to be designed in series. The large size of SPAD pixels makes it impossible to integrate a large number of SPAD pixels per unit chip area to improve the effective resolution of CIS. At the same time, the SPAD pixel circuit array occupies a large area of ​​the logic layer chip and must correspond one-to-one with the SPAD array in the SPAD pixel layer. Therefore, auxiliary modules such as the image signal processing (ISP) module and the port module can only be placed outside the SPAD pixel circuit array, resulting in inconsistent sizes between the SPAD pixel layer chip and the logic layer chip and affecting the stacking and optical design of the CIS chip in the camera module.

[0035] In order to solve the above technical problems, the present application provides an image sensor and an electronic device. The technical concept of the present application is that a shift register design is adopted in the SPAD pixel to realize a SPAD pixel circuit without a counter, thereby reducing the size of the SPAD pixel. Since the counter is not used, the circuit module required for the logic layer of the image sensor can be simplified, which is conducive to achieving the same size of the SPAD pixel layer chip and the logic layer chip while optimizing the stacking and optical design of the CIS chip in the camera module.

[0036] The image sensor and the electronic device provided in the embodiments of the present application are described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0037] Figure 4 is a structural schematic diagram of an image sensor according to an embodiment of the present application. Figure 5 FIG. 1 is another schematic diagram of the structure of an image sensor according to an embodiment of the present application. Figure 4 or Figure 5As shown, the image sensor provided by the embodiment of the present application includes a SPAD pixel array, the SPAD pixel array includes SPAD pixels 1 arranged in multiple rows and columns, the SPAD pixel 1 includes a SPAD and a register 12, wherein the SPAD is marked as 11 in the figure, the register 12 is electrically connected to the SPAD, and the output end of the register 12 of the i-th SPAD pixel in the same column of SPAD pixels is electrically connected to the input end of the register 12 of the i+a-th SPAD pixel, and the output end of the last stage register in the multiple cascade registers in the same column of SPAD pixels is connected to the input end of the column scanning circuit 3, where a is greater than or equal to 1. It can be understood that i is an integer, and the i-th SPAD pixel and the i+a-th SPAD pixel are any two SPAD pixels in the same column of SPAD pixels.

[0038] After the SPAD is exposed to light, it will stimulate a corresponding electrical signal. The register is electrically connected to the SPAD, and the register can be used to transmit and temporarily store the signal generated by the SPAD after exposure to light.

[0039] The output end of the register of the i-th SPAD pixel in the same column is electrically connected to the input end of the register of the i+a-th SPAD pixel, and a plurality of registers electrically connected to each other can form a shift register. In the two registers connected to each other, the output end of the upper register is electrically connected to the input end of the lower register, and the upper register can transfer the signal generated by the photosensitization of the SPAD device to the lower shift register, and then transfer it to the last shift register in sequence, and the last shift register outputs it to the column scanning circuit 3. For example, the registers of m1 SPAD pixels in the same column are cascaded to each other, the first register can transfer the signal generated by the photosensitization of the SPAD device to the second register, and then the second register can transfer the signal to the third register, ... until the signal is transferred to the last register (such as the m1-th register), and the signal can be output to the column scanning circuit through the last register.

[0040] Exemplarily, the column scanning circuit may be disposed outside the image sensor, or the image sensor includes the column scanning circuit.

[0041] Exemplarily, in the same column of SPAD pixels, SPAD pixels that are not in a cascade relationship are connected to different input terminals of the column scanning circuit. SPAD pixels in different columns are connected to different input terminals of the column scanning circuit, so that the column scanning circuit can distinguish the SPAD pixel to which the signal connected thereto belongs.

[0042] According to the image sensor provided by the embodiment of the present application, the SPAD pixel includes a SPAD and a register, the register is electrically connected to the SPAD, and the registers of multiple SPAD pixels in the same column are cascaded to form a shift register, and the signal generated by the SPAD photosensitivity can be transferred pixel by pixel through the cascaded registers, and the signal is output to the column scanning circuit by the last-level register; in the embodiment of the present application, the design method of cascading the registers of SPAD pixels in the same column can process and output the light signal captured by the SPAD device at a high speed and effectively, thereby improving the pixel operation energy efficiency; and the SPAD pixel does not include a complex counter and the clock control circuit required by the counter, which simplifies the circuit structure of the SPAD pixel, so that the unit area occupied by a single SPAD pixel is greatly reduced, which is conducive to integrating a larger number of SPAD pixels per unit chip area to improve the effective resolution of the CIS; and the SPAD pixel does not include a complex counter, which simplifies the composition and complexity of the circuit on the chip, can provide space for more auxiliary modules, and also makes it possible to have the same size of logic layer and pixel layer chips.

[0043] In some optional embodiments, such as Figure 4 As shown, when a is equal to 1, the registers 12 of multiple SPAD pixels 1 in the same column are electrically connected in sequence.

[0044] In this example, in the same column of SPAD pixels, the registers 12 in each row of SPAD pixels 1 are electrically connected to the corresponding registers 12 in the SPAD pixels 1 corresponding to the next row (Row). Exemplarily, all SPAD pixels on each row (Row) can receive the same pixel control signal provided by the clock and control circuit, thereby realizing row-by-row scanning.

[0045] In the same column of SPAD pixels, the signal output by the SPAD on each row in one time period is received by the register in the SPAD pixel and transferred to the register in the SPAD pixel on the next row in the next time period. After being transferred to the register in the last row of SPAD pixels, the register in the last row of SPAD pixels outputs the signal. For example, the output end of the register in the last row of SPAD pixels is electrically connected to the column scanning circuit, and the register in the last row of SPAD pixels can output the signal to the column scanning circuit. The column scanning circuit can continuously scan the SPAD pixel signal transmitted from each column and output it to the signal processing circuit. Finally, the port circuit outputs the final signal to the outside of the chip.

[0046] Exemplarily, in the same column, within a scanning frame, the registers in the first to last rows of SPAD pixels sequentially transfer the signals generated by the photosensitization of the first row of SPAD pixels, and the registers in the last row of SPAD pixels output the signals generated by the first row of SPAD pixels. Next, the registers in the second to last rows of SPAD pixels sequentially transfer the signals generated by the photosensitization of the second row of SPAD pixels, and the registers in the last row of SPAD pixels output the signals generated by the second row of SPAD pixels. Next, the registers in the third to last rows of SPAD pixels sequentially transfer the signals generated by the photosensitization of the third row of SPAD pixels, and the registers in the last row of SPAD pixels output the signals generated by the third row of SPAD pixels. Until the signals generated by the photosensitization of the last row of SPAD pixels are directly output by the registers in the last row of SPAD pixels.

[0047] In some optional embodiments, such as Figure 5 As shown, when a>1, the output end of the register 12 of the i+bth SPAD pixel 1 in the same column of SPAD pixels 1 is electrically connected to the input end of the register 12 of the i+a+bth SPAD pixel 1, and b is any one from 1 to a-1. That is, the registers of the embodiment of the present application are cascaded in alternate rows.

[0048] As an example, if a=2, then b=1. For example, a pixel array has 8 rows of SPAD pixels.

[0049] When i=1, in the same column of SPAD pixels, the output end of the register of the SPAD pixels in the 1st row is electrically connected to the input end of the register of the SPAD pixels in the 3rd row, and the output end of the register of the SPAD pixels in the 2nd row is electrically connected to the input end of the register of the SPAD pixels in the 4th row.

[0050] When i=5, in the same column of SPAD pixels, the output end of the register of the 5th row of SPAD pixels is electrically connected to the input end of the register of the 7th row of SPAD pixels, and the output end of the register of the 6th row of SPAD pixels is electrically connected to the input end of the register of the 8th row of SPAD pixels.

[0051] In this example, in the same column, the registers in the 1st, 3rd, 5th, and 7th rows of SPAD pixels constitute a first shift register, which sequentially transfers the signals generated by the photosensitization of the 1st, 3rd, 5th, and 7th rows of SPAD pixels, and outputs them from the registers in the 7th row of SPAD pixels. The registers in the 2nd, 4th, 6th, and 8th rows of SPAD pixels constitute a second shift register, which sequentially transfers the signals generated by the photosensitization of the 2nd, 4th, 6th, and 8th rows of SPAD pixels, and outputs them from the registers in the 8th row of SPAD pixels.

[0052] Exemplarily, all SPAD pixels on multiple rows (Row) can receive the same pixel control signal provided by the clock and control circuit, thereby realizing multi-row scanning. For example, in the above example, the 1st and 2nd rows of SPAD pixels are scanned simultaneously, then the 3rd and 4th rows of SPAD pixels are scanned simultaneously, then the 5th and 6th rows of SPAD pixels are scanned simultaneously, and finally the 7th and 8th rows of SPAD pixels are scanned simultaneously. That is to say, in this example, 2 rows of SPAD pixels can be scanned simultaneously.

[0053] As another example, a=3, then b=1 or 2. For example, a pixel array has 12 rows of SPAD pixels.

[0054] When i=1, in the same column of SPAD pixels, the output end of the register of the SPAD pixels in the 1st row is electrically connected to the input end of the register of the SPAD pixels in the 4th row; when b=1, the output end of the register of the SPAD pixels in the 2nd row is electrically connected to the input end of the register of the SPAD pixels in the 5th row; when b=2, the output end of the register of the SPAD pixels in the 3rd row is electrically connected to the input end of the register of the SPAD pixels in the 6th row.

[0055] When i=7, in the same column of SPAD pixels, the output end of the register of the SPAD pixels in the 7th row is electrically connected to the input end of the register of the SPAD pixels in the 10th row; when b=1, the output end of the register of the SPAD pixels in the 8th row is electrically connected to the input end of the register of the SPAD pixels in the 11th row; when b=2, the output end of the register of the SPAD pixels in the 9th row is electrically connected to the input end of the register of the SPAD pixels in the 12th row.

[0056] In this example, in the same column, the registers in the 1st, 4th, 7th, and 10th rows of SPAD pixels constitute the third shift register, which sequentially transfers the signals generated by the photosensitization of the 1st, 4th, 7th, and 10th rows of SPAD pixels, and outputs them from the registers in the 10th row of SPAD pixels. The registers in the 2nd, 5th, 8th, and 11th rows of SPAD pixels constitute the fourth shift register, which sequentially transfers the signals generated by the photosensitization of the 2nd, 5th, 8th, and 11th rows of SPAD pixels, and outputs them from the registers in the 11th row of SPAD pixels. The registers in the 3rd, 6th, 9th, and 12th rows of SPAD pixels constitute the fifth shift register, which sequentially transfers the signals generated by the photosensitization of the 3rd, 6th, 9th, and 12th rows of SPAD pixels, and outputs them from the registers in the 12th row of SPAD pixels.

[0057] In this example, 3 rows of SPAD pixels can be scanned simultaneously. For example, in the above example, the 1st, 2nd, and 3rd rows of SPAD pixels are scanned simultaneously, then the 4th, 5th, and 6th rows of SPAD pixels are scanned simultaneously, then the 7th, 8th, and 9th rows of SPAD pixels are scanned simultaneously, and finally the 10th, 11th, and 12th rows of SPAD pixels are scanned simultaneously.

[0058] It is understandable that when a>1, that is, when the registers are cascaded in alternate rows, a rows of SPAD pixels can be scanned simultaneously. Scanning multiple rows of pixels simultaneously can speed up the scanning speed.

[0059] In some embodiments, Figure 6 As shown, the SPAD pixel also includes a first switch device 13, a shaping circuit 14, and a selector 15, and the register 12 includes a D flip-flop. Among them, the shaping circuit 14 includes a NOT gate, and the selector 15 includes a multiplexer (Multiplexer, MUX). The shaping circuit 14 is used to convert the sensing signal of the SPAD into a square wave pulse signal, and the selector 15 is used to selectively output the signal of its first input terminal or the second input terminal.

[0060] The first switch device 13 is connected in series with the SPAD. Specifically, the first end of the first switch device 13 is used to connect the first voltage VDD, and the second end of the first switch device 13 is used to access the control signal S CLK The third end of the first switch device 13 is connected to the first end of the SPAD, and the second end of the SPAD is used to connect to a second voltage VSS, which is lower than the first voltage.

[0061] The first switch device 13 can be implemented by a MOS tube, for example, a PMOS or an NMOS. When a PMOS is selected, the source of the PMOS is connected to a first voltage, which can be a power supply voltage VDD, the drain is connected to the cathode of the SPAD, and the gate is connected to the control signal S CLK When NMOS is selected, the drain of NMOS is connected to the first voltage, that is, the power supply voltage VDD, the source is connected to the cathode of SPAD, and the gate is connected to the control signal S CLK ; The anode of SPAD can be connected to a second voltage, which can be grounded or connected to a negative voltage VSS.

[0062] The connection point between the first switching device 13 and the SPAD is electrically connected to the input end of the shaping circuit 14, the output end of the shaping circuit 14 is electrically connected to the first input end of the selector 15, the output end of the selector 15 is electrically connected to the input end of the D flip-flop, and in the two SPAD pixels 1 belonging to the two cascaded registers 12, the second input end of the selector 15 in the next-level SPAD pixel 1 is electrically connected to the output end of the D flip-flop in the previous-level SPAD pixel 1.

[0063] The selection control terminal of the selector M15 is connected to the selection signal S SEL , when selecting signal S SEL Under the control of , the selector 15 transmits the signal from the shaping circuit 14 to the D flip-flop, or transmits the signal output from the previous stage D flip-flop to the current stage D flip-flop.

[0064] In this embodiment, the signal generated by the light-sensing SPAD device is converted into a digital signal by the shaping circuit 14, and then transmitted to the first input terminal of the selector 15, and then can be transmitted to the D flip-flop through the selector 15. The signal SOUT output by the D flip-flop in the previous SPAD pixel can be transmitted to the second input terminal of the selector MUX in the next SPAD pixel, and then transmitted to the D flip-flop in the next SPAD pixel through the selector 15. That is to say, under the drive of the clock signal of the D flip-flop, the D flip-flops in a column of pixels in a unit time are connected in series to form a shift register and the S flip-flops in the previous row of pixels are connected in series to form a shift register. OUT The signal is transferred to the D flip-flop of the next row, and the cycle continues until it reaches the last D flip-flop, and is output by the last D flip-flop. For example, the last D flip-flop outputs the signal to the column scan circuit module. Of course, in other examples, the signal output by the register can also be read by other reading modules, and other reading modules can be set outside the image sensor.

[0065] In this embodiment, by providing the selector 15 and the D flip-flop, the step-by-step transmission of the signal can be realized, the structure is relatively simple, and the occupied area is small.

[0066] It is understandable that for any SPAD pixel, if it needs to transfer the S OUT If the signal generated by the SPAD device itself is needed to be transferred, the first input terminal of the SPAD pixel selector 15 is connected to the input terminal of the D trigger in the SPAD pixel.

[0067] In multiple cascaded SPAD pixels, the second input terminal of the selector 15 in the first-stage SPAD pixel may be suspended, or the first-stage SPAD pixel may not include a selector, and the output terminal of the shaping circuit 14 in the first-stage SPAD pixel is directly connected to the input terminal of the D trigger.

[0068] In some embodiments, Figure 6 As shown, the selection control terminals of the multiple selectors 15 in the same row of SPAD pixels 1 are electrically connected to the same selection signal line 21, and the selection signal line 21 is used to transmit the selection signal S SELThe clock terminals of the multiple D flip-flops in the same row of SPAD pixels 1 are electrically connected to the same clock signal line 22, which is used to transmit the clock signal S required by the D flip-flops. D_CLK ; Moreover, the selection control terminals of the multiple selectors 15 in different rows of SPAD pixels 1 are electrically connected to different selection signal lines 21, and the clock terminals of the multiple D flip-flops in different rows of SPAD pixels 1 are electrically connected to different clock signal lines 22.

[0069] In this example, the input selection controls of all selectors 15 of a row of SPAD pixels share one selection signal S SEL , and all D flip-flops in a row of SPAD pixels share one D flip-flop clock signal S D_CLK The selection control signal S of the SPAD pixel selector 15 SEL The clock signal S of the D flip-flop D_CLK It is a row parallel signal.

[0070] For example, the image sensor may be provided with a clock and control circuit, and the selection signal S SEL And the clock signal S required by the D flip-flop D_CLK It can be provided by the clock and control circuit. Of course, in other examples, the selection signal S SEL And the clock signal S required by the D flip-flop D_CLK It can also be provided by other modules, and the module is arranged outside the image sensor.

[0071] It is understandable that at the same moment, all selectors MUX of the same row of SPAD pixels have the same state, that is, all selectors MUX of the same row of SPAD pixels output the signal of their first input terminal, or all selectors MUX of the same row of SPAD pixels output the signal of their second input terminal. At the same moment, all D flip-flops of the same row of SPAD pixels have the same state, that is, all D flip-flops of the same row of SPAD pixels output the signal generated by the photosensitization of the previous row of SPAD pixels, or all D flip-flops of the same row of SPAD pixels output the signal generated by the photosensitization of the current row of SPAD pixels.

[0072] In other embodiments, Figure 7 As shown, the selection control terminals of the multiple selectors 15 in the same column of SPAD pixels 1 are electrically connected to the same selection signal line 21, and the selection signal line 21 is used to transmit the selection signal S SEL The clock terminals of the multiple D flip-flops in the same column of SPAD pixels 1 are electrically connected to the same clock signal line 22, which is used to transmit the clock signal S required by the D flip-flops. D_CLKMoreover, the selection control terminals of the multiple selectors 15 in different columns of SPAD pixels are electrically connected to different selection signal lines 21, and the clock terminals of the multiple D flip-flops in different columns of SPAD pixels are electrically connected to different clock signal lines 22.

[0073] In this example, Figure 7 The examples shown are similar to Figure 6 The differences include: the input selection control of all selectors 15 of a column of SPAD pixels share one selection signal S SEL , and all D flip-flops in a column of SPAD pixels share one D flip-flop clock signal S D_CLK The selection control signal S of the SPAD pixel selector 15 SEL The clock signal S of the D flip-flop D_CLK It is a column parallel signal.

[0074] In the column parallel design, a column of SPAD pixels will receive the same selection signal S SEL And the clock signal S D_CLK When a column of SPAD pixels is selected, the selection signal S SEL And the clock signal S D_CLK The shift register in this column of SPAD pixels is controlled to operate, and the signal generated by the SPAD device in each pixel is shifted and transmitted until it is output to the D flip-flop in the last level of SPAD pixels, and output through the D flip-flop in the last level of SPAD pixels, for example, output to the column scanning circuit. Since the signals generated by all SPAD pixels in each column must be fully output before jumping to the next column, in the embodiment of the present application, the circuit for reading the register output signal (for example, the column scanning circuit) will operate at a lower scanning frequency. When implementing the reading and output steps of the SPAD pixels, the energy efficiency of the column scanning circuit module and the corresponding circuit will be greatly improved, and the workload of the column scanning circuit may be greatly reduced.

[0075] For example, Figure 6 or Figure 7 As shown, the switch control signal S CLK Control the on and off of the first switch device 13 (such as PMOS) in the SPAD. The control terminals of the multiple switch elements in the same row of SPAD pixels 1 are electrically connected to the same switch control signal line 23. The switch control signal line 23 is used to transmit the switch control signal S CLK .

[0076] Figure 6 and Figure 7 The basic structure and implementation of the clock and control circuits in the structure shown can be consistent. The differences include: Figure 6The selection control signal S of the selector 15 of the SPAD pixel SEL , the clock signal S of the D flip-flop D_CLK And the switch control signal S CLK They are all parallel signals. Figure 7 The selection control signal S of the selector 15 of the SPAD pixel SEL , the clock signal S of the D flip-flop D_CLK is a column parallel signal, the switch control signal S CLK It is a row parallel signal.

[0077] In some embodiments, Figure 4 As shown, the image sensor also includes a column scanning circuit 3, and the output end of the last-stage register 12 in the multiple cascade registers 12 in the same column of SPAD pixels 1 is connected to the input end of the column scanning circuit 3. When a=1, that is, when the registers of the multiple SPAD pixels in the same column are electrically connected in sequence, the multiple input ends of the column scanning circuit 3 correspond one-to-one to the multiple SPAD pixel columns.

[0078] For example, the image sensor includes N columns of SPAD pixels 1, and the column scanning circuit 3 may include N input terminals, and the N input terminals of the column scanning circuit 3 are electrically connected to the N columns of SPAD pixels 1 in a one-to-one correspondence. In this way, in the case of row-by-row scanning, the column scanning circuit can simultaneously access the signals output by the SPAD pixels in the same row of the N columns of SPAD pixels; in the case of simultaneous scanning of multiple rows, the column scanning circuit can simultaneously access the signals output by the SPAD pixels in multiple rows of the N columns of SPAD pixels.

[0079] In other embodiments, Figure 5 As shown, a is greater than 1, the output end of the register 12 of the i+bth SPAD pixel in the same column of SPAD pixels is electrically connected to the input end of the register 12 of the i+a+bth SPAD pixel, b is any one from 1 to a-1, and the output end of the last stage register 12 cascaded by the register 12 of the i-th SPAD pixel and the output end of the last stage register 12 cascaded by the register 12 of the i+bth SPAD pixel are connected to different input ends of the column scanning circuit 3.

[0080] For example, Figure 5In the embodiment, the registers of the odd-numbered SPAD pixels in the same column are cascaded, and the registers of the even-numbered SPAD pixels in the same column are cascaded, and the registers of the last odd-numbered SPAD pixels and the last even-numbered SPAD pixels are connected to different input terminals of the column scanning circuit. For example, there are 8 SPAD pixels in a column, wherein the registers of the 1st, 3rd, 5th, and 7th SPAD pixels are cascaded, and the registers of the 2nd, 4th, 6th, and 8th SPAD pixels are cascaded, and the registers of the 7th SPAD pixel and the 8th SPAD pixel in the same column are connected to different input terminals of the column scanning circuit.

[0081] In addition, it can be understood that the last-stage registers of different columns are connected to different input terminals of the column scanning circuit.

[0082] Figure 5 Relative to Figure 4 In terms of Figure 5 The input terminals of the column scanning circuits can be doubled. Or, in other examples, the corresponding Figure 5 The cascaded manner of the registers shown can double the number of column scanning circuits. For example, the registers of the odd-numbered SPAD pixels in the same column are cascaded, and the registers of the even-numbered SPAD pixels in the same column are cascaded. Two column scanning circuits can be set, one of which is connected to the registers of the odd-numbered SPAD pixels, and the other is connected to the registers of the even-numbered SPAD pixels. Figure 4 As shown, the image sensor also includes a signal processing circuit 5 and a port circuit 6. The column scanning circuit 3 transmits the signal output by the SPAD pixel to the signal processing circuit 5. The signal processing circuit 5 processes the signal, and the processed signal is output through the port circuit 6.

[0083] As an example, Figure 8 As shown, the column scanning circuit 3 includes N input terminals, and the column scanning circuit 3 includes a gating circuit 31 and a first demultiplexer 32. In this article, the demultiplexer is (DEMUltipleXer, DEMUX). In the case where the SPAD pixel array includes N SPAD pixel columns, the first demultiplexer 32 can be an N-bit demultiplexer (N-bit DEMUX).

[0084] The gating circuit 31 includes N switches, Figure 8 The N switches are marked as SW1 to SWN, the first ends of the N switches correspond to the N input ends one by one, that is, the first ends of the N switches serve as N input ends respectively, the second ends of the N switches are electrically connected to each other, and the first demultiplexer 32 is used to control the N switches to be turned on in sequence.

[0085] As an example, please refer to Figure 4 and Figure 8 , when a=1, that is, when the registers of multiple SPAD pixels in the same column are electrically connected in sequence, for a SPAD pixel array with N columns, the output signal S of each column of SPAD pixels is OUT Can be transmitted to the column scanning circuit 3. In the column scanning circuit 3, corresponding to each column of SPAD pixels, there is a controllable switch (SW1, SW2...SWN) on the link. The control of each controllable switch comes from an N-bit first demultiplexer 32. For example, under the control of the N-bit first counter 33 or an external control signal, this first demultiplexer 32 outputs control signals (SW1, SW2...SWN) of N switches to control the opening and closing of the controllable switches. The links corresponding to all SPAD pixel columns are merged and output after passing through their respective controllable switches. In a unit time, only the switch of the link corresponding to one column of SPAD pixels is closed. Therefore, after N unit times, the signals of all columns are output. All output signals S OUT Transmitted to the signal processing circuit module for subsequent signal processing.

[0086] As another example, Figure 5 As shown, a is greater than 1, the output end of the register 12 of the i+bth SPAD pixel in the same column of SPAD pixels is electrically connected to the input end of the register 12 of the i+a+bth SPAD pixel, and b is any one of 1 to a-1. Taking a=2 as an example, the registers of the odd-numbered SPAD pixels in the same column of SPAD pixels are cascaded, and the registers of the even-numbered SPAD pixels in the same column of SPAD pixels are cascaded, then the column scanning circuit needs to be configured with two input ends for one column of SPAD pixels. For example, if there are 100 columns of SPAD pixels, the column scanning circuit can be configured with 200 input ends, and correspondingly, the column scanning circuit can be configured with 200 switches. Among them, the two switches corresponding to the same column of SPAD pixels can be turned on at the same time, or they can be turned on in time-sharing.

[0087] In some embodiments, Figure 4 As shown, the image sensor further includes a clock and control circuit 4, which is electrically connected to the SPAD pixel 1. The clock and control circuit 4 is used to provide the clock signal and control signal required by the SPAD pixel 1.

[0088] As an example, Fig. 9 As shown, the clock and control circuit 4 includes a second counter 41, a first clock circuit 42, a second clock circuit 43 and a plurality of second demultiplexers 44. For a pixel array having M rows of SPAD pixels, the second counter 41 may be an M-bit counter and the second demultiplexer 44 may be an M-bit demultiplexer.

[0089] The second counter 41 is electrically connected to multiple second demultiplexers 44, the first clock circuit 42 is electrically connected to one of the second demultiplexers 44, the second clock circuit 43 is electrically connected to another one of the second demultiplexers 44, and the multiple second demultiplexers 44 output the clock and control signals required for the SPAD pixels under the control of the second counter 41, the first clock circuit 42, and the second clock circuit 43.

[0090] For example, one of the second demultiplexers 44 outputs a selection control signal S SEL , another second demultiplexer 44 outputs a clock signal S D_CLK , and another second demultiplexer 44 outputs a switch control signal S CLK For example, the selection control signal S required by the SPAD pixel selector 15 is SEL The clock signal S required by the D flip-flop in the SPAD pixel is provided by controlling an M-bit second demultiplexer 44 through an M-bit second counter 41. D_CLK The switching control signal S is provided by an M-bit second counter 41 and another M-bit second demultiplexer 44 controlled by a first clock circuit 42. CLK The M-bit second counter 41 and the second clock circuit 43 control another M-bit second demultiplexer 44 to provide. In addition, the clock and control circuit 4 may further include a column scanning circuit controller 45, and the counter clock signal and control signal required by the column scanning circuit may also be provided by the column scanning circuit controller 45 in the clock and control circuit. For example, the clock and control circuit may further include a column scanning circuit controller, and the column scanning circuit controller is used to provide the counting clock signal / control signal required by the column scanning circuit.

[0091] In some embodiments, Figure 4 As shown, the image sensor includes a pixel layer 01 and a logic layer 02. In the drawings marked with 01 and 02 in this application, the dotted box marked with 01 represents the pixel layer, and the dotted box marked with 02 represents the logic layer. The pixel array is arranged in the pixel layer 01, and the column scanning circuit 3, the clock and control circuit 4, the signal processing circuit 5, and the port circuit 6 of the image sensor are arranged in the logic layer. It can be understood that the SPAD device and the register 12 in the SPAD pixel 1 are located in the pixel layer 01. In the case where the SPAD pixel includes a first switching device 13, a shaping circuit 14, and a selector 15, the first switching device 13, the shaping circuit 14, and the selector 15 are also located in the pixel layer 01.

[0092] In this embodiment, the circuit layout on the logic layer chip is changed, and no digital counters or similar circuits are used at all. That is, counters corresponding to SPAD pixels are no longer set on the logic layer, which greatly simplifies the composition and complexity of the circuits on the logic layer chip, can provide space for more auxiliary modules, and makes it possible for the logic layer and pixel layer chips to be the same size.

[0093] In some embodiments, the pixel layer and the logic layer are connected via a through silicon via (TSV), or the pixel layer and the logic layer are connected via bonding, for example, a Cu-Cu bonding connection. It is understood that the signal between the pixel layer and the logic layer is transmitted via the TSV or bonding terminal.

[0094] In some embodiments, Fig.10 As shown, the SPAD pixel 1 includes a plurality of SPADs, and the plurality of SPADs are connected in parallel. Exemplarily, the plurality of SPADs in the same SPAD pixel 1 are all electrically connected to the first switch device 13 , and the plurality of SPADs share one first switch device 13 .

[0095] For some high-resolution imaging scenes, the pixels on the CIS chip can use a binning structure. For example, for a Y-in-1 pixel, the design of a single SPAD pixel can include Y SPAD devices. Fig.10 As shown, each SPAD device is connected to a separate valve switch transistor TX, which is controlled by an independent switch control signal S TX Control. Switch control signal S TX Generated by the clock and control circuit, and transmitted to each row of SPAD pixels through row parallel wires. The signals generated by all SPAD devices are collected together after passing through their respective individual valve switch transistors, sharing a quenching circuit (for example, a PMOS switch transistor) and a subsequent shaping circuit (NOT) as well as a selector MUX and a D flip-flop. For different light scenes, the analog pulse signals generated by one or more SPAD devices will increase in number in the time domain. For example, in a dark scene, all SPAD devices are enabled to increase the unit photosensitivity area. After the valve switch transistor corresponding to each SPAD device is turned on, it is connected to the PMOS transistor to complete the charging process after quenching. In a bright scene, due to the large number of photons, one SPAD device can be enabled by the switch control signal STX, and the transistors TX corresponding to other SPAD devices remain disconnected.

[0096] It is understandable that the transistors TX1 to TXY may be electrically connected to the clock and control circuit via different signal lines, respectively.

[0097] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, including a central processing unit and an image sensor as described in any of the above embodiments. It can be understood that the electronic device has the beneficial effects of the image sensor provided in the embodiment of the present application, and the specific description of the image sensor in the above embodiments can be referred to, and this embodiment will not be repeated here.

[0098] For example, see Fig.11 The electronic device includes N compressed camera modules (Compact Camera Module, CCM), each of which is provided with an image sensor; each of the image sensors is connected to the image signal processing ISP module in the central processing unit.

[0099] As a photosensitive component, the image sensor CIS chip is the core component of the compression camera module CCM. At present, the system structure of a typical mobile communication device represented by a mobile phone is as follows: Fig.11 As shown. N CCM module systems may be provided, each CCM module is equipped with a CIS chip, and the CIS chip communicates bidirectionally with the central processor such as the application processor (AP) or the ISP module in the system on chip (SoC) through a port link. The AP / SoC sends a control signal to the CIS chip in each CCM, and the CIS generates an image signal and transmits it back to the ISP module for back-end processing.

[0100] It should be noted that this embodiment is Figure 4 The implementation method of the electronic device corresponding to the illustrated embodiment can be found in the relevant introduction in the aforementioned embodiment for its specific implementation method, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0101] The electronic device may be a terminal or other device other than a terminal. For example, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc. It may also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., and the embodiments of the present application are not specifically limited.

[0102] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0103] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. An image sensor, characterized in that: It includes a SPAD pixel array, which includes SPAD pixels arranged in multiple rows and columns, and the SPAD pixels include a SPAD and a register, the register is electrically connected to the SPAD, and the output end of the register of the i-th SPAD pixel in the same column of SPAD pixels is electrically connected to the input end of the register of the i+a-th SPAD pixel, and the output end of the last stage register of multiple cascade registers in the same column of SPAD pixels is connected to the input end of the column scanning circuit, where a is greater than or equal to 1.

2. The image sensor according to claim 1, characterized in that The a is equal to 1, and the registers of the plurality of SPAD pixels in the same column are electrically connected in sequence.

3. The image sensor according to claim 1, characterized in that said a is greater than 1, The output end of the register of the i+bth SPAD pixel in the same column of SPAD pixels is electrically connected to the input end of the register of the i+a+bth SPAD pixel, where b is any one from 1 to a-1.

4. The image sensor according to any one of claims 1 to 3, characterized in that: The SPAD pixel further includes a first switch device, a shaping circuit, and a selector, and the register includes a D flip-flop; The first switch device and the SPAD are connected in series, the connection point between the first switch device and the SPAD is electrically connected to the input end of the shaping circuit, the output end of the shaping circuit is electrically connected to the first input end of the selector, the output end of the selector is electrically connected to the input end of the D flip-flop, and in the two SPAD pixels to which the two cascaded registers belong, the second input end of the selector in the next-level SPAD pixel is electrically connected to the output end of the D flip-flop in the previous-level SPAD pixel; The shaping circuit is used to convert the sensing signal of the SPAD into a square wave pulse signal, and the selector is used to selectively output the signal of the first input terminal or the second input terminal thereof.

5. The image sensor according to claim 4, characterized in that: The selection control terminals of the plurality of selectors in the same row of SPAD pixels are electrically connected to the same selection signal line, and the clock terminals of the plurality of D flip-flops in the same row of SPAD pixels are electrically connected to the same clock signal line; Furthermore, the selection control terminals of the multiple selectors in different rows of SPAD pixels are electrically connected to different selection signal lines, and the clock terminals of the multiple D flip-flops in different rows of SPAD pixels are electrically connected to different clock signal lines.

6. The image sensor according to claim 4, characterized in that: The selection control terminals of the plurality of selectors in the same column of SPAD pixels are electrically connected to the same selection signal line, and the clock terminals of the plurality of D flip-flops in the same column of SPAD pixels are electrically connected to the same clock signal line; Furthermore, the selection control terminals of the multiple selectors in different columns of SPAD pixels are electrically connected to different selection signal lines, and the clock terminals of the multiple D flip-flops in different columns of SPAD pixels are electrically connected to different clock signal lines.

7. The image sensor according to any one of claims 1 to 3, characterized in that: The image sensor further includes the column scanning circuit; a is equal to 1, and the multiple input terminals of the column scanning circuit correspond one-to-one to the multiple SPAD pixel columns; Alternatively, a is greater than 1, the output end of the register of the i+bth SPAD pixel in the same column of SPAD pixels is electrically connected to the input end of the register of the i+a+bth SPAD pixel, b is any one from 1 to a-1, and the output end of the last stage register cascaded with the register of the i-th SPAD pixel and the output end of the last stage register cascaded with the register of the i+bth SPAD pixel are connected to different input ends of the column scanning circuit.

8. The image sensor according to claim 7, characterized in that: The column scanning circuit includes N input terminals, and the column scanning circuit includes a gating circuit and a first demultiplexer; The gating circuit includes N switches, the first ends of the N switches correspond to the N input ends one by one, the second ends of the N switches are electrically connected to each other, and the first demultiplexer is used to control the N switches to be turned on in sequence.

9. The image sensor according to any one of claims 1 to 3, characterized in that: The image sensor further includes a clock and control circuit, wherein the clock and control circuit is electrically connected to the SPAD pixel; The clock and control circuit includes a counter, a first clock circuit, a second clock circuit and multiple second demultiplexers. The counter, the first clock circuit and the second clock circuit are all electrically connected to the multiple second demultiplexers. The multiple second demultiplexers output the clock and control signals required by the SPAD pixels under the control of the counter, the first clock circuit and the second clock circuit.

10. The image sensor according to any one of claims 1 to 3, characterized in that: The image sensor comprises a pixel layer and a logic layer, the SPAD pixel array is arranged in the pixel layer, and the column scanning circuit, clock and control circuit, signal processing circuit and port circuit of the image sensor are arranged in the logic layer.

11. The image sensor according to any one of claims 1 to 3, characterized in that: The SPAD pixel includes a plurality of SPADs, and the plurality of SPADs are connected in parallel.

12. An electronic device, characterized in that: The device comprises a central processing unit and an image sensor as claimed in any one of claims 1 to 11.

Images