VDMOS chip for lithium battery charging system and preparation method thereof

Abstract

The present invention discloses a VDMOS chip for a lithium battery charging system, including a substrate, a first epitaxial layer, a groove extending from the first epitaxial layer to the substrate, a second epitaxial layer and a third epitaxial layer staggered from the first epitaxial layer into the groove, an oxide layer on both sides of the groove on the first epitaxial layer, an opening between the oxide layers and a polysilicon layer in the opening, a first injection region connected to part of the oxide layer formed in the first epitaxial layer on both sides of the groove, a second injection region on the first injection region in the first epitaxial layer, a third injection region extending from the substrate into the groove and connected to the first epitaxial layer and the third epitaxial layer, a dielectric layer connected to part of the second injection region on the polysilicon layer. The present invention also provides a method for preparing a VDMOS chip for a lithium battery charging system, which effectively ensures that the battery and the charging system are protected from over-temperature damage, and improves the over-temperature feedback speed and the reliability of the lithium battery charging system.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor chips, and in particular relates to a VDMOS chip for a lithium battery charging system and a preparation method thereof. Background Art

[0002] With the development of science and technology, lithium batteries are widely used in life, military and other fields because of their special charging and discharging characteristics. However, lithium batteries have certain limitations in use. For example, if the current is not limited during charging, the battery will overheat or even explode during charging, posing a great threat to personal safety. Moreover, if the charging temperature of lithium batteries is too high, the battery life will be reduced rapidly. Therefore, it is necessary to effectively control and manage the charging of lithium batteries to avoid overheating of lithium batteries. For the above reasons, temperature sensors and over-temperature protection circuits must be arranged in the lithium battery charging system to detect the temperature and protect the charging system from over-temperature. The temperature sensor can monitor the temperature of the system in real time and feed back the temperature information to the over-temperature protection circuit. When the temperature of the system is too high, the over-temperature protection circuit can shut down the VDMOS in time to prevent the lithium battery from being damaged due to over-temperature. In commonly used charging systems, temperature detection and over-temperature protection structures are directly connected to the circuit. The over-temperature protection structure needs to control the opening or closing of two VDMOS devices, but cannot accurately and timely extract the working environment temperature of the devices, causing the lithium battery to be damaged by overheating in the charging system. Adding the temperature detection structure to the charging system increases circuit losses, thereby reducing the reliability of the lithium battery charging system. Summary of the invention

[0003] In view of this, the present invention provides a VDMOS chip for a lithium battery charging system and a preparation method thereof, which can accurately and timely extract the working environment temperature of the device and improve the over-temperature feedback speed, to solve the above-mentioned technical problems, and specifically adopts the following technical solutions to achieve this.

[0004] In a first aspect, the present invention provides a VDMOS chip for a lithium battery charging system, comprising:

[0005] a substrate of a first conductivity type;

[0006] A first epitaxial layer of a first conductivity type is formed on the substrate, a trench is extended from the upper surface of the first epitaxial layer to the substrate, and a second epitaxial layer of a second conductivity type and a third epitaxial layer of the first conductivity type are alternately formed from the upper surface of the first epitaxial layer into the trench;

[0007] An oxide layer formed on the first epitaxial layer and located at both sides of the trench, an opening located between the oxide layers and corresponding to the second epitaxial layer, and a polysilicon layer formed on the oxide layer and located in the opening;

[0008] A first implantation region of the second conductivity type formed in the first epitaxial layer at both sides of the trench and connected to a portion of the oxide layer, a second implantation region of the first conductivity type formed in the first epitaxial layer and located on the first implantation region and connected to a portion of the oxide layer, and a third implantation region of the second conductivity type extending from the lower surface of the substrate to the trench and connected to the first epitaxial layer and the third epitaxial layer;

[0009] A dielectric layer formed on the polysilicon layer and connected to a portion of the second injection region, a first contact hole penetrating the dielectric layer and located on the upper surface of the polysilicon layer, a second contact hole located on a portion of the first injection region and a portion of the second injection region, a first metal layer formed in the first contact hole, a second metal layer in the second contact hole, and a third metal layer formed at intervals on the lower surface of the substrate and arranged corresponding to the first metal layer and the second metal layer.

[0010] In a second aspect, the present invention further provides a method for preparing a VDMOS chip for a lithium battery charging system, comprising the following steps:

[0011] Providing a substrate of a first conductivity type, and forming a first epitaxial layer of the first conductivity type on the substrate;

[0012] Forming a trench by photolithography from the upper surface of the first epitaxial layer to the substrate, and alternately filling a second epitaxial layer of the second conductivity type and a third epitaxial layer of the first conductivity type into the trench from the upper surface of the first epitaxial layer;

[0013] An oxide layer is formed on the first epitaxial layer and on both sides of the trench, an opening is formed between the oxide layers and corresponding to the second epitaxial layer, and a polysilicon layer is formed on the oxide layer and in the opening;

[0014] forming a first implantation region of the second conductivity type connected to a portion of the oxide layer in the first epitaxial layer at both sides of the trench, and forming a second implantation region of the first conductivity type located on the first implantation region and connected to a portion of the oxide layer in the first epitaxial layer;

[0015] Forming a dielectric layer connected to a portion of the second injection region on the polysilicon layer, forming a first contact hole penetrating the dielectric layer and located on the upper surface of the polysilicon layer, forming a second contact hole located on a portion of the first injection region and a portion of the second injection region, forming a first metal layer in the first contact hole, and forming a second metal layer in the second contact hole;

[0016] A third implantation region of the second conductivity type is formed from the lower surface of the substrate into the groove and connected to the first epitaxial layer and the third epitaxial layer, and a third metal layer is formed on the lower surface of the substrate and is arranged corresponding to the first metal layer and the second metal layer.

[0017] The present invention provides a VDMOS chip for a lithium battery charging system and a preparation method thereof, which has the following beneficial effects compared with the prior art:

[0018] The invention forms a first epitaxial layer on a substrate, and forms a groove extending from the epitaxial layer to the substrate, wherein the bottom of the groove contacts the substrate, and the second epitaxial layer and the third epitaxial layer of different conductive types are filled in the groove to form a PN junction group in the groove, and an oxide layer arranged at intervals is formed on the first epitaxial layer and the groove as an opening between the gate oxide layer and the oxide layer, and a polysilicon layer is formed in the opening and on the oxide layer, and a first injection region and a second injection region of different conductive types are formed in the first epitaxial layer, and a first metal layer is formed on the polysilicon layer corresponding to the opening, and a second metal layer is formed on the first injection region and the second injection region, and the second metal layer is symmetrically arranged with respect to the first metal layer, and a third injection region is arranged corresponding to the first metal layer and is located in the substrate and connected with the first epitaxial layer and the third epitaxial layer. Integrating the temperature detection and over-temperature protection structure into the VDMOS device simplifies the circuit structure of the lithium battery charging system and reduces the manufacturing cost of the device. At the same time, it can accurately and timely extract the working environment temperature information of the device. When the temperature is too high, the device automatically cuts off the charging current, which can effectively protect the battery and charging system from over-temperature damage, and also improves the over-temperature feedback speed, thereby improving the working reliability of the lithium battery charging system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A flow chart of a method for preparing a VDMOS chip for a lithium battery charging system provided by an embodiment of the present invention;

[0021] Figures 2 to 7 A process diagram of a method for preparing a VDMOS chip for a lithium battery charging system provided by an embodiment of the present invention;

[0022] Figure 8 A circuit diagram of a lithium battery charging system provided by an embodiment of the present invention;

[0023] Fig. 9 A schematic diagram of a VDMOS chip for a lithium battery charging system provided in an embodiment of the present invention.

[0024] The main component symbols are described as follows:

[0025] 10-substrate; 11-first epitaxial layer; 12-groove; 13-second epitaxial layer; 14-third epitaxial layer; 15-oxide layer; 16-opening; 17-polysilicon layer; 18-first injection region; 19-second injection region; 20-third injection region; 21-dielectric layer; 22-first contact hole; 23-second contact hole; 24-first metal layer; 25-second metal layer; 26-third metal layer. DETAILED DESCRIPTION

[0026] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0027] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may also be a centered element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a centered element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0028] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0029] See also Figure 1 , Figures 2 to 7The present invention provides a method for preparing a VDMOS chip for a lithium battery charging system, comprising the following steps:

[0030] S1: providing a substrate 10 of a first conductivity type, and forming a first epitaxial layer of a first conductivity type on the substrate 10;

[0031] See also Figure 2 In this embodiment, the first conductivity type is N type, the second conductivity type is P type, the ions of the first conductivity type are phosphorus, and the ions of the second conductivity type are boron. The substrate 10 is divided into two types: a drawing substrate and a chemical substrate. The drawing substrate refers to a picture or text that fills the entire page to form a background. The chemical substrate is commonly made of nitride substrate material, and silicon is preferably used as the substrate material, which is low in price and easy to implement. The first epitaxial layer 11 has the same conductivity type as the substrate 10. The first epitaxial layer 11 is prepared by epitaxial growth technology, which is convenient for subsequent preparation processes.

[0032] S2: forming a trench 12 by photolithography from the upper surface of the first epitaxial layer 11 to the substrate 10, and alternately filling a second epitaxial layer 13 of the second conductivity type and a third epitaxial layer 14 of the first conductivity type from the upper surface of the first epitaxial layer 11 into the trench 12;

[0033] See also Figure 3 In this embodiment, a photoresist is firstly coated on the first epitaxial layer 11 at intervals (not shown in the figure), and a groove 12 extending into the substrate 10 is formed by photolithography along the middle position of the first epitaxial layer 11, that is, the area not covered by the photoresist. The resistivity range of the second epitaxial layer 13 and the third epitaxial layer 14 is 0.5-2ohm.cm. The second epitaxial layer 13 and the third epitaxial layer 14 are alternately arranged in the groove 12. The second epitaxial layer 13 and the third epitaxial layer 14 have different conductivity types and can form multiple PN junctions. The second epitaxial layer 13 is located at the top of the groove 12, and the third epitaxial layer 14 is located at the bottom of the groove 12. Preferably, three groups, namely three second epitaxial layers 13 and three third epitaxial layers 14, are used, and the thickness of the second epitaxial layer 13 and the third epitaxial layer 14 is the same.

[0034] It should be noted that a trench 12 is formed on the front side of the silicon wafer by dry etching, the bottom of the trench 12 is in contact with the N-type substrate 10, and a P / N-type epitaxial is filled in the trench 12. There is at least one group of P / N structures, and the specific number and epitaxial doping can be determined according to the VDMOS turn-on voltage and the safe operating temperature. The higher the doping concentration, the lower the breakdown voltage of the PN group, the more the number of PN junctions, the higher the breakdown voltage of the PN group, the higher the breakdown voltage, the higher the over-temperature protection start-up temperature, thereby improving the voltage resistance and over-temperature protection capability of the device.

[0035] S3: forming an oxide layer 15 on the first epitaxial layer 11 and on both sides of the trench 12, forming an opening 16 corresponding to the second epitaxial layer 13 between the oxide layers 15, and forming a polysilicon layer 17 on the oxide layer 15 and in the opening 16;

[0036] See also Figure 4 In this embodiment, a layer of silicon oxide is first deposited on the first epitaxial layer 11 and the groove 12, and the corresponding part of the silicon oxide on both sides of the first epitaxial layer 11 and the second epitaxial layer 13 is removed, and the silicon oxide on both sides of the groove 12 is retained to form an oxide layer 15 arranged at intervals, the oxide layer 15 is a gate oxide layer, the thickness of the oxide layer 15 is 300-1500Å, and an opening 16 is formed between the oxide layers 15. Then, polysilicon is deposited in the oxide layer 15 and the opening 16 to form a polysilicon layer 17, the polysilicon layer 17 is connected to the second epitaxial layer 13 in the groove 12, the polysilicon layer 17 is a gate polysilicon, and the thickness of the polysilicon layer 17 is greater than the oxide layer 15.

[0037] S4: forming a first implantation region 18 of the second conductivity type connected to a portion of the oxide layer 15 in the first epitaxial layer 11 at both sides of the trench 12, and forming a second implantation region 19 of the first conductivity type located on the first implantation region 18 and connected to a portion of the oxide layer 15 in the first epitaxial layer 11;

[0038] See also Figure 5 In this embodiment, ion implantation is performed into the first epitaxial layer 11 not covered by the oxide layer 15, and second conductive type ions are implanted and diffused to form a first implantation region 18, and then first conductive type ions are implanted into the first implantation region 18 and diffused to form a second implantation region 19. Both the first implantation region 18 and the second implantation region 19 are connected to the oxide layer 15, and the junction depth of the first implantation region 18 is greater than the junction depth of the second implantation region 19. The first implantation region 18 is a P-type body region, and the second implantation region 19 is an N-type source region. The thickness of the oxide layer 15 is 300-1500Å, the implantation dose of the first implantation region 18 is 1E12-1E13, and the implantation dose of the second implantation region 19 is 1E15-1E16. A conductive channel can be formed under the oxide layer 15, thereby improving the working stability of the device.

[0039] S5: forming a dielectric layer 21 connected to a portion of the second injection region 19 on the polysilicon layer 17, forming a first contact hole 22 penetrating the dielectric layer 21 and located on the upper surface of the polysilicon layer 17, forming a second contact hole 23 located on a portion of the first injection region 18 and a portion of the second injection region 19, forming a first metal layer 24 in the first contact hole 22, and forming a second metal layer 25 in the second contact hole 23;

[0040] See also Figure 6In this embodiment, dielectric growth is first performed on the first injection region 18, the second injection region 19 and the polysilicon layer 17, and the dielectric corresponding to the opening 16 is removed by dry etching to form a first contact hole 22. The width of the first contact hole 22 is smaller than the width of the opening 16. Similarly, the dielectric on the first injection region 18 and part of the second injection region 19 forms a second contact hole 23, and the dielectric part located on the second injection region 19 is retained, which can ensure that the oxide layer 15 is isolated from the metal and reduce the conduction loss of the device. Metal is deposited on the first contact hole 22, the second contact hole 23 and the dielectric layer 21 by magnetron sputtering technology, and the metal on the dielectric layer 21 is removed to form a first metal layer 24 and a second metal layer 25 arranged at intervals. The second metal layer 25 is symmetrically arranged with respect to the first metal layer 24, and the thickness of the first metal layer 24 is greater than the thickness of the first contact hole 22, and the thickness of the second metal layer 25 is greater than the thickness of the second contact hole 23, so as to facilitate the extraction of electrodes and the access to the circuit.

[0041] S6: A third injection region 20 of the second conductivity type connected to the first epitaxial layer 11 and the third epitaxial layer 14 is formed from the lower surface of the substrate 10 into the groove 12, and a third metal layer 26 corresponding to the first metal layer 24 and the second metal layer 25 is formed on the lower surface of the substrate 10.

[0042] See also Figure 7 In this embodiment, the second conductive type ions are first implanted into the substrate 10 at the position corresponding to the groove 12 along the lower surface of the substrate 10 and diffused to form a third implant region 20. The third implant region 20 is connected to the third epitaxial layer 14 and the first epitaxial layer 11 at the bottom of the groove 12. The projection area of ​​the third implant region 20 in the direction perpendicular to the substrate 10 is larger than the projection area of ​​the third metal layer 26 in the direction perpendicular to the substrate 10. The implantation dose of the third implant region 20 is 1E16, and the junction depth of the third implant region 20 is larger than the thickness of the substrate 10. The third implant region 20 and the substrate 10 have different conductivity types and can form a PN junction. The third implant region 20 and the first epitaxial layer 11 and the third epitaxial layer 14 have different conductivity types and can form a PN junction. The third metal layer 26 is arranged at intervals on the lower surface of the substrate 10, preferably three third metal layers 26, the third metal layer 26 located on the lower surface of the third injection region 20 is used as a gate metal layer and is grounded, the third metal layer 26 on both sides of the substrate 10 is a drain metal, the first metal layer 24 is a gate metal, and the second metal layer 25 is a source metal. The front structure of the device is first formed according to the conventional semiconductor manufacturing process, and then the back structure of the device is formed to simplify the device preparation process and reduce the manufacturing cost.

[0043] See again Figure 7 The present invention also provides a VDMOS chip for a lithium battery charging system, comprising:

[0044] A substrate 10 of a first conductivity type;

[0045] A first epitaxial layer 11 of a first conductivity type is formed on the substrate 10, a trench 12 is extended from the upper surface of the first epitaxial layer 11 to the substrate 10, and a second epitaxial layer 13 of a second conductivity type and a third epitaxial layer 14 of the first conductivity type are alternately formed from the upper surface of the first epitaxial layer 11 into the trench 12;

[0046] An oxide layer 15 formed on the first epitaxial layer 11 and located on both sides of the trench 12, an opening 16 located between the oxide layers 15 and corresponding to the second epitaxial layer 13, and a polysilicon layer 17 formed on the oxide layer 15 and located in the opening 16;

[0047] A first implantation region 18 of the second conductivity type formed in the first epitaxial layer 11 on both sides of the trench 12 and connected to a portion of the oxide layer 15, a second implantation region 19 of the first conductivity type formed in the first epitaxial layer 11 and located on the first implantation region 11 and connected to a portion of the oxide layer 15, and a third implantation region 20 of the second conductivity type extending from the lower surface of the substrate 10 to the trench 12 and connected to the first epitaxial layer 11 and the third epitaxial layer 14;

[0048] A dielectric layer 21 formed on the polysilicon layer 17 and connected to a portion of the second injection region 19, a first contact hole 22 penetrating the dielectric layer 21 and located on the upper surface of the polysilicon layer 17, a second contact hole 23 located on a portion of the first injection region 18 and a portion of the second injection region 19, a first metal layer 24 formed in the first contact hole 22, a second metal layer 25 in the second contact hole 23, and a third metal layer 26 formed at intervals on the lower surface of the substrate 10 and arranged corresponding to the first metal layer 24 and the second metal layer 25.

[0049] In this embodiment, the first conductivity type is N type, the second conductivity type is P type, the thickness of the second epitaxial layer 13 is the same as the thickness of the third epitaxial layer 14, the second metal layer 25 is symmetrically arranged about the first metal layer 24, the width of the first contact hole 22 is smaller than the width of the opening 16, the thickness of the polysilicon layer 17 is greater than the thickness of the oxide layer 15, and the thickness of the first metal layer 24 is greater than the thickness of the dielectric layer 21. In order to effectively suppress the short channel effect and maintain a good subthreshold slope, the thickness of the gate oxide layer should decrease in the same proportion as the channel length, and the performance of the MOS transistor depends on the thickness of the gate oxide layer. The reduction in the thickness of the gate oxide layer enhances the current driving capability of the transistor and improves the speed and power characteristics. The bottom of the trench 12 is located in the substrate 10 to form multiple groups of PN junctions, the oxide layer 15 is located on both sides of the trench 12 and a polysilicon layer 17 is formed on the oxide layer 15 and in the opening 16, and the polysilicon layer 17 is connected to the second epitaxial layer 13 to form a current path.

[0050] It should be noted that three metal layers are formed on the front side of the device, and three third metal layers 26 are correspondingly formed on the back side of the device. The temperature sensor can be integrated into the VDMOS device, and the working environment temperature information of the device can be accurately and timely extracted. When the temperature is too high, the device automatically cuts off the charging current. The application in the lithium battery charging system can effectively protect the lithium battery and the charging system from over-temperature damage. The new device of the present invention can be used in the charging system to reduce the manufacturing cost, speed up the over-temperature feedback speed and improve the reliability of the system.

[0051] See also Figure 8 It should be understood that the new VDMOS chip integrates a temperature detection system. When the temperature is too high, it can send an electrical signal to start charging in the power control system, cut off the current, and protect the safety of the lithium battery and the system. The lithium battery charging system only needs to use a new VDMOS chip to complete the functions of VDMOS1, VDMOS2 and the temperature detection system in the prior art, and the temperature detection structure is integrated in the VDMOS, which improves the response speed and temperature measurement accuracy, and also reduces the manufacturing cost of the charging system.

[0052] See also Fig. 9The third metal layer 26 located on the lower surface of the third injection region 20, i.e., the back gate metal, is connected to zero potential, the first metal layer 24, i.e., the front gate metal, is connected to the control start port of the control circuit, the third metal layer 26, i.e., the drain metal, on the lower surface of the substrate 10 is connected to the input end of the charging circuit, and the second metal layer 25, i.e., the front source metal, is connected to the lithium battery. The temperature detection and over-temperature protection structure of the new VDMOS exists in the dotted box. The power control circuit controls the VDMOS to turn on through the voltage on the gate metal. Charging starts after VDMOS is turned on. At normal temperature, the breakdown voltage of the PN junction group composed of the P / N / P / N epitaxial structure in the dotted box is greater than the turn-on voltage of VDMOS. After the control circuit outputs a high voltage to turn on VDMOS, the device is turned on normally. As the operating temperature increases, the breakdown voltage of the PN junction group gradually decreases. After exceeding the safe operating temperature, the breakdown voltage is less than the turn-on voltage of VDMOS. The high voltage applied to the gate causes the PN junction group to turn on, the gate is turned on, and VDMOS cannot be turned on. VDMOS is disconnected, the charging system stops working, and the system temperature decreases. After returning to normal, the breakdown voltage of the PN junction group is greater than the turn-on voltage of VDMOS, and charging is restored, thereby improving the working stability of the device.

[0053] The present invention provides a VDMOS chip for a lithium battery charging system and a preparation method thereof, wherein a first epitaxial layer 11 is formed on a substrate 10, a groove 12 is formed extending from the first epitaxial layer 11 to the substrate 10, the bottom of the groove 12 is in contact with the substrate 10, a second epitaxial layer 13 and a third epitaxial layer 14 of different conductive types are filled in the groove 10 to form a PN junction group in the groove 12, and an oxide layer 15 arranged at intervals is formed on the first epitaxial layer 11 and the groove 12 as a gate oxide layer and between the oxide layer 15. The opening 16 is provided, a polysilicon layer 17 is formed in the opening 16 and on the oxide layer 15, a first injection region 18 and a second injection region 19 of different conductivity types are formed in the first epitaxial layer 11, a first metal layer 24 is formed on the polysilicon layer 17 corresponding to the opening 16, a second metal layer 25 is formed on the first injection region 18 and the second injection region 19, the second metal layer 25 is symmetrically arranged with respect to the first metal layer 24, and a third injection region 20 is arranged corresponding to the first metal layer 24 and is located in the substrate 10 and connected to the first epitaxial layer 11 and the third epitaxial layer 14. The temperature detection and over-temperature protection structure are integrated in the VDMOS device, which simplifies the circuit structure of the lithium battery charging system, can accurately and timely extract the working environment temperature information of the device, and the device automatically cuts off the charging current when the temperature is too high, which can effectively protect the battery and the charging system from over-temperature damage, reduce the manufacturing cost of the device, and also improve the over-temperature feedback speed, thereby improving the working reliability of the lithium battery charging system.

[0054] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

[0055] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0056] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A VDMOS chip for a lithium battery charging system, characterized in that: include: a substrate of a first conductivity type; A first epitaxial layer of a first conductivity type is formed on the substrate, a trench is extended from the upper surface of the first epitaxial layer to the substrate, and a second epitaxial layer of a second conductivity type and a third epitaxial layer of the first conductivity type are alternately formed from the upper surface of the first epitaxial layer into the trench; An oxide layer formed on the first epitaxial layer and located at both sides of the trench, an opening located between the oxide layers and corresponding to the second epitaxial layer, and a polysilicon layer formed on the oxide layer and located in the opening; A first implantation region of the second conductivity type formed in the first epitaxial layer at both sides of the trench and connected to a portion of the oxide layer, a second implantation region of the first conductivity type formed in the first epitaxial layer and located on the first implantation region and connected to a portion of the oxide layer, and a third implantation region of the second conductivity type extending from the lower surface of the substrate to the trench and connected to the first epitaxial layer and the third epitaxial layer; A dielectric layer formed on the polysilicon layer and connected to a portion of the second injection region, a first contact hole penetrating the dielectric layer and located on the upper surface of the polysilicon layer, a second contact hole located on a portion of the first injection region and a portion of the second injection region, a first metal layer formed in the first contact hole, a second metal layer in the second contact hole, and a third metal layer formed at intervals on the lower surface of the substrate and arranged corresponding to the first metal layer and the second metal layer.

2. The VDMOS chip for a lithium battery charging system according to claim 1, characterized in that: The first conductivity type is N type, the second conductivity type is P type, and the thickness of the second epitaxial layer is the same as that of the third epitaxial layer.

3. The VDMOS chip for a lithium battery charging system according to claim 1, characterized in that: The second metal layer is symmetrically arranged with respect to the first metal layer, and the width of the first contact hole is smaller than the width of the opening.

4. The VDMOS chip for a lithium battery charging system according to claim 1, characterized in that: The thickness of the polysilicon layer is greater than the thickness of the oxide layer, and the thickness of the first metal layer is greater than the thickness of the dielectric layer.

5. A method for preparing a VDMOS chip for a lithium battery charging system, characterized in that: The following steps are involved: Providing a substrate of a first conductivity type, and forming a first epitaxial layer of the first conductivity type on the substrate; Forming a trench by photolithography from the upper surface of the first epitaxial layer to the substrate, and alternately filling a second epitaxial layer of the second conductivity type and a third epitaxial layer of the first conductivity type into the trench from the upper surface of the first epitaxial layer; An oxide layer is formed on the first epitaxial layer and on both sides of the trench, an opening is formed between the oxide layers and corresponding to the second epitaxial layer, and a polysilicon layer is formed on the oxide layer and in the opening; forming a first implantation region of the second conductivity type connected to a portion of the oxide layer in the first epitaxial layer at both sides of the trench, and forming a second implantation region of the first conductivity type located on the first implantation region and connected to a portion of the oxide layer in the first epitaxial layer; Forming a dielectric layer connected to a portion of the second injection region on the polysilicon layer, forming a first contact hole penetrating the dielectric layer and located on the upper surface of the polysilicon layer, forming a second contact hole located on a portion of the first injection region and a portion of the second injection region, forming a first metal layer in the first contact hole, and forming a second metal layer in the second contact hole; A third implantation region of the second conductivity type is formed from the lower surface of the substrate into the groove and connected to the first epitaxial layer and the third epitaxial layer, and a third metal layer is formed on the lower surface of the substrate and is arranged corresponding to the first metal layer and the second metal layer.

6. The method for preparing a VDMOS chip for a lithium battery charging system according to claim 5, characterized in that: The first conductivity type is N type, the second conductivity type is P type, and the resistivity range of the second epitaxial layer and the third epitaxial layer is 0.5-2 ohm.cm.

7. The method for preparing a VDMOS chip for a lithium battery charging system according to claim 5, characterized in that: The thickness of the oxide layer is 300-1500Å, the implantation dose of the first implantation region is 1E12-1E13, and the implantation dose of the second implantation region is 1E15-1E16.

8. The method for preparing a VDMOS chip for a lithium battery charging system according to claim 5, characterized in that: The implantation dose of the third implantation region is 1E16, and the junction depth of the third implantation region is greater than the thickness of the substrate.

9. The method for preparing a VDMOS chip for a lithium battery charging system according to claim 5, characterized in that: A projection area of ​​the third injection region in a direction perpendicular to the substrate is larger than a projection area of ​​the third metal layer in a direction perpendicular to the substrate.

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