Voltage-insensitive low-temperature drift current source

Abstract

The invention discloses a voltage-insensitive low-temperature drift current source which comprises a power supply VCC, a grounding VEE, a first resistor R1, a second resistor R2, a third resistor R3, a first NPN tube Q1, a second NPN tube Q2, a third NPN tube Q3, a fourth NPN tube Q4, a fifth NPN tube Q5, a first PNP tube Q6, a second PNP tube Q7 and an NJFET tube Jn1. According to the low-temperature drift current source, starting current is provided through the NJFETs, the resistance proportion and the transistor area ratio are adjusted, the low-temperature drift current source which is simple in structure, small in component consumption, capable of being used for a wide working voltage range and insensitive to bipolar process voltage is obtained, and the low-temperature drift current source can be achieved through the pure bipolar process and is easy to achieve and low in cost.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a voltage-insensitive low-temperature drift current source. Background Art

[0002] For an integrated circuit to work properly, a suitable static operating point must be set. Therefore, a current source is needed to provide a reasonable bias current for the internal circuit. The stability of the bias current directly affects the function and characteristics of the circuit.

[0003] The traditional current sources used in integrated circuits are simple current sources, V BE Self-biased current source and bandgap reference bias current source. The simple current source reference current depends largely on the power supply voltage, that is, the power supply voltage is highly sensitive and can only be used in circuits with fixed power supply voltages, not in circuits where the power supply voltage is adjustable within a certain range; V BE The self-biased current source reference current is insensitive to the power supply voltage and the current size depends on the transistor V BE voltage, while V BE The voltage has a negative temperature coefficient, and the reference current has a negative temperature coefficient accordingly. The traditional method with better characteristics is to use a current source with a bandgap reference bias. Since the bandgap reference voltage is insensitive to the power supply voltage and has a low temperature coefficient, the reference current generated by it is correspondingly insensitive to the power supply voltage and has a low temperature coefficient. However, this structure uses one or two error amplifiers, the circuit structure is more complex, and more components are used, thereby consuming more power supply current and die area. Power consumption and die area are very important points in integrated circuit design. Summary of the invention

[0004] The object of the present invention is to provide a voltage-insensitive low-temperature drift current source to overcome the shortcomings of the prior art, such as complex structure, large chip area and much consumables.

[0005] In order to achieve the above object, the present invention adopts the following technical solution:

[0006] A voltage-insensitive low-temperature drift current source comprises a power supply VCC, a ground VEE, a first resistor R1, a second resistor R2, a third resistor R3, a first NPN tube Q1, a second NPN tube Q2, a third NPN tube Q3, a fourth NPN tube Q4, a fifth NPN tube Q5, a first PNP tube Q6, a second PNP tube Q7, and an NJFET tube (N-channel junction field effect transistor) Jn1;

[0007] The gate of the NJFET tube Jn1 is grounded, the drain of Jn1 is connected to the power supply VCC, the source of Jn1 is connected to the collector and base of the third NPN tube Q3, the base of the fourth NPN tube Q4, and the base of the fifth NPN tube Q5; the emitter of the third NPN tube Q3 is connected to the collector of the first NPN tube Q1 and the base of the second NPN tube Q2; the base of the first NPN tube Q1 is connected to the collector of the second NPN tube Q2 and the emitter of the fourth NPN tube Q4, and the emitter of the first NPN tube Q1 is grounded; the emitter of the second NPN tube Q2 is connected to one end of the second resistor R2 , the other end of the second resistor R2 is grounded; the collector of the fourth NPN tube Q4 is connected to the base of the first PNP tube Q6, the collector of the second PNP tube Q7 and the collector of the fifth NPN tube Q5; the emitter of the fifth NPN tube Q5 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the collector of the first PNP tube Q6 is grounded, and the emitter of the first PNP tube Q6 is connected to the base of the second PNP tube Q7 and the bias voltage VB; the emitter of the second PNP tube Q7 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the power supply VCC.

[0008] Furthermore, the current source circuit provides a startup current through the NJFET tube Jn1. Since the pinch-off voltage of the NJFET is relatively small, it can be pinched off at a relatively low power supply voltage, and thus a relatively stable startup bias current can be provided within a relatively large power supply voltage range.

[0009] Furthermore, after the current source circuit is powered on, a current path is formed through the power supply VCC, the NJFET tube Jn1, the fourth NPN tube Q4 or the third NPN tube Q3, the first NPN tube Q1 or the second NPN tube Q2, the first resistor R1, and the ground VEE, driving the circuit to get rid of the zero degenerate operating point.

[0010] Furthermore, the NJFET tube Jn1 is a bipolar process parasitic structure, that is, although the NJFET tube is not a bipolar device, it can be implemented in a bipolar process without adding a photolithography plate, so the circuit structure of the current source can be implemented using a pure bipolar process. After producing a low-temperature drift reference current IREF that is insensitive to the power supply voltage, it can be mirrored to each level inside the operational amplifier through a β-enhanced current mirror to provide the required current for each level.

[0011] Furthermore, the emitter area of ​​the second NPN transistor Q2 is equal to the emitter area of ​​the fourth NPN transistor Q4. The currents of the second NPN transistor Q2 and the fourth NPN transistor Q4 are approximately equal, so the BE junction voltages of the second NPN transistor Q2 and the fourth NPN transistor Q4 are approximately equal.

[0012] Furthermore, under the influence of the current amplification factor of the NPN tube, its base current can be ignored, so the collector current of the first NPN tube Q1 is approximately equal to the collector current of the third NPN tube Q3, and the collector current of the second NPN tube Q2 is approximately equal to the collector current of the fourth NPN tube Q4.

[0013] Furthermore, the emitter area ratio of the first NPN transistor Q1, the second NPN transistor Q2, the third NPN transistor Q3, and the fourth NPN transistor Q4 is equal to the ratio of the product of the second NPN transistor Q2 and the third NPN transistor Q3 to the product of the first NPN transistor Q1 and the fourth NPN transistor Q4.

[0014] Furthermore, the first resistor R1 and the second resistor R2 satisfy the following relationship:

[0015] R1L =23.256

[0016] R2

[0017] Where n is the emitter area ratio of the first NPN tube Q1, the second NPN tube Q2, the third NPN tube Q3, and the fourth NPN tube Q4.

[0018] Compared with the prior art, the present invention has the following beneficial technical effects:

[0019] The current source circuit designed by the present invention provides a start-up current through an NJFET tube, adjusts the resistance ratio and the transistor area ratio, and obtains a low-temperature drift current source with a simple structure, a small amount of components, and a bipolar process voltage-insensitive current source that can be used in a wide operating voltage range. The circuit has power supply voltage insensitivity and low temperature drift characteristics, and can stabilize the static operating point of the circuit under different voltages and different temperature conditions, thereby stabilizing the circuit power consumption and circuit characteristics, and can meet the circuits with high requirements for power consumption current power supply voltage stability and temperature stability. The consumables selected by the present invention can all be realized by bipolar technology, so the circuit of the present invention can be realized by pure bipolar technology, which is simple to realize and low in cost. The present invention has low power supply voltage sensitivity and temperature coefficient, a simple circuit structure, and is realized by using fewer static tubes, consuming less power supply current and chip area in applications. It has low power supply voltage sensitivity and temperature coefficient, and can be widely used in various bipolar processes or BiCMOS (bipolar metal oxide semiconductor) process circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of a voltage-insensitive low-temperature drift current source according to an embodiment of the present invention.

[0021] Figure 2 Schematic diagram of an application of a voltage-insensitive low-temperature drift current source in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] Embodiment 1:

[0025] like Figure 1 The figure shows a voltage-insensitive low-temperature drift current source circuit diagram in an embodiment of the present invention, including a power supply VCC, a ground VEE, a first resistor R1, a second resistor R2, a third resistor R3, a first NPN tube Q1, a second NPN tube Q2, a third NPN tube Q3, a fourth NPN tube Q4, a fifth NPN tube Q5, a first PNP tube Q6, a second PNP tube Q7, and an NJFET tube (N-channel junction field effect transistor) Jn1;

[0026] The gate of the NJFET tube Jn1 is grounded, the drain of Jn1 is connected to the power supply VCC, the source of Jn1 is connected to the collector and base of the third NPN tube Q3, the base of the fourth NPN tube Q4, and the base of the fifth NPN tube Q5; the emitter of the third NPN tube Q3 is connected to the collector of the first NPN tube Q1 and the base of the second NPN tube Q2; the base of the first NPN tube Q1 is connected to the collector of the second NPN tube Q2 and the emitter of the fourth NPN tube Q4, and the emitter of the first NPN tube Q1 is grounded; the emitter of the second NPN tube Q2 is connected to one end of the second resistor R2 , the other end of the second resistor R2 is grounded; the collector of the fourth NPN tube Q4 is connected to the base of the first PNP tube Q6, the collector of the second PNP tube Q7 and the collector of the fifth NPN tube Q5; the emitter of the fifth NPN tube Q5 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the collector of the first PNP tube Q6 is grounded, and the emitter of the first PNP tube Q6 is connected to the base of the second PNP tube Q7 and the bias voltage VB; the emitter of the second PNP tube Q7 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the power supply VCC.

[0027] Furthermore, the current source circuit provides a startup current through the NJFET tube Jn1. Since the pinch-off voltage of the NJFET is relatively small, it can be pinched off at a relatively low power supply voltage, and thus a relatively stable startup bias current can be provided within a relatively large power supply voltage range.

[0028] Furthermore, after the current source circuit is powered on, a current path is formed through the power supply VCC, the NJFET tube Jn1, the fourth NPN tube Q4 or the third NPN tube Q3, the first NPN tube Q1 or the second NPN tube Q2, the first resistor R1, and the ground VEE, driving the circuit to get rid of the zero degenerate operating point.

[0029] Furthermore, the NJFET tube Jn1 is a bipolar process parasitic structure, which can be implemented in the bipolar process without adding a photolithography plate, so the circuit structure of the current source is implemented using a pure bipolar process. After producing a low-temperature drift reference current IREF that is insensitive to the power supply voltage, it can be mirrored to each level inside the operational amplifier through a β-enhanced current mirror to provide the required current for each level. The β-enhanced current mirror is a circuit design for improving the accuracy and stability of the current mirror. The current mirror is a basic unit circuit in an analog circuit, and its main function is to copy a reference current in other branches to reduce errors caused by changes in voltage, temperature, etc.

[0030] Further, ignoring the base current of the first PNP tube Q6, the reference current IREF is the sum of the collector current of the fifth NPN tube Q5 and the collector current of the fourth NPN tube Q4, wherein the collector current of the fifth NPN tube Q5 is:

[0031]

[0032] In the formula, ICQ5 is the collector current of the fifth NPN tube Q5, VBE1 is the BE junction voltage of the first NPN tube Q1, VBE4 is the BE junction voltage of the fourth NPN tube Q4, VBE5 is the BE junction voltage of the fifth NPN tube Q5, and R1 is the first resistor.

[0033] In the circuit design, the emitter area of ​​the second NPN transistor Q2 is equal to the emitter area of ​​the fourth NPN transistor Q4, and the current of the second NPN transistor Q2 is approximately equal to that of the fourth NPN transistor Q4. Therefore, the BE junction voltages of the second NPN transistor Q2 and the fourth NPN transistor Q4 are approximately equal, that is, VBE2≈VBE4. Then, formula (1) can be simplified to the following formula:

[0034]

[0035] The collector current of the fourth NPN tube Q4 is:

[0036]

[0037] In the formula, ICQ4 is the collector current of the fourth NPN tube Q4, VBE1 is the BE junction voltage of the first NPN tube Q1, VBE4 is the BE junction voltage of the fourth NPN tube Q4, VBE3 is the BE junction voltage of the third NPN tube Q3, VBE2 is the BE junction voltage of the second NPN tube Q2, and R2 is the second resistor.

[0038] From equation (2) and equation (3), we can get the following equation:

[0039]

[0040] Wherein IS1 is the reverse saturation current of the first NPN tube Q1, IS2 is the reverse saturation current of the second NPN tube Q2, IS3 is the reverse saturation current of the third NPN tube Q3, and IS4 is the reverse saturation current of the fourth NPN tube Q4.

[0041] Furthermore, under the influence of the current amplification factor of the NPN tube, its base current can be ignored, so the collector current of the first NPN tube Q1 is approximately equal to the collector current of the third NPN tube Q3, and the collector current of the second NPN tube Q2 is approximately equal to the collector current of the fourth NPN tube Q4, that is, ICQ1≈ICQ3, ICQ2≈ICQ4. Under the condition of a certain process, IS1 is proportional to the emitter area of ​​Q1, IS2 is proportional to the emitter area of ​​Q2, IS3 is proportional to the emitter area of ​​Q3, and IS4 is proportional to the emitter area of ​​Q4.

[0042] Furthermore, in the circuit design, the emitter area of ​​the first NPN tube Q1, the second NPN tube Q2, the third NPN tube Q3, and the fourth NPN tube Q4 is adjusted so that the emitter area ratio of Q1, Q2, Q3, and Q4 is equal to the ratio of the product of the second NPN tube Q2 and the third NPN tube Q3 to the product of the first NPN tube Q1 and the fourth NPN tube Q4. Combining with formula (3), we can get the following formula:

[0043]

[0044] Furthermore, the reference current IREF is equal to the sum of the collector current of the fourth NPN transistor Q4 and the collector current of the fifth NPN transistor Q5, from which the following formula can be obtained:

[0045] I REF =I CQ4 +I CQ5 (6)

[0046] From equation (3) and equation (5), it can be concluded that ICQ4 and ICQ5 are both insensitive to the power supply voltage. Combining equation (6), it can be concluded that the reference current IREF is insensitive to the power supply voltage.

[0047] Furthermore, to calculate the temperature coefficient of the reference current IREF, without considering the temperature coefficient of the resistor, the reference current IREF is derived with respect to temperature to obtain the following formula:

[0048]

[0049] From formula (7), we can get the following formula:

[0050]

[0051] In formula (8), VT is the temperature coefficient of the reference current IREF, q and k are both constants, and the ratio of the two is q / k=0.086, so VT has a positive temperature coefficient of +0.086mV / ℃.

[0052] Further, we can get the following formula:

[0053]

[0054] From formula (9), we can get that the temperature coefficient of VBE is related to the size of VBE itself. At room temperature, its temperature coefficient is -2mV / ℃, so VBE is a voltage with a negative temperature coefficient, but it is not inversely proportional to the temperature and has a nonlinear temperature characteristic.

[0055] Furthermore, if the temperature coefficient of the reference voltage IREF is to be reduced, the following equation should be satisfied:

[0056]

[0057] Where n is the ratio of the emitter area of ​​the first NPN tube Q1, the second NPN tube Q2, the third NPN tube Q3, and the fourth NPN tube Q4. After simplifying formula (10), we get:

[0058]

[0059] That is, in the circuit of the present invention, by adjusting the ratio of the first resistor R1 to the second resistor R2 and the emitter area ratio n of the first NPN transistor Q1, the second NPN transistor Q2, the third NPN transistor Q3, and the fourth NPN transistor Q4 so that they satisfy equation (11), a reference current IREF with a low temperature coefficient can be obtained.

[0060] Embodiment 2:

[0061] like Figure 2 The figure shows a schematic diagram of a voltage-insensitive low-temperature drift current source application of the present invention. In this embodiment, the current source of the present invention is applied to a low-power operational amplifier circuit, including a power supply VCC, a ground VEE, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first NPN tube Q1, a second NPN tube Q2, a third NPN tube Q3, a fourth NPN tube Q4, a fifth NPN tube Q5, a sixth NPN tube Q10, a seventh NPN tube Q11, a first PNP tube Q6, a second PNP tube Q7, a third PNP tube Q8, a fourth PNP tube Q9, an NJFET tube (N-channel junction field effect transistor) Jn1, a first output terminal IO1, and a second output terminal IO2;

[0062] The gate of the NJFET tube Jn1 is grounded, the drain of Jn1 is connected to the power supply VCC, the source of Jn1 is connected to the collector and base of the third NPN tube Q3, the base of the fourth NPN tube Q4, and the base of the fifth NPN tube Q5; the emitter of the third NPN tube Q3 is connected to the collector of the first NPN tube Q1 and the base of the second NPN tube Q2; the base of the first NPN tube Q1 is connected to the collector of the second NPN tube Q2 and the emitter of the fourth NPN tube Q4, and the emitter of the first NPN tube Q1 is grounded; the emitter of the second NPN tube Q2 is connected to one end of the second resistor R2 , the other end of the second resistor R2 is grounded; the collector of the fourth NPN tube Q4 is connected to the base of the first PNP tube Q6, the collector of the second PNP tube Q7 and the collector of the fifth NPN tube Q5; the emitter of the fifth NPN tube Q5 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the collector of the first PNP tube Q6 is grounded, and the emitter of the first PNP tube Q6 is connected to the base of the second PNP tube Q7 and the bias voltage VB; the emitter of the second PNP tube Q7 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the power supply VCC.

[0063] One end of the bias voltage VB is connected to the base of the second PNP tube Q7, and the other end is connected to the base of the third PNP tube Q8 and the base of the fourth PNP tube Q9. The emitter of the third PNP tube Q8 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the power supply VCC. The collector of the third PNP tube Q8 is connected to the collector of the sixth NPN tube Q10 and the base of the sixth NPN tube Q10 and the base of the seventh NPN tube Q11. The emitter of the seventh NPN tube Q11 is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is grounded, and the collector of the seventh NPN tube Q11 is connected to the second output terminal IO2; the emitter of the fourth PNP tube Q9 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to the power supply VCC, and the collector of the fourth PNP tube Q9 is connected to the first output terminal IO1.

[0064] Furthermore, the current source circuit described in this embodiment satisfies the condition of formula (11) in Example 1. The low-power operational amplifier circuit using the current source circuit designed by the present invention is tape-out, that is, trial production is carried out, and the designed chip pattern is converted from computer data into a physical structure on an actual silicon wafer. After being sent to the manufacturer, a certain number of sample chips are produced for testing, and the power supply voltage sensitivity of the low-power operational amplifier circuit is obtained to be approximately 0.048, that is, when the power supply voltage changes by 10%, the power supply current changes by approximately 0.48%; the temperature coefficient is approximately 530ppm / ℃, which has low power supply voltage sensitivity and temperature coefficient, and can be widely used in various bipolar processes or BiCMOS (bipolar metal oxide semiconductor) process circuits.

Claims

1. A voltage-insensitive low-temperature drift current source, characterized in that: It includes a power supply VCC, a ground VEE, a first resistor R1, a second resistor R2, a third resistor R3, a first NPN tube Q1, a second NPN tube Q2, a third NPN tube Q3, a fourth NPN tube Q4, a fifth NPN tube Q5, a first PNP tube Q6, a second PNP tube Q7, and a NJFET tube Jn1; The gate of the NJFET tube Jn1 is grounded, the drain of Jn1 is connected to the power supply VCC, the source of Jn1 is connected to the collector and base of the third NPN tube Q3, the base of the fourth NPN tube Q4, and the base of the fifth NPN tube Q5; the emitter of the third NPN tube Q3 is connected to the collector of the first NPN tube Q1 and the base of the second NPN tube Q2; the base of the first NPN tube Q1 is connected to the collector of the second NPN tube Q2 and the emitter of the fourth NPN tube Q4, and the emitter of the first NPN tube Q1 is grounded; the emitter of the second NPN tube Q2 is connected to one end of the second resistor R2 , the other end of the second resistor R2 is grounded; the collector of the fourth NPN tube Q4 is connected to the base of the first PNP tube Q6, the collector of the second PNP tube Q7 and the collector of the fifth NPN tube Q5; the emitter of the fifth NPN tube Q5 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; the collector of the first PNP tube Q6 is grounded, and the emitter of the first PNP tube Q6 is connected to the base of the second PNP tube Q7 and the bias voltage VB; the emitter of the second PNP tube Q7 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the power supply VCC.

2. The voltage-insensitive low-temperature drift current source according to claim 1, characterized in that: The current source circuit provides a startup current through the NJFET tube Jn1.

3. The voltage-insensitive low-temperature drift current source according to claim 2, characterized in that: After the circuit is powered on, a current path is formed through the power supply VCC, the NJFET tube Jn1, the fourth NPN tube Q4 or the third NPN tube Q3, the first NPN tube Q1 or the second NPN tube Q2, the first resistor R1, and the ground VEE to drive the circuit out of the zero degenerate operating point.

4. The voltage-insensitive low-temperature drift current source according to claim 1, characterized in that: The NJFET tube Jn1 is a bipolar process parasitic structure.

5. The voltage-insensitive low-temperature drift current source according to claim 4, characterized in that: The circuit structure of the current source adopts a pure bipolar process.

6. The voltage-insensitive low-temperature drift current source according to claim 1, characterized in that: The emitter area of ​​the second NPN transistor Q2 is equal to the emitter area of ​​the fourth NPN transistor Q4.

7. The voltage-insensitive low-temperature drift current source according to claim 6, characterized in that: The currents of the second NPN tube Q2 and the fourth NPN tube Q4 are approximately equal, so the BE junction voltages of the second NPN tube Q2 and the fourth NPN tube Q4 are approximately equal.

8. The voltage-insensitive low-temperature drift current source according to claim 7, characterized in that: Under the influence of the current amplification factor of the NPN tube, its base current can be ignored, so the collector current of the first NPN tube Q1 is approximately equal to the collector current of the third NPN tube Q3, and the collector current of the second NPN tube Q2 is approximately equal to the collector current of the fourth NPN tube Q4.

9. The voltage-insensitive low-temperature drift current source according to claim 8, characterized in that: The emitter area ratio of the first NPN tube Q1, the second NPN tube Q2, the third NPN tube Q3, and the fourth NPN tube Q4 is equal to the ratio of the product of the second NPN tube Q2 and the third NPN tube Q3 to the product of the first NPN tube Q1 and the fourth NPN tube Q4.

10. The voltage-insensitive low-temperature drift current source according to claim 9, characterized in that: The first resistor R1 and the second resistor R2 satisfy the following relationship: R1L ＝23.256 R2 Where n is the emitter area ratio of the first NPN tube Q1, the second NPN tube Q2, the third NPN tube Q3, and the fourth NPN tube Q4.

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