Method for effectively improving LDO power supply rejection ratio through Cascode compensation

Abstract

The invention discloses a method for effectively improving the power supply rejection ratio of an LDO (Low Dropout Regulator) through Cascode compensation, and relates to a method for improving the power supply rejection ratio, which comprises an LDO circuit with a Cascode compensation and a high power supply rejection ratio. The circuit comprises a band-gap reference circuit VREF, an error amplifier EA, a PMOS (P-channel Metal Oxide Semiconductor) power tube and resistance feedback networks R5 and R6, the band-gap reference circuit is not provided with an operational amplifier structure, PTAT current is generated through the current mirror, and the influence of power supply voltage on output reference voltage is reduced; according to the low dropout regulator circuit, the error amplifier EA is improved, the Cascode compensation is adopted to eliminate the right half plane zero point problem caused by Miller compensation, and the power supply rejection ratio (PSRR) output by the LDO circuit is increased. The EA module is designed, and the output LDO voltage is fed back to the current compensation circuit, so that the current compensation of each branch in the circuit is realized, the output voltage of the LDO is stable, and the power supply rejection ratio (PSRR) is remarkably improved.

Description

Technical Field

[0001] The invention relates to a method for improving a power supply rejection ratio, and in particular to a method for effectively improving a LDO power supply rejection ratio through cascode compensation. Background Art

[0002] With the rapid development of electronic chips, portable devices have become an indispensable part of people's lives. In order to make electronic devices work stably and well, the design of power supply is particularly important. Low dropout linear regulator (LDO) is an important type of power management chip. It has the advantages of simplicity, cheapness, easy integration, good linear regulation rate and load regulation rate, but its PSRR and accuracy are not very ideal. For this reason, many people have made a lot of efforts to improve the accuracy and PSRR of LDO.

[0003] People have also made a lot of efforts to improve the PSRR of LDO. High PSRR can be obtained by improving the structure of Wilson current source and operational amplifier, or by designing a multi-stage buffer, but it will lead to poor loop stability. The power supply rejection ratio can also be improved by improving the structure of the error amplifier. The most common way to improve the internal structure of the error amplifier is to add Miller compensation. However, for the two-stage operational amplifier with Miller compensation, due to the existence of a feedforward path, a zero point in the right half plane will be introduced, thereby making the frequency response stability worse. This can be solved by adding a zero adjustment resistor. In addition, this invention proposes that the defects of Miller compensation can be eliminated through Cascode compensation, thereby improving the power supply rejection ratio. Summary of the invention

[0004] The purpose of the present invention is to propose a method for effectively improving the power supply rejection ratio of an LDO by cascode compensation. The method uses a high power supply rejection ratio LDO circuit compensated by cascode to stabilize the LDO output voltage and significantly improve the power supply rejection ratio (PSRR).

[0005] To achieve the above object, the technical solution of the present invention is as follows: A method for effectively improving the power supply rejection ratio of an LDO by cascode compensation, the method comprising an LDO circuit with a high power supply rejection ratio and cascode compensation, wherein the circuit is configured as follows: A bandgap reference circuit module, wherein an output terminal VREF of the bandgap reference circuit is connected to a negative input terminal of an error amplifier EA, so as to provide a reference voltage VREF for the error amplifier; The error amplifier EA includes a folded common-source common-gate amplifier and a cascode compensation circuit; the voltage VFB collected by the feedback network is input to the positive input terminal of the error amplifier EA, compared with the reference voltage VREF at the negative input terminal, and then amplified to obtain the required voltage; A PMOS power tube, wherein a gate of the PMOS power tube is connected to an output end of the error amplifier; A resistor feedback network generates a feedback voltage VFB and outputs it to the positive input terminal of the error amplifier.

[0006] In the above-mentioned method for effectively improving the power supply rejection ratio of an LDO by cascode compensation, a high power supply rejection ratio LDO circuit with cascode compensation, the bandgap reference circuit includes transistors Q1-Q4, resistors R1-R4, capacitor C1, and MOS tubes M1-M27; The power supply is connected to the source of the MOS tube M1, the source of the MOS tube M7, the source of the MOS tube M2, the source of the MOS tube M3, the source of the MOS tube M4, the source of the MOS tube M11, the source of the MOS tube M5, the source of the MOS tube M6, the source of the MOS tube M20, the drain of the MOS tube M24, the source of the MOS tube M26, and the positive end of the resistor R4;The drain of MOS tube M1 is connected to the gate of MOS tube M15, the gate and source of MOS tube M16, the drain of MOS tube M8, and the gate end of MOS tube M17. The gate of MOS tube M1 is connected to the drain of MOS tube M26 and the drain of MOS tube M27. The gate of MOS tube M2 is connected to the gate of MOS tube M3, the gate of MOS tube M4, the drain of MOS tube M9, the gate of MOS tube M11, the gate of MOS tube M12, the gate of MOS tube M13, and the source of MOS tube M17. The drain of MOS tube M2 is connected to the source of MOS tube M8, the drain of MOS tube M3 is connected to the source of MOS tube M9, the drain of MOS tube M4 is connected to the gate of MOS tube M1 The source of MOS tube M0 is connected, the drain of MOS tube M11 is connected to the drain of MOS tube M12, the drain of MOS tube M13, the drain of MOS tube M19, the gate of MOS tube M20, the gate of MOS tube M21, the gate of MOS tube M22, and the gate of MOS tube M23. The drain of MOS tube M5 is connected to the source of MOS tube M12, the drain of MOS tube M6 is connected to the source of MOS tube M13, the gate of MOS tube M5 and the gate of MOS tube M6 are connected to the external opposite signals A and B, the gate of MOS tube M7 is connected to the gate and drain of MOS tube M14, the source of MOS tube M15, the gate of MOS tube M8, the gate of MOS tube M9, and the gate of MOS tube M10. The drain of MOS tube M7 is connected to the source of MOS tube M14, the drain of MOS tube M15 is connected to the emitter of transistor Q1, the drain of MOS tube M16 is connected to the emitter of transistor Q2, the drain of MOS tube M17 is connected to the positive end of resistor R1, the negative end of resistor R1 is connected to the emitter of transistor Q3, the drain of MOS tube M10 is connected to the positive end of resistor R2 and the output end VREF of the bandgap reference circuit, the negative end of resistor R2 is connected to the positive end of resistor R3, the negative end of resistor R3 is connected to the emitter of transistor Q4, the negative end of resistor R4 is connected to the gate and drain of MOS tube M18, the gate of MOS tube M19, and the positive end of capacitor C1, and ground is connected to the positive end of transistor Q1. The base and collector, the base and collector of transistor Q2, the base and collector of transistor Q3, the base and collector of transistor Q4, the source of MOS tube M18, the source of MOS tube M19, the negative end of capacitor C1, the source of MOS tube M23, the drain of MOS tube M25, and the source of MOS tube M27 are connected, the drain of MOS tube M20 is connected to the source of MOS tube M21 and the source of MOS tube M24, the drain of MOS tube M21 is connected to the drain of MOS tube M22, the gate of MOS tube M24, the gate of MOS tube M25, the gate of MOS tube M26, and the gate of MOS tube M27, and the source of MOS tube M22 is connected to the drain of MOS tube M23. ;

[0007] In the above-mentioned method of effectively improving the LDO power supply rejection ratio through Cascode compensation, there is a LDO circuit with a high power supply rejection ratio with Cascode compensation, wherein the error amplifier EA includes MOS tubes M28-M41, resistors R5-R6 and a compensation capacitor Cc;.

[0008] Among them, the gate of the MOS tube M28 is connected to the reference voltage VREF of the bandgap reference, the gate of the MOS tube M29 and the gate of the MOS tube M30 are connected to the feedback voltage VFB, the negative end of the resistor R5, and the positive end of the resistor R6, the source of the MOS tube M28 is connected to the source of the MOS tube M29 and the drain of the MOS tube M31, the drain of the MOS tube M28 is connected to the drain of the MOS tube M34 and the drain of the MOS tube M36, the drain of the MOS tube M29 is connected to the drain of the MOS tube M38, the drain of the MOS tube M39, and the positive end of the compensation capacitor Cc, the drain of the MOS tube M32 is connected to the source of the MOS tube M30, the gate of the MOS tube M31 and the gate of the MOS tube M32 are connected to the external voltage terminal VB1 to form a current source, the drain of the MOS tube M30 is connected to the gate and drain of the MOS tube M35, the gate of the MOS tube M36, and the gate of the MOS tube M39, the gate and drain of the MOS tube M33 are connected to the gate and drain of the MOS tube M34, and the gate of the MOS tube M36. The gate of the MOS tube M7 is connected to the source of the MOS tube M34, the gate of the MOS tube M34 and the gate of the MOS tube M38 are connected to the external voltage terminal VB2 to form a current source, the drain of the MOS tube M37 is connected to the source of the MOS tube M38 and the gate of the MOS tube M40, the power supply is connected to the source of the MOS tube M31, the source of the MOS tube M32, the source of the MOS tube M33, the source of the MOS tube M37, the source of the MOS tube M40, and the source of the MOS tube M41, The drain of the MOS tube M40 is connected to the gate of the MOS tube M41, the negative end of the compensation capacitor Cc, and the drain of the MOS tube M42. The gate of the MOS tube M42 is connected to the external voltage terminal VB3 to form a current source. The ground is connected to the source of the MOS tube M35, the source of the MOS tube M36, the source of the MOS tube M39, the source of the MOS tube M42, and the negative end of the resistor R6. The drain of the MOS tube M41 is connected to the positive end of the resistor R5 and the LDO output voltage terminal VOUT.

[0009] In the above-mentioned method for effectively improving the power supply rejection ratio of an LDO through Cascode compensation, a LDO circuit with a high power supply rejection ratio with Cascode compensation is provided, wherein the error amplifier EA includes a folded cascode amplifier and a Cascode compensation part, and the folded cascode amplifier can output a larger output voltage swing while ensuring the loop gain of the LDO; PMOS transistors M28 and M29 are used to form an input pair of transistors, MOS transistors M31 and M32 provide suitable bias for the input pair of transistors, compare the reference voltage VREF and the feedback voltage VFB, and operate in the saturation region through M34 and M35 to adjust the startup voltage of the LDO circuit.

[0010] In the above-mentioned method for effectively improving the power supply rejection ratio of an LDO by Cascode compensation, a LDO circuit with a high power supply rejection ratio with Cascode compensation is provided, wherein the Cascode compensation circuit includes a MOS tube M40, a MOS tube M42, a MOS tube M38, and a compensation capacitor Cc; the drain of the MOS tube M40 is connected to the drain of the MOS tube M42 and the negative end of the compensation capacitor Cc, the output VO of the folded cascode amplifier is connected to the positive end of the compensation capacitor Cc, the drain of the MOS tube M38, and the drain of the MOS tube M39, the source of the MOS tube M40 is connected to the power supply, and the source of the MOS tube M42 is connected to the ground.

[0011] In the above-mentioned method of effectively improving the LDO power supply rejection ratio through Cascode compensation, a LDO circuit with a high power supply rejection ratio with Cascode compensation, the resistor feedback network includes a resistor R5 and a resistor R6, the negative end of the resistor R5 and the positive end of the resistor R6 are connected to the negative input terminal VFB of the error amplifier EA, the positive end of the resistor R5 is connected to the output terminal VOUT of the LDO, and the negative end of the resistor R6 is connected to the ground.

[0012] The advantages and effects of the present invention are: 1. The present invention includes a bandgap reference circuit VREF, an error amplifier EA, a PMOS power tube, and a resistor feedback network R5 and R6; the bandgap reference circuit of the present invention has no operational amplifier structure, generates a PTAT current through a current mirror, and reduces the influence of the power supply voltage on the output reference voltage; the present invention improves the error amplifier EA, adopts Cascode compensation to eliminate the right half plane zero point problem caused by Miller compensation, and improves the power supply rejection ratio (PSRR) of the LDO circuit output. The present invention designs an EA module and feeds back the output LDO voltage to the current compensation circuit, thereby realizing current compensation for each branch in the circuit, thereby stabilizing the LDO output voltage and significantly improving the power supply rejection ratio (PSRR).

[0013] 2. The bandgap reference circuit of the present invention is used to generate the reference voltage required by LDO. Compared with the traditional bandgap reference circuit, the structure does not adopt an operational amplifier structure, and only generates PTAT current through a current mirror, thereby reducing the influence of the power supply voltage on the output reference voltage.

[0014] 3. The error amplifier of the present invention includes a folded cascode amplifier and a Cascode compensation part. For the folded cascode amplifier, a MOS tube M30 is added as one end of the differential pair. The gate of the MOS tube M30 is connected to the gate of the MOS tube M29, which serves as the positive input end of the error amplifier. A common-mode feedback network is added to stabilize the common-mode level and static operating point of the circuit. At the same time, Cascode compensation is added to the error amplifier, eliminating the problem of the right half plane zero point of the Maitreya effect, making the circuit more stable and improving the power supply rejection ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The overall schematic diagram of the LDO with high power supply rejection ratio with cascode compensation of the present invention; Figure 2 Schematic diagram of the bandgap reference circuit of the present invention; Figure 3 It is a schematic diagram of the error amplifier EA of the present invention; Figure 4 Cascode compensation circuit diagram of the present invention; Figure 5 It is a PSRR performance curve diagram of the circuit of the present invention. DETAILED DESCRIPTION

[0016] In order to clearly and completely describe the purpose and technical solution of the present invention and make the advantages more clearly understood, the embodiments of the present invention are further described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are part of the embodiments of the present invention, not all of them, and are only used to explain the embodiments of the present invention, and are not used to limit the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] To address the problem of unsatisfactory PSRR of LDO circuit, Cascode compensation is added to the output of the error amplifier to make the LDO output more stable and greatly improve the power supply rejection ratio.

[0018] High power supply rejection ratio LDO circuit with cascode compensation, such as Figure 1 As shown, it includes: a bandgap reference circuit, an error amplifier EA, a PMOS power tube, and a resistor feedback network R5-R6; Among them, the output terminal VREF of the bandgap reference circuit is connected to the negative input terminal of the error amplifier EA, aiming to provide a reference voltage VREF for the error amplifier; the error amplifier EA includes a folded common source and common gate amplifier and a cascode compensation circuit; the voltage VFB collected by the feedback network is input to the positive input terminal of the error amplifier EA, compared with the reference voltage VREF at the negative input terminal, and then amplified to obtain the required voltage; the gate of the PMOS power tube is connected to the output terminal of the error amplifier; the feedback voltage VFB generated by the resistor feedback network is output to the positive input terminal of the error amplifier.

[0019] like Figure 2 As shown, the bandgap reference circuit includes transistors Q1-Q4, resistors R1-R4, capacitor C1, MOS tubes M1-M27; The power supply is connected to the source of the MOS tube M1, the source of the MOS tube M7, the source of the MOS tube M2, the source of the MOS tube M3, the source of the MOS tube M4, the source of the MOS tube M11, the source of the MOS tube M5, the source of the MOS tube M6, the source of the MOS tube M20, the drain of the MOS tube M24, the source of the MOS tube M26, and the positive end of the resistor R4;The drain of MOS tube M1 is connected to the gate of MOS tube M15, the gate and source of MOS tube M16, the drain of MOS tube M8, and the gate end of MOS tube M17. The gate of MOS tube M1 is connected to the drain of MOS tube M26 and the drain of MOS tube M27. The gate of MOS tube M2 is connected to the gate of MOS tube M3, the gate of MOS tube M4, the drain of MOS tube M9, the gate of MOS tube M11, the gate of MOS tube M12, the gate of MOS tube M13, and the source of MOS tube M17. The drain of MOS tube M2 is connected to the source of MOS tube M8, the drain of MOS tube M3 is connected to the source of MOS tube M9, the drain of MOS tube M4 is connected to the gate of MOS tube M1 The source of MOS tube M0 is connected, the drain of MOS tube M11 is connected to the drain of MOS tube M12, the drain of MOS tube M13, the drain of MOS tube M19, the gate of MOS tube M20, the gate of MOS tube M21, the gate of MOS tube M22, and the gate of MOS tube M23. The drain of MOS tube M5 is connected to the source of MOS tube M12, the drain of MOS tube M6 is connected to the source of MOS tube M13, the gate of MOS tube M5 and the gate of MOS tube M6 are connected to the external opposite signals A and B, the gate of MOS tube M7 is connected to the gate and drain of MOS tube M14, the source of MOS tube M15, the gate of MOS tube M8, the gate of MOS tube M9, and the gate of MOS tube M10. The drain of MOS tube M7 is connected to the source of MOS tube M14, the drain of MOS tube M15 is connected to the emitter of transistor Q1, the drain of MOS tube M16 is connected to the emitter of transistor Q2, the drain of MOS tube M17 is connected to the positive end of resistor R1, the negative end of resistor R1 is connected to the emitter of transistor Q3, the drain of MOS tube M10 is connected to the positive end of resistor R2 and the output end VREF of the bandgap reference circuit, the negative end of resistor R2 is connected to the positive end of resistor R3, the negative end of resistor R3 is connected to the emitter of transistor Q4, the negative end of resistor R4 is connected to the gate and drain of MOS tube M18, the gate of MOS tube M19, and the positive end of capacitor C1, and ground is connected to the positive end of transistor Q1. The base and collector, the base and collector of transistor Q2, the base and collector of transistor Q3, the base and collector of transistor Q4, the source of MOS tube M18, the source of MOS tube M19, the negative end of capacitor C1, the source of MOS tube M23, the drain of MOS tube M25, and the source of MOS tube M27 are connected, the drain of MOS tube M20 is connected to the source of MOS tube M21 and the source of MOS tube M24, the drain of MOS tube M21 is connected to the drain of MOS tube M22, the gate of MOS tube M24, the gate of MOS tube M25, the gate of MOS tube M26, and the gate of MOS tube M27, and the source of MOS tube M22 is connected to the drain of MOS tube M23. ;

[0020] The bandgap reference circuit has no operational amplifier structure and only generates PTAT current through a current mirror, thereby reducing the influence of the power supply voltage on the output reference voltage. MOS tube M16 and MOS tube M17 form a current mirror structure, the drain voltage of MOS tube M16 is equal to the drain voltage of MOS tube M17, the base-emitter voltage VBE2 of transistor Q2 is equal to the sum of the base-emitter voltage VBE3 of transistor Q3 and the voltage of resistor R1, the voltage difference between the base-emitter voltage VBE2 of transistor Q2 and the base-emitter voltage VBE3 of transistor Q3 is divided by resistor R1 to obtain the PTAT current, the current is copied by the current mirror to the resistor R2, the resistor R3 branch, and a positive temperature coefficient voltage is obtained, the base-emitter voltage VBE4 of transistor Q4 is a negative temperature coefficient voltage, and the two are added to obtain a zero temperature coefficient voltage VREF.

[0021] like Figure 3 As shown, the error amplifier EA includes MOS tubes M28-M41, resistors R5-R6 and a compensation capacitor Cc;.

[0022] Among them, the gate of the MOS tube M28 is connected to the reference voltage VREF of the bandgap reference, the gate of the MOS tube M29 and the gate of the MOS tube M30 are connected to the feedback voltage VFB, the negative end of the resistor R5, and the positive end of the resistor R6, the source of the MOS tube M28 is connected to the source of the MOS tube M29 and the drain of the MOS tube M31, the drain of the MOS tube M28 is connected to the drain of the MOS tube M34 and the drain of the MOS tube M36, the drain of the MOS tube M29 is connected to the drain of the MOS tube M38, the drain of the MOS tube M39, and the positive end of the compensation capacitor Cc, the drain of the MOS tube M32 is connected to the source of the MOS tube M30, the gate of the MOS tube M31 and the gate of the MOS tube M32 are connected to the external voltage terminal VB1 to form a current source, the drain of the MOS tube M30 is connected to the gate and drain of the MOS tube M35, the gate of the MOS tube M36, and the gate of the MOS tube M39, the gate and drain of the MOS tube M33 are connected to the gate and drain of the MOS tube M34, and the gate of the MOS tube M36. The gate of the MOS tube M7 is connected to the source of the MOS tube M34, the gate of the MOS tube M34 and the gate of the MOS tube M38 are connected to the external voltage terminal VB2 to form a current source, the drain of the MOS tube M37 is connected to the source of the MOS tube M38 and the gate of the MOS tube M40, the power supply is connected to the source of the MOS tube M31, the source of the MOS tube M32, the source of the MOS tube M33, the source of the MOS tube M37, the source of the MOS tube M40, and the source of the MOS tube M41, The drain of the MOS tube M40 is connected to the gate of the MOS tube M41, the negative end of the compensation capacitor Cc, and the drain of the MOS tube M42. The gate of the MOS tube M42 is connected to the external voltage terminal VB3 to form a current source. The ground is connected to the source of the MOS tube M35, the source of the MOS tube M36, the source of the MOS tube M39, the source of the MOS tube M42, and the negative end of the resistor R6. The drain of the MOS tube M41 is connected to the positive end of the resistor R5 and the LDO output voltage terminal VOUT.

[0023] The error amplifier EA includes a folded cascode amplifier and a cascode compensation part. The folded cascode amplifier can output a larger output voltage swing while ensuring the LDO loop gain. PMOS transistors M28 and M29 are used to form an input pair of transistors. MOS transistors M31 and M32 provide appropriate bias for the input pair of transistors, compare the reference voltage VREF and the feedback voltage VFB, and work in the saturation region through M34 and M35 to adjust the startup voltage of the LDO circuit.

[0024] like Figure 4As shown, the cascode compensation circuit includes a MOS tube M40, a MOS tube M42, a MOS tube M38, and a compensation capacitor Cc; the drain of the MOS tube M40 is connected to the drain of the MOS tube M42 and the negative end of the compensation capacitor Cc, the output VO of the folded common source amplifier is connected to the positive end of the compensation capacitor Cc, the drain of the MOS tube M38, and the drain of the MOS tube M39, the source of the MOS tube M40 is connected to the power supply, and the source of the MOS tube M42 is connected to the ground.

[0025] The Cascode compensation circuit uses the MOS tube M38 as a current buffer and moves one end of the compensation capacitor Cc from point X to point Y, changing the compensation from general Miller compensation to Cascode compensation. The Cascode is used to cut off the feedforward path from point X through the capacitor Cc to the output, pushing the right half plane zero point to a very high frequency, greatly improving the power supply rejection ratio.

[0026] The power supply rejection ratio PSRR performance curve is as follows Figure 5 As shown, the horizontal axis is frequency in Hz, and the vertical axis is PSRR in dB. It can be seen from the figure that the PSRR is at low frequency, and as the frequency increases, the PSRR gradually decreases. It can be seen that the PSRR is as high as 97dB at 1kHz.

[0027] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been demonstrated as above with a preferred embodiment, it is not used to limit the present invention. Any technician familiar with this patent can make some changes or modify it into an equivalent embodiment with equivalent changes by using the technical content suggested above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the solution of the present invention.

Claims

1. A method to effectively improve the LDO power supply rejection ratio through cascode compensation. It is characterized in that The method includes a high power supply rejection ratio LDO circuit with cascode compensation, the circuit configuration comprising: A bandgap reference circuit module, wherein an output terminal VREF of the bandgap reference circuit is connected to a negative input terminal of the error amplifier EA, so as to provide a reference voltage VREF for the error amplifier; The error amplifier EA includes a folded common source and common gate amplifier and a cascode compensation circuit; The voltage VFB collected by the feedback network is input to the positive input terminal of the error amplifier EA, compared with the reference voltage VREF at the negative input terminal, and then amplified to obtain the required voltage; A PMOS power tube, wherein the gate of the PMOS power tube is connected to the output end of the error amplifier; The resistor feedback network generates a feedback voltage VFB and outputs it to the positive input terminal of the error amplifier.

2. According to claim 1, a method for effectively improving the LDO power supply rejection ratio by cascode compensation, It is characterized in that The bandgap reference circuit includes transistors Q1-Q4, resistors R1-R4, capacitor C1, and MOS tubes M1-M27; The power supply is connected to the source of the MOS tube M1, the source of the MOS tube M7, the source of the MOS tube M2, the source of the MOS tube M3, the source of the MOS tube M4, the source of the MOS tube M11, the source of the MOS tube M5, the source of the MOS tube M6, the source of the MOS tube M20, the drain of the MOS tube M24, the source of the MOS tube M26, and the positive end of the resistor R4;The drain of MOS tube M1 is connected to the gate of MOS tube M15, the gate and source of MOS tube M16, the drain of MOS tube M8, and the gate end of MOS tube M17. The gate of MOS tube M1 is connected to the drain of MOS tube M26 and the drain of MOS tube M27. The gate of MOS tube M2 is connected to the gate of MOS tube M3, the gate of MOS tube M4, the drain of MOS tube M9, the gate of MOS tube M11, the gate of MOS tube M12, the gate of MOS tube M13, and the source of MOS tube M17. The drain of MOS tube M2 is connected to the source of MOS tube M8, the drain of MOS tube M3 is connected to the source of MOS tube M9, the drain of MOS tube M4 is connected to the gate of MOS tube M1 The source of MOS tube M0 is connected, the drain of MOS tube M11 is connected to the drain of MOS tube M12, the drain of MOS tube M13, the drain of MOS tube M19, the gate of MOS tube M20, the gate of MOS tube M21, the gate of MOS tube M22, and the gate of MOS tube M23. The drain of MOS tube M5 is connected to the source of MOS tube M12, the drain of MOS tube M6 is connected to the source of MOS tube M13, the gate of MOS tube M5 and the gate of MOS tube M6 are connected to the external opposite signals A and B, the gate of MOS tube M7 is connected to the gate and drain of MOS tube M14, the source of MOS tube M15, the gate of MOS tube M8, the gate of MOS tube M9, and the gate of MOS tube M10. The drain of MOS tube M7 is connected to the source of MOS tube M14, the drain of MOS tube M15 is connected to the emitter of transistor Q1, the drain of MOS tube M16 is connected to the emitter of transistor Q2, the drain of MOS tube M17 is connected to the positive end of resistor R1, the negative end of resistor R1 is connected to the emitter of transistor Q3, the drain of MOS tube M10 is connected to the positive end of resistor R2 and the output end VREF of the bandgap reference circuit, the negative end of resistor R2 is connected to the positive end of resistor R3, the negative end of resistor R3 is connected to the emitter of transistor Q4, the negative end of resistor R4 is connected to the gate and drain of MOS tube M18, the gate of MOS tube M19, and the positive end of capacitor C1, and ground is connected to the positive end of transistor Q1. The base and collector, the base and collector of transistor Q2, the base and collector of transistor Q3, the base and collector of transistor Q4, the source of MOS tube M18, the source of MOS tube M19, the negative end of capacitor C1, the source of MOS tube M23, the drain of MOS tube M25, and the source of MOS tube M27 are connected, the drain of MOS tube M20 is connected to the source of MOS tube M21 and the source of MOS tube M24, the drain of MOS tube M21 is connected to the drain of MOS tube M22, the gate of MOS tube M24, the gate of MOS tube M25, the gate of MOS tube M26, and the gate of MOS tube M27, and the source of MOS tube M22 is connected to the drain of MOS tube M23. ; 3. According to claim 1, a method for effectively improving the LDO power supply rejection ratio by cascode compensation, It is characterized in that The error amplifier EA includes MOS tubes M28-M41, resistors R5-R6 and a compensation capacitor Cc; Among them, the gate of the MOS tube M28 is connected to the reference voltage VREF of the bandgap reference, the gate of the MOS tube M29 and the gate of the MOS tube M30 are connected to the feedback voltage VFB, the negative end of the resistor R5, and the positive end of the resistor R6, the source of the MOS tube M28 is connected to the source of the MOS tube M29 and the drain of the MOS tube M31, the drain of the MOS tube M28 is connected to the drain of the MOS tube M34 and the drain of the MOS tube M36, the drain of the MOS tube M29 is connected to the drain of the MOS tube M38, the drain of the MOS tube M39, and the positive end of the compensation capacitor Cc, the drain of the MOS tube M32 is connected to the source of the MOS tube M30, the gate of the MOS tube M31 and the gate of the MOS tube M32 are connected to the external voltage terminal VB1 to form a current source, the drain of the MOS tube M30 is connected to the gate and drain of the MOS tube M35, the gate of the MOS tube M36, and the gate of the MOS tube M39, the gate and drain of the MOS tube M33 are connected to the gate and drain of the MOS tube M34, and the gate of the MOS tube M36. The gate of the MOS tube M7 is connected to the source of the MOS tube M34, the gate of the MOS tube M34 and the gate of the MOS tube M38 are connected to the external voltage terminal VB2 to form a current source, the drain of the MOS tube M37 is connected to the source of the MOS tube M38 and the gate of the MOS tube M40, the power supply is connected to the source of the MOS tube M31, the source of the MOS tube M32, the source of the MOS tube M33, the source of the MOS tube M37, the source of the MOS tube M40, and the source of the MOS tube M41, The drain of the MOS tube M40 is connected to the gate of the MOS tube M41, the negative end of the compensation capacitor Cc, and the drain of the MOS tube M42. The gate of the MOS tube M42 is connected to the external voltage terminal VB3 to form a current source. The ground is connected to the source of the MOS tube M35, the source of the MOS tube M36, the source of the MOS tube M39, the source of the MOS tube M42, and the negative end of the resistor R6. The drain of the MOS tube M41 is connected to the positive end of the resistor R5 and the LDO output voltage terminal VOUT.

4. According to claim 3, a method for effectively improving the LDO power supply rejection ratio by cascode compensation, It is characterized in that The error amplifier EA includes a folded cascode amplifier and a cascode compensation part. The folded cascode amplifier can output a larger output voltage swing while ensuring the LDO loop gain. PMOS transistors M28 and M29 are used to form an input pair of transistors. MOS transistors M31 and M32 provide appropriate bias for the input pair of transistors, compare the reference voltage VREF and the feedback voltage VFB, and work in the saturation region through M34 and M35 to adjust the startup voltage of the LDO circuit.

5. According to claim 4, a method for effectively improving the LDO power supply rejection ratio by cascode compensation, It is characterized in that The cascode compensation circuit includes a MOS tube M40, a MOS tube M42, a MOS tube M38, and a compensation capacitor Cc; the drain of the MOS tube M40 is connected to the drain of the MOS tube M42 and the negative end of the compensation capacitor Cc, the output VO of the folded common source amplifier is connected to the positive end of the compensation capacitor Cc, the drain of the MOS tube M38, and the drain of the MOS tube M39, the source of the MOS tube M40 is connected to the power supply, and the source of the MOS tube M42 is connected to the ground.

6. According to claim 1, a method for effectively improving the LDO power supply rejection ratio through cascode compensation, It is characterized in that The resistor feedback network includes a resistor R5 and a resistor R6, the negative end of the resistor R5 and the positive end of the resistor R6 are connected to the negative input terminal VFB of the error amplifier EA, the positive end of the resistor R5 is connected to the output terminal VOUT of the LDO, and the negative end of the resistor R6 is connected to the ground.

Images