Wafer-level layering failure analysis and sample preparation method of chip

Abstract

The invention provides a wafer-level layering failure analysis and sample preparation method of a chip, which comprises the following steps of: preprocessing a chip sample, positioning crystal grains, grinding and thinning according to the plane projection of the crystal grains to carry out primary processing, cutting a target sample, continuously carrying out plane grinding to remove a ball grid array (BGA) solder ball, and preparing the wafer-level layering failure analysis and sample preparation method of the wafer-level layering failure analysis and sample preparation method of the chip. The method comprises the following steps of: adding the raw materials into a first chemical reagent, a second chemical reagent and a third chemical reagent in sequence to react so as to release the residual stress of the packaging structure to the greatest extent, reduce the damage to failure morphology in a sample preparation process and obtain separated bare crystal grains, and finally scanning and analyzing the bare crystal grains by using an ultrasonic acoustic microscope. The method is used for determining whether the advanced technology chip has potential poor layering of the low-dielectric-constant insulating layer and determining the specific position of the poor layering. According to the invention, the technical problem of sample damage caused by external stress in the analysis process can be effectively improved, and subsequent accurate focused ion beam FIB and other physical destructive analysis can be conveniently carried out on the failure position.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor chips, and in particular to a chip wafer-level delamination failure analysis and sample preparation method. Background Art

[0002] With the development of VLSI, it is crucial to reduce the delay of back-end metal interconnects and insulate such interconnects in order to improve chip performance. One of the best ways to achieve this is to use low-k / ultra-low-k interlayer insulating materials to reduce parasitic capacitance, thereby achieving faster operation and accommodating more components in a single chip.

[0003] Low dielectric constant / ultra-low dielectric constant insulating films are generally produced by chemical vapor deposition or spin coating processes, and common materials include black diamond. The preparation of low dielectric constant interlayer insulating films is divided into two steps, including chemical vapor deposition of organosilicon glass and thermally inert organic phase, and then curing and removing the inert phase by ultraviolet irradiation, thereby inducing porosity, reorganizing and strengthening the remaining silicon oxide matrix to form the final nano-scale porous film. However, some technical indicators of this porous structure film have certain defects, such as low elastic modulus, low mechanical strength, poor adhesion, and residual tensile stress. At present, the industry has generally found that there is a delamination problem at the interface of low dielectric constant insulating films. For example, in packaging processes such as wafer cutting, damage to the cutting path may cause slight delamination of the bonding surface of the low dielectric constant insulating film and other metal layers or insulating layers. Since the area of ​​the delamination area and the gaps generated by the delamination are very small, reaching the micron level, the electrical performance is less affected when the package is just completed. Therefore, after the chip is packaged, it is possible to pass the final electrical test FT (Final Test) and flow out to the end user. This type of chip with micro-layering of low dielectric constant insulating film may experience layer expansion under the combined effects of various environmental stresses (such as high and low temperature cycles, moisture, etc.) and electrical stress in subsequent actual work, resulting in adverse phenomena such as voids, cracks, and stacking faults, which will eventually cause current leakage between metal interconnects or even short circuits and other failures.

[0004] In actual engineering, the functional impact of chip failure is confirmed, the actual problem of failure is analyzed, the cause of failure is clarified, and finally a response strategy is drawn up to reduce or even avoid the occurrence of failure. This analysis process includes a variety of methods and tools such as physical, chemical, and electrical. Taking a typical advanced process chip packaging form-wafer-level flip chip FCCSP (Flip Chip Chip Scale Package) as an example, the conventional analysis method for the delamination failure of low dielectric constant insulating film is generally to use epoxy resin cold embedding and then perform fine cutting such as cross-section grinding of the sample, and observe the location of the delamination with a scanning electron microscope. However, the above conventional analysis methods for the delamination failure of low dielectric constant insulating film have the following disadvantages:

[0005] 1. Advanced process chips have many metal interconnect layers (generally more than 10 layers), and there are through holes between the metal layers, forming a complex multi-layer structure of metal-insulating layer-through hole-silicon. Due to the differences in hardness and elasticity of various materials, coupled with the stress accumulated during wafer manufacturing, the plane pulling during cross-section grinding can easily lead to further fragmentation and dislocation of the multi-layer structure, destroying the original defect morphology;

[0006] 2. Low dielectric constant insulating film delamination defects are often not stably characterized and screened in chip functional performance testing, which greatly increases the uncertainty of finding the defect location using the cross-sectional grinding method. There is a certain probability that the expected delamination failure phenomenon is not found after grinding to the suspected location, resulting in analysis failure.

[0007] Based on the above situation, there is an urgent need for an analysis and sample preparation solution that can improve sample damage caused by external stress during the analysis process. Summary of the invention

[0008] The present invention provides a chip wafer-level delamination failure analysis and sample preparation method, which can effectively improve the technical problem of sample damage caused by external stress during the analysis process. The present invention can improve the ability to identify delamination defects without damaging the failure morphology, ensure the success rate of locating potential low-dielectric constant insulating layer delamination failures, and ensure the effect of subsequent further analysis.

[0009] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0010] A chip wafer-level delamination failure analysis and sample preparation method includes the following processes:

[0011] S1. Provide chip samples to be analyzed and pre-treat the samples;

[0012] S2, positioning the crystal grains of the sample, determining the plane projection area of ​​the crystal grains, and thinning the plastic encapsulation epoxy resin on the top of the chip to expose the back of the crystal grains;

[0013] S3, cutting and removing the plastic encapsulation epoxy resin and the PCB substrate in the area outside the projection area of ​​the crystal grain to obtain a target sample;

[0014] S4, performing plane grinding on the surface of the PCB substrate of the target sample to remove the BGA solder balls (Ball Grid Array, ball grid array packaging), and stopping grinding after the metal pads are exposed on the surface of the PCB substrate;

[0015] S5, immersing the ground target sample in a first chemical reagent with a preset ratio and heated to react until the plastic encapsulation epoxy resin, the bottom filling glue, and the metal wire of the PCB substrate are removed;

[0016] S6, placing the target sample after the immersion treatment in a second chemical reagent with a preset ratio to react until the solder ball bumps are completely removed and the grains fall off the PCB substrate;

[0017] S7, soaking the fallen grains in a third chemical reagent to remove the polyimide protective film on the surface of the grains, and washing and drying them;

[0018] S8. Place the dried bare die under an ultrasonic acoustic microscope for scanning, and finally determine whether there is poor delamination of the low dielectric constant insulating layer based on the scanning result, and determine the specific location of the poor delamination.

[0019] The present invention first pre-treats the chip sample to stimulate the potential poor delamination of the low dielectric constant insulating layer, then locates the grains, grinds and thins them according to their plane projection for preliminary treatment, and then cuts the target sample, then continues plane grinding to remove the BGA solder balls, and puts them into a variety of chemical reagents for reaction to release the residual stress of the packaging structure to the greatest extent, reduce the damage to the failure morphology during the sample preparation process, and finally uses an ultrasonic acoustic microscope to scan and analyze the bare grains to determine whether there is potential poor delamination of the low dielectric constant insulating layer in the advanced process chip and to determine the location of the poor delamination. The present invention can effectively improve the technical problem of sample damage caused by external stress during the analysis process, and facilitate the subsequent precise physical destructive analysis of the failure position such as focused ion beam FIB (Focused Ion Beam).

[0020] Furthermore, the structure of the chip sample in step S1 includes a PCB substrate, a crystal grain fixed on the PCB substrate with the active area facing the substrate using a low dielectric constant insulating film process, solder ball bumps connecting the crystal grain and the PCB substrate, a bottom filling glue filling between the crystal grain and the PCB substrate, and an epoxy resin that is injection molded and wraps the crystal grain.

[0021] Further, in step S1, the process of pre-treating the sample is as follows:

[0022] The samples were placed in a high temperature and high humidity environmental stress test box. The environmental stress setting conditions were 120°C to 140°C and 80% to 90% humidity for at least 96 hours. After the pretreatment, the chips were sealed in an antistatic bag for 12 to 24 hours.

[0023] Through pretreatment, the delamination position of the low dielectric constant insulating layer of the chip sample is conducive to the absorption of moisture, which can stimulate the potential poor delamination of the low dielectric constant insulating layer.

[0024] Further, in step S2, X-rays of preset energy are used to perform perspective observation of the sample and determine the planar projection area where the grains are located, wherein the energy voltage of the X-rays is set to 60-70 kV, and then a metallographic grinder is used to perform planar grinding and thinning on the top of the chip to expose the back of the grains, wherein the grinding disk speed of the metallographic grinder is set to 50-100 r / min.

[0025] During positioning, X-rays can be used for accurate perspective determination to improve positioning accuracy, and then plane grinding is performed to expose the back of the crystal grain in the chip sample to facilitate subsequent processing.

[0026] Further, in step S3, a cutting machine is used to cut and remove the plastic encapsulation epoxy resin and the PCB substrate in the area outside the projection area of ​​the die, wherein the blade of the cutting machine is made of diamond material, and the spindle speed of the cutting machine is set to 100-150 r / min.

[0027] The chip samples can be quickly cut by using a cutting machine to obtain the target samples, remove useless waste materials, and further improve the subsequent processing efficiency.

[0028] Further, in step S4, a metallographic grinder is used to plane grind the surface of the PCB substrate where the BGA solder balls are located, wherein the grinding disc speed of the metallographic grinder is set to 50-100 r / min.

[0029] After obtaining the target sample, the BGA solder balls on the surface of the PCB substrate of this part need to be further ground and removed to avoid affecting the subsequent sample preparation process.

[0030] Further, in step S5, the first chemical reagent is a mixed acid solution prepared by mixing fuming nitric acid and fuming sulfuric acid and baking at high temperature, wherein the mass fraction of fuming nitric acid and fuming sulfuric acid is 98% to 100%, the volume ratio of fuming nitric acid to fuming sulfuric acid is 3:1, the heating temperature is 100°C to 110°C, and the chip immersion reaction time is 10 to 15S.

[0031] The target sample is immersed in a mixed acid solution, which can reduce the corrosion of metals such as the under bump metallurgy (UBM) and redistribution metal layer (RDL) on the surface of the grain while corroding the plastic encapsulation epoxy resin and the bottom filling glue, effectively releasing the residual stress of the packaging structure and reducing the damage to the failure morphology during the sample preparation process.

[0032] Further, in step S6, the second chemical reagent is a tin stripping solution prepared by mixing nitric acid and alkyl sulfonic acid, wherein the mass fraction of nitric acid is 60% to 70%, and the nitric acid content in the tin stripping solution is 30% to 40%, and the alkyl sulfonic acid content is 10% to 15%.

[0033] The above-mentioned second chemical reagent can effectively remove the solder ball bumps connecting the crystal grain and the PCB substrate until the crystal grain is separated from the PCB substrate.

[0034] Further, in step S7, the third chemical reagent is a heated anhydrous ethylenediamine solvent.

[0035] The anhydrous ethylenediamine solvent can be used to effectively clean the crystal grains and remove the polyimide protective film on the surface of the crystal grains.

[0036] Further, in step S8, after obtaining the final bare grain sample, the grain is placed horizontally with the back side facing upward, and then an ultrasonic tomography analysis is performed vertically on the grain from the back side using an ultrasonic acoustic microscope to confirm the location of the delamination defect;

[0037] In the image acquisition system of the ultrasonic acoustic microscope, if a point-shaped, line-shaped or block-shaped white abnormality is found in the scanning image of the grain projection surface, it is confirmed that the position is the location where the low dielectric constant insulating layer has poor delamination.

[0038] The present invention utilizes an ultrasonic acoustic microscope to scan and observe the bare crystal grains, and can effectively and accurately obtain the position of the abnormality occurring in the bare crystal grains, thereby improving the success rate of locating the delamination failure of the low dielectric constant insulating layer.

[0039] The beneficial effects of the present invention are as follows:

[0040] The failure analysis and sample preparation method of the present invention releases the residual stress of the packaging structure to the maximum extent, reduces the damage to the failure morphology during the sample preparation process, and finally achieves the purpose of detecting whether there is potential poor delamination of the low dielectric constant insulating layer in the advanced process chip and determining the location of the poor delamination, so as to facilitate the subsequent accurate physical destructive analysis of the failure location such as focused ion beam FIB (Focused Ion Beam). The present invention can improve the recognition ability of delamination defects without damaging the failure morphology, ensure the success rate of locating the potential low dielectric constant insulating layer delamination failure, and ensure the effect of subsequent further analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic flow chart of a chip wafer-level delamination failure analysis and sample preparation method of the present invention;

[0042] Figure 2 This is the structural cross-section diagram of the FCCSP chip sample;

[0043] Figure 3 It is a structural cross-section diagram of the local magnification of the bump and the nearby grains;

[0044] Figure 4 The structure cross-section diagram of the obtained grain after partial enlargement;

[0045] Figure 5 Schematic diagram of a grain with abnormally layered low dielectric constant insulating layer under an ultrasonic acoustic microscope.

[0046] In the figure: PCB substrate 1, BGA solder balls 2, crystal grains 3, solder ball bumps 4, bottom filling glue 5, plastic encapsulation epoxy resin 6, under bump metal layer 7, polyimide protective film 8, redistribution metal layer 9, first passivation layer 10, second passivation layer 11, interconnection metal layer 12, low dielectric constant insulating layer 13, metal through hole 14, substrate active area 15. DETAILED DESCRIPTION

[0047] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0048] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] Embodiment 1:

[0050] like Figure 1 As shown, this embodiment provides a chip wafer-level delamination failure analysis and sample preparation method, including the following process:

[0051] S1. Provide chip samples to be analyzed and pre-treat the samples;

[0052] S2, positioning the crystal grain 3 of the sample, determining the plane projection area where the crystal grain 3 is located, and thinning the plastic encapsulation epoxy resin 6 on the top of the chip to expose the back of the crystal grain 3;

[0053] S3, cutting and removing the plastic encapsulation epoxy resin 6 and the PCB substrate 1 in the area outside the projection area of ​​the crystal grain 3 to obtain a target sample;

[0054] S4, performing plane grinding on the surface of the PCB substrate 1 of the target sample to remove the BGA solder balls 2 (Ball Grid Array, ball grid array packaging), and stopping grinding until the metal pads are exposed on the surface of the PCB substrate 1;

[0055] S5, immersing the ground target sample in a first chemical reagent with a preset ratio and heated to react until the plastic epoxy resin 6, the bottom filling glue 5, and the metal wires of the PCB substrate 1 are removed;

[0056] S6, placing the target sample after the immersion treatment in a second chemical reagent with a preset ratio to react until the solder ball bumps 4 are completely removed and the grains 3 fall off from the PCB substrate 1;

[0057] S7, placing the fallen grains 3 in a third chemical reagent for immersion, removing the polyimide protective film 8 on the surface of the grains 3, and washing and drying them;

[0058] S8, placing the dried bare die 3 under an ultrasonic acoustic microscope for scanning, and finally judging whether there is poor delamination of the low dielectric constant insulating layer 13 according to the scanning result, and determining the specific location of the poor delamination.

[0059] In this embodiment, the structure of the chip sample in step S1 includes a PCB substrate 1, a crystal grain 3 fixed on the PCB substrate 1 with an active area facing the substrate using a low dielectric constant insulating film process, a solder ball bump 4 connecting the crystal grain 3 and the PCB substrate 1, a bottom filling glue 5 filling between the crystal grain 3 and the PCB substrate 1, and a plastic encapsulation epoxy resin 6 that is injection molded and wraps the crystal grain 3.

[0060] The process of pre-processing the sample in step S1 is as follows:

[0061] The samples were placed in a high temperature and high humidity environmental stress test box. The environmental stress setting conditions were 120°C to 140°C and 80% to 90% humidity for at least 96 hours. After the pretreatment, the chips were sealed in an antistatic bag for 12 to 24 hours.

[0062] The pretreatment is beneficial for the delamination position of the low dielectric constant insulating layer 13 of the chip sample to absorb moisture, and can stimulate potential delamination failure of the low dielectric constant insulating layer 13 .

[0063] In step S2 of this embodiment, X-rays with preset energy are used to observe the sample in perspective and determine the plane projection area where the grain 3 is located, wherein the energy voltage of the X-rays is set to 60-70 kV, and then a metallographic grinder is used to plane grind and thin the top of the chip to expose the back of the grain 3, wherein the grinding disk speed of the metallographic grinder is set to 50-100 r / min. When positioning, X-rays can be used for accurate perspective determination to improve the positioning accuracy, and then plane grinding is performed to expose the back of the grain 3 of the chip sample for subsequent processing.

[0064] In step S3 of this embodiment, a cutting machine is used to cut and remove the plastic epoxy resin 6 and the PCB substrate 1 in the area outside the projection area of ​​the die 3, wherein the blade of the cutting machine is made of diamond material, and the spindle speed of the cutting machine is set to 100-150r / min. The cutting machine can be used to quickly cut the chip sample to obtain the target sample, cut and remove the useless waste, and further improve the subsequent processing efficiency.

[0065] In step S4 of this embodiment, a metallographic grinder is used to plane grind the surface of the PCB substrate 1 where the BGA solder balls 2 are located, wherein the grinding disc speed of the metallographic grinder is set to 50-100 r / min. After obtaining the target sample, the BGA solder balls 2 on the surface of the PCB substrate 1 of this part need to be further ground and removed to avoid affecting the subsequent sample preparation process.

[0066] In step S5 of this embodiment, the first chemical reagent is a mixed acid solution prepared by mixing fuming nitric acid and fuming sulfuric acid and baking at high temperature, wherein the mass fraction of fuming nitric acid and fuming sulfuric acid is 98% to 100%, the volume ratio of fuming nitric acid to fuming sulfuric acid is 3:1, the heating temperature is 100°C to 110°C, and the chip immersion reaction time is 10 to 15S.

[0067] The present invention utilizes a mixed acid solution to immerse the target sample, which can reduce the corrosion of metals such as the under bump metallurgy layer 7 (UBM) and the redistribution metal layer 9 (RDL) on the surface of the grain 3 while corroding the plastic epoxy resin 6 and the bottom filling glue 5, effectively releasing the residual stress of the packaging structure and reducing the damage to the failure morphology during the sample preparation process.

[0068] In step S6 of the present embodiment, the second chemical reagent is a tin stripping solution prepared by mixing nitric acid and alkyl sulfonic acid, wherein the mass fraction of nitric acid is 60% to 70%, and the nitric acid content in the tin stripping solution is 30% to 40%, and the alkyl sulfonic acid content is 10% to 15%. The above-mentioned second chemical reagent can effectively remove the solder ball bump 4 connecting the crystal grain 3 and the PCB substrate 1 until the crystal grain 3 is separated from the PCB substrate 1.

[0069] In step S7 of this embodiment, the third chemical reagent is a heated anhydrous ethylenediamine solvent. The anhydrous ethylenediamine solvent can be used to effectively clean the crystal grains 3 and remove the polyimide protective film 8 on the surface of the crystal grains 3.

[0070] In step S8 of this embodiment, after obtaining the final bare die 3 sample, the die 3 is placed horizontally with the back side facing upward, and then an ultrasonic tomography analysis is performed vertically on the back side of the die 3 using an ultrasonic acoustic microscope to confirm the location of the delamination defect;

[0071] In the image acquisition system of the ultrasonic acoustic microscope, if a point-shaped, line-shaped or block-shaped white abnormality is found in the scanning image of the projection surface of the grain 3, it is confirmed that the position is the position where the low dielectric constant insulating layer 13 has delamination defects.

[0072] The present invention utilizes an ultrasonic acoustic microscope to scan and observe the bare crystal grain 3, and can effectively and accurately obtain the position of the abnormality occurring in the bare crystal grain 3, thereby improving the success rate of locating the delamination failure of the low dielectric constant insulating layer 13.

[0073] In the following, this embodiment takes FCCSP chip as an example to further illustrate the failure analysis and sample preparation method of FCCSP chip. It should be clear that the application object of the present invention is chip products under the advanced wafer manufacturing process below 0.18um, and the packaging form is not limited to the FCCSP packaged chip described in this preferred embodiment, but can also be applied to other packaging forms commonly used in advanced chip processes such as FCBGA (Flip Chip Ball Grid Array), WLCSP (Wafer Level Chip Scale Package), CoWoS (Chipon Wafer on Silicon), etc.

[0074] In this embodiment, if Figure 2 and Figure 3 As shown in the figure, the wafer manufacturing process of the FCCSP chip sample is TSMC 40LP (TSMC 40nm process), the chip size is 20mm*20mm*2mm in length, width and height, and the bump pitch is 110um. The overall structure of the chip includes a PCB substrate 1, a BGA solder ball 2, a crystal grain 3 fixed on the PCB substrate 1 with the active area facing the substrate using a low dielectric constant insulating film process, a solder ball bump 4 connecting the crystal grain and the PCB substrate, a bottom filling glue 5 filling the gap between the crystal grain 3 and the PCB substrate 1, and a plastic encapsulation epoxy resin 6 that is molded by injection and wraps the crystal grain 3; in addition, the morphology of the local multilayer structure of the solder ball bump 4 and the nearby crystal grain 3 after enlargement is shown in the figure. Figure 3 As shown, it includes solder ball bumps 4, under-bump metal layer 7, polyimide protective film 8 on the surface of grain 3, redistribution metal layer 9, first passivation layer 10, second passivation layer 11, interconnection metal layer 12, low dielectric constant insulating layer 13, metal through hole 14, and substrate active area 15 where the transistor is located.

[0075] The wafer-level delamination failure analysis and sample preparation method of the above-mentioned FCCSP chip includes the following processes:

[0076] 1. Obtain the FCCSP chip samples to be analyzed and place them in a high temperature and high humidity environmental stress test box. The environmental stress setting conditions are 130°C, 85% humidity, and a duration of 96 hours. After completion, place the chip in an antistatic bag and seal it for 24 hours;

[0077] 2. Use X-rays with an energy voltage of 70 kV to observe the sample and determine the plane projection area where the grain 3 is located. Then use a high-precision metallographic grinder with a grinding disc speed set to 50 r / min to plane grind and thin the plastic encapsulation epoxy resin 6 on the top of the chip until the back of the grain 3 is exposed;

[0078] 3. Use a low-speed precision cutting machine to cut and remove the plastic epoxy resin 6 and the PCB substrate 1 outside the projection area of ​​the die 3 to obtain the target sample, wherein the cutting blade is made of diamond material and the spindle speed is set to 100r / min;

[0079] 4. Use a high-precision metallographic grinder with a grinding disc speed set to 50 r / min to plane grind the surface of the PCB substrate 1 of the target sample, remove the BGA solder balls 2 on the substrate, and stop grinding after the metal pads are exposed on the substrate surface, leaving the PCB substrate 1;

[0080] 5. Place the ground target sample in a first chemical reagent for reaction until the plastic epoxy resin 6, the bottom filling glue 5, and the metal wires of the PCB substrate 1 are removed; wherein the first chemical reagent is prepared by mixing 98% by mass fuming nitric acid and 100% by mass fuming sulfuric acid and baking them at high temperature, the volume ratio of fuming nitric acid to fuming sulfuric acid is 3:1, the heating temperature is 110°C, and the chip immersion reaction time is 12s; practice has proved that a good chemical reagent ratio, heating temperature, and reaction time can reduce the corrosion of metals such as UBM and RDL on the surface of the grain 3 while corroding the molding epoxy resin 6 and the bottom filling glue 5;

[0081] 6. Place the target sample after the immersion treatment in a second chemical reagent for reaction, wherein the reagent is a tin stripping solution with nitric acid and alkyl sulfonic acid as main components, the mass fraction of nitric acid in the tin stripping solution is 70%, the nitric acid content is 40%, and the alkyl sulfonic acid content is 15%. The second chemical reagent can effectively remove the solder ball bumps 4 connecting the crystal grain 3 and the PCB substrate 1 until the crystal grain 3 is separated from the PCB substrate 1;

[0082] 7. Soak the fallen grain 3 in a third chemical reagent to remove the polyimide protective film 8 on the surface of the grain 3, and then clean and dry it. The third chemical reagent is anhydrous ethylenediamine with a mass fraction of >99%. After observing that the polyimide protective film 8 is fallen off or dissolved, take out the grain 3, and clean it in an ultrasonic cleaning machine in the order of dilute sulfuric acid, alcohol, and deionized water. Finally, take out the bare grain 3 and dry it naturally at room temperature. The morphology of the obtained grain 3 is as follows: Figure 4 As shown;

[0083] 8. After obtaining the final bare grain 3 sample, the grain 3 is placed horizontally with the back side facing upward, and an ultrasonic tomography analysis is performed vertically on the grain 3 from the back side using an ultrasonic acoustic microscope to confirm the location of the delamination defect; wherein the frequency of the ultrasonic transducer selected by the acoustic microscope is 250 MHz, the focal length is 1.4 mm, the scanning mode is C-scan reflection mode, and the focus position is the RDL / passivation layer interface, the low dielectric constant insulating layer 13 / interconnection metal layer 12 interface, and the low dielectric constant insulating layer 13 / low dielectric constant insulating layer 13 interface; Figure 5 As shown, in the image acquisition system of the acoustic microscope, if white abnormal shadows such as point S901, line S902 or block S903 are found in the scanning image of the projection surface of the grain 3, it is confirmed that the shadow position is the position where the low dielectric constant insulating layer 13 has poor delamination.

[0084] The failure analysis and sample preparation method of the present invention releases the residual stress of the packaging structure to the maximum extent, reduces the damage to the failure morphology during the sample preparation process, and finally achieves the purpose of detecting whether there is potential poor delamination of the low dielectric constant insulating layer 13 in the advanced process chip and determining the location of the poor delamination, which facilitates the subsequent accurate physical destructive analysis of the failure location such as focused ion beam FIB (Focused Ion Beam). The present invention can improve the recognition ability of delamination defects without damaging the failure morphology, ensure the success rate of positioning the potential low dielectric constant insulating layer 13 delamination failure, and ensure the effect of subsequent further analysis.

[0085] The above embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Any equivalent substitution or change made by a person skilled in the art based on the present invention is within the protection scope of the present invention.

Claims

1. A chip wafer-level delamination failure analysis and sample preparation method, characterized in that: The process includes: S1. Provide chip samples to be analyzed and pre-treat the samples; S2, positioning the crystal grain (3) of the sample, determining the plane projection area of ​​the position of the crystal grain (3), and thinning the plastic encapsulation epoxy resin (6) on the top of the chip to expose the back of the crystal grain (3); S3, cutting and removing the plastic encapsulation epoxy resin (6) and the PCB substrate (1) in the area outside the projection area of ​​the crystal grain (3) to obtain a target sample; S4, plane grinding is performed on the surface of the PCB substrate (1) of the target sample to remove the BGA solder balls (2), and the grinding is stopped after the metal pads are exposed on the surface of the PCB substrate (1); S5, immersing the ground target sample in a first chemical reagent with a preset ratio and heated to react until the plastic encapsulation epoxy resin (6), the bottom filling glue (5), and the metal wires of the PCB substrate (1) are removed; S6, placing the target sample after the immersion treatment in a second chemical reagent with a preset ratio to react until the solder ball bumps (4) are completely removed and the grains (3) fall off from the PCB substrate (1); S7, placing the detached crystal grains (3) in a third chemical reagent for immersion, removing the polyimide protective film (8) on the surface of the crystal grains (3), and washing and drying them; S8, placing the air-dried bare crystal grain (3) under an ultrasonic acoustic microscope for scanning, and finally judging whether there is poor delamination of the low dielectric constant insulating layer (13) based on the scanning result, and determining the specific location of the poor delamination.

2. The wafer-level delamination failure analysis and sample preparation method of a chip according to claim 1, characterized in that: The structure of the chip sample in step S1 comprises a PCB substrate (1), a crystal grain (3) fixed on the PCB substrate (1) with an active region facing the substrate by adopting a low dielectric constant insulating film process, a solder ball bump (4) connecting the crystal grain (3) and the PCB substrate (1), a bottom filling glue (5) filling between the crystal grain (3) and the PCB substrate (1), and a plastic encapsulation epoxy resin (6) that is molded by injection molding and wraps the crystal grain (3).

3. The wafer-level delamination failure analysis and sample preparation method of a chip according to claim 1, characterized in that: In step S1, the process of pre-treating the sample is as follows: The samples were placed in a high temperature and high humidity environmental stress test box. The environmental stress setting conditions were 120°C to 140°C and 80% to 90% humidity for at least 96 hours. After the pretreatment, the chips were sealed in an antistatic bag for 12 to 24 hours.

4. The wafer-level delamination failure analysis and sample preparation method of a chip according to claim 1, characterized in that: In step S2, X-rays of preset energy are used to perform perspective observation on the sample and determine the plane projection area where the grain (3) is located, wherein the energy voltage of the X-rays is set to 60-70 kV, and then a metallographic grinder is used to plane grind and thin the top of the chip until the back of the grain (3) is exposed, wherein the grinding wheel speed of the metallographic grinder is set to 50-100 r / min.

5. The wafer-level delamination failure analysis and sample preparation method of a chip according to claim 1, characterized in that: In step S3, a cutting machine is used to cut and remove the plastic encapsulation epoxy resin (6) and the PCB substrate (1) in the area outside the projection area of ​​the grain (3), wherein the blade of the cutting machine is made of diamond material and the spindle speed of the cutting machine is set to 100-150 r / min.

6. The wafer-level delamination failure analysis and sample preparation method of a chip according to claim 1, characterized in that: In step S4, a metallographic grinder is used to plane grind the surface of the PCB substrate (1) where the BGA solder ball (2) is located, wherein the grinding disc speed of the metallographic grinder is set to 50-100 r / min.

7. The wafer-level delamination failure analysis and sample preparation method of a chip according to claim 1, characterized in that: In step S5, the first chemical reagent is a mixed acid solution prepared by mixing fuming nitric acid and fuming sulfuric acid and baking at high temperature, wherein the mass fraction of fuming nitric acid and fuming sulfuric acid is 98% to 100%, the volume ratio of fuming nitric acid to fuming sulfuric acid is 3:1, the heating temperature is 100°C to 110°C, and the chip immersion reaction time is 10 to 15S.

8. The wafer-level delamination failure analysis and sample preparation method of a chip according to claim 1, characterized in that: In step S6, the second chemical reagent is a tin stripping solution prepared by mixing nitric acid and alkyl sulfonic acid, wherein the mass fraction of nitric acid is 60% to 70%. At the same time, the nitric acid content in the tin stripping solution is 30% to 40%, and the alkyl sulfonic acid content is 10% to 15%.

9. The wafer-level delamination failure analysis and sample preparation method of a chip according to claim 1, characterized in that: In step S7, the third chemical reagent is a heated anhydrous ethylenediamine solvent.

10. The wafer-level delamination failure analysis and sample preparation method of a chip according to claim 1, characterized in that: In step S8, after obtaining the final bare grain (3) sample, the grain (3) is placed horizontally with the back side facing upward, and then an ultrasonic acoustic microscope is used to vertically perform ultrasonic tomography analysis on the grain (3) from the back side of the grain (3), and the location of the delamination defect is confirmed; In the image acquisition system of the ultrasonic acoustic microscope, if a point-shaped, line-shaped or block-shaped white abnormality is found in the scanning image of the projection surface of the grain (3), it is confirmed that the position is the position where the low dielectric constant insulating layer (13) has poor delamination.

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