Asymmetric AMP architecture driving and control integrated system based on ARM + FPGA platform

Abstract

The invention relates to the related technical field of drive control, in particular to an asymmetric AMP architecture drive control integrated system based on an ARM + FPGA platform, which adopts an asymmetric AMP architecture based on the ARM + FPGA platform and comprises an ARM end, an FPGA end and a PCIE bare core of the asymmetric AMP architecture. The FPGA end is used for realizing a motor control flow, a sensor reading flow, a hardware alarm signal processing flow and an oscilloscope data acquisition flow; the ARM end is used for realizing processes corresponding to the lower computer, the upper computer, the ECAT module and the communication module respectively; and the PCIE bare core is respectively connected with the ARM end and the FPGA end, and is used for realizing real-time stable transmission between the FPGA and the ARM through a preset communication protocol, and ensuring a microsecond-level communication period by utilizing high-speed transmission of the PCIE bare core and the stability of a bare core timer.

Description

Technical Field

[0001] The present application relates to the technical field related to drive control, and specifically to an asymmetric AMP architecture integrated drive control system, device, electronic device and storage medium based on an ARM+FPGA platform. Background Art

[0002] In traditional industrial robot applications, building a robot system usually requires independent control systems, drive systems, and power systems, which not only increases development costs, but also may encounter large volume and compatibility issues during integration due to the independence of the systems. In particular, stability issues in any one system may lead to instability in the entire robot system. Therefore, the industry seeks a drive-control integrated solution to reduce costs, reduce volume, and ensure efficient and stable operation of the system. However, the complexity and functional implementation of this integrated solution place higher requirements on the development platform. Summary of the invention

[0003] In view of this, the embodiments of the present application are directed to providing an asymmetric AMP architecture drive-control integrated system based on an ARM+FPGA platform.

[0004] The present application provides an asymmetric AMP architecture drive-control integrated system based on an ARM+FPGA platform, which adopts an asymmetric AMP architecture based on an ARM+FPGA platform, including: an ARM side, an FPGA side, and a PCIE bare core of an asymmetric AMP architecture;

[0005] The FPGA side is used to implement the motor control process, sensor reading process, hardware alarm signal processing process, and oscilloscope data acquisition process;

[0006] The ARM side is used to implement the corresponding processes of the lower computer, upper computer, ECAT module and communication module respectively;

[0007] The PCIE bare core is connected to the ARM end and the FPGA end respectively, and is used to realize the real-time and stable transmission between FPGA and ARM through the preset communication protocol, and utilizes the high-speed transmission of the PCIE bare core and the stability of the bare core timer to ensure the communication cycle in microseconds.

[0008] In some embodiments, the PCIE bare core is specifically used to communicate using a custom communication protocol that is only used for the integrated driver and control software service;

[0009] Among them, the communication protocols that only serve the integrated drive and control software include:

[0010] Each data is divided into two parts: read and write, corresponding to the offset respectively. PCIE only accepts the data width of this part to be sent, so that FPGA can communicate with ARM end efficiently.

[0011] In some embodiments, the PCIE bare core utilizes the bare core CPU's timer to synchronize data transmission, ensuring the timing and stability of communication.

[0012] In some embodiments, the FPGA end is specifically used to receive the motor position command and the motor speed command sent from the robot model and transmit the data of the robot system after the algorithm processing:

[0013] The data include: current, motor encoder position, electrical angle, speed information;

[0014] Obtain the feedback signal of the system, perform voltage feedforward correction according to the current information, and then filter out the noise through low-pass filtering; perform corresponding PID control according to the received instructions, convert the user's intention into a motion target through the instruction parsing module, first eliminate some noise through feedforward control, and then perform coordinate transformation according to the electrical angle; then, the robot model module calculates the corresponding motion plan, including the path and speed curve, according to the physical and dynamic characteristics of the robot; the motion plan calculation results are passed to the torque algorithm module to determine the specific force and torque required to execute these movements; among them, the instructions include: position instructions, speed instructions or torque instructions; the speed instruction is directly passed to the speed PI module for calculation through trapezoidal acceleration and deceleration;

[0015] The torque control system includes two control modes: one is to adjust the motor speed through the speed regulator and PI controller to achieve the required torque output; the other is to use the acceleration sensor and secondary control mechanism for fine adjustment to ensure the accuracy of the torque output; based on the pre-equipped position and speed control module, the position and speed of the motor are adjusted in real time using the feedback information of the position and speed sensors to maintain the desired trajectory and speed;

[0016] The current sensor monitors the motor current to prevent overload and provide feedback to optimize control. The vector controller is responsible for adjusting the direction and strength of the motor's magnetic field and generates precise control signals for the drive motor based on SVPWM (space vector pulse width modulation) technology. The dead zone compensation module eliminates the dead zone effect in the drive circuit and reduces control errors.

[0017] The duty cycle of 6-way PWM is output based on SVPWM (space vector pulse width modulation) technology, and finally the hardware drive system is driven to control the motor through 6-way PWM signal output.

[0018] In some embodiments, the FPGA end is specifically used to read the alarm signals issued by the hardware system through level monitoring, where the alarm signals include: driver overcurrent signal, overload signal, overtemperature signal, bus overcurrent signal and undervoltage signal; whenever an alarm signal is detected, the system is enabled and an error message is sent to the ARM end through PCIE bare core communication.

[0019] In some embodiments, the FPGA end is used for, for current acquisition, using the Sigma-Delta ADC reading method, reading through sinc filtering; for encoders, using 485 serial port communication to read; for conveyor belt encoders, reading through the ABZ pulse counting method; for data acquisition by the oscilloscope, the required data is transmitted to the ARM end through PCIE bare core communication for storage and real-time display.

[0020] In some embodiments, the process corresponding to the upper computer is responsible for interaction, displaying data information transmitted by the lower computer and sending user input information to the lower computer, and realizing logical processing of preset functions.

[0021] In some embodiments, the corresponding process of the lower computer is responsible for sending the parameters received by each part to the robot model and calculating the corresponding data and outputting it to the upper computer for display.

[0022] In some embodiments, the process corresponding to the communication module is responsible for regularly uploading the parameters of the entire robot model to the cloud, and controlling the logic of the integrated drive and control software through the cloud.

[0023] In some embodiments, the process corresponding to the ECAT module is used to expand the axis through the ECAT protocol, implement the ECAT master station protocol, expand the external axis, and control it in conjunction with the ECAT bus universal servo.

[0024] The present application provides an asymmetric AMP architecture drive-control integrated system based on an ARM+FPGA platform, which adopts an asymmetric AMP architecture based on an ARM+FPGA platform, including: an ARM end, an FPGA end, and a PCIE bare core of an asymmetric AMP architecture; an FPGA end, which is used to implement a motor control process, a sensor reading process, a hardware alarm signal processing process, and an oscilloscope data acquisition process; an ARM end, which is used to implement the processes corresponding to the lower computer, the upper computer, the ECAT module, and the communication module; a PCIE bare core, which is connected to the ARM end and the FPGA end respectively, is used to realize the real-time and stable transmission of FPGA and ARM through a preset communication protocol, and utilizes the high-speed transmission of the PCIE bare core and the stability of the bare core timer to ensure a microsecond communication cycle. In this way, through the PCIE bare core, the ARM end and the FPGA end can realize high-speed and low-latency data transmission. This communication method allows real-time processing of motor control instructions and sensor data to ensure the responsiveness and accuracy of the system. The ARM end integrates the ECAT (Ethernet Control Automation Technology) module to realize communication with other automation equipment. This helps to build a more flexible and scalable automation control system. The asymmetric AMP architecture allows the system to be expanded and maintained without sacrificing performance. The various modules of the system can be upgraded or replaced as needed to adapt to changing application requirements. Through this architecture, the system can achieve high-performance motor control while maintaining the stability and real-time performance of communication. This design not only improves the efficiency of the system, but also enhances the reliability and safety of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0026] Figure 1 It is a structural diagram of an asymmetric AMP architecture drive-control integrated system based on an ARM+FPGA platform provided by an embodiment of the present application.

[0027] Figure 2 It is a schematic diagram of an asymmetric AMP architecture drive-control integrated system based on an ARM+FPGA platform provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] Application Overview

[0030] In traditional industrial robot applications, building a robot system usually requires independent control systems, drive systems, and power systems, which not only increases development costs, but also may encounter large volume and compatibility issues during integration due to the independence of the systems. In particular, stability issues in any one system may lead to instability in the entire robot system. Therefore, the industry seeks a drive-control integrated solution to reduce costs, reduce volume, and ensure efficient and stable operation of the system. However, the complexity and functional implementation of this integrated solution place higher requirements on the development platform.

[0031] The ARM+FPGA platform uses a combination of a quad-core ARM Cortex-A55 processor and a programmable logic FPGA, which communicate via the AMP bare core for PCIE. The advantage of this architecture is its powerful performance and substitutability, allowing flexible configuration options on the ARM side and the FPGA side. The ARM+FPGA architecture can bring comprehensive comparative advantages in performance, cost, power consumption, etc. ARM and FPGA can perform their respective duties and give full play to the unique advantages of the original architecture, and can also cooperate with each other to deal with more complex problems. This platform design can not only efficiently integrate the control system, drive system and power system, but also monitor and process the status of the power system in real time through the parallel processing capability and low latency characteristics of the FPGA, thereby ensuring the efficient and stable operation of the entire robot system. Based on this platform, the ECAT protocol is used for axis expansion through the ARM-side network port; each networked device can be managed through the ARM-side 4G module, including operation status management and usage permission management. Therefore, this platform based on quad-core ARM Cortex-A55 and FPGA is a cost-effective alternative solution for achieving integrated drive and control.

[0032] After introducing the basic principles of the present application, various non-limiting embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0033] Exemplary Methods

[0034] like Figure 1 Figure 2 As shown, the present application provides an asymmetric AMP architecture drive-control integrated system based on an ARM+FPGA platform, which adopts an asymmetric AMP architecture based on an ARM+FPGA platform, including: an ARM end, an FPGA end, and a PCIE bare core of an asymmetric AMP architecture; an FPGA end, which is used to implement a motor control process, a sensor reading process, a hardware alarm signal processing process, and an oscilloscope data acquisition process; an ARM end, which is used to implement the processes corresponding to the lower computer, the upper computer, the ECAT module, and the communication module; a PCIE bare core, which is connected to the ARM end and the FPGA end respectively, is used to realize the real-time and stable transmission of FPGA and ARM through a preset communication protocol, and utilizes the high-speed transmission of the PCIE bare core and the stability of the bare core timer to ensure a microsecond communication cycle. In this way, through the PCIE bare core, the ARM end and the FPGA end can realize high-speed and low-latency data transmission. This communication method allows real-time processing of motor control instructions and sensor data to ensure the responsiveness and accuracy of the system. The ARM end integrates an ECAT (Ethernet Control Automation Technology) module to realize communication with other automation equipment. This helps to build a more flexible and scalable automation control system. The asymmetric AMP architecture allows the system to be expanded and maintained without sacrificing performance. The various modules of the system can be upgraded or replaced as needed to adapt to changing application requirements. Through this architecture, the system can achieve high-performance motor control while maintaining the stability and real-time performance of communication. This design not only improves the efficiency of the system, but also enhances the reliability and safety of the system.

[0035] Specifically, the PCIE bare core communication protocol realizes real-time and stable transmission between FPGA and ARM, and uses the high-speed transmission of PCIE and the stability of the bare core timer to ensure a microsecond communication cycle. The PCIE bare core is specifically used to communicate using a customized communication protocol that only serves the integrated drive and control software; wherein, the communication protocol that only serves the integrated drive and control software includes: dividing each data into two parts, read and write, corresponding to offsets respectively, and PCIE only accepts the data width of this part to enable the FPGA to communicate efficiently with the ARM end. The PCIE bare core uses the bare core CPU timer to synchronize data transmission to ensure the timing and stability of communication.

[0036] Among them, custom communication protocol refers to designing a communication protocol specifically for drive-control software services to meet the needs of specific applications. The protocol can include a simplified data packet structure to reduce processing time and improve transmission efficiency. Divide the data into two parts, read and write, each corresponding to a specific offset. This slicing method helps optimize data transmission because the PCIe interface only processes the necessary data part. Data width matching, that is, adjusting the data width of PCIe according to the read and write requirements of the data to ensure that only the necessary amount of data is transmitted. This helps reduce the load on the PCIe bus and improve overall communication efficiency. Use the bare core CPU timer to synchronize data transmission to ensure the timing and stability of communication. The timer can trigger the sending and receiving of data, as well as monitor communication delays. By optimizing the communication protocol and hardware design, a communication cycle of microseconds can be achieved. This is critical for real-time control systems such as motor control. The design goal of the PCIE bare core communication protocol is to achieve real-time and stable data transmission. This includes handling possible transmission errors and ensuring data integrity.

[0037] Furthermore, the communication protocol should include error detection mechanisms, such as CRC check, to ensure the accuracy of data transmission. At the same time, there should be error handling mechanisms, such as retransmission requests, to deal with possible transmission errors. It is also necessary to ensure that both the ARM processor and the FPGA support the custom communication protocol, including the necessary hardware interfaces and processing capabilities. The communication protocol is implemented in the software on the ARM side and the FPGA side, including data encapsulation, transmission, and decapsulation.

[0038] In practical applications, the performance of the communication protocol can be verified through simulation and actual testing to ensure that it meets the requirements of real-time and stability. Through this highly customized communication protocol and hardware design, the system can achieve efficient data transmission, which is crucial to ensure the performance of the motor control system. This design approach allows the system to handle complex control tasks while maintaining a high response speed.

[0039] In some embodiments, the FPGA end is specifically used to receive the motor position command and motor speed command sent from the robot model and transmit the algorithm to process and parse various data of the robot system: the data includes: current, motor encoder position, electrical angle, speed information; obtain the feedback signal of the system, perform voltage feedforward correction according to the current information, and then filter out the noise through low-pass filtering; perform corresponding PID control according to the received instructions, convert the user's intention into a motion target through the instruction parsing module, first eliminate part of the noise through feedforward control, and then perform coordinate transformation according to the electrical angle; then, the robot model module calculates the corresponding motion plan according to the physical and dynamic characteristics of the robot, including the path and speed curve; the motion plan calculation results are passed to the torque algorithm module to determine the specific force and torque required to execute these movements; wherein the instructions include: position instructions, speed instructions or torque instructions; the speed instructions are directly transmitted to the speed algorithm module through trapezoidal acceleration and deceleration. The torque control system includes two control modes: one is to adjust the motor speed through the speed regulator and PI controller to achieve the required torque output; the other is to use the acceleration sensor and the secondary control mechanism for fine adjustment to ensure the accuracy of the torque output; based on the pre-equipped position and speed control module, the position and speed of the motor are adjusted in real time using the feedback information of the position and speed sensors to maintain the desired trajectory and speed; the current sensor monitors the current of the motor to prevent overload and provides feedback to optimize the control; the vector controller is responsible for adjusting the direction and strength of the motor's magnetic field and generating precise control signals for driving the motor based on SVPWM (space vector pulse width modulation) technology; the dead zone compensation module eliminates the dead zone effect in the drive circuit and reduces the control error; the duty cycle of the 6-way PWM is output based on the SVPWM (space vector pulse width modulation) technology, and finally the 6-way PWM signal output drives the hardware drive system to control the motor.

[0040] In practical applications, precise control of the robot motor is achieved through the coordinated work of multiple control modules and sensors. The following are some key components of the system and their functions:

[0041] A highly integrated and automated motor control system that achieves precise control of the robot's motors through the collaborative work of multiple control modules and sensors. The following are some of the key components of the system and their functions:

[0042] 1. Command reception and analysis:

[0043] The system receives motor position commands, speed commands, and torque commands from the robot model.

[0044] The command parsing module converts the user input command into the motor's motion target.

[0045] 2. Data collection and processing:

[0046] Collect the motor's current, encoder position, electrical angle and speed information.

[0047] Voltage feed-forward correction and low-pass filtering techniques are used to optimize data quality and reduce noise.

[0048] 3.PID control:

[0049] According to the type of instruction received (position, speed or torque), the corresponding PID control algorithm is executed.

[0050] The PID controller adjusts the input to the motor to ensure that the motor output meets the command requirements.

[0051] 4. Motion Planning:

[0052] The robot model module calculates the motion plan, including the path and velocity curve, based on the physical and dynamic characteristics of the robot.

[0053] 5. Torque control:

[0054] The motor speed is adjusted by the speed regulator and PI controller to achieve the required torque output.

[0055] Acceleration sensors and secondary control mechanisms are used for fine adjustment to ensure the accuracy of torque output.

[0056] 6. Position and speed control:

[0057] Using feedback information from position and speed sensors, the position and speed of the motor are adjusted in real time to maintain the desired trajectory and speed.

[0058] 7. Current monitoring:

[0059] Current sensors monitor the current in the motor to prevent overload and provide feedback to optimize control.

[0060] 8. Vector control and SVPWM:

[0061] A vector controller adjusts the direction and strength of the motor's magnetic field.

[0062] SVPWM technique is used to generate precise motor control signals.

[0063] 9. Dead zone compensation:

[0064] The dead zone compensation module eliminates the dead zone effect in the drive circuit and reduces the control error.

[0065] 10.PWM signal output:

[0066] The SVPWM outputs the duty cycle of the 6-channel PWM to control the precise movement of the motor.

[0067] 6-channel PWM signal output to drive the hardware drive system to control the motor.

[0068] 11. System feedback and optimization:

[0069] The system continuously optimizes the control strategy through feedback signals to improve the accuracy and response speed of motor control.

[0070] 12. Security and monitoring:

[0071] The system monitors the motor status to ensure timely response in abnormal situations, such as overcurrent, overload, overtemperature and undervoltage.

[0072] The design of this system needs to take into account real-time performance, accuracy and robustness to ensure that the robot can operate stably under various working conditions. Each control link needs to be carefully designed and debugged to ensure the coordinated operation of the entire system. In addition, the safety and reliability of the system are also important considerations during the design.

[0073] Furthermore, the FPGA end is specifically used to read the alarm signals issued by the hardware system through level monitoring, where the alarm signals include: driver overcurrent signal, overload signal, overtemperature signal, bus overcurrent signal and undervoltage signal; whenever an alarm signal is detected, the system is enabled and an error message is sent to the ARM end through PCIE bare core communication.

[0074] Specifically, level monitoring and alarm processing are important links to ensure the safe operation of the system. The following are the detailed steps and mechanisms of this process:

[0075] 1. Level monitoring:

[0076] The system detects the status of the driver through level monitoring hardware (such as GPIO ports or dedicated monitoring circuits).

[0077] The monitored parameters include key signals such as overcurrent, overload, overtemperature, bus overcurrent, undervoltage, etc.

[0078] 2. Definition of alarm signal:

[0079] Clearly defined alarm signals are provided for each possible fault condition, and these signals are usually generated by hardware circuits when an anomaly is detected.

[0080] 3. Alarm detection:

[0081] The logic circuit or software on the FPGA side will continuously check the status of these alarm signals.

[0082] Once an alarm signal is detected, the FPGA will immediately identify and process it.

[0083] 4. Enable under the system:

[0084] For safety reasons, once an alarm signal is detected, the FPGA will send a signal to the drive circuit to enable (disable) the motor drive and stop the motor from running.

[0085] This usually involves setting the driver circuit's enable signal low, thereby removing power from the motor.

[0086] 5. Error message generation:

[0087] The FPGA generates an error message that contains the error type and related information.

[0088] 6.PCIe bare core communication:

[0089] Using the PCIe bare core communication mechanism, the FPGA sends an error message to the ARM side.

[0090] This communication is usually carried out through preset communication protocols and data formats to ensure accurate transmission of information.

[0091] 7.ARM side processing:

[0092] After receiving the error message, the ARM side will perform corresponding processing.

[0093] This may include logging the error, triggering an alarm on the user interface, sending a notification to maintenance personnel, or executing other predefined error handling procedures.

[0094] 8. User Interface Feedback:

[0095] The system may display an alarm message through the user interface so that the operator can take immediate action.

[0096] 9. System recovery:

[0097] After the fault is corrected, the system needs to have a recovery process to ensure that the motor can be restarted safely.

[0098] This may include steps such as manual reset, automatic detection and automatic restart after confirming safe conditions.

[0099] 10. Recording and analysis:

[0100] The system records detailed information about alarm events, including time, type, and possible cause.

[0101] These records are very important for subsequent fault analysis and system maintenance.

[0102] Through such a mechanism, the system can respond quickly when potential dangers or faults are detected, ensuring the safety of equipment and operators, while providing necessary information for fault diagnosis and system maintenance.

[0103] Furthermore, the FPGA side is used for current acquisition, using the Sigma-Delta ADC reading method, and reading through sinc filtering; for the encoder, using 485 serial port communication to read; for the conveyor belt encoder, reading through the ABZ pulse counting method; for data acquisition by the oscilloscope, the required data is transmitted to the ARM side through PCIE bare core communication for storage and real-time display.

[0104] Specifically, the FPGA side is responsible for collecting data from various sensors and data sources, and transmitting this data to the ARM side through efficient communication methods. The following is a detailed description of these data collection and transmission processes:

[0105] 1. Current collection:

[0106] Sigma-Delta ADC: Use a Sigma-Delta analog-to-digital converter (ADC) to acquire the current signal. Sigma-Delta ADC is suitable for accurately measuring analog signals with its high resolution and good anti-aliasing properties.

[0107] Sinc filter: The collected current signal is digitally filtered through a sinc filter. The sinc filter is an ideal low-pass filter that can effectively remove high-frequency noise and retain useful signal components.

[0108] 2. Encoder reading:

[0109] RS-485 serial communication: Encoder data is read via RS-485 serial communication. RS-485 is a reliable serial communication standard suitable for long-distance and high-speed data transmission in industrial environments.

[0110] Data processing: The FPGA receives the data sent by the encoder and performs necessary decoding and processing to obtain the position and speed information of the motor.

[0111] 3. Conveyor belt encoder reading:

[0112] ABZ pulse counting: Conveyor encoders are usually equipped with ABZ output, where the A and B phases are pulse signals with a 90-degree phase difference, and the Z phase is the zero position pulse, which is used to determine the reference position of the encoder.

[0113] Pulse counting method: The FPGA side determines the rotation position and direction of the encoder by counting the AB phase pulses, and uses the Z phase pulse to correct the reference position.

[0114] 4. Oscilloscope data acquisition:

[0115] Data acquisition: The FPGA collects various signals in the motor control system, such as voltage, current, position and speed.

[0116] PCIe bare core communication: The collected data is transmitted to the ARM side through PCIe bare core communication. PCIe bare core communication provides a high-speed, low-latency data transmission channel, which is suitable for real-time data transmission.

[0117] 5. ARM-side data processing:

[0118] Data reception: The ARM side receives data transmitted by FPGA through the PCIe interface.

[0119] Data preservation: The received data is saved in the storage medium of the ARM side, such as RAM or hard disk, for subsequent analysis and processing.

[0120] Real-time display: The software interface on the ARM side displays these data in real time and provides them to operators for monitoring and analysis.

[0121] 6. System monitoring and user interaction:

[0122] Monitoring interface: The user interface on the ARM side provides functions such as real-time data display, historical data query, system configuration and fault alarm.

[0123] User interaction: Operators can monitor system status through the user interface and perform necessary operations and adjustments.

[0124] This design enables efficient data acquisition and processing, ensuring accurate monitoring and control of the motor control system. This highly integrated system design helps improve the performance and reliability of the robot.

[0125] In some embodiments, the ARM side is used to implement the processes corresponding to the lower computer, the upper computer, the ECAT module and the communication module respectively; the process corresponding to the upper computer is responsible for interaction, displaying the data information transmitted by the lower computer and sending the user input information to the lower computer, and realizing the logical processing of the preset function. The process corresponding to the lower computer is responsible for sending the parameters received by each part to the robot model and calculating the corresponding data to output to the upper computer for display. The process corresponding to the communication module is responsible for regularly uploading the parameters of the entire robot model to the cloud, and logically controlling the drive-control integrated software through the cloud. The process corresponding to the ECAT module is used to expand the axis through the ECAT protocol, realize the ECAT master station protocol, and is used to expand the external axis and control it with the ECAT bus universal servo.

[0126] In the system, the ARM side plays the core role of data processing and communication. It implements various functions through different modules. The following is a functional description of each part of the ARM side:

[0127] Host computer part:

[0128] User interaction: Provides a user interface that allows operators to interact with the system, including viewing data and inputting control commands.

[0129] Data display: Displays data information transmitted from the lower computer, such as motor status, sensor readings, alarm information, etc.

[0130] Logical processing: Implement the system's advanced logical processing functions, such as data analysis, trend prediction, fault diagnosis, etc.

[0131] User input: Receive information input by the user, such as control commands, parameter settings, etc., and send this information to the lower computer.

[0132] Lower computer part:

[0133] Parameter forwarding: forward the control instructions of the host computer and the parameters input by the user to the robot model.

[0134] Data processing: Process the raw data received from the FPGA, perform necessary calculations, and output the processed data to the host computer for display.

[0135] Control logic: Implement control logic directly related to the robot model, such as PID control, motion planning, etc.

[0136] 4G module part:

[0137] Data upload: The robot model parameters and operation data are regularly uploaded to the cloud via the 4G network.

[0138] Remote control: allows remote logical control of the drive-control software through the cloud, realizing remote monitoring and operation.

[0139] ECAT module part:

[0140] Axis expansion: When more external axes are needed or more than six axes are required, axis expansion can be performed through the ECAT (Ethernet Control Automation Technology) protocol.

[0141] ECAT Master Protocol: Implements the ECAT master protocol, which is used to communicate with ECAT slave devices (such as servo drives) and expand external axes.

[0142] Universal servo control: It can be controlled with ECAT bus universal servo to achieve more complex automation control requirements.

[0143] This modular design enables the ARM side to flexibly handle various tasks and communicate effectively with other systems and devices. The separation design of the host and slave computers helps to simplify the system architecture and improve data processing efficiency. The addition of 4G modules and ECAT modules expands the system's communication capabilities and control range, allowing the system to adapt to a wider range of application scenarios.

[0144] The entire system is designed to achieve efficient and reliable motor control while providing flexible data processing and communication capabilities to meet the needs of different users.

[0145] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An asymmetric AMP architecture drive-control integrated system based on ARM+FPGA platform, It is characterized in that It adopts an asymmetric AMP architecture based on the ARM+FPGA platform, including: ARM side, FPGA side, and PCIE bare core of the asymmetric AMP architecture; The FPGA side is used to implement the motor control process, sensor reading process, hardware alarm signal processing process, and oscilloscope data acquisition process; The ARM side is used to implement the corresponding processes of the lower computer, upper computer, ECAT module and communication module respectively; The PCIE bare core is connected to the ARM end and the FPGA end respectively, and is used to realize the real-time and stable transmission between FPGA and ARM through the preset communication protocol, and utilizes the high-speed transmission of the PCIE bare core and the stability of the bare core timer to ensure the communication cycle in microseconds.

2. According to claim 1, the asymmetric AMP architecture drive-control integrated system based on the ARM+FPGA platform, It is characterized in that PCIE bare core, specifically used for communication using a custom communication protocol that only serves the integrated drive and control software; Among them, the communication protocols that only serve the integrated drive and control software include: Each data is divided into two parts: read and write, corresponding to the offset respectively. PCIE only accepts the data width of this part to be sent, so that FPGA can communicate with ARM end efficiently.

3. The asymmetric AMP architecture integrated drive and control system based on the ARM+FPGA platform according to claim 2, It is characterized in that Also includes: The PCIE bare core uses the bare core CPU's timer to synchronize data transmission to ensure the timing and stability of communication.

4. The asymmetric AMP architecture integrated drive and control system based on the ARM+FPGA platform according to claim 1, It is characterized in that The FPGA end is specifically used to receive the motor position command and motor speed command sent from the robot model and transmit the algorithm to process and analyze the various data of the robot system: The data include: current, motor encoder position, electrical angle, speed information; Obtain the feedback signal of the system, perform voltage feedforward correction according to the current information, and then filter out the noise through low-pass filtering; perform corresponding PID control according to the received instructions, convert the user's intention into a motion target through the instruction parsing module, first eliminate some noise through feedforward control, and then perform coordinate transformation according to the electrical angle; then, the robot model module calculates the corresponding motion plan, including the path and speed curve, according to the physical and dynamic characteristics of the robot; the motion plan calculation results are passed to the torque algorithm module to determine the specific force and torque required to execute these movements; among them, the instructions include: position instructions, speed instructions or torque instructions; the speed instruction is directly passed to the speed PI module for calculation through trapezoidal acceleration and deceleration; The torque control system includes two control modes: one is to adjust the motor speed through the speed regulator and PI controller to achieve the required torque output; the other is to use the acceleration sensor and secondary control mechanism for fine adjustment to ensure the accuracy of the torque output; based on the pre-equipped position and speed control module, the position and speed of the motor are adjusted in real time using the feedback information of the position and speed sensors to maintain the desired trajectory and speed; The current sensor monitors the motor current to prevent overload and provide feedback to optimize control. The vector controller is responsible for adjusting the direction and strength of the motor's magnetic field and generates precise control signals for the drive motor based on SVPWM (space vector pulse width modulation) technology. The dead zone compensation module eliminates the dead zone effect in the drive circuit and reduces control errors. The duty cycle of 6-way PWM is output based on SVPWM (space vector pulse width modulation) technology, and finally the hardware drive system is driven to control the motor through 6-way PWM signal output.

5. The asymmetric AMP architecture integrated drive and control system based on the ARM+FPGA platform according to claim 4, It is characterized in that The FPGA end is specifically used to read the alarm signals issued by the hardware system through level monitoring, where the alarm signals include: driver overcurrent signal, overload signal, overtemperature signal, bus overcurrent signal and undervoltage signal; whenever an alarm signal is detected, the system is enabled and an error message is sent to the ARM end through PCIE bare core communication.

6. The asymmetric AMP architecture integrated drive and control system based on the ARM+FPGA platform according to claim 5, It is characterized in that The FPGA side is used for current acquisition, using the Sigma-Delta ADC reading method and reading through sinc filtering; for encoders, using 485 serial port communication to read; for conveyor belt encoders, using the ABZ pulse counting method to read; for data acquisition by the oscilloscope, the required data is transmitted to the ARM side through PCIE bare core communication for storage and real-time display.

7. The asymmetric AMP architecture integrated drive and control system based on ARM+FPGA platform according to claim 1, It is characterized in that The corresponding process of the upper computer is responsible for interaction, displaying the data information transmitted by the lower computer, sending the user input information to the lower computer, and realizing the logical processing of the preset functions.

8. The asymmetric AMP architecture integrated drive and control system based on the ARM+FPGA platform according to claim 7, It is characterized in that The corresponding process of the lower computer is responsible for sending the parameters received by each part to the robot model and calculating the corresponding data and outputting it to the upper computer for display.

9. The asymmetric AMP architecture integrated drive and control system based on the ARM+FPGA platform according to claim 8, It is characterized in that The process corresponding to the communication module is responsible for regularly uploading the parameters of the entire robot model to the cloud, and controlling the logic of the integrated drive and control software through the cloud.

10. The asymmetric AMP architecture integrated drive and control system based on ARM+FPGA platform according to claim 9, It is characterized in that The process corresponding to the ECAT module is used to expand the axis through the ECAT protocol, implement the ECAT master protocol, and is used to expand the external axis and control it with the ECAT bus universal servo.

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