Semiconductor structure and forming method thereof
By forming trench and isolation layers in the semiconductor structure and adding a third dielectric layer of silicon oxide to the silicon nitride layer, the stack cracking and machine downtime caused by the stress differences between the silicon nitride layer and the metal material are solved. Ensures the stability and performance improvement of semiconductor manufacturing processes.
Patent Information
- Application Number
- CN202411259325.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2024-12-13
AI Technical Summary
In the semiconductor structure, the stress difference between the silicon nitride layer and the metal material in the through hole leads to cracking of the stack layer and machine downtime, affecting the smooth progress of the semiconductor manufacturing process.
The trench is formed in the stacked dielectric layer and the silicon nitride layer is backfilled to form an isolation layer. After that, through holes are formed to isolate the silicon nitride layer and the conductive connection structure to avoid direct contact between the metal and the silicon nitride layer, while at the same time, in the silicon nitride A third dielectric layer of silicon oxide is added to the layer to relieve stress.
It effectively avoids stack cracks and machine downtime, ensures the stability of semiconductor manufacturing processes, and improves semiconductor structural performance.
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Figure CN119133094A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] In a semiconductor structure, it is usually necessary to form a conductive connection structure to achieve electrical connection between different conductive layers. When forming a conductive connection structure, it is usually necessary to form a stacked layer consisting of multiple dielectric layers stacked on top of a front conductive layer, and then form a through hole exposing the front conductive layer by etching the multiple dielectric layers. Afterwards, the conductive connection structure is formed by filling a conductive material in the through hole to lead out the signal of the front conductive layer. In the current deposition process of a multi-layer dielectric layer, it is usually necessary to deposit multiple oxide layers and a silicon nitride layer located between adjacent oxide layers. However, the silicon nitride layer itself has compressive stress, while the conductive material such as metal filled into the through hole has tensile stress. Therefore, after the conductive material such as metal is filled into the through hole, due to the opposite stress performance of the metal and the silicon nitride layer, the direct contact between the metal and the silicon nitride layer will cause the problem of cracking of the stacked layer, and it is very easy to cause the downtime of a semiconductor machine (such as a deposition machine or an etching machine), affecting the smooth progress of the semiconductor manufacturing process.
[0003] Therefore, how to alleviate the stress problem between the silicon nitride layer and the metal material in the through hole, thereby avoiding cracking of the dielectric stack layer and machine downtime, while improving the performance of the semiconductor structure and ensuring the smooth and stable progress of the semiconductor manufacturing process, is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present invention provides a semiconductor structure and a method for forming the same, which are used to alleviate the stress problem between the silicon nitride layer and the metal material in the through hole, thereby avoiding the cracking of the dielectric stack layer and the occurrence of machine downtime problems, while improving the performance of the semiconductor structure and ensuring the smooth and stable progress of the semiconductor manufacturing process.
[0005] According to some embodiments, the present invention provides a method for forming a semiconductor structure, comprising the following steps:
[0006] forming a substrate, the substrate comprising a first conductive layer and a stacked dielectric layer located above the first conductive layer along a first direction, the stacked dielectric layer comprising at least a silicon nitride layer;
[0007] forming a groove located in the stacked dielectric layer and corresponding to the position of the first conductive layer, wherein the groove at least penetrates the silicon nitride layer;
[0008] backfilling the trench to form an isolation layer;
[0009] forming a through hole penetrating the middle of the isolation layer along the first direction and exposing the first conductive layer, with the remaining isolation layer distributed around the periphery of the through hole;
[0010] Filling metal material into the through hole to form a conductive connection structure electrically connected to the first conductive layer.
[0011] In some embodiments, the specific steps of forming the substrate include:
[0012] forming a first dielectric layer covering the first conductive layer;
[0013] forming a second dielectric layer covering a surface of the first dielectric layer facing away from the first conductive layer;
[0014] forming a silicon nitride layer covering a surface of the second dielectric layer facing away from the first dielectric layer;
[0015] forming a third dielectric layer covering a surface of the silicon nitride layer facing away from the second dielectric layer;
[0016] A fourth dielectric layer is formed to cover a surface of the third dielectric layer facing away from the silicon nitride layer.
[0017] In some embodiments, the material of the first dielectric layer and the material of the third dielectric layer are both silicon oxide, and the material of the second dielectric layer and the material of the fourth dielectric layer are both silicon oxynitride.
[0018] In some embodiments, the thickness of the third dielectric layer is The thickness of the fourth dielectric layer is
[0019] In some embodiments, the specific steps of forming a groove located in the stacked dielectric layer and corresponding to the position of the first conductive layer include:
[0020] The trench is formed along the first direction, penetrating the fourth dielectric layer, the third dielectric layer, and the silicon nitride layer and extending only to the second dielectric layer.
[0021] In some embodiments, the specific steps of backfilling the trench to form an isolation layer include:
[0022] A silicon oxide material is deposited into the trench to form the isolation layer that fills the trench and covers the surface of the fourth dielectric layer.
[0023] In some embodiments, the specific steps of forming a through hole penetrating the middle portion of the isolation layer along the first direction and exposing the first conductive layer include:
[0024] defining a through hole region and an edge region distributed around the periphery of the through hole region in the isolation layer;
[0025] The isolation layer in the through-hole region and the second dielectric layer and the first dielectric layer remaining below the isolation layer are etched to form a through-hole exposing the first conductive layer.
[0026] In some embodiments, the specific steps of filling the metal material into the through hole to form a conductive connection structure electrically connected to the first conductive layer include:
[0027] forming a diffusion barrier layer covering an inner wall of the through hole and electrically connected to the first conductive layer;
[0028] A conductive metal layer is formed to cover the diffusion barrier layer and fill the through hole, and the diffusion barrier layer and the conductive metal layer together serve as the conductive connection structure.
[0029] According to some other embodiments, the present invention further provides a semiconductor structure, including:
[0030] a first conductive layer;
[0031] A stacked dielectric layer, located above the first conductive layer along a first direction, and the stacked dielectric layer at least includes a silicon nitride layer;
[0032] A conductive connection structure, penetrating the stacked dielectric layer and electrically connected to the first conductive layer;
[0033] The isolation layer is located in the stacked dielectric layer, and the isolation layer is distributed around the periphery of the conductive connection structure, and the isolation layer is at least located between the conductive connection structure and the silicon nitride layer.
[0034] In some embodiments, the stacked dielectric layers include:
[0035] A first dielectric layer covering the surface of the first conductive layer;
[0036] A second dielectric layer covers a surface of the first dielectric layer away from the first conductive layer, and the silicon nitride layer covers a surface of the second dielectric layer away from the first dielectric layer;
[0037] a third dielectric layer, covering a surface of the silicon nitride layer away from the second dielectric layer;
[0038] A fourth dielectric layer covers a surface of the third dielectric layer away from the silicon nitride layer.
[0039] In some embodiments, the material of the first dielectric layer and the material of the third dielectric layer are both silicon oxide, and the material of the second dielectric layer and the material of the fourth dielectric layer are both silicon oxynitride.
[0040] In some embodiments, the thickness of the third dielectric layer is The thickness of the fourth dielectric layer is
[0041] In some embodiments, the isolation layer is made of silicon oxide.
[0042] In some embodiments, the isolation layer is continuously distributed between the fourth dielectric layer and the conductive connection structure, between the third dielectric layer and the conductive connection structure, between the silicon nitride layer and the conductive connection structure, and between a portion of the second dielectric layer and the conductive connection structure.
[0043] The semiconductor structure and its formation method provided by the present invention, before etching the stacked dielectric layer to form a through hole exposing the first conductive layer, first form a groove located in the stacked dielectric layer and corresponding to the position of the first conductive layer, and make the groove at least penetrate the silicon nitride layer, and then backfill the groove to form an isolation layer, and then form a through hole that penetrates the middle of the isolation layer along the first direction and exposes the first conductive layer, and the remaining isolation layer is distributed around the periphery of the through hole, so that the silicon nitride layer and the conductive connection structure in the through hole are isolated by the isolation layer, avoiding direct contact between the silicon nitride layer and the metal material in the conductive connection structure, thereby avoiding the internal cracking of the stacked dielectric layer caused by the opposite stress performance of the silicon nitride layer and the metal material in the conductive connection structure, reducing the occurrence of machine downtime, while improving the performance of the semiconductor structure, ensuring the smooth and stable progress of the semiconductor manufacturing process. In addition, the present invention relieves the compressive stress of the silicon nitride layer and the tensile stress of the metal material in the conductive connection structure by adding a third dielectric layer made of silicon oxide on the silicon nitride layer, thereby further helping to improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention;
[0045] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention;
[0046] Figure 3 is a schematic structural diagram after a first photoresist layer is formed on a substrate in a specific embodiment of the present invention;
[0047] Figure 4 is a schematic diagram of a structure after a groove is formed in a stacked dielectric layer in a specific embodiment of the present invention;
[0048] Figure 5 is a schematic diagram of the structure after forming an isolation layer in a specific embodiment of the present invention;
[0049] Figure 6 is a schematic structural diagram after a second photoresist layer is formed on a substrate in a specific embodiment of the present invention;
[0050] Figure 7 is a schematic diagram of a structure after a conductive connection structure and a second conductive layer are formed in a specific embodiment of the present invention;
[0051] Figure 8 It is another structural schematic diagram after the conductive connection structure and the second conductive layer are formed in a specific embodiment of the present invention. DETAILED DESCRIPTION
[0052] The specific implementation manner of the semiconductor structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0053] This specific embodiment provides a method for forming a semiconductor structure. Figure 1 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention. Figure 1 As shown, the method for forming the semiconductor structure comprises the following steps:
[0054] Step S11, forming a substrate, wherein the substrate includes a first conductive layer and a stacked dielectric layer located above the first conductive layer along a first direction, wherein the stacked dielectric layer includes at least a silicon nitride layer;
[0055] Step S12, forming a groove located in the stacked dielectric layer and corresponding to the position of the first conductive layer, wherein the groove at least penetrates the silicon nitride layer;
[0056] Step S13, backfilling the trench to form an isolation layer;
[0057] Step S14, forming a through hole that penetrates the middle of the isolation layer along the first direction and exposes the first conductive layer, and the remaining isolation layer is distributed around the periphery of the through hole;
[0058] Step S15, filling metal material into the through hole to form a conductive connection structure electrically connected to the first conductive layer.
[0059] Figure 2 Schematic diagram of the structure of the substrate in a specific embodiment of the present invention. Figure 2 As shown, the specific steps of forming the substrate include:
[0060] forming a first dielectric layer 22 covering the first conductive layer 21;
[0061] forming a second dielectric layer 23 covering a surface of the first dielectric layer 22 facing away from the first conductive layer 21;
[0062] forming a silicon nitride layer 24 covering a surface of the second dielectric layer 23 facing away from the first dielectric layer 22;
[0063] forming a third dielectric layer 25 covering a surface of the silicon nitride layer 24 facing away from the second dielectric layer 23;
[0064] A fourth dielectric layer 26 is formed to cover a surface of the third dielectric layer 25 facing away from the silicon nitride layer 24 .
[0065] In some embodiments, the material of the first dielectric layer 22 and the material of the third dielectric layer 25 are both silicon oxide, and the material of the second dielectric layer 23 and the material of the fourth dielectric layer 26 are both silicon oxynitride.
[0066] For example, the substrate includes an underlying dielectric layer 20 and the first conductive layer 21 located in the underlying dielectric layer 20. In one example, the first conductive layer 21 includes a metal layer and an adhesive layer covering the surface of the metal layer. After forming the first conductive layer 21, a silicon oxide material is deposited on the surface of the underlying dielectric layer 20 and the first conductive layer 21 to form the first dielectric layer 22 that continuously covers the underlying dielectric layer 20 and the first conductive layer 21. In one example, the thickness of the first dielectric layer 22 is Next, silicon oxynitride material is deposited on the surface of the first dielectric layer 22 to form the second dielectric layer 23 covering the surface of the first dielectric layer 22 away from the first conductive layer 21. In one example, the thickness of the second dielectric layer 23 is Then, a silicon nitride material is deposited on the surface of the second dielectric layer 23 to form the silicon nitride layer 24 covering the surface of the second dielectric layer 23 away from the first dielectric layer 22. In one example, the thickness of the silicon nitride layer 24 is Afterwards, a silicon oxide material is deposited on the surface of the silicon nitride layer 24 to form the third dielectric layer 25. Finally, a silicon oxynitride material is deposited on the surface of the third dielectric layer 25 to form the fourth dielectric layer 26. The fourth dielectric layer 26 can be used as an anti-reflection layer. By adding the third dielectric layer 25 of silicon oxide material between the anti-reflection layer and the silicon nitride layer 24, the compressive stress of the silicon nitride layer 24 and the tensile stress of the metal material subsequently filled in the through hole can be relieved at the same time, thereby further improving the performance of the semiconductor structure.
[0067] In some embodiments, the thickness of the third dielectric layer 25 is The thickness of the fourth dielectric layer 26 is Thereby, the compressive stress of the silicon nitride layer 24 and the tensile stress of the metal material subsequently filled in the through hole can be relieved at the same time, and the thickness of the stacked dielectric layer can be prevented from being too large to affect the overall size of the semiconductor structure.
[0068] Figure 3 is a schematic diagram of a structure after a first photoresist layer is formed on a substrate in a specific embodiment of the present invention, Figure 4 is a schematic diagram of a structure after a trench is formed in a stacked dielectric layer in a specific embodiment of the present invention. Figure 3 and Figure 4 As shown, the specific steps of forming the groove 40 located in the stacked dielectric layer and corresponding to the position of the first conductive layer 21 include:
[0069] The trench 40 is formed along the first direction D1 and penetrates the fourth dielectric layer 26 , the third dielectric layer 25 , and the silicon nitride layer 24 and only extends to the second dielectric layer 23 .
[0070] For example, in the formation of Figure 2 After the dielectric layers are stacked as shown, a patterned first photoresist layer 30 is formed on the top surface of the fourth dielectric layer 26 (i.e., the surface of the fourth dielectric layer 26 facing away from the third dielectric layer 25), and the first photoresist layer 30 has a first etching window 31 exposing the fourth dielectric layer 26, as shown in FIG. Figure 3 The stacked dielectric layer is etched downward along the first etching window 31 to form the trench 40 that penetrates the fourth dielectric layer 26, the third dielectric layer 25, and the silicon nitride layer 24 along the first direction D1 and only extends to the second dielectric layer 23, as shown. Figure 4 The bottom surface of the groove 40 is located in the second dielectric layer 23 or the bottom of the groove 40 exposes the top surface of the second dielectric layer 23 (i.e., the surface of the second dielectric layer 23 facing away from the first dielectric layer 22), which can ensure that the groove 40 fully penetrates the silicon nitride layer 24, so that the isolation layer formed subsequently can fully isolate the silicon nitride layer and the conductive connection structure, and facilitates the control of the etching endpoint to avoid over-etching affecting the first conductive layer 21.
[0071] Figure 5 Schematic diagram of the structure after forming the isolation layer in a specific embodiment of the present invention. Figure 5 As shown, the specific steps of backfilling the trench 40 and forming the isolation layer 50 include:
[0072] A silicon oxide material is deposited into the trench 40 to form the isolation layer 50 that fills the trench 40 and covers the surface of the fourth dielectric layer 26 .
[0073] Figure 6 2 is a schematic diagram of a structure after forming a second photoresist layer on a substrate in a specific embodiment of the present invention. In some embodiments, the specific steps of forming a through hole that penetrates the middle of the isolation layer 50 along the first direction D1 and exposes the first conductive layer 21 include:
[0074] A through hole region and an edge region distributed around the periphery of the through hole region are defined in the isolation layer 50;
[0075] The isolation layer 50 in the through-hole region and the second dielectric layer 23 and the first dielectric layer 22 remaining below the isolation layer 50 are etched to form a through-hole exposing the first conductive layer 21 .
[0076] For example, a silicon oxide material is deposited into the groove 40 to form the isolation layer 50 that fills the groove 40 and covers the surface of the fourth dielectric layer 26. Afterwards, the isolation layer 50 is planarized using a chemical mechanical polishing process. In one example, the isolation layer 50 on the surface of the fourth dielectric layer 26 is not completely removed during the planarization process, so that after the planarization process, the isolation layer 50 is still retained on the top surface of the fourth dielectric layer 26. Next, a patterned second photoresist layer 60 is formed on the isolation layer 50, and the second photoresist layer 60 has a second etching window 61 that exposes the isolation layer 50, such as Figure 6 As shown. The projection of the second etching window 61 on the substrate is located in the through-hole region in the isolation layer 50. Next, the isolation layer 50 and the remaining second dielectric layer 23 and the first dielectric layer 22 below the isolation layer 50 are etched downward along the second etching window to form the through-hole exposing the first conductive layer 21. Since the projection of the second etching window 61 on the substrate is located in the through-hole region in the isolation layer 50, the remaining isolation layer 50 after etching is distributed around the periphery of the through-hole.
[0077] Figure 7 FIG. 1 is a schematic diagram of a structure after forming a conductive connection structure and a second conductive layer in a specific embodiment of the present invention. Figure 7 As shown, the specific steps of filling the metal material into the through hole to form a conductive connection structure electrically connected to the first conductive layer 21 include:
[0078] forming a diffusion barrier layer 70 covering the inner wall of the through hole and electrically connected to the first conductive layer 21;
[0079] A conductive metal layer 71 is formed to cover the diffusion barrier layer 70 and fill the through hole. The diffusion barrier layer 70 and the conductive metal layer 71 together serve as the conductive connection structure.
[0080] For example, Ti / TiN material is deposited in the through hole to form the diffusion barrier layer 70 covering the inner wall of the through hole. Metal tungsten is deposited in the through hole to form a conductive metal layer 71 covering the diffusion barrier layer 70 and filling the through hole, and the diffusion barrier layer 70 and the conductive metal layer 71 together serve as the conductive connection structure. Since the conductive connection structure is isolated from the silicon nitride layer 24 by the isolation layer 50, direct contact between the silicon nitride layer 24 with compressive stress and the conductive connection structure with tensile stress is avoided, thereby avoiding the problem of internal cracking of the stacked dielectric layer caused by the opposite stress performance of the metal material in the silicon nitride layer and the conductive connection structure, thereby reducing the occurrence of machine downtime. Thereafter, a metal material is deposited on the substrate to form a second conductive layer 72 located above the substrate along the first direction D1, and the conductive connection structure electrically connects the first conductive layer 21 and the second conductive layer 72, as shown in FIG. Figure 7 shown.
[0081] Figure 8 is another schematic diagram of a structure after forming a conductive connection structure and a second conductive layer in a specific embodiment of the present invention. Figure 8 As shown, during the planarization process of the isolation layer 50, the isolation layer 50 on the top surface of the fourth dielectric layer 26 can be completely removed, and only the isolation layer 50 located in the groove 40 is retained, so that the second conductive layer 72 formed subsequently directly covers the top surface of the fourth dielectric layer 26. In another example, the isolation layer 50 on the surface of the fourth dielectric layer 26 is not completely removed during the planarization process, so that after the planarization process, the isolation layer 50 is still retained on the top surface of the fourth dielectric layer 26. After the conductive connection structure is formed and before the second conductive layer 72 is deposited, the isolation layer 50 on the top surface of the fourth dielectric layer 26 is removed, so that the second conductive layer 72 formed subsequently directly covers the top surface of the fourth dielectric layer 26, as shown in FIG. Figure 8 shown.
[0082] This specific embodiment also provides a semiconductor structure. The semiconductor structure provided in this specific embodiment can be used as follows Figure 1-Figure 8 The semiconductor structure is formed by the method of forming the semiconductor structure shown in the figure, and the schematic diagram of the semiconductor structure provided in this specific embodiment can be referred to Figure 7 or Figure 8 .like Figure 7 and Figure 8 As shown, the semiconductor structure comprises:
[0083] A first conductive layer 21;
[0084] A stacked dielectric layer, located above the first conductive layer 21 along a first direction D1, and the stacked dielectric layer at least includes a silicon nitride layer 24;
[0085] A conductive connection structure, penetrating the stacked dielectric layer and electrically connected to the first conductive layer 21;
[0086] The isolation layer 50 is located in the stacked dielectric layer, and the isolation layer 50 is distributed around the periphery of the conductive connection structure, and the isolation layer 50 is at least located between the conductive connection structure and the silicon nitride layer 24 .
[0087] This specific embodiment avoids direct contact between the silicon nitride layer and the metal material in the conductive connection structure by setting the isolation layer 50 between the conductive connection structure and the silicon nitride layer 24, thereby avoiding the internal cracking problem of the stacked dielectric layer caused by the opposite stress performance of the silicon nitride layer and the metal material in the conductive connection structure, reducing the occurrence of machine downtime, and ensuring the smooth and stable progress of the semiconductor manufacturing process while improving the performance of the semiconductor structure.
[0088] In some embodiments, the stacked dielectric layers include:
[0089] A first dielectric layer 22, covering the surface of the first conductive layer 21;
[0090] A second dielectric layer 23 covers a surface of the first dielectric layer 22 away from the first conductive layer 21 , and the silicon nitride layer 24 covers a surface of the second dielectric layer 23 away from the first dielectric layer 22 ;
[0091] A third dielectric layer 25 covering a surface of the silicon nitride layer 24 away from the second dielectric layer 23;
[0092] The fourth dielectric layer 26 covers the surface of the third dielectric layer 25 away from the silicon nitride layer 24 .
[0093] In some embodiments, the material of the first dielectric layer 22 and the material of the third dielectric layer 25 are both silicon oxide, and the material of the second dielectric layer 23 and the material of the fourth dielectric layer 26 are both silicon oxynitride.
[0094] Specifically, the fourth dielectric layer 26 can be used as an anti-reflection layer. By adding the third dielectric layer 25 of silicon oxide material between the anti-reflection layer and the silicon nitride layer 24, the compressive stress of the silicon nitride layer 24 and the tensile stress of the metal material subsequently filled in the through hole can be relieved at the same time, thereby further improving the performance of the semiconductor structure.
[0095] In some embodiments, the thickness of the third dielectric layer 25 is The thickness of the fourth dielectric layer 26 is
[0096] In some embodiments, the isolation layer 50 is made of silicon oxide.
[0097] In some embodiments, the isolation layer 50 is continuously distributed between the fourth dielectric layer 26 and the conductive connection structure, between the third dielectric layer 25 and the conductive connection structure, between the silicon nitride layer 24 and the conductive connection structure, and between part of the second dielectric layer 23 and the conductive connection structure.
[0098] The semiconductor structure and its formation method provided in this specific embodiment, before etching the stacked dielectric layer to form a through hole exposing the first conductive layer, first form a groove located in the stacked dielectric layer and corresponding to the position of the first conductive layer, and make the groove at least penetrate the silicon nitride layer, and then backfill the groove to form an isolation layer, and then form a through hole that penetrates the middle of the isolation layer along the first direction and exposes the first conductive layer, and the remaining isolation layer is distributed around the periphery of the through hole, so that the silicon nitride layer and the conductive connection structure in the through hole are isolated by the isolation layer, avoiding direct contact between the silicon nitride layer and the metal material in the conductive connection structure, thereby avoiding the internal cracking of the stacked dielectric layer caused by the opposite stress performance of the silicon nitride layer and the metal material in the conductive connection structure, reducing the occurrence of machine downtime, and improving the performance of the semiconductor structure while ensuring the smooth and stable progress of the semiconductor manufacturing process. In addition, this specific embodiment relieves the compressive stress of the silicon nitride layer and the tensile stress of the metal material in the conductive connection structure by adding a third dielectric layer made of silicon oxide on the silicon nitride layer, thereby further helping to improve the performance of the semiconductor structure.
[0099] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for forming a semiconductor structure, characterized in that: The steps include: forming a substrate, the substrate comprising a first conductive layer and a stacked dielectric layer located above the first conductive layer along a first direction, the stacked dielectric layer comprising at least a silicon nitride layer; forming a groove located in the stacked dielectric layer and corresponding to the position of the first conductive layer, wherein the groove at least penetrates the silicon nitride layer; backfilling the trench to form an isolation layer; forming a through hole penetrating the middle of the isolation layer along the first direction and exposing the first conductive layer, with the remaining isolation layer distributed around the periphery of the through hole; Filling metal material into the through hole to form a conductive connection structure electrically connected to the first conductive layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming the substrate include: forming a first dielectric layer covering the first conductive layer; forming a second dielectric layer covering a surface of the first dielectric layer facing away from the first conductive layer; forming a silicon nitride layer covering a surface of the second dielectric layer facing away from the first dielectric layer; forming a third dielectric layer covering a surface of the silicon nitride layer facing away from the second dielectric layer; A fourth dielectric layer is formed to cover a surface of the third dielectric layer facing away from the silicon nitride layer.
3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the first dielectric layer and the material of the third dielectric layer are both silicon oxide, and the material of the second dielectric layer and the material of the fourth dielectric layer are both silicon oxynitride.
4. The method for forming a semiconductor structure according to claim 3, characterized in that: The thickness of the third dielectric layer is The thickness of the fourth dielectric layer is 5. The method for forming a semiconductor structure according to claim 3, wherein: The specific step of forming a groove located in the stacked dielectric layer and corresponding to the position of the first conductive layer includes: forming the groove penetrating the fourth dielectric layer, the third dielectric layer, the silicon nitride layer along the first direction and extending only to the second dielectric layer.
6. The method for forming a semiconductor structure according to claim 5, characterized in that: The specific steps of backfilling the trench to form an isolation layer include: A silicon oxide material is deposited into the trench to form the isolation layer that fills the trench and covers the surface of the fourth dielectric layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: The specific steps of forming a through hole penetrating the middle portion of the isolation layer along the first direction and exposing the first conductive layer include: defining a through hole region and an edge region distributed around the periphery of the through hole region in the isolation layer; The isolation layer in the through-hole region and the second dielectric layer and the first dielectric layer remaining below the isolation layer are etched to form a through-hole exposing the first conductive layer.
8. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of filling the metal material into the through hole to form a conductive connection structure electrically connected to the first conductive layer include: forming a diffusion barrier layer covering the inner wall of the through hole and electrically connected to the first conductive layer; A conductive metal layer is formed to cover the diffusion barrier layer and fill the through hole, and the diffusion barrier layer and the conductive metal layer together serve as the conductive connection structure.
9. A semiconductor structure, characterized in that: include: a first conductive layer; A stacked dielectric layer, located above the first conductive layer along a first direction, and the stacked dielectric layer at least includes a silicon nitride layer; A conductive connection structure, penetrating the stacked dielectric layer and electrically connected to the first conductive layer; The isolation layer is located in the stacked dielectric layer, and the isolation layer is distributed around the periphery of the conductive connection structure, and the isolation layer is at least located between the conductive connection structure and the silicon nitride layer.
10. The semiconductor structure according to claim 9, characterized in that: The stacked dielectric layer comprises: A first dielectric layer covering the surface of the first conductive layer; A second dielectric layer covers a surface of the first dielectric layer away from the first conductive layer, and the silicon nitride layer covers a surface of the second dielectric layer away from the first dielectric layer; a third dielectric layer, covering a surface of the silicon nitride layer away from the second dielectric layer; A fourth dielectric layer covers a surface of the third dielectric layer away from the silicon nitride layer.
11. The semiconductor structure according to claim 10, characterized in that: The material of the first dielectric layer and the material of the third dielectric layer are both silicon oxide, and the material of the second dielectric layer and the material of the fourth dielectric layer are both silicon oxynitride.
12. The semiconductor structure according to claim 11, characterized in that: The thickness of the third dielectric layer is The thickness of the fourth dielectric layer is 13. The semiconductor structure according to claim 11, characterized in that: The material of the isolation layer is silicon oxide.
14. The semiconductor structure according to claim 9, characterized in that: The isolation layer is continuously distributed between the fourth dielectric layer and the conductive connection structure, between the third dielectric layer and the conductive connection structure, between the silicon nitride layer and the conductive connection structure, and between a portion of the second dielectric layer and the conductive connection structure.