Bonding wafer scribing method and chip bare crystal

Abstract

The invention provides a bonding wafer scribing method and a chip die, and the bonding wafer comprises a first body material layer of a first wafer, a second body material layer of a second wafer, and a middle layer located between the first body material layer and the second body material layer. The method comprises the following steps: processing and penetrating through a first body material layer through a first wafer scribing process to generate a first groove; processing from the bottom surface of the first groove through a second wafer scribing process and penetrating through the intermediate layer to generate a second groove; and processing from the bottom surface of the second groove and penetrating through the second body material layer to obtain a bare chip. According to the technical scheme, the silicon material of the first body material layer of the first wafer is removed in advance, the middle layer containing the functional layer of the wafer is exposed, and then the middle layer is directly subjected to scribing cutting, so that damage to the middle layer, especially the functional layer, caused by the wafer scribing method is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip packaging, and more specifically, to a method for bonding wafer dicing and a chip bare die. Background Art

[0002] Wafer dicing process refers to cutting a single or multiple chip dies from a wafer for subsequent die bonding, wire bonding and testing processes, etc. Among them, bonded wafers are mostly formed by bonding at least two wafers. For example, a bonded wafer can be formed by hybrid bonding of two wafers, wherein an intermediate layer can be provided between the bulk material layers of the two wafers, and the intermediate layer can be composed of a functional layer of a wafer including metal wiring and dielectric material and a bonding layer including bonding metal, wherein the functional layer can include a low dielectric (low k) layer or an extremely low dielectric (ELK) layer with low dielectric strength or weak interlayer bonding force.

[0003] Most wafer scribing methods at this stage use direct blade scribing or laser grooving followed by blade scribing. For bonded wafers, especially hybrid bonded wafers, the direct blade scribing method will cause the middle layer, especially the functional layer of the wafer, to be delaminated or cracked due to stress, especially the low k layer or ELK layer, and these defects are difficult to effectively inspect because they are blocked by the main material layer of the wafer on the top layer; the laser grooving method requires the removal of the main material and the middle layer of the top wafer. Since the thickness of the main material layer and the middle layer is relatively thick, the laser processing grooving method requires a larger laser grooving energy, which increases the heat-affected zone of the middle layer, especially the functional layer of the wafer, and the defects such as thermal damage caused by laser grooving are difficult to be effectively inspected because they are blocked by the main material layer of the wafer on the top layer. Summary of the invention

[0004] The present application provides a method for slicing a bonded wafer and a chip bare crystal obtained by the method, wherein the silicon material of the slicing path of the first main material layer is removed in advance to expose the middle layer, and then the middle layer is directly sliced ​​and cut, thereby reducing the damage to the middle layer, especially the functional layer of the wafer, caused by the wafer slicing method.

[0005] In a first aspect, a method for slicing a bonded wafer is provided, wherein the bonded wafer includes a first bulk material layer of a first wafer, a second bulk material layer of a second wafer, and an intermediate layer located between the first bulk material layer and the second bulk material layer, the method comprising: processing and penetrating the first bulk material layer through a first wafer slicing process to generate a first groove; processing from the bottom surface of the first groove and penetrating the intermediate layer through a second wafer slicing process to generate a second groove; processing from the bottom surface of the second groove and penetrating the second bulk material layer to obtain a chip bare crystal.

[0006] According to the technical solution provided in the present application, the material in the dicing area of ​​the first main material layer is removed in advance to expose the intermediate layer, and then the intermediate layer is directly processed, thereby avoiding defects such as delamination and cracking of the intermediate layer, especially the functional layer of the wafer, caused by direct blade dicing, and large heat-affected zone and thermal damage of the intermediate layer, especially the functional layer of the wafer, caused by laser processing dicing.

[0007] In combination with the first aspect, in certain implementations of the first aspect, the width of the second groove is smaller than the width of the first groove, so that the middle sublayer of the chip bare crystal includes a first portion located at the edge of the middle sublayer and not covered by the first body material sublayer of the chip bare crystal.

[0008] According to the technical solution provided in the present application, the wafer scribing process for processing the intermediate layer will not affect the side wall surface of the first groove, and the defects of the intermediate layer or the intermediate sublayer on the connecting surface between the first main material layer and the intermediate layer can be directly obtained through appearance inspection.

[0009] In combination with the first aspect, in certain implementations of the first aspect, a reference cable is disposed on the surface of the first portion of the intermediate sublayer close to the first main material sublayer, and the reference cable is used to determine the processing position of the first wafer dicing process and / or the second wafer dicing process.

[0010] According to the technical solution provided in the present application, the first wafer dicing process and the second wafer dicing process can be aligned using a reference cable, the alignment is relatively accurate, and the reference cable can be used to check whether the processing position of the wafer dicing process is offset.

[0011] In combination with the first aspect, in some implementations of the first aspect, the first wafer dicing process includes a plasma etching process.

[0012] According to the technical solution provided in the present application, the end position of the first wafer scribing process can be determined by determining the rate of removing the bottom surface material of the first groove.

[0013] In combination with the first aspect, in some implementations of the first aspect, the second wafer scribing process includes a laser processing process.

[0014] According to the technical solution provided by the present application, it can be ensured that all materials in the scribe line area of ​​the middle layer are removed and the middle sublayer will not crack or delaminate. In addition, since the thickness of the middle layer is thinner than that of the first main body material layer, compared with the first main body material layer and the middle layer with a larger total thickness processed by laser, the present application uses laser to directly process the thinner middle layer, and the power or grooving energy used by the laser grooving is smaller, and thus the heat-affected zone and the laser processing cause less thermal damage to the middle layer, especially the functional layer of the wafer.

[0015] In combination with the first aspect, in some implementations of the first aspect, processing from the bottom surface of the second groove and penetrating the second body material layer includes: processing from the bottom surface of the second groove to generate a third groove until penetrating the second body material layer.

[0016] In combination with the first aspect, in some implementations of the first aspect, the third wafer dicing process includes a blade cutting process.

[0017] According to the technical solution provided in this application, the dicing efficiency of the blade cutting process is faster and the cost is lower.

[0018] In combination with the first aspect, in certain implementations of the first aspect, the width of the third groove is smaller than the width of the second groove, so that the second body material sublayer of the chip bare crystal includes a first portion located at the edge of the second body material sublayer and not covered by the middle sublayer of the chip bare crystal.

[0019] According to the technical solution provided in the present application, the third wafer dicing process does not cause damage to the side wall of the second groove, that is, it does not cause damage to the middle sublayer, ensuring that the metal wiring and dielectric material in the middle sublayer will not be affected.

[0020] In combination with the first aspect, in some implementations of the first aspect, the bottom surface of the first groove is a first surface connecting the intermediate layer and the first body material layer.

[0021] According to the technical solution provided in the present application, the first wafer dicing process has almost no impact on the intermediate layer and can save the processing cost of the first wafer dicing process.

[0022] In combination with the first aspect, in some implementations of the first aspect, the bonded wafer is formed by hybrid bonding of a first wafer and a second wafer.

[0023] In a second aspect, a chip bare crystal is provided, comprising a first body material sublayer, an intermediate sublayer and a second body material sublayer; the intermediate sublayer is located between the first body material sublayer and the second body material sublayer and connects the first body material sublayer and the second body material sublayer, the intermediate sublayer comprises a first part and a second part, the first part of the intermediate sublayer is located at the edge of the intermediate sublayer and is not covered by the first body material sublayer, and the second part of the intermediate sublayer is covered by the first body material sublayer.

[0024] According to the technical solution provided in the present application, defects at the connection surface between the intermediate sub-layer and the first main body material sub-layer can be effectively inspected.

[0025] In combination with the second aspect, in some implementations of the second aspect, the side surface of the first body material sub-layer is formed by a plasma etching process.

[0026] In combination with the second aspect, in certain implementations of the second aspect, the side surface of the first portion of the intermediate sublayer is formed by a laser processing process.

[0027] In combination with the second aspect, in certain implementations of the second aspect, the second main body material sublayer includes a first part and a second part, the first part of the second main body material sublayer is located at the edge of the second main body material sublayer and is not covered by the intermediate sublayer, and the second part of the second main body material sublayer is covered by the intermediate sublayer.

[0028] In combination with the second aspect, in some implementations of the second aspect, the side surface of the first portion of the second body material sub-layer is formed by a blade cutting process.

[0029] In combination with the second aspect, in certain implementations of the second aspect, a reference cable is disposed on the first portion of the intermediate sublayer near the surface of the first main material sublayer, and the reference cable is located between the side surface of the first main material sublayer and the side surface of the first portion of the intermediate sublayer.

[0030] In a third aspect, an integrated circuit chip is provided, comprising the second aspect or any possible chip bare crystal of the second aspect.

[0031] Optionally, the integrated circuit chip may be any one of a microprocessor chip, a memory chip, a sensor chip, a driver chip and a communication chip.

[0032] In a fourth aspect, an electronic device is provided, which includes the second aspect or any possible chip bare crystal of the second aspect or the integrated circuit chip of the third aspect.

[0033] Optionally, the electronic device may be an intelligent terminal device such as a mobile phone, a personal computer or an information processing center, or may be a device or server with data processing capabilities such as a cloud server, a network server, an application server or a management server. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of a wafer dicing process provided in an embodiment of the present application.

[0035] Figure 2 It is a schematic diagram of a bonded wafer provided in an embodiment of the present application.

[0036] Figure 3 It is a schematic flow chart of a wafer dicing method provided in an embodiment of the present application.

[0037] Figure 4 It is a flow chart of a wafer dicing method provided in an embodiment of the present application.

[0038] Figure 5 It is a schematic diagram of a bonded wafer including a reference cable provided in an embodiment of the present application.

[0039] Figure 6 It is a schematic diagram of a chip bare crystal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0041] In the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0042] The business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0043] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0044] In order to facilitate understanding of the technical solution of the present application, the professional terms mentioned in the present application are briefly explained below.

[0045] 1. Wafer dicing

[0046] The process of wafer dicing is to divide the entire wafer containing chips or integrated circuits into individual chip dies according to the size of the chips or integrated circuits.

[0047] Figure 1 A schematic diagram 100 of a wafer dicing process is shown. Figure 1 (a) in FIG. 1 shows a wafer 110 , which may include a bulk material layer such as a silicon material layer, and a functional layer provided with metal wiring or a dielectric material. Figure 1 (b) in FIG. 1 shows a wafer 110 including one or more integrated circuits 120. The surface of the wafer 110 is marked with a scribe line 130 to indicate the wafer division position during the wafer dicing process. The scribe line 130 does not include the metal wiring of the integrated circuit 120, so the division position of the scribe line 130 will not directly cut into the circuit in the wafer. Finally, the wafer 110 is divided into the following Figure 1 The chip dies 140 and 150 may be two chip dies made of different materials, using different processes or having different functions. For example, the chip dies 140 and 150 may be a memory chip and a processor chip, respectively.

[0048] Figure 1(d) in the figure shows a schematic diagram of an integrated circuit chip including chip dies 140 and 150. The integrated chip packages the chip dies 140 and 150 together to form a three-dimensional stacked chip structure. Among them, the chip dies 140 and 150 can be regarded as top chips, and the silicon interposer 160 can be regarded as the bottom chip. The chip dies 140, 150 and the silicon interposer 160 can be interconnected vertically through micro-bumps 152 and through silicon vias 162, and the silicon interposer 160 and the packaging substrate 170 are connected vertically through solder 172, and finally a packaged integrated circuit chip including chip dies 140 and 150 is formed.

[0049] 2. Wafer bonding

[0050] Wafer bonding refers to the technology of combining two homogeneous or heterogeneous wafers under certain conditions and bonding the two wafers into one through van der Waals forces, molecular forces, or even atomic forces. For ease of understanding, the chip formed by the two bonded wafers is called a "bonded wafer."

[0051] Figure 2 A schematic diagram of a bonded wafer including two wafers is shown. Figure 2 (a) shows a front view of the bonded wafer, which includes a first bulk material layer of the first wafer, a second bulk material layer of the second wafer, and an intermediate layer, wherein the intermediate layer may include a functional layer, a bonding layer, etc. of the first wafer and / or the second wafer.

[0052] Figure 2 (b) in the figure shows a cross-sectional schematic diagram of a bonded wafer formed by a hybrid bonding method, wherein the bonded wafer includes a first bulk material layer 210 and a first functional layer 220 of a first wafer, a second functional layer 240 and a second bulk material layer 250 of a second wafer, and a bonding layer 230 between the first wafer and the second wafer. The first functional layer 220 and the second functional layer 240 include an inner metal 224 for circuit wiring, and a dielectric material (the cross-sectional shaded area of ​​the first functional layer 220 and the second functional layer 240 is shown in the figure). The bonding layer 230 may include an adhesive or bonding metal for realizing a bonding connection, for example, in the process of hybrid bonding, the bonding layer may include a bonding metal 236, such as copper. Optionally, the first functional layer 220 and / or the second functional layer 240 also include a sealing coil 218 for dividing the circuit range and sealing and protecting the circuit. Optionally, the first bulk material layer 210 may include a through silicon via 212 for forming a circuit such as Figure 1The micro bumps 152 shown in (d) in FIG. In the above hybrid bonding method, the combination of the first functional layer 220, the bonding layer 230 and the second functional layer 240 can be regarded as an intermediate layer located between the bulk material layers of the two wafers in the bonded wafer.

[0053] The bonded wafer can also be obtained by other bonding methods, for example, the bonded wafer can be obtained by a fusing bonding method. Figure 2 As shown in (c), during the melt bonding process, the first bulk material layer 210 of the first wafer and the second functional layer 250 of the second wafer are bonded to each other through the bonding layer 230. At this time, the combination of the bonding layer 230 and the second functional layer 250 can be regarded as an intermediate layer between the bulk material layers of the two wafers in the bonded wafer. In some other embodiments of the present application, the intermediate layer may not include the bonding layer 230, that is, the first bulk material layer 210 and the second functional layer 250 can be directly bonded by intermolecular forces or the like.

[0054] It is worth noting that Figure 2 The cross-sectional views of the bonded wafers shown in (b) and (c) do not limit the structure of the bonded wafer of the present application. The present application can also use other bonding methods to obtain the bonded wafer, such as diffusion bonding.

[0055] In the embodiments of the present application, Figure 1 The wafer 110 shown in (a) and (b) is Figure 2 The structure of the bonded wafer is shown in FIG. Figure 2 The dicing road area shown in FIG. is diced to obtain Figure 1 One or more chip bare crystals shown in (c). According to the current wafer dicing method, the bonded wafer can be regarded as a three-layer structure, including a first bulk material layer of the first wafer, a second bulk material layer of the second wafer, and an intermediate layer located between the first bulk material layer and the second bulk material layer. Correspondingly, the obtained chip bare crystal includes a three-layer structure, namely a first bulk material sublayer, a second bulk material sublayer, and an intermediate sublayer located between the first bulk material sublayer and the second bulk material sublayer. For the convenience of description, the intermediate layer composed of the functional layer and / or the bonding layer is described as a whole in the following figures.

[0056] At present, wafer scribing methods mostly use direct blade scribing or laser grooving followed by blade scribing. For example, the direct blade scribing method can be to use a high-speed rotating diamond knife (a blade made of diamond particles and resin, ceramic or metal) to directly cut the scribing path; the laser grooving followed by blade scribing method can be to first use laser to process the scribing paths of the first bulk material layer and the middle layer, and after the laser processing penetrates the first bulk material layer and the middle layer, the scribing paths of the second bulk material layer are cut by a high-speed rotating diamond knife.

[0057] In the current wafer scribing method, the first bulk material layer and the intermediate layer are mostly processed by the same wafer scribing process, which increases the difficulty of processing silicon materials and dielectric materials at the same time. Moreover, in the intermediate layer, the dielectric material of the functional layer of the wafer is usually a brittle material such as SiO2, SiCN, or a material with weak interlayer bonding force. The direct blade scribing method is prone to cause defects such as delamination or cracking of the dielectric material, and fragmentation of the contact surface between the first bulk material layer and the intermediate layer. When the first bulk material layer and the intermediate layer are laser processed, due to the large total thickness of the first bulk material layer and the intermediate layer, the laser processing requires a large power or slotting energy so that the laser can cleanly remove the material in the scribing area of ​​the first bulk material layer and the intermediate layer. Furthermore, due to the large power or energy required for laser processing, the area of ​​the heat-affected zone caused by laser processing increases, thereby causing thermal damage to the intermediate layer, especially the functional layer of the wafer.

[0058] In order to reduce the damage caused by the dicing method to the intermediate layer, especially the functional layer of the wafer, the present application shows a wafer dicing method 300, which can be applied to Figure 2 Slicing of the bonded wafer is shown. Figure 3 3 shows a schematic flow chart of a method 300, Figure 4 The flowchart of method 300 is shown. Method 300 includes steps 310 to 330, which first removes the silicon material of the scribe line of the first body material layer to expose the middle layer, and then directly scribes and cuts the middle layer, thereby reducing the damage of the wafer scribe method to the middle layer, especially the functional layer of the wafer.

[0059] Optionally, before step 310, method 300 may further include a pre-processing step. In an embodiment of the present application, the pre-processing step may include a thinning process of the first body material layer, such as mechanical grinding and polishing, abrasion and the like. The thinning process of the first body material layer may also realize the exposure of the silicon through hole, and then the pre-processing step may also include forming a silicon through hole by sputtering, photolithography, electroplating and the like. Figure 1In some other embodiments of the present application, the pre-processing step may include forming a passivation layer by chemical vapor deposition (CVD). The pre-processing step may also include flattening the wafer surface by chemical-mechanical planarization (CMP). Finally, the bonded wafer obtained after the pre-processing step is as shown in FIG. Figure 4 as shown in step 1 in .

[0060] Step 310: A first trench is generated by performing a first wafer scribing process and penetrating the first body material layer.

[0061] It should be understood that Figure 4 As shown in step 2 of the first wafer dicing process, the material in the dicing lane area of ​​the first bulk material layer can be removed to form a first groove to expose the bulk material of the intermediate layer. The first wafer dicing process has a small effect on removing the intermediate layer, especially the functional layer of the wafer, and thus will not cause defects such as delamination or cracking of the intermediate layer, especially the functional layer of the wafer.

[0062] Optionally, the first wafer dicing process may be a process that has a good removal effect on the first bulk material layer but has an insignificant removal effect on the intermediate layer. For example, the first wafer dicing process may be a process in which the rate of etching the silicon material is greater than or much greater than the rate of etching the dielectric material. Furthermore, the rate of etching the first bulk material layer is greater than the rate of etching the intermediate layer, so that the end position of the first wafer dicing process can be determined by the rate of etching the bottom material of the first groove. For example, when the etching depth of the first groove changes slowly or the etching rate is greatly reduced, it means that the bottom surface of the first groove is located in the intermediate layer, and the first wafer dicing process can be stopped.

[0063] Exemplarily, the first wafer dicing process may be a plasma etching process. In an embodiment of the present application, the plasma etching process is preferably plasma dry etching. For example, the plasma dry etching may be a Bosch process, that is, the alternating etching action of etching gas SF6 and passivation gas C4F8. Among them, the Bosch process etches the silicon material of the first bulk material layer by SF6, and deposits C4F8 on the silicon surface to prevent the reaction of fluorine ions with silicon, forming periodic etching and passivation, so that each step of etching the first groove is only carried out along the depth direction of the first bulk material layer, and finally the sidewall of the first groove is a scallop morphology. Preferably, the surface roughness of the sidewall of the first groove is less than 5μm.

[0064] Exemplarily, the first wafer dicing process may be a solution wet etching process, for example, a potassium hydroxide (KOH) solution may be used to rapidly etch the silicon material of the first bulk material layer, while the KOH solution has a slow etching rate for oxides or nitrides in the intermediate layer.

[0065] Optionally, in an embodiment of the present application, the bottom surface of the first groove is preferably the surface where the intermediate layer is connected to the first bulk material layer, or in other words, the first wafer scribing process stops when the intermediate layer is processed. In this way, the first wafer scribing process has almost no effect on the intermediate layer, and the etching cost of the first wafer scribing process can be saved. In other embodiments of the present application, the first wafer scribing process can also be stopped after processing to a certain depth of the intermediate layer. In this way, it can be ensured that the silicon material of the first bulk material layer in the first groove can be completely removed.

[0066] Optionally, the sidewall angle of the first groove may be 80° to 100°, and the roughness of the sidewall may be less than 5 μm, so that the obtained chip bare die meets the process requirements of packaging.

[0067] Step 320: Processing from the bottom surface of the first groove and penetrating the middle layer through a second wafer scribing process to generate a second groove.

[0068] It should be understood that step 310 removes all materials of the first body material layer in the scribe line area to expose the middle layer, and the second wafer dicing process can directly process the surface exposed from the middle layer, that is, process the bottom surface of the first groove. Figure 4 As shown in step 3 of the above, the second wafer scribing process processes the bottom surface of the first groove until it penetrates the middle layer. The bottom surface of the second groove can be the surface where the middle layer is connected to the second body material layer, or it can be Figure 4 On the second body material layer shown.

[0069] Optionally, the second wafer scribing process may be a laser processing process, wherein the exposed material of the intermediate layer is removed by laser until the bottom surface of the laser removal area extends to the second bulk material layer, so as to ensure that all the material in the scribing street area of ​​the intermediate layer is removed.

[0070] In this way, the middle sublayer of the chip bare crystal obtained after wafer dicing will not crack or delaminate. In addition, since the thickness of the middle layer may be thinner than the thickness of the first main material layer, compared with the first main material layer and the middle layer with a larger total thickness processed by laser, the present application uses laser to directly process the thinner middle layer, and the power or grooving energy used by the laser grooving is smaller, and thus the heat-affected zone and the laser processing cause less thermal damage to the middle layer, especially the functional layer of the wafer.

[0071] In some other embodiments of the present application, the second wafer dicing process may also be a direct process that penetrates the intermediate layer and the second body material layer. The above situation is introduced in step 330 and will not be described in detail here.

[0072] Optionally, in an embodiment of the present application, the width of the second groove may be the same as the width of the first groove, that is, both are Figure 2 The width of the scribe line area shown in . However, when the width of the second groove is the same as the width of the first groove, the process of processing the second groove by the second wafer dicing process will inevitably damage the sidewall of the first groove. This will cause the sidewall of the first groove to be uneven or damaged. In addition, the defects of the intermediate layer will not only appear on the sidewall of the second groove, but also on the connection surface between the first bulk material layer and the intermediate layer, especially the functional layer of the wafer. When the width of the second groove is the same as the width of the first groove, the first bulk material layer blocks the defects on the connection surface, making it difficult to effectively detect these defects.

[0073] Optionally, in order to solve the problem that the above defects are difficult to be effectively tested, such as Figure 4 As described in the third step of , the width of the second groove can be less than the width of the first groove. In this way, the middle sublayer of the chip bare crystal includes a first part located at the edge of the middle sublayer and not covered by the first body material sublayer, and a second part covered by the first body material sublayer. Preferably, the interval between the top edge of the sidewall of the second groove and the bottom edge of the sidewall of the first groove on the same side is 5 to 15 μm, that is, the width of the first part of the middle sublayer is 5 to 15 μm. By observing the appearance of the surface exposed by the first part of the middle sublayer, for example, using automated optical inspection (AOI), it is determined whether there are defects caused by wafer dicing on the side of the middle sublayer and the connection surface between the middle sublayer and the first body material sublayer. In addition, the second wafer dicing process does not contact the sidewall of the first groove, and thus does not damage the sidewall of the first groove.

[0074] Optionally, the widths of the first groove and the second groove may be determined by a reference cable. Figure 5 A schematic diagram of a bonded wafer 500 including a reference wire 510 is shown. Figure 5 (a) in FIG. 5 shows a cross-sectional view of the bonded wafer 500. If the bare chip is Figure 1 As shown in the square in (b), the sealing coil is arranged around the square integrated circuit, and the reference cable 510 is arranged on the periphery of the sealing coil. Figure 5 (b) in FIG. 5 shows a top view of the bonded wafer 500. The arrangement of the sealing coil is the same as that of the reference cable 510, which is also arranged around the square integrated circuit. Figure 5As shown in (a), the reference cable 510 is between the side of the first bulk material sublayer and the side of the intermediate sublayer, or in other words, between the sidewall of the first groove and the sidewall of the second groove. The edge of the second portion of the reference cable 510 close to the intermediate sublayer corresponds to the side of the first bulk material sublayer or the sidewall of the first groove, and the edge of the second portion away from the intermediate sublayer corresponds to the side of the intermediate sublayer or the sidewall of the second groove.

[0075] Exemplarily, an embodiment of the present application shows a method for wafer dicing based on a reference cable 510 .

[0076] In step 310, the first body material layer is processed by a first wafer scribing process. When the surface of the reference cable 510 close to the first body material layer is completely exposed, the first wafer scribing process is stopped. Figure 5 When the surface of the reference cable 510 near the first body material layer is just completely exposed, and the bottom edge of the sidewall of the first groove just coincides with the edge of the second portion of the reference cable 510 near the middle sublayer, the first wafer scribing process is stopped. For another example, when the distance between the bottom edge of the sidewall of the first groove and the edge of the second portion of the reference cable 510 near the middle sublayer is a first distance threshold, the first wafer scribing process is stopped. For example, the first distance threshold may be 1 to 5 μm.

[0077] In step 320, if Figure 5 As shown in (b), the processing start position of the second wafer dicing process or the processing start point of the second groove may be the edge of the second part of the reference cable 510 away from the middle sublayer. In other embodiments of the present application, the processing start position of the second wafer dicing process may also be separated from the edge of the second part of the reference cable 510 away from the middle sublayer by a second distance threshold. For example, the second distance threshold may be 1 to 5 μm.

[0078] In this way, by referring to the position difference between the cable 510 and the bottom edge of the side wall of the first groove and the top edge of the side wall of the second groove, it can be determined whether there is a problem such as processing position deviation, over-processing or under-processing.

[0079] Step 330: Processing from the bottom surface of the second trench and penetrating the second body material layer to obtain a chip bare crystal.

[0080] Optionally, the process for processing the bottom surface of the second groove may still be the second wafer scribing process, that is, the second wafer scribing process is used to process and penetrate the intermediate layer and the second body material layer.

[0081] Exemplarily, the second wafer dicing process can be a laser processing process. Since the heat affected zone of the second main material layer caused by laser processing has little effect on the intermediate layer, especially the functional layer of the wafer, the chip bare crystal can be obtained by continuing to laser process and penetrate the second main material layer.

[0082] Optionally, the process for processing the bottom surface of the second groove can be a third wafer scribing process, and the third wafer scribing process processes the second bulk material layer to form a third groove until it penetrates the second bulk material layer. In an embodiment of the present application, the third wafer scribing process is preferably a blade cutting process with faster scribing efficiency and lower cost, that is, the bulk material of the second bulk material layer in the scribing area is directly cut by diamond knife scribing.

[0083] Optionally, the third wafer scribing process may also be the same as the first wafer scribing process mentioned above, such as a plasma dry etching process or a solution wet etching process, so as to quickly remove the material of the second body material layer.

[0084] Alternatively, if Figure 4 As shown in the fourth step in , the width of the third groove generated by the third wafer dicing process can be smaller than the width of the second groove, so that the second body material sublayer of the chip bare crystal includes a first part located at the edge of the second body material sublayer and not covered by the middle sublayer, and a second part covered by the middle sublayer. In this way, the third wafer dicing process does not cause damage to the side wall of the second groove, that is, it does not cause damage to the side of the middle sublayer. For example, when the third wafer dicing process is a blade cutting process, since the blade is not in direct contact with the middle layer, the damage caused by the final blade cutting process will not affect the middle layer, especially the functional layer of the wafer.

[0085] In an embodiment of the present application, the bonded wafer includes two wafers. Optionally, in other embodiments of the present application, the bonded wafer may include more than two wafers, that is, at least three wafers and the at least three wafers are bonded one by one from top to bottom, and the body material layers of each two bonded wafers include an intermediate layer, and finally form a three-dimensional stacked structure. The wafer dicing method shown in the present application can also be applied to the above-mentioned embodiments, that is, before dicing the kth intermediate layer, the silicon material in the dicing road area of ​​the wafer body material layer above the kth intermediate layer is first removed, thereby exposing the kth intermediate layer. After dicing the kth intermediate layer, the silicon material in the dicing road area of ​​the wafer body material layer below the kth intermediate layer is removed, thereby exposing the k+1th intermediate layer. Until the processing penetrates the wafer body material layer at the bottom of the bonded wafer, a chip bare crystal with multiple body material sublayers and multiple intermediate sublayers is obtained.

[0086] The present application pre-processes the material in the dicing area of ​​the first main material layer to expose the intermediate layer, and then directly processes the intermediate layer, thereby avoiding the delamination and cracking of the intermediate layer, especially the functional layer of the wafer, caused by direct blade dicing, and the large heat-affected zone and thermal damage of the intermediate layer, especially the functional layer of the wafer, caused by laser processing dicing.

[0087] In addition, in the embodiment of the present application, the width of the second groove formed by processing the intermediate layer is smaller than the width of the first groove formed by processing the first bulk material layer in the previous process, so that the intermediate sublayer includes a first portion located at the edge of the intermediate sublayer and not covered by the first bulk material sublayer. In this way, the second wafer dicing process for processing the intermediate layer will not affect the sidewall surface of the first groove, and defects of the intermediate layer or the intermediate sublayer on the connection surface between the first bulk material layer and the intermediate layer can be directly obtained through appearance inspection.

[0088] Through the wafer dicing method shown in the present application, one or more chip bare crystals are finally obtained. Figure 6 The schematic diagram of the structure of a chip bare die 600 is shown. The chip bare die 600 includes a first body material sub-layer 610, an intermediate sub-layer 620, a second body material sub-layer 630, micro-bumps, and the like.

[0089] like Figure 6 As shown, when the width of the second groove is smaller than the width of the first groove, the intermediate sublayer 620 includes a first portion located at the edge of the intermediate sublayer 620 and not covered by the first body material sublayer 610, and a second portion covered by the first body material sublayer 610. In this way, defects at the connection surface between the intermediate sublayer 620 and the first body material sublayer 610 can be effectively inspected.

[0090] Alternatively, if Figure 6 As shown, when the width of the third trench is smaller than the width of the second trench, the second body material sublayer 630 includes a first portion located at the edge of the second body material sublayer 630 and not covered by the middle sublayer 620, and a second portion covered by the middle sublayer 620. In this way, the third wafer scribing process will not damage the sidewalls of the second trench, that is, will not damage the middle sublayer 620 and the functional layers in the middle sublayer 620, such as metal wiring and dielectric materials.

[0091] Alternatively, if Figure 6 As shown, the first portion of the intermediate sublayer 620 is provided with a Figure 5 Reference cables shown (not included) Figure 6The reference cable 510 is located between the side of the first main body material sublayer 610 and the side of the middle sublayer 620, and is used to determine the processing position of the first wafer scribing process and / or the second wafer scribing process. In this way, the first wafer scribing process and the second wafer scribing process can be aligned using the reference cable 510, and the alignment is relatively accurate, and the reference cable 510 can be used to check whether the processing position of the wafer scribing process is offset.

[0092] like Figure 1 As shown in (d) in Figure 6 The chip bare die shown can be used as a chip component in an integrated circuit chip, and the integrated circuit chip can be any one of a microprocessor chip, a memory chip, a sensor chip, a driver chip, and a communication chip. The chip bare die or integrated circuit chip shown in the present application can also be set on an electronic device, such as a mobile phone, a personal computer, or an information processing center, etc., which is provided with an integrated circuit chip for realizing communication processing, storage, and expansion, and the integrated circuit chip includes one or more such as Figure 6 Chip bare die with the structure shown.

[0093] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for dicing a bonded wafer, characterized in that: The bonded wafer comprises a first bulk material layer of a first wafer, a second bulk material layer of a second wafer, and an intermediate layer between the first bulk material layer and the second bulk material layer, and the method comprises: A first trench is generated by processing through a first wafer scribing process and penetrating the first bulk material layer; Processing from the bottom surface of the first groove and penetrating the middle layer through a second wafer scribing process to generate a second groove; The second body material layer is processed from the bottom surface of the second groove to obtain a chip bare crystal.

2. The method according to claim 1, characterized in that The width of the second groove is smaller than the width of the first groove, so that the middle sublayer of the chip die includes a first portion located at an edge of the middle sublayer and not covered by the first body material sublayer of the chip die.

3. The method according to claim 2, characterized in that A reference cable is disposed on a first portion of the intermediate sublayer close to a surface of the first main body material sublayer, and the reference cable is used to determine a processing position of the first wafer dicing process and / or the second wafer dicing process.

4. The method according to any one of claims 1 to 3, characterized in that The first wafer dicing process includes a plasma etching process.

5. The method according to any one of claims 1 to 4, characterized in that The second wafer scribing process includes a laser processing process.

6. The method according to any one of claims 1 to 5, characterized in that The processing from the bottom surface of the second groove and penetrating the second body material layer comprises: A third trench is generated by processing from the bottom surface of the second trench through a third wafer scribing process until the third trench penetrates the second body material layer.

7. The method according to claim 6, characterized in that The third wafer dicing process includes a blade cutting process.

8. The method according to claim 6 or 7, characterized in that: The width of the third groove is smaller than the width of the second groove, so that the second body material sublayer of the chip die includes a first portion located at an edge of the second body material sublayer and not covered by the middle sublayer of the chip die.

9. The method according to any one of claims 1 to 8, characterized in that The bottom surface of the first groove is a first surface where the intermediate layer is connected to the first body material layer.

10. The method according to any one of claims 1 to 9, characterized in that: The bonded wafer is formed by hybrid bonding of the first wafer and the second wafer.

11. A chip bare die, characterized in that: include: a first sublayer of bulk material, an intermediate sublayer, and a second sublayer of bulk material; The intermediate sublayer is located between the first body material sublayer and the second body material sublayer and connects the first body material sublayer and the second body material sublayer, the intermediate sublayer includes a first part and a second part, the first part of the intermediate sublayer is located at the edge of the intermediate sublayer and is not covered by the first body material sublayer, and the second part of the intermediate sublayer is covered by the first body material sublayer.

12. The chip bare die according to claim 11, characterized in that: The side surface of the first body material sub-layer is formed by a plasma etching process.

13. The chip bare die according to claim 11 or 12, characterized in that: The side surface of the first part of the intermediate sub-layer is formed by a laser processing process.

14. The chip bare die according to any one of claims 11 to 13, characterized in that: The second bulk material sublayer includes a first portion and a second portion. The first portion of the second bulk material sublayer is located at the edge of the second bulk material sublayer and is not covered by the intermediate sublayer. The second portion of the second bulk material sublayer is covered by the intermediate sublayer.

15. The chip bare die according to claim 14, characterized in that: The side surface of the first portion of the second body material sub-layer is formed by a blade cutting process.

16. The chip bare die according to any one of claims 11 to 15, characterized in that: A reference cable is disposed on a surface of the first portion of the intermediate sublayer close to the first bulk material sublayer, and the reference cable is located between a side surface of the first bulk material sublayer and a side surface of the first portion of the intermediate sublayer.

17. An integrated circuit chip, characterized in that: Comprising the chip bare die as claimed in any one of claims 11 to 16.

18. An electronic device, characterized in that: It comprises the chip bare die as claimed in any one of claims 11 to 16 or the integrated circuit chip as claimed in claim 17.

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