Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor structure, the semiconductor structure comprises a semiconductor body and a first dielectric layer, and the first dielectric layer is located on one side of the semiconductor body; a trimming conductive contact hole is formed in the first dielectric layer, and an opening, close to one side of the semiconductor body, of the trimming conductive contact hole is smaller than an opening, away from one side of the semiconductor body, of the trimming conductive contact hole; the conductive layer is located on the side, away from the semiconductor body, of the first dielectric layer, fills the trimming conductive contact hole and penetrates through the trimming conductive contact hole to be electrically connected with the semiconductor structure. According to the technical scheme provided by the embodiment of the invention, the filling quality of the conductive layer in the conductive contact hole is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In semiconductor devices of integrated circuits, as the size of semiconductor devices decreases and the aspect ratio of conductive contact holes in dielectric layers increases, holes are easily generated in the conductive layer during the process of filling the conductive contact holes, resulting in low filling quality of the conductive layer in the conductive contact holes, and further resulting in low stability of the semiconductor devices. Summary of the invention

[0003] The present invention provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, so as to improve the filling quality of a conductive layer in a conductive contact hole.

[0004] According to one aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor structure, wherein the semiconductor structure comprises a semiconductor body and a first dielectric layer, wherein the first dielectric layer is located on one side of the semiconductor body;

[0005] The first dielectric layer is provided with a trimming conductive contact hole, wherein an opening of the trimming conductive contact hole close to a side of the semiconductor body is smaller than an opening of the trimming conductive contact hole away from the semiconductor body;

[0006] A conductive layer is located on a side of the first dielectric layer away from the semiconductor body, the conductive layer fills the trimmed conductive contact hole, and passes through the trimmed conductive contact hole to be electrically connected to the semiconductor structure.

[0007] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0008] Prepare a semiconductor structure, wherein the semiconductor structure comprises a semiconductor body and a first dielectric layer, and the first dielectric layer is located on one side of the semiconductor body;

[0009] forming a trimming conductive contact hole in the first dielectric layer, wherein an opening of the trimming conductive contact hole close to the semiconductor body is smaller than an opening of the trimming conductive contact hole away from the semiconductor body;

[0010] A conductive layer is formed on a side of the first dielectric layer away from the semiconductor body, wherein the conductive layer fills the trimmed conductive contact hole and passes through the trimmed conductive contact hole to be electrically connected to the semiconductor structure.

[0011] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, wherein the substrate is used for carrying the semiconductor device.

[0012] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0013] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0014] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any of the embodiments of the present invention, wherein the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it into the load.

[0015] The semiconductor device and preparation method, power module, power conversion circuit and vehicle provided by the embodiments of the present invention have an opening close to one side of the semiconductor body and a trimmed conductive contact hole smaller than the opening away from the side of the semiconductor body in the first dielectric layer located on one side of the semiconductor body, thereby improving the formation quality of the conductive layer on the side wall of the trimmed conductive contact hole and the filling quality of the conductive layer in the trimmed conductive contact hole, thereby avoiding the problem of holes in the conductive layer filled in the trimmed conductive contact hole, and further improving the stability of the semiconductor device.

[0016] Among them, in the first aspect, the opening of the trimmed conductive contact hole close to the semiconductor body is smaller than the opening of the trimmed conductive contact hole away from the semiconductor body, so that the filling material of the conductive layer flows better to the bottom of the trimmed conductive contact hole, and the coverage rate of the conductive layer on the side wall is improved, thereby improving the formation quality of the conductive layer on the side wall of the trimmed conductive contact hole and the filling quality of the conductive layer in the trimmed conductive contact hole. In the second aspect, the opening of the trimmed conductive contact hole close to the semiconductor body is smaller than the opening of the trimmed conductive contact hole away from the semiconductor body, which avoids premature sealing during the filling process of the filling material of the conductive layer and the formation of holes. In the third aspect, the opening of the trimmed conductive contact hole close to the semiconductor body is smaller than the opening of the trimmed conductive contact hole away from the semiconductor body, which improves the coverage rate of the conductive layer on the side wall, and there is no need to limit the first dielectric layer to borophosphosilicate glass with good adhesion, and the slope angle of the side wall of the trimmed conductive contact hole is reduced by annealing and reflow, so that the conductive layer can have a good filling effect, so that the flexibility of material selection of the first dielectric layer is increased; and the precipitation of crystals during the annealing process of borophosphosilicate glass can be avoided, resulting in metal cracks or holes in the conductive layer. Furthermore, the selection of the conductive layer is not restricted by the material requiring excellent fluidity, so that the conductive layer can have a good filling effect.

[0017] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art;

[0020] Figure 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0021] Figure 3 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0022] Figure 4-Figure 10 It is a structural schematic diagram corresponding to each step of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0023] Fig.11 yes Figure 3 A schematic diagram of the process included in S120;

[0024] Fig.12 yes Fig.11 The schematic diagram of the process included in S1203;

[0025] Fig.13 It is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations of "including" and "having" are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] like Figure 1 As shown, Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art, and the semiconductor device is a metal-oxide field effect transistor (MOSFET). The semiconductor device includes: a semiconductor structure 01, the semiconductor structure 01 includes a semiconductor body 100 and a first dielectric layer 200, the first dielectric layer 200 is provided with a conductive contact hole 201, the conductive contact hole 201 is completed by a single etching process, the side wall of the conductive contact hole 201 is relatively steep, and after the conductive layer 300 is filled in the conductive contact hole 201, the formation quality of the conductive layer 300 located on the side wall of the conductive contact hole 201 is poor.

[0029] For example, Figure 1As shown, the semiconductor body 100 includes a substrate 101; an epitaxial layer 102, the epitaxial layer 102 is located on one side of the substrate 101, and a well region 103 and an active region 104 are provided on the side of the epitaxial layer 102 away from the substrate 101, and the active region 104 includes a first region 105 and a second region 106. The semiconductor structure 01 also includes a second dielectric layer 107 and a gate 108, the second dielectric layer 107 is located on the side of the epitaxial layer 102 away from the substrate 101, and the gate 108 is located on the side of the second dielectric layer 107 away from the epitaxial layer 102. The first dielectric layer 200 is located on the side of the gate 108 away from the second dielectric layer 107. The conductive layer 300 includes a gate conductive layer 301 and a source conductive layer 302. The semiconductor device also includes a drain 400.

[0030] by Figure 1 Taking the MOSFET power device shown as an example, after the conductive layer 300 is filled in the conductive contact hole 201, the sidewalls of the conductive contact hole 201 are relatively steep, resulting in poor formation quality of the gate conductive layer 301 and the source conductive layer 302 included in the conductive layer 300 located on the sidewalls of the conductive contact hole 201.

[0031] The conductive layer 300 may be made of metal aluminum, and the first dielectric layer 200 may be made of borophosphosilicate glass (BPSG). Metal aluminum has the characteristics of good stability, low resistivity, easy deposition and etching. Borophosphosilicate glass has good adhesion to aluminum. Metal aluminum and borophosphosilicate glass can complete metal contact and metal interconnection at one time. However, as the size of semiconductor device processes in integrated circuits decreases and the aspect ratio of the conductive contact hole 201 increases, the uniformity and adhesion of metal aluminum in the conductive contact hole 201 deteriorate, making it easy for the metal aluminum in the conductive contact hole 201 to produce holes. On the basis of the existing technology in which the conductive contact hole 201 is completed by a one-time etching process, in order to improve the filling capacity of metal aluminum and alleviate the reliability problem of the interconnection line of metal aluminum, on the one hand, the slope angle of the side wall of the conductive contact hole 201 can be reduced by annealing and reflowing the borophosphosilicate glass, and on the other hand, the fluidity of the aluminum filling process can be improved by a hot aluminum process. However, the slope angle of the side wall of the conductive contact hole 201 is reduced to a certain extent by annealing and reflowing the borophosphosilicate glass, but the slope angle is still too large to meet the filling requirements of the metal aluminum, and the metal aluminum will also precipitate crystals during the annealing process of the borophosphosilicate glass, resulting in metal cracks or holes in the metal aluminum. In addition, the hot aluminum process will aggravate the puncture phenomenon. When the metal aluminum contacts the semiconductor material silicon, the silicon will dissolve in the aluminum to generate cracks, and the aluminum atoms will enter the cracks to form punctures, thereby causing the interconnection conductivity of the metal aluminum to be poor or even failure.

[0032] In order to improve the filling quality of the conductive layer in the conductive contact hole, the embodiment of the present invention provides the following technical solution:

[0033] like Figure 2 As shown, Figure 2 1 is a schematic diagram of a semiconductor device provided by an embodiment of the present invention, wherein the semiconductor device comprises: a semiconductor structure 01, wherein the semiconductor structure 01 comprises a semiconductor body 100 and a first dielectric layer 200, wherein the first dielectric layer 200 is located on one side of the semiconductor body 100; the first dielectric layer 200 is provided with a trimmed conductive contact hole 202, wherein the opening of the trimmed conductive contact hole 202 close to the semiconductor body 100 is smaller than the opening of the trimmed conductive contact hole 202 away from the semiconductor body 100. A conductive layer 300, wherein the conductive layer 300 is located on the side of the first dielectric layer 200 away from the semiconductor body 100, and the conductive layer 300 fills the trimmed conductive contact hole 202, and is electrically connected to the semiconductor structure 01 through the trimmed conductive contact hole 202.

[0034] In the semiconductor device provided by the embodiment of the present invention, a trimmed conductive contact hole 202 is provided in the first dielectric layer 200 located on one side of the semiconductor body 100, and the opening close to the side of the semiconductor body 100 is smaller than the opening away from the side of the semiconductor body 100. The formation quality of the conductive layer 300 on the side wall of the trimmed conductive contact hole 202 and the filling quality of the conductive layer 300 in the trimmed conductive contact hole 202 are improved, thereby avoiding the problem of holes in the conductive layer 300 filled in the trimmed conductive contact hole 202, thereby improving the stability of the semiconductor device.

[0035] Among them, on the first aspect, the opening of the trimmed conductive contact hole 202 close to the semiconductor body 100 is smaller than the opening of the trimmed conductive contact hole 202 away from the semiconductor body 100, so that the filling material of the conductive layer 300 flows better to the bottom of the trimmed conductive contact hole 202, and the coverage of the sidewall by the conductive layer 300 is improved, thereby improving the formation quality of the conductive layer 300 on the sidewall of the trimmed conductive contact hole 202 and the filling quality of the conductive layer 300 in the trimmed conductive contact hole 202. On the second aspect, the opening of the trimmed conductive contact hole 202 close to the semiconductor body 100 is smaller than the opening of the trimmed conductive contact hole 202 away from the semiconductor body 100, which avoids premature sealing of the filling material of the conductive layer 300 during the filling process to form holes. Thirdly, the opening of the conductive contact hole 202 close to the semiconductor body 100 is adjusted to be smaller than the opening of the conductive contact hole 202 away from the semiconductor body 100, thereby improving the coverage of the sidewall by the conductive layer 300. It is not necessary to limit the first dielectric layer 200 to borophosphosilicate glass with good adhesion, and the slope angle of the sidewall of the conductive contact hole 202 is reduced by annealing and reflow, so that the conductive layer 300 can have a good filling effect, and the flexibility of the material selection of the first dielectric layer 200 is increased; and the crystal precipitation during the annealing process of the borophosphosilicate glass can be avoided, resulting in metal cracks or holes in the conductive layer 300. Moreover, the selection of the conductive layer 300 is not limited by the need for excellent fluidity of the material, so that the conductive layer 300 can have a good filling effect.

[0036] Optionally, based on the above technical solution, Figure 2 As shown, the slope angle of the sidewall of the conductive contact hole 202 is adjusted to be greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0037] like Figure 2 As shown, in the right triangle framed by the red lines, the height H of the side wall of the trimmed conductive contact hole 202 and the width W of the side wall of the trimmed conductive contact hole 202 serve as two right-angled sides of the right triangle. The tangent value of the slope angle α of the side wall of the trimmed conductive contact hole 202 is equal to the ratio of the height H of the side wall of the trimmed conductive contact hole 202 to the width W of the side wall of the trimmed conductive contact hole 202; the height H of the side wall of the trimmed conductive contact hole 202 is the size of the side wall of the trimmed conductive contact hole 202 in the first direction, and the width W of the side wall of the trimmed conductive contact hole 202 is the size of the side wall of the trimmed conductive contact hole 202 in the second direction, and the second direction is perpendicular to the first direction. In the embodiment of the present invention, the first direction is Figure 2 The second direction is set perpendicular to the first direction. Figure 2 The X direction in .

[0038] For example, the slope angle of the sidewall of the conductive contact hole 202 may be adjusted to 60 degrees, 70 degrees, or 80 degrees.

[0039] Specifically, the slope angle of the sidewall of the trimmed conductive contact hole 202 is greater than or equal to 60 degrees and less than or equal to 80 degrees, so that the verticality of the sidewall of the trimmed conductive contact hole 202 is relatively small. On the one hand, the filling material of the conductive layer 300 can flow to the bottom of the trimmed conductive contact hole 202 better, improving the coverage of the conductive layer 300 on the sidewall, thereby improving the formation quality of the conductive layer 300 on the sidewall of the trimmed conductive contact hole 202 and the filling quality of the conductive layer 300 in the trimmed conductive contact hole 202. On the other hand, the opening of the trimmed conductive contact hole 202 is relatively large, which avoids premature sealing during the filling process of the filling material of the conductive layer 300 to form a hole.

[0040] The above technical solution can be applied to MOSFET power devices, and is specifically described as follows:

[0041] Optionally, based on the above technical solution, Figure 2 As shown, the semiconductor body 100 in the semiconductor structure 01 includes a first surface 100a and a second surface 100b arranged opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 105, the first region 105 is arranged on the first surface 100a, and the well region 103 is arranged on a side of the first region 105 away from the first surface 100a; the semiconductor structure 01 also includes a gate structure, the gate structure is arranged on the first surface 100a or the gate structure extends from the first surface 100a to the semiconductor body 100; the gate structure includes a second dielectric layer 107 and a gate 108, the second dielectric layer 108 is provided. The dielectric layer 107 is used to insulate the spacer gate 108 and the semiconductor body 100; the conductive layer 300 includes a gate conductive layer 301 and a source conductive layer 302, the gate conductive layer 301 is filled with the trimmed conductive contact hole 202 to achieve electrical connection with the gate 108; the source conductive layer 302 is filled with the trimmed conductive contact hole 202 to achieve electrical connection with the first region 105; the first dielectric layer 200 is located on the side of the gate 108 away from the second dielectric layer 107, and is used to insulate the spacer gate 108 and the source conductive layer 302; the semiconductor device also includes a drain 400, and the drain 400 is located on the second surface 100b.

[0042] It should be particularly noted that the drawings of the embodiments of the present invention are introduced by taking a planar MOSFET power device as an example. In other embodiments, the drawings are also applicable to a single trench MOSFET power device and a double trench MOSFET power device. In the single trench MOSFET power device and the double trench MOSFET power device, the gate structure composed of the second dielectric layer 107 and the gate 108 extends from the first surface 100a to the semiconductor body 100. In the planar MOSFET power device, the gate structure composed of the second dielectric layer 107 and the gate 108 is arranged on the first surface 100a.

[0043] Exemplarily, the semiconductor body 100 includes a substrate 101 and an epitaxial layer 102. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 102. The epitaxial layer 102 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 101. The epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0044] The active region 104 may include only the first region 105 , or may include the first region 105 and the second region 106 , and the second region 106 may form a good ohmic contact with the source conductive layer 302 .

[0045] Specifically, in the MOSFET power device, a trimming conductive contact hole 202 is provided in the first dielectric layer 200 located on one side of the semiconductor body 100, which is close to the opening on one side of the semiconductor body 100 and smaller than the opening on one side of the semiconductor body 100. During the process of filling the gate conductive layer 301 and the source conductive layer 302 in the trimming conductive contact hole 202, the formation quality of the gate conductive layer 301 and the source conductive layer 302 on the side wall of the trimming conductive contact hole 202 and the filling quality of the gate conductive layer 301 and the source conductive layer 302 in the trimming conductive contact hole 202 are improved, thereby avoiding the problem of holes in the gate conductive layer 301 and the source conductive layer 302 filled in the trimming conductive contact hole 202, thereby improving the stability of the MOSFET power device.

[0046] Optionally, the JFET region between the well regions 103 may be doped with a doping type opposite to that of the well region 103 and a doping concentration greater than that of the epitaxial layer 102 , so as to reduce the on-resistance of the power device.

[0047] Optionally, based on the above technical solution, Figure 2As shown, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body. The MOSFET power device corresponding to the silicon carbide semiconductor body is a silicon carbide MOSFET power device. The MOSFET power device corresponding to the gallium nitride semiconductor body is a gallium nitride MOSFET power device.

[0048] Specifically, silicon carbide MOSFET power devices or gallium nitride MOSFET power devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices. When silicon carbide or gallium nitride materials are used as the semiconductor body 100, due to the high temperature resistance of silicon carbide or gallium nitride materials, it can also prevent particles in the semiconductor body 100 from dissolving in the conductive layer 300 to generate cracks when the filling material of the conductive layer 300 contacts the semiconductor body 100, thereby further improving the formation quality of the conductive layer 300 of the side wall of the trimmed conductive contact hole 202 and the filling quality of the conductive layer 300 in the trimmed conductive contact hole 202.

[0049] The present invention also provides a method for manufacturing a semiconductor device. Figure 3 As shown, Figure 3 1 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, and the method for preparing a semiconductor device includes:

[0050] S110 , preparing a semiconductor structure, wherein the semiconductor structure includes a semiconductor body and a first dielectric layer, and the first dielectric layer is located on one side of the semiconductor body.

[0051] like Figure 4 As shown, a semiconductor structure 01 is prepared. The semiconductor structure 01 includes a semiconductor body 100 and a first dielectric layer 200, and the first dielectric layer 200 is located on one side of the semiconductor body 100. The semiconductor body 100 can be a film layer that realizes the semiconductor function of a MOSFET power device.

[0052] S120 , forming a trimmed conductive contact hole in the first dielectric layer, wherein an opening of the trimmed conductive contact hole close to the semiconductor body is smaller than an opening of the trimmed conductive contact hole away from the semiconductor body.

[0053] Alternatively, if Fig.11 As shown, Fig.11 yes Figure 3 The process diagram of S120 includes the following steps: S120 forms a trimmed conductive contact hole in the first dielectric layer and includes:

[0054] S1201 , forming a mask layer on a side of the first dielectric layer away from the semiconductor body, wherein the mask layer includes a through hole, and the through hole exposes the first dielectric layer.

[0055] like Figure 5 As shown, when the mask layer 500 is a photoresist, the mask layer 500 can be formed on the side of the first dielectric layer 200 away from the semiconductor body 100 by a photolithography process, wherein the mask layer 500 includes a through hole 501, and the through hole 501 exposes the first dielectric layer 200. The through hole 501 is a mask pattern of the mask layer 500. In other embodiments, the mask layer 500 can also be other materials.

[0056] S1202 , forming an initial conductive contact hole in the first dielectric layer through a primary etching process according to the mask layer, wherein the initial conductive contact hole is connected to the through hole.

[0057] like Figure 5 As shown, according to the mask layer 500, an initial conductive contact hole 2020 is formed in the first dielectric layer 200 through a primary etching process, wherein the initial conductive contact hole 2020 is connected to the through hole 501. The verticality of the initial conductive contact hole 2020 is relatively high, and the opening of the initial conductive contact hole 2020 close to the semiconductor body 100 and the opening of the initial conductive contact hole 2020 away from the semiconductor body 100 are equal, and at least one subsequent etching process is required to reduce the opening of the trimmed conductive contact hole 202 close to the semiconductor body 100 to be smaller than the opening of the trimmed conductive contact hole 202 away from the semiconductor body 100.

[0058] S1203 , at least once, etching the sidewall of the initial conductive contact hole at a depth less than the depth of the initial conductive contact hole by a second etching process according to the mask layer after the trimming and enlarging process, so as to obtain a trimmed conductive contact hole.

[0059] The etching depth of the re-etching process gradually decreases as the number of re-etching processes increases; the mask layer after the trimming and enlarging process is the mask layer after the through hole of the mask layer of the initial etching process is trimmed and enlarged.

[0060] by Figure 6-Figure 9 For example, after each modification and enlargement of the through hole of the mask layer 500, a second etching process is performed to obtain the modified conductive contact hole 202. The specific process is as follows:

[0061] like Figure 6 As shown, the opening area of ​​the through hole 501 is enlarged to achieve a trimming and enlarging process of the opening area of ​​the through hole 501 of the mask layer 500 .

[0062] like Figure 7 As shown, according to Figure 6After the mask layer 500 is trimmed and enlarged, the sidewall of the initial conductive contact hole 2020 is etched again at the first etching depth to enlarge the opening of the initial conductive contact hole 2020 to obtain the trimmed conductive contact hole 202 .

[0063] like Figure 8 As shown, the opening area of ​​the through hole 501 is enlarged again, so as to adjust and increase the opening area of ​​the through hole 501 of the mask layer 500 .

[0064] like Fig. 9 As shown, according to Figure 8 The mask layer 500 after the trimming and enlarging process is etched again to etch the sidewall of the initial conductive contact hole 2020 at a second etching depth to increase the opening of the trimmed conductive contact hole 202, wherein the second etching depth is less than the first etching depth.

[0065] Figure 6-Figure 9 The mask layer 500 after two trimming and enlarging processes is shown as an example, and the sidewall of the initial conductive contact hole 2020 is etched at a depth less than the depth of the initial conductive contact hole 2020 through a re-etching process to obtain a trimmed conductive contact hole 202. The etching depth of the re-etching process gradually decreases as the number of re-etching processes increases; the mask layer 500 after the trimming and enlarging process is the mask layer after the through hole 501 of the mask layer 500 of the initial etching process is trimmed and enlarged.

[0066] Specifically, the adjusted conductive contact hole 202 can be obtained by increasing the number of times the opening area of ​​the through hole 501 of the mask layer 500 is adjusted and enlarged and the number of times the etching is repeated.

[0067] S1204, removing the mask layer.

[0068] like Fig.10 As shown, the mask layer 500 is removed. When the mask layer 500 is a photoresist, ultraviolet light irradiation can be selected to remove it.

[0069] S130, forming a conductive layer on a side of the first dielectric layer away from the semiconductor body, wherein the conductive layer fills the trimmed conductive contact hole and is electrically connected to the semiconductor structure through the trimmed conductive contact hole.

[0070] like Figure 2 As shown, a conductive layer 300 may be formed on a side of the first dielectric layer 200 away from the semiconductor body 100 by a conductive layer filling process, wherein the conductive layer 300 fills the trimmed conductive contact hole 202 .

[0071] In the method for preparing a semiconductor device provided by an embodiment of the present invention, a trimmed conductive contact hole 202 is provided in the first dielectric layer 200 located on one side of the semiconductor body 100, and the opening is closer to the side of the semiconductor body 100 and smaller than the opening away from the side of the semiconductor body 100. This improves the formation quality of the conductive layer 300 on the sidewall of the trimmed conductive contact hole 202 and the filling quality of the conductive layer 300 in the trimmed conductive contact hole 202, thereby avoiding the problem of holes in the conductive layer 300 filled in the trimmed conductive contact hole 202, thereby improving the stability of the semiconductor device.

[0072] Among them, on the first aspect, the opening of the trimmed conductive contact hole 202 close to the semiconductor body 100 is smaller than the opening of the trimmed conductive contact hole 202 away from the semiconductor body 100, so that the filling material of the conductive layer 300 flows better to the bottom of the trimmed conductive contact hole 202, and the coverage of the sidewall by the conductive layer 300 is improved, thereby improving the formation quality of the conductive layer 300 on the sidewall of the trimmed conductive contact hole 202 and the filling quality of the conductive layer 300 in the trimmed conductive contact hole 202. On the second aspect, the opening of the trimmed conductive contact hole 202 close to the semiconductor body 100 is smaller than the opening of the trimmed conductive contact hole 202 away from the semiconductor body 100, which avoids premature sealing of the filling material of the conductive layer 300 during the filling process to form holes. Thirdly, the opening of the conductive contact hole 202 close to the semiconductor body 100 is adjusted to be smaller than the opening of the conductive contact hole 202 away from the semiconductor body 100, thereby improving the coverage of the sidewall by the conductive layer 300. It is not necessary to limit the first dielectric layer 200 to borophosphosilicate glass with good adhesion, and the slope angle of the sidewall of the conductive contact hole 202 is reduced by annealing and reflow, so that the conductive layer 300 can have a good filling effect, and the flexibility of the material selection of the first dielectric layer 200 is increased; and the crystal precipitation during the annealing process of the borophosphosilicate glass can be avoided, resulting in metal cracks or holes in the conductive layer 300. Moreover, the selection of the conductive layer 300 is not limited by the need for excellent fluidity of the material, so that the conductive layer 300 can have a good filling effect.

[0073] Furthermore, the trimmed conductive contact hole 202 is a conductive contact hole completed by a primary etching process and at least one secondary etching process. Since the mask layer used in the primary etching process and at least one secondary etching process is prepared by a mask layer formation process, it is only necessary to trim and increase the opening area of ​​the through hole of the mask layer of the previous etching process before the secondary etching process, thereby simplifying the preparation process of the semiconductor device and reducing the preparation cost. Exemplarily, when the mask layer is prepared by photoresist, the preparation of the mask layer only requires one photolithography process, wherein the photolithography process at least includes spin coating, exposure and development processes of the photoresist.

[0074] Specifically, the conductive contact hole 202 is adjusted by increasing the opening of the initial conductive contact hole by at least one re-etching process; the etching depth of at least one re-etching process is less than the etching depth of the initial conductive contact hole; the etching depth of the re-etching process gradually decreases as the number of re-etching processes increases. The more times the re-etching process is performed, the larger the opening of the adjusted conductive contact hole 202 is; the smaller the difference in etching depth between two adjacent etching processes is, the smoother the sidewall of the adjusted conductive contact hole 202 is. Since the mask layer 500 used in the initial etching process and at least one re-etching process is prepared by a mask layer formation process, it is only necessary to adjust and increase the opening area of ​​the through hole of the mask layer 500 of the previous etching process before the re-etching process. Compared with the technical solution of increasing the opening of the initial conductive contact hole by multiple etching processes and forming a new mask layer before each etching process, the number of times the mask layer is formed is reduced, thereby simplifying the preparation process of the semiconductor device, reducing the preparation cost, and achieving the effect of reducing cost and increasing efficiency.

[0075] Optionally, based on the above technical solution, Fig.12 As shown, Fig.12 yes Fig.11 The process diagram included in S1203, S1203, at least once, according to the mask layer after the trimming and enlarging process, the side wall of the initial conductive contact hole is etched with an etching depth less than the initial conductive contact hole depth by a re-etching process to obtain the trimmed conductive contact hole, including performing the following operations at least once:

[0076] S12030, expanding the opening area of ​​the through hole to adjust and increase the opening area of ​​the through hole of the mask layer.

[0077] like Figure 6 As shown, the opening area of ​​the through hole 501 is enlarged to achieve a trimming and enlarging process of the opening area of ​​the through hole 501 of the mask layer 500 .

[0078] S12031. According to the mask layer after the trimming and enlarging process, the sidewall of the initial conductive contact hole is etched again by an etching process at a depth less than that of the previous etching process to increase the opening of the sidewall of the initial conductive contact hole.

[0079] like Figure 7 As shown, according to Figure 6 After the mask layer 500 is trimmed and enlarged, the sidewall of the initial conductive contact hole 2020 is etched again with a depth less than that of the last etching process to increase the opening of the initial conductive contact hole 2020 .

[0080] It should be noted that the previous etching process may be a primary etching process or a previous re-etching process.

[0081] The above process is Figure 6 and Figure 7 For example, the specific process of performing a re-etching process to increase the opening of the initial conductive contact hole 2020 after trimming and enlarging the through hole of the mask layer 500 is introduced. The more times the re-etching process is performed, the larger the opening of the trimmed conductive contact hole 202 is; the smaller the difference in etching depth between two adjacent etching processes is, the smoother the sidewall of the trimmed conductive contact hole 202 is.

[0082] Optionally, based on the above technical solution, S1201 forming a mask layer on a side of the first dielectric layer away from the semiconductor body includes:

[0083] A mask layer including photoresist is formed on a side of the first dielectric layer away from the semiconductor body.

[0084] like Figure 5 As shown, a mask layer 500 including photoresist is formed on a side of the first dielectric layer 200 away from the semiconductor body 100 by a photolithography process. The photolithography process includes at least spin coating, exposure and development processes.

[0085] Specifically, the mask layer 500 is made of photoresist. Since the mask layer 500 used in the initial etching process and at least one secondary etching process is prepared through a mask layer 500 photolithography process, it is only necessary to adjust and increase the opening area of ​​the through hole 501 of the mask layer 500 of the previous etching process before the secondary etching process. Compared with the technical solution of using multiple etching processes and forming a new mask layer before each etching process to increase the opening of the initial conductive contact hole 2020, the number of times the mask layer is formed through the photolithography process is reduced, thereby simplifying the preparation process of the semiconductor device, reducing the preparation cost, and achieving the effect of reducing cost and increasing efficiency.

[0086] Optionally, based on the above technical solution, S12030 enlarging the opening area of ​​the through hole to adjust and increase the opening area of ​​the through hole of the mask layer includes:

[0087] The opening area of ​​the through hole is enlarged by a gas etching process, so as to adjust and increase the opening area of ​​the through hole of the mask layer.

[0088] like Figure 6As shown, the opening area of ​​the through hole 501 can be enlarged by an etching process with gases such as oxygen, so as to achieve a one-time adjustment and enlargement of the opening area of ​​the through hole 501 of the mask layer 500, thereby reducing the number of times the mask layer 500 is formed by a photolithography process, thereby simplifying the preparation process of the semiconductor device, reducing the preparation cost, and achieving the effect of reducing cost and increasing efficiency.

[0089] Optionally, based on the above technical solution, S1203, at least once, according to the mask layer after the trimming and enlarging process, a sidewall of the initial conductive contact hole is etched with an etching depth less than the initial conductive contact hole depth by a re-etching process to obtain a trimmed conductive contact hole, including:

[0090] At least once, according to the mask layer after the trimming and enlargement processing, the side wall of the initial conductive contact hole is etched again by an etching process with an etching depth less than the depth of the initial conductive contact hole to obtain a trimmed conductive contact hole with a side wall slope angle greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0091] like Figure 2 As shown, in the right triangle framed by the red lines, the height H of the side wall of the trimmed conductive contact hole 202 and the width W of the side wall of the trimmed conductive contact hole 202 serve as two right-angled sides of the right triangle. The tangent value of the slope angle α of the side wall of the trimmed conductive contact hole 202 is equal to the ratio of the height H of the side wall of the trimmed conductive contact hole 202 to the width W of the side wall of the trimmed conductive contact hole 202; the height H of the side wall of the trimmed conductive contact hole 202 is the size of the side wall of the trimmed conductive contact hole 202 in the first direction, and the width W of the side wall of the trimmed conductive contact hole 202 is the size of the side wall of the trimmed conductive contact hole 202 in the second direction, and the second direction is perpendicular to the first direction. In the embodiment of the present invention, the first direction is Figure 2 The second direction is set perpendicular to the first direction. Figure 2 The X direction in .

[0092] For example, Figure 6-Figure 9 As shown, after the mask layer 500 has been trimmed and enlarged twice, the sidewall of the initial conductive contact hole 2020 is etched again with an etching depth less than the depth of the initial conductive contact hole 2020 to increase the opening of the sidewall of the initial conductive contact hole 2020, thereby obtaining a trimmed conductive contact hole 202 with a slope angle greater than or equal to 60 degrees and less than or equal to 80 degrees.

[0093] Specifically, the slope angle of the sidewall of the trimmed conductive contact hole 202 is greater than or equal to 60 degrees and less than or equal to 80 degrees, so that the verticality of the sidewall of the trimmed conductive contact hole 202 is relatively small. On the one hand, the filling material of the conductive layer 300 can flow to the bottom of the trimmed conductive contact hole 202 better, improving the coverage of the sidewall of the trimmed conductive contact hole 202 by the conductive layer 300, thereby improving the formation quality of the conductive layer 300 on the sidewall of the trimmed conductive contact hole 202 and the filling quality of the conductive layer 300 in the trimmed conductive contact hole 202. On the other hand, the opening of the trimmed conductive contact hole 202 is relatively large, which avoids premature sealing during the filling process of the filling material of the conductive layer 300 to form holes.

[0094] The embodiment of the present invention also provides a method for preparing a MOSFET power device having a trimmed conductive contact hole 202. Fig.13 As shown, Fig.13 1 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, the method comprising the following steps:

[0095] S210, providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being arranged on the first surface, and the well region being arranged on a side of the first region away from the first surface.

[0096] Exemplarily, the semiconductor body 100 includes a substrate 101 and an epitaxial layer 102. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 102. The epitaxial layer 102 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 101. The epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0097] Taking the semiconductor body 100 including a substrate 101 and an epitaxial layer 102 as an example, the semiconductor body 100 includes:

[0098] like Figure 4 As shown, a substrate 101 is provided. The substrate 101 may be a silicon carbide substrate or a gallium nitride substrate.

[0099] like Figure 4 As shown, an epitaxial layer 102 is formed on one side of a substrate 101 by an epitaxial process, wherein a well region 103 and an active region 104 are provided on a side of the epitaxial layer 102 away from the substrate 101. Exemplarily, the active region 104 includes a first region 105 and a second region 106. The active region 104 may include only the first region 105, or may include the first region 105 and the second region 106, and the second region 106 may form a good ohmic contact with the source conductive layer 302.

[0100] S220, forming a gate structure on the first surface, wherein the gate structure is disposed on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure comprises a second dielectric layer and a gate, wherein the second dielectric layer is used for insulating and spacing the gate and the semiconductor body.

[0101] like Figure 4 As shown, a second dielectric layer 107 is formed on the epitaxial layer 102 away from the substrate 101 through a film forming process. The second dielectric layer 107 can be made of silicon oxide or a dielectric layer with a higher dielectric constant.

[0102] like Figure 4 As shown, a gate 108 is formed on a side of the second dielectric layer 107 away from the epitaxial layer 102. The gate 108 may be a polysilicon gate.

[0103] It should be particularly noted that the drawings of the embodiments of the present invention are introduced by taking a planar MOSFET power device as an example. In other embodiments, the drawings are also applicable to a single trench MOSFET power device and a double trench MOSFET power device. In the single trench MOSFET power device and the double trench MOSFET power device, the gate structure composed of the second dielectric layer 107 and the gate 108 extends from the first surface 100a to the semiconductor body 100. In the planar MOSFET power device, the gate structure composed of the second dielectric layer 107 and the gate 108 is arranged on the first surface 100a.

[0104] S230 , forming a first dielectric layer on a side of the gate away from the second dielectric layer.

[0105] like Figure 4 As shown, a first dielectric layer 200 is formed on the side of the gate 108 away from the second dielectric layer 107 by film formation. The first dielectric layer 200 is used to insulate the gate 108 and the subsequently formed conductive layer 300. The embodiment of the present invention does not specifically limit the material of the first dielectric layer 200, and a dielectric layer with an absolute performance can be selected.

[0106] S240, forming a trimmed conductive contact hole in the first dielectric layer, wherein an opening of the trimmed conductive contact hole close to the semiconductor body is smaller than an opening of the trimmed conductive contact hole away from the semiconductor body.

[0107] like Figure 5 As shown, when the mask layer 500 is photoresist, the mask layer 500 can be formed on the side of the first dielectric layer 200 away from the semiconductor body 100 by a photolithography process, wherein the mask layer 500 includes a through hole 501 , and the through hole 501 exposes the first dielectric layer 200 .

[0108] like Figure 5As shown, according to the mask layer 500 , an initial conductive contact hole 2020 is formed in the first dielectric layer 200 through a primary etching process, wherein the initial conductive contact hole 2020 is connected to the through hole 501 .

[0109] Figure 6-Figure 9 The mask layer 500 after two trimming and enlarging processes is shown as an example, and the sidewall of the initial conductive contact hole 2020 is etched at a depth less than the depth of the initial conductive contact hole 2020 through a re-etching process to obtain a trimmed conductive contact hole 202. The etching depth of the re-etching process gradually decreases as the number of re-etching processes increases; the mask layer 500 after the trimming and enlarging process is the mask layer after the through hole 501 of the mask layer 500 of the initial etching process is trimmed and enlarged.

[0110] like Fig.10 As shown, the mask layer 500 is removed. When the mask layer 500 is a photoresist, ultraviolet light irradiation can be selected to remove it.

[0111] S250, forming a gate conductive layer and a source conductive layer on a side of the first dielectric layer away from the semiconductor body, wherein the gate conductive layer is filled with a trimmed conductive contact hole to achieve connection with the gate; and the source conductive layer is filled with a trimmed conductive contact hole to achieve connection with the active area.

[0112] like Figure 2 As shown, a conductive layer 300 may be formed on a side of the first dielectric layer 200 away from the semiconductor body 100 by a conductive layer filling process, wherein the conductive layer 300 fills the trimmed conductive contact hole 202. Figure 2 As shown, the formation of the conductive layer 300 includes the preparation of a gate conductive layer 301 and a source conductive layer 302. The gate conductive layer 301 fills the trimmed conductive contact hole 202 to achieve electrical connection with the gate 108; the source conductive layer 302 fills the trimmed conductive contact hole to achieve electrical connection with the first region 105.

[0113] S260, forming a drain on the second surface.

[0114] like Figure 2 As shown, the drain 400 is formed on a side of the substrate 101 away from the epitaxial layer 102 by a film forming process.

[0115] Specifically, in the MOSFET power device, a trimming conductive contact hole 202 is provided in the first dielectric layer 200 located on one side of the semiconductor body 100, which is close to the opening on one side of the semiconductor body 100 and smaller than the opening on one side of the semiconductor body 100. During the process of filling the gate conductive layer 301 and the source conductive layer 302 in the trimming conductive contact hole 202, the formation quality of the gate conductive layer 301 and the source conductive layer 302 on the side wall of the trimming conductive contact hole 202 and the filling quality of the gate conductive layer 301 and the source conductive layer 302 in the trimming conductive contact hole 202 are improved, thereby avoiding the problem of holes in the gate conductive layer 301 and the source conductive layer 302 filled in the trimming conductive contact hole 202, thereby improving the stability of the MOSFET power device.

[0116] Optionally, based on the above technical solution, S110 provides the semiconductor body 100 including providing a silicon carbide semiconductor body or a gallium nitride semiconductor body. The MOSFET power device corresponding to the silicon carbide semiconductor body is a silicon carbide MOSFET power device. The MOSFET power device corresponding to the gallium nitride semiconductor body is a gallium nitride MOSFET power device.

[0117] Specifically, silicon carbide MOSFET power devices or gallium nitride MOSFET power devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices. When silicon carbide or gallium nitride materials are used as the semiconductor body 100, due to the high temperature resistance of silicon carbide or gallium nitride materials, it can also prevent particles in the semiconductor body 100 from dissolving in the conductive layer 300 to generate cracks when the filling material of the conductive layer 300 contacts the semiconductor body 100, thereby further improving the formation quality of the conductive layer 300 of the side wall of the trimmed conductive contact hole 202 and the filling quality of the conductive layer 300 in the trimmed conductive contact hole 202.

[0118] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device as described in any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device as described in any embodiment of the present invention are not described in detail here.

[0119] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board. Therefore, the beneficial effects of the power conversion circuit including the semiconductor device described in any embodiment of the present invention are not repeated here.

[0120] The embodiment of the present invention further provides a vehicle, comprising a load and any power conversion circuit as in the embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention are not repeated here.

[0121] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0122] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor structure, wherein the semiconductor structure comprises a semiconductor body and a first dielectric layer, and the first dielectric layer is located on one side of the semiconductor body; The first dielectric layer is provided with a trimming conductive contact hole, wherein an opening of the trimming conductive contact hole close to the semiconductor body is smaller than an opening of the trimming conductive contact hole away from the semiconductor body; A conductive layer is located on a side of the first dielectric layer away from the semiconductor body, the conductive layer fills the trimmed conductive contact hole, and passes through the trimmed conductive contact hole to be electrically connected to the semiconductor structure.

2. The semiconductor device according to claim 1, wherein: The slope angle of the sidewall of the trimmed conductive contact hole is greater than or equal to 60 degrees and less than or equal to 80 degrees.

3. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor body comprises a first surface and a second surface arranged opposite to each other; The semiconductor body further comprises a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; The semiconductor structure further comprises a gate structure, wherein the gate structure is arranged on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure comprises a second dielectric layer and a gate, wherein the second dielectric layer is used for insulating and spacing the gate and the semiconductor body; The conductive layer comprises a gate conductive layer and a source conductive layer, wherein the gate conductive layer fills the trimmed conductive contact hole to achieve electrical connection with the gate; the source conductive layer fills the trimmed conductive contact hole to achieve electrical connection with the first region; The first dielectric layer is located on a side of the gate away from the second dielectric layer, and is used for insulating and spacing the gate and the source conductive layer; The semiconductor device further includes a drain electrode, and the drain electrode is located on the second surface.

4. The semiconductor device according to claim 1, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

5. A method for preparing a semiconductor device, characterized in that: include: Prepare a semiconductor structure, wherein the semiconductor structure comprises a semiconductor body and a first dielectric layer, and the first dielectric layer is located on one side of the semiconductor body; forming a trimming conductive contact hole in the first dielectric layer, wherein an opening of the trimming conductive contact hole close to the semiconductor body is smaller than an opening of the trimming conductive contact hole away from the semiconductor body; A conductive layer is formed on a side of the first dielectric layer away from the semiconductor body, wherein the conductive layer fills the trimmed conductive contact hole and passes through the trimmed conductive contact hole to be electrically connected to the semiconductor structure.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: Forming a trimmed conductive contact hole in the first dielectric layer includes: forming a mask layer on a side of the first dielectric layer away from the semiconductor body, wherein the mask layer includes a through hole, and the through hole exposes the first dielectric layer; According to the mask layer, forming an initial conductive contact hole in the first dielectric layer through a primary etching process, wherein the initial conductive contact hole is connected to the through hole; At least once, according to the mask layer after the trimming and enlarging process, the side wall of the initial conductive contact hole is etched at an etching depth less than the initial conductive contact hole depth through a re-etching process to obtain the trimmed conductive contact hole; the etching depth of the re-etching process gradually decreases as the number of re-etching processes increases; the mask layer after the trimming and enlarging process is the mask layer after the opening area of ​​the through hole of the mask layer of the previous etching process is trimmed and enlarged; The mask layer is removed.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: At least once, etching the sidewall of the initial conductive contact hole at a depth less than the depth of the initial conductive contact hole by a second etching process according to the mask layer after the trimming and enlarging process to obtain the trimmed conductive contact hole, including performing the following operations at least once: Enlarging the opening area of ​​the through hole to achieve trimming and enlarging the opening area of ​​the through hole of the mask layer; According to the mask layer after the trimming and enlarging process, the sidewall of the initial conductive contact hole is etched again with a less etching depth than the last etching process to increase the opening of the initial conductive contact hole.

8. The method for preparing a semiconductor device according to claim 6 or 7, characterized in that: Forming a mask layer on a side of the first dielectric layer away from the semiconductor body comprises: A mask layer including photoresist is formed on a side of the first dielectric layer away from the semiconductor body.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: Enlarging the opening area of ​​the through hole to adjust and increase the opening area of ​​the through hole of the mask layer includes: The opening area of ​​the through hole is enlarged by a gas etching process, so as to adjust and increase the opening area of ​​the through hole of the mask layer.

10. The method for preparing a semiconductor device according to claim 6, characterized in that: At least once, etching the sidewall of the initial conductive contact hole at a depth less than the depth of the initial conductive contact hole by a second etching process according to the mask layer after the trimming and enlarging process to obtain the trimmed conductive contact hole, comprising: At least once, according to the mask layer after the trimming and enlargement processing, the side wall of the initial conductive contact hole is etched again by an etching process with an etching depth less than the depth of the initial conductive contact hole to obtain a trimmed conductive contact hole with a side wall slope angle greater than or equal to 60 degrees and less than or equal to 80 degrees.

11. The method for preparing a semiconductor device according to claim 5, 6, 7, 9 or 10, characterized in that: The preparation of semiconductor structures includes: A semiconductor body is provided, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region and a first region, wherein the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; A gate structure is formed on the first surface, wherein the gate structure is arranged on the first surface or the gate structure extends from the first surface into the semiconductor body; the gate structure comprises a second dielectric layer and a gate, wherein the second dielectric layer is used for insulating and spacing the gate and the semiconductor body; forming a first dielectric layer on a side of the gate away from the second dielectric layer; Forming a conductive layer on a side of the first dielectric layer away from the semiconductor body comprises: A gate conductive layer and a source conductive layer are formed on a side of the first dielectric layer away from the semiconductor body, wherein the gate conductive layer fills the trimmed conductive contact hole to achieve electrical connection with the gate; and the source conductive layer fills the trimmed conductive contact hole to achieve electrical connection with the first region; After forming a conductive layer on a side of the first dielectric layer away from the semiconductor body, the method further comprises: A drain electrode is formed on the second surface.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: The semiconductor body provided includes: A silicon carbide semiconductor body is provided or a gallium nitride semiconductor body is provided.

13. A power module, characterized in that: It comprises a substrate and at least one semiconductor device as claimed in any one of claims 1 to 4, wherein the substrate is used for carrying the semiconductor device.

14. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device as claimed in claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

15. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 14, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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