Offset error calibration circuit and method

Abstract

The invention discloses an offset error calibration circuit and method, and relates to the field of integrated circuit design, and the circuit comprises an analog-to-digital conversion module which is used for responding to a trimming instruction, generating an analog signal and a channel control signal, and converting the analog signal to obtain a conversion result before trimming; the trimming register module is used for storing N groups of initial trimming data; the calibration value management module is used for selecting target trimming value data from a plurality of groups of initial trimming values stored in the trimming register module according to the channel control signal in the effective state and the calibration control signal and outputting the target trimming value data; the calibration module is used for performing calibration according to the conversion result and the target trimming value data; according to the method and the device, the problem that the mapping relation of the trimming value-ADC channel-to-be-calibrated module is remodified under the condition that a software main program is not modified is solved, the calibration efficiency can be improved, and the use complexity and cost are reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an offset error calibration circuit and method. Background Art

[0002] In the technical fields of analog-to-digital converters (ADCs), programmable gain amplifiers (PGAs), operational amplifiers (OPAs), and temperature sensors, accurate measurement and calibration are crucial. The performance of these devices is often affected by factors such as temperature and environment, resulting in offset errors. In order to ensure the accuracy and stability of the equipment, these errors need to be calibrated.

[0003] However, for different development board solutions, the module to be calibrated connected to the sampling channel of the ADC in the DSP is likely to change. However, the calibration values ​​in the DSP chip can only be stored in a fixed area to store the calibration values ​​of the fixed calibration module. When the ADC channel corresponding to the module to be calibrated changes, the calibration value stored in the chip cannot be used.

[0004] The current solutions of the existing technology are as follows: When the module to be calibrated is not integrated in the DSP chip. In the existing technology, a common solution is to re-establish the mapping relationship between different modules to be calibrated and different calibration values ​​by modifying the program through software. The disadvantage of this method is that it takes up software resources and takes time to process the calibration process. Moreover, the more modules that need to be calibrated, the longer the software takes. When the application solution needs to meet high-speed scenarios, this method is simply impossible to meet the requirements. The advantage of this method is that when the hardware does not support the automatic calibration function, the application developer can write the corresponding program to implement the calibration as needed.

[0005] When all modules to be calibrated are integrated in the DSP chip, the DSP can establish a fixed mapping relationship of "adjustment value-ADC channel-module to be calibrated" according to the connection relationship between its own module to be calibrated and the ADC sampling channel, as well as the storage location of the calibration value. When this fixed mapping relationship needs to be changed due to some practical reasons, once the DSP is made, this mapping relationship cannot be changed. The mapping relationship of "adjustment value-ADC channel-module to be calibrated" can only be modified by modifying the software.

[0006] Therefore, the prior art has the following problems to be solved urgently: (1) How to modify the mapping relationship between “adjustment value-ADC channel-module to be calibrated” without modifying the main software program; (2) How to eliminate the problem of offset errors that cannot be calibrated due to different board-level solutions in a simple and easy way during use; (3) How to achieve universal calibration for different types of equipment and reduce the complexity and cost of use.

[0007] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims of this application and are not admitted to be prior art by inclusion in this section. Summary of the invention

[0008] In view of the above technical problems in the related art, the present invention provides an offset error calibration circuit and method.

[0009] In order to achieve the above-mentioned invention object, the present invention adopts the following technical scheme: In a first aspect, the present invention provides an offset error calibration circuit, including an analog-to-digital conversion module, a trimming register module, a calibration value management module, and a calibration module: An analog-to-digital conversion module, used for outputting a conversion result; the analog-to-digital conversion module has N conversion channels; A trimming storage module, used for storing N groups of initial trimming data; A calibration value management module is connected to the analog-to-digital conversion module and the trimming register module respectively, and is used to receive N channel control signals, and select target trimming value data from the trimming register module according to the channel control signals and output them to the calibration module; the state of the channel control signal includes a valid state and an invalid state, and only one of the N channel control signals is in a valid state, and the rest are in an invalid state; The calibration module is connected to the analog-to-digital conversion module and the calibration value management module respectively, and is used to perform calibration according to the conversion result and the target adjustment value data to obtain calibration data.

[0010] Specifically, the calibration value management module includes a calibration control register, N logic decoding units, N decoding selectors and N channel selectors; the logic decoding unit is connected to the calibration control register and the decoding selector, and is used to convert the value of the calibration control register into a calibration control signal; the decoding selector controls the opening and closing of the switch in the decoding signal control end to select the channel control signal output in the valid state according to the calibration control signal output by the logic decoding unit connected to it; the channel selector has a channel selection output end, a channel selection input end and a channel signal control end, the channel selection input end is used to connect with the sub-register in the trimming register module, the channel signal control end is connected to the decoding selector, and the channel selection output end is connected to the calibration module, and is used for when a certain channel control signal is in a valid state and the signal end of the channel signal control end corresponding to the channel selector is in a valid state, at this time, the initial trimming data of the sub-register in the trimming register connected to the channel selection input end of the channel selector is used as the target trimming data; the signal end state of the channel signal control end includes a valid state and an invalid state.

[0011] Specifically, the trimming register module includes: an ADC+PGA trimming register, used to store ADC+PGA initial trimming data; an ADC+OPA trimming register, used to store ADC+OPA initial trimming data; an ADC+temperature sensor trimming register, used to store ADC+temperature sensor initial trimming data; and an ADC own trimming register, used to store ADC own initial trimming data.

[0012] Specifically, the calibration control register is an 8-bit register; the logic decoding unit is a 2-4 decoder; the calibration value management module includes a first logic decoding unit, a second logic decoding unit, a third logic decoding unit and a fourth logic decoding unit; bit [7:6] of the calibration control register corresponds to bit [1:0] of the fourth logic decoding unit; bit [5:4] of the calibration control register corresponds to bit [1:0] of the third logic decoding unit; bit [3:2] of the calibration control register corresponds to bit [1:0] of the second logic decoding unit; bit [1:0] of the calibration control register corresponds to bit [1:0] of the first logic decoding unit.

[0013] Specifically, the decoding selector includes a first decoding signal control terminal, a second decoding signal control terminal, a third decoding signal control terminal and a fourth decoding signal control terminal; the calibration value management module includes a first channel selector, a second channel selector, a third channel selector and a fourth channel selector; The first channel selector is connected to the ADC+PGA trimming register; the second channel selector is connected to the ADC+OPA trimming register; the third channel selector is connected to the ADC+temperature sensor trimming register; and the fourth channel selector is connected to the ADC trimming register itself.

[0014] Specifically, the analog-to-digital conversion module is used to respond to the adjustment instruction, generate an analog signal and N channel control signals, and has N different conversion channels corresponding to the N channel control signals one by one. The conversion channel corresponding to the channel control signal in the valid state is used to access the analog signal, and the analog signal is converted to obtain the conversion result before adjustment.

[0015] Specifically, the analog-to-digital conversion module includes a built-in analog-to-digital converter, a programmable gain amplifier, an operational amplifier and a temperature sensor; N is a positive integer greater than or equal to 4; The analog-to-digital converter has a conversion result output terminal, a first analog-to-digital conversion input terminal, a second analog-to-digital conversion input terminal, a third analog-to-digital conversion input terminal and a fourth analog-to-digital conversion input terminal, and the conversion result output terminal is connected to the calibration module; The first analog-to-digital conversion input terminal is connected to a programmable gain amplifier, the second analog-to-digital conversion input terminal is connected to an operational amplifier, and the third analog-to-digital conversion input terminal is connected to a temperature sensor; Among them, the analog-to-digital converter and the programmable gain amplifier, the analog-to-digital converter and the operational amplifier, the analog-to-digital converter and the temperature sensor and the analog-to-digital converter itself constitute four conversion channels respectively; the channel control signals corresponding to the four conversion channels of the analog-to-digital converter and the programmable gain amplifier, the analog-to-digital converter and the operational amplifier, the analog-to-digital converter and the temperature sensor and the analog-to-digital converter itself are channel control signal 1, channel control signal 2, channel control signal 3 and channel control signal 4 respectively.

[0016] Specifically, the calibration control signal includes: "00", "01", "10" and "11"; When the channel control signal 1 is in a valid state and the first logic decoding unit inputs "00", the channel signal control terminal signal end of the first channel selector is in a valid state, and the channel signal control terminal switch end of the first channel selector is closed, and the ADC+PGA initial trimming data stored in the ADC+PGA trimming register is selected as the target trimming data; When the channel control signal 2 is in a valid state and the second logic decoding unit inputs "01", the channel signal control terminal signal end of the second channel selector is in a valid state, and the channel signal control terminal switch end of the second channel selector is closed, and the ADC+OPA initial trimming data stored in the ADC+OPA trimming register is selected as the target trimming data; When the channel control signal 3 is in a valid state and the third logic decoding unit inputs "10", the channel signal control terminal signal end of the third channel selector is in a valid state, and the channel signal control terminal switch end of the third channel selector is closed, and the ADC+temperature sensor initial trimming data stored in the ADC+temperature sensor trimming register is selected as the target trimming data; When the channel control signal 4 is in a valid state and the fourth logic decoding unit inputs "11", the channel signal control terminal signal end of the fourth channel selector is in a valid state, and the channel signal control terminal switch end of the fourth channel selector is closed. At this time, the ADC's own initial trimming data stored in the ADC's own trimming register is selected as the target trimming data.

[0017] Specifically, the calibration module includes an adding circuit and a trimmed result register; The adding circuit has a first adding input terminal, a second adding input terminal and an adding output terminal, the first adding input terminal is connected to the analog-to-digital conversion module, the second adding input terminal is connected to the output terminal of the calibration value management module, and the adding output terminal is used to output the calibration data after the conversion result before adjustment and the target adjustment data are added; The adjusted result register is connected to the output end of the adding circuit and is used to store calibration data.

[0018] Specifically, the value of the calibration control register is set to "11100100".

[0019] The present invention selects and outputs target trimming data from multiple groups of initial trimming data according to the channel control signal and the calibration control signal in the effective state through the calibration value management module, and then calibrates according to the conversion result and the target trimming data to obtain calibration data. The offset error calibration circuit of the embodiment of the present invention is calibrated in a full hardware manner, which can improve the calibration efficiency and reduce the complexity and cost of use.

[0020] In a second aspect, the present invention provides an offset error calibration method, based on the high-safety offset error calibration circuit described in any one of the first aspects, the method comprising the following steps: In response to the adjustment instruction, an analog signal and N channel control signals are generated; the states of the channel control signals include a valid state and an invalid state, one of the N channel control signals is in a valid state, and the rest are in an invalid state; Input the analog signal to the conversion channel corresponding to the channel control signal in the valid state to obtain a conversion result before adjustment, and the conversion result is used to output to the calibration module; According to the channel control signal of the effective state and the calibration control signal, the target trimming value data is selected from the multiple groups of initial trimming values ​​stored in the trimming register module through the calibration value management module; the calibration value management module includes a calibration control register, N decoding selectors, N channel selectors and N logic decoding units; the logic decoding unit is connected to the calibration control register and the decoding selector, and is used to convert the value of the calibration control register into a calibration control signal; the decoding selector controls the opening and closing of the switch in the decoding signal control end according to the calibration control signal output by the connected logic decoding unit to select the channel control of the effective state Signal output; the channel selector has a channel selection output terminal, a channel selection input terminal and a channel signal control terminal, the channel selection input terminal is used to connect with the sub-register in the trimming register module, the channel signal control terminal is connected to the decoding selector, and the channel selection output terminal is connected to the calibration module, and is used to use the initial trimming data of the sub-register in the trimming register connected to the channel selection input terminal of the channel selector as the target trimming data when a certain channel control signal is in a valid state and the signal terminal of the channel signal control terminal corresponding to the channel selector is in a valid state; the signal terminal state of the channel signal control terminal includes a valid state and an invalid state; Calibration is performed according to the conversion result and the target adjustment value data to obtain calibration data.

[0021] In a third aspect, the present invention provides an offset error calibration device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the offset error calibration method as described in the above-mentioned second aspect embodiment is implemented.

[0022] In a fourth aspect, the present invention provides a readable storage medium for offset error calibration, storing computer executable instructions, wherein the computer executable instructions are used to execute the offset error calibration method as described in the embodiment of the second aspect above.

[0023] Compared with the prior art, the present invention has the following beneficial effects: 1. Strong flexibility: The present invention can flexibly bind the selection bit of the calibration data and the selection bit of the ADC channel, and automatically select different calibration data according to actual needs, thereby improving the flexibility and efficiency of calibration.

[0024] 2. Comprehensiveness: The present invention can not only calibrate ADC+PGA, ADC+OPA, ADC+temperature sensor, but also calibrate the offset error of modules such as the ADC itself, thereby achieving more comprehensive calibration.

[0025] 3. Strong adaptability: The present invention is not only applicable to DSPs with built-in PGA, OPA, temperature sensor and ADC, but also to DSPs with external modules to be calibrated to eliminate offset errors through software programs. It has strong adaptability (with complete hardware resources, customers can also calibrate through software according to their own needs).

[0026] 4. Simplified operation: The present invention can conveniently perform offset error calibration of different modules by designing a programmable calibration control register without complicated operations, which greatly simplifies the operation process.

[0027] 5. Reduce costs: The present invention can not only reduce additional offset errors caused by errors, environment and other factors, but also avoid the need to redesign and adjust the main program due to different types of development boards, thereby reducing the complexity and cost of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 is a schematic diagram of an offset error calibration circuit provided according to an embodiment of the present invention; Figure 2 1 is a schematic diagram of a specific structure of an offset error calibration circuit provided according to an embodiment of the present invention; Figure 3 is a schematic diagram of an offset error calibration method provided according to an embodiment of the present invention; Among them, I1 is the analog-to-digital conversion module, I2 is the adjustment register module, I3 is the calibration value management module, I4 is the addition circuit, and I5 is the adjusted result register. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0031] In the description of the present invention, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0032] In the description of the present invention, it should be understood that descriptions involving orientation, such as orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0033] In the description of the present invention, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0034] Embodiment 1.

[0035] refer to Figure 1-2 The present embodiment provides an offset error calibration circuit, an offset error calibration circuit, comprising an analog-to-digital conversion module I1, a trimming register module I2, a calibration value management module I3 and a calibration module: The analog-to-digital conversion module I1 is used to output the conversion result; the analog-to-digital conversion module has N conversion channels; Specifically, the analog-to-digital conversion module I1 is used to respond to the adjustment instruction, generate an analog signal and N channel control signals, and has N different conversion channels corresponding to the N channel control signals one by one. The conversion channel corresponding to the channel control signal in the valid state is used to access the analog signal, and the analog signal is converted to obtain the conversion result before the adjustment; the state of the channel control signal includes a valid state and an invalid state, one of the N channel control signals is in a valid state, and the rest are in an invalid state; N is a positive integer greater than or equal to 4. Preferably, the value of N in this embodiment is 4; refer to Figure 2 The analog-to-digital conversion module includes a built-in analog-to-digital converter, a programmable gain amplifier, an operational amplifier and a temperature sensor.

[0036] The analog-to-digital converter has a conversion result output terminal, a first analog-to-digital conversion input terminal, a second analog-to-digital conversion input terminal, a third analog-to-digital conversion input terminal and a fourth analog-to-digital conversion input terminal, and the conversion result output terminal is connected to the calibration module; The first analog-to-digital conversion input terminal is connected to a programmable gain amplifier, the second analog-to-digital conversion input terminal is connected to an operational amplifier, and the third analog-to-digital conversion input terminal is connected to a temperature sensor; Among them, the analog-to-digital converter and the programmable gain amplifier, the analog-to-digital converter and the operational amplifier, the analog-to-digital converter and the temperature sensor and the analog-to-digital converter itself constitute four conversion channels respectively.

[0037] It is understandable that the Programmable Gain Amplifier (PGA), Operational Amplifier (OPA) and temperature sensor are all at the front end of the Analog to Digital Converter (ADC), and their output values ​​are sent to the ADC for sampling and quantization into digital codes. The performance of these devices is often affected by factors such as temperature and environment, resulting in offset errors. In order to ensure the accuracy and stability of the equipment, these errors need to be calibrated.

[0038] The channel control signal is given by the digital core of the DSP (Digital Signal Processor). The channel control signal controls which module's signal is sent to the ADC, and also controls which group of trimming values ​​are sent to the adder. The two must correspond one to one in order to complete the trimming function of the corresponding trimming value and the corresponding module.

[0039] In some embodiments of the present invention, the channel control signals corresponding to the four conversion channels of the analog-to-digital converter and programmable gain amplifier, the analog-to-digital converter and operational amplifier, the analog-to-digital converter and temperature sensor, and the analog-to-digital converter itself are channel control signal 1, channel control signal 2, channel control signal 3, and channel control signal 4, respectively.

[0040] If the conversion results of the analog-to-digital converter and the programmable gain amplifier need to be calibrated, the output channel control signal 1 is in a valid state, and the other channel control signals are in an invalid state. At this time, the analog signal will be connected to the input end of the programmable gain amplifier; if the conversion results of the analog-to-digital converter and the operational amplifier need to be calibrated, the output channel control signal 2 is in a valid state, and the other channel control signals are in an invalid state. At this time, the analog signal will be connected to the input end of the operational amplifier; if the conversion results of the analog-to-digital converter and the temperature sensor need to be calibrated, the output channel control signal 3 is in a valid state, and the other channel control signals are in an invalid state. At this time, the analog signal will be connected to the input end of the temperature sensor; if the conversion results of the analog-to-digital converter itself need to be calibrated, the output channel control signal 4 is in a valid state, and the other channel control signals are in an invalid state. At this time, the analog signal will be connected to the input end of the analog-to-digital converter itself; If the conversion results of the analog-to-digital converter and the programmable gain amplifier need to be calibrated, the output channel control signal 1 is high, and the channel control signal 2, the channel control signal 3 and the channel control signal 4 are all low. At this time, the analog signal will be connected to the input end of the programmable gain amplifier; if the conversion results of the analog-to-digital converter and the operational amplifier need to be calibrated, the output channel control signal 2 is high, and the channel control signal 1, the channel control signal 3 and the channel control signal 4 are all low. At this time, the analog signal will be connected to the input end of the operational amplifier; if the conversion results of the analog-to-digital converter and the temperature sensor need to be calibrated, the output channel control signal 3 is high, and the channel control signal 1, the channel control signal 2 and the channel control signal 4 are all low. At this time, the analog signal will be connected to the input end of the temperature sensor; if the conversion result of the analog-to-digital converter itself needs to be calibrated, the output channel control signal 4 is high, and the channel control signal 1, the channel control signal 2 and the channel control signal 3 are all low. At this time, the analog signal will be connected to the input end of the analog-to-digital converter itself; When the channel control signal is at a low level, it indicates an invalid state, and when the channel control signal is at a high level, it indicates a valid state.

[0041] The analog-to-digital converter described in this example is an 8-bit ADC with 4 input channels; this example does not limit the specific specifications of the analog-to-digital converter, and analog-to-digital converters with different bit numbers can be selected according to specific needs, and can also be 16-bit, 24-bit, or 32-bit. The number of analog signals, conversion channels, and channel control signals also increases and corresponds accordingly according to the number of bits of the analog-to-digital converter.

[0042] The embodiment of the present invention establishes a one-to-one correspondence between the module to be calibrated (including a programmable gain amplifier, an operational amplifier, a temperature sensor and the analog-to-digital converter itself) and the input channel of the analog-to-digital converter to obtain multiple conversion channels, and then selects and outputs the adjustment data of a certain module to be calibrated through the channel control signal of the conversion channel. When the analog-to-digital converter switches the input channel, the channel control signal will also change accordingly. Therefore, this process can be automatically operated without any human intervention. The embodiment of the present invention can automatically select different adjustment data according to actual needs by flexibly binding the selection bit of the adjustment data and the selection bit of the conversion channel, thereby improving the flexibility and efficiency of calibration.

[0043] The trimming storage module I2 is used to store N groups of initial trimming data; The trimming register module I2 includes N sub-registers, where N is a multiple of 4; each sub-register is used to store the trimming data corresponding to each conversion channel, and the number of N is determined by the number of channel control signals; The trimming register module I2 described in this embodiment includes 4 sub-registers, including: an ADC+PGA trimming register, used to store ADC+PGA initial trimming data; an ADC+OPA trimming register, used to store ADC+OPA initial trimming data; an ADC+temperature sensor trimming register, used to store ADC+temperature sensor initial trimming data; and an ADC own trimming register, used to store ADC own initial trimming data, storing a total of 4 groups of 8-bit width initial trimming data.

[0044] In this embodiment, the specific model of the sub-register is not limited, and all registers that can store and output 8-bit initial trimming data are protected.

[0045] The calibration value management module I3 is connected to the analog-to-digital conversion module I1 and the trimming register module I2, respectively, and is used to select and output target trimming value data from multiple groups of initial trimming values ​​stored in the trimming register module I2 according to the channel control signal in the effective state and the calibration control signal; The calibration value management module I3 includes a calibration control register, N logic decoding units, N decoding selectors and N channel selectors; A decoding selector, having a decoding selection output terminal and a plurality of decoding signal control terminals, wherein the plurality of decoding selection control terminals are used to input N channel control signals in a one-to-one correspondence, and are used to control the opening and closing of switches in the decoding signal control terminals to select the channel control signal output of a valid state according to the calibration control signal output by the connected logic decoding unit; The logic decoding unit is connected to the calibration control register and the decoding selector, and the logic decoding unit converts the value of the calibration control register into a calibration control signal of the decoding selection control terminal and then selects a channel control signal from N channel control signals for output; the number of the decoding signal control terminals is the same as the number of bits of the logic decoding unit; A channel selector having a channel selection output terminal, a channel selection input terminal and a channel signal control terminal, wherein the channel selection input terminal is used to be connected to a sub-register in the trimming register module I2, the channel signal control terminal is connected to the decoding selector, and the channel selection output terminal is connected to the calibration module, and is used to use the initial trimming data of the sub-register in the trimming register connected to the channel selection input terminal of the channel selector as the target trimming data when a certain channel control signal is in a valid state and the signal terminal of the channel signal control terminal corresponding to the channel selector is in a valid state; In a possible implementation, the calibration control register is an 8-bit register; the calibration value management module I3 includes four logic decoding units, a first logic decoding unit, a second logic decoding unit, a third logic decoding unit and a fourth logic decoding unit; the logic decoding unit is a 2-4 decoder; A logic decoding unit, also called a decoder, is a combinational logic circuit that converts an input code into a specific output signal. A 2-4 logic decoding unit has 2 inputs and 4 outputs.

[0046] The working principle of the 2-4 logic decoding unit is that according to the 2-bit binary code input, it will produce a high level on one of the 4 outputs, while the other outputs remain low. This means that for any given input combination, only one output signal is active.

[0047] Therefore, in this embodiment, the logic decoding unit has four decoding output signals, including a first decoding output signal, a second decoding output signal, a third decoding output signal and a fourth decoding output signal. The output signal states include a valid state and an invalid state. When one of the output signals is in a valid state, the other output signals are in an invalid state.

[0048] When the decoding output signal is at a low level, it indicates an invalid state, and when the decoding output signal is at a high level, it indicates a valid state.

[0049] Set bit[7:6] of the calibration control register to bit[1:0] of the fourth logic decoding unit; set bit[5:4] of the calibration control register to bit[1:0] of the third logic decoding unit; set bit[3:2] of the calibration control register to bit[1:0] of the second logic decoding unit; set bit[1:0] of the calibration control register to bit[1:0] of the first logic decoding unit.

[0050] The calibration value management module I3 includes four decoding selectors; the decoding selectors include four decoding signal control terminals, and the decoding selectors control the opening and closing of a switch in the decoding signal control terminal according to the calibration control signal output by the connected logic decoding unit and the channel control signal in the valid state.

[0051] In this embodiment, the calibration control signal includes: "00", "01", "10" and "11"; The decoding signal control end includes a signal end and a switch end, and can control the opening and closing of the switch end according to the high / low level of the signal input to the signal end. All logic circuits or components that can realize the above functions are protected.

[0052] The decoding signal control terminal in this example may be composed of an internal logic circuit of an integrated circuit chip, or may be an external discrete device, such as a relay; preferably, the decoding signal control terminal in this embodiment is a relay.

[0053] Specifically, the decoding selector includes a first decoding signal control terminal, a second decoding signal control terminal, a third decoding signal control terminal and a fourth decoding signal control terminal; when the first decoding output signal is in a valid state, the switch terminal of the first decoding signal control terminal is closed; when the second decoding output signal is in a valid state, the switch terminal of the second decoding signal control terminal is closed; when the third decoding output signal is in a valid state, the switch terminal of the third decoding signal control terminal is closed; when the fourth decoding output signal is in a valid state, the switch terminal of the fourth decoding signal control terminal is closed.

[0054] When the calibration control signal input to the signal terminal of the first decoding signal control terminal is "00", the switch terminal of the first decoding signal control terminal is closed, and the other decoding signal control terminals are opened, and the decoding selection output terminal outputs the channel control signal 1; When the calibration control signal input to the signal terminal of the second decoding signal control terminal is "01", the switch terminal of the second decoding signal control terminal is closed, and the other decoding signal control terminals are opened, and the decoding selection output terminal outputs the channel control signal 2; When the calibration control signal input to the signal terminal of the third decoding signal control terminal is "10", the switch terminal of the third decoding signal control terminal is closed, and the other decoding signal control terminals are opened. At this time, the decoding selection output terminal outputs the channel control signal 3; When the calibration control signal input to the signal terminal of the fourth decoding signal control terminal is "11", the switch terminal of the fourth decoding signal control terminal is closed, and the other decoding signal control terminals are opened, and the decoding selection output terminal outputs the channel control signal 4; The signal terminal state of the channel signal control terminal includes a valid state and an invalid state; The state of the signal end of the channel signal control end corresponds to the open and closed state of the decoding signal control end. When the signal end of the channel signal control end is in a valid state, the corresponding decoding control signal end is in a closed state; when the signal end of the channel signal control end is in an invalid state, the corresponding decoding control signal end is in an open state. When the channel control signal is at a low level, it indicates an invalid state, and when the channel control signal is at a high level, it indicates a valid state.

[0055] The channel signal control end includes a signal end and a switch end, and the opening and closing of the switch end can be controlled according to the high / low level of the signal input signal at the signal end. All logic circuits or components that can realize the above functions are protected.

[0056] The channel signal control terminal in this example may be composed of an internal logic circuit of an integrated circuit chip, or may be an external discrete device, such as a relay; preferably, the channel signal control terminal in this embodiment is a relay.

[0057] The calibration value management module I3 includes four channel selectors, namely the first channel selector, the second channel selector, the third channel selector and the fourth channel selector; the channel signal control end of each channel selector is connected to the output of a decoding selector in a one-to-one correspondence; each channel selection input end is connected to a sub-register in the adjustment register module I2 in a one-to-one correspondence.

[0058] When a channel control signal is in a valid state and the channel signal control terminal of the corresponding channel selector is in a valid state, the switch terminal of the channel signal control terminal of the channel selector is closed, and at this time, the initial trimming data of the sub-register in the trimming register module I2 connected to the channel selection input terminal of the channel selector is used as the target trimming data; Specifically, in this embodiment, the first channel selector is connected to the ADC+PGA trimming register; the second channel selector is connected to the ADC+OPA trimming register; the third channel selector is connected to the ADC+temperature sensor trimming register I2; and the fourth channel selector is connected to the ADC's own trimming register.

[0059] In order to effectively control the different channel selectors to receive the target adjustment data of different modules to be calibrated by combining the calibration control register with the channel control signal, the value of the calibration control register is preferably set to "11100100" in this example; When the channel control signal 1 is in a valid state and the first logic decoding unit inputs "00", the channel signal control terminal signal end of the first channel selector is in a valid state, and the channel signal control terminal switch end of the first channel selector is closed, and the ADC+PGA initial trimming data stored in the ADC+PGA trimming register is selected as the target trimming data; When the channel control signal 2 is in a valid state and the second logic decoding unit inputs "01", the channel signal control terminal signal end of the second channel selector is in a valid state, and the channel signal control terminal switch end of the second channel selector is closed, and the ADC+OPA initial trimming data stored in the ADC+OPA trimming register is selected as the target trimming data; When the channel control signal 3 is in a valid state and the third logic decoding unit inputs "10", the channel signal control terminal signal end of the third channel selector is in a valid state, and the channel signal control terminal switch end of the third channel selector is closed, and the ADC+temperature sensor initial trimming data stored in the ADC+temperature sensor trimming register is selected as the target trimming data; When the channel control signal 4 is in a valid state and the fourth logic decoding unit inputs "11", the channel signal control terminal of the fourth channel selector is in a valid state, and the channel signal control terminal switch terminal of the fourth channel selector is closed, and the ADC initial trimming data stored in the trimming register of the ADC itself is selected as the target trimming data; It can be understood that in another possible implementation, the calibration control register can be 16 bits, 24 bits, 32 bits, etc., and the value of the bit number of the calibration control register can vary according to the number of channel control signals, which is not specifically limited here.

[0060] A calibration module, connected to the analog-to-digital conversion module I1 and the calibration value management module I3, respectively, for performing calibration according to the conversion result and the target adjustment value data to obtain calibration data; The calibration module includes an adding circuit I4 and a trimmed result register I5; The adding circuit I4 has a first adding input terminal, a second adding input terminal and an adding output terminal, the first adding input terminal is connected to the analog-to-digital conversion module I1, the second adding input terminal is connected to the output terminal of the calibration value management module I3, and the adding output terminal is used to output the calibration data after the conversion result before adjustment and the target adjustment data are added; The adjusted result register I5 is connected to the output end of the adding circuit I4 and is used to store calibration data.

[0061] The calibration data is equal to the result of adding the conversion result and the target trimming data. It should be noted that the working principle of the adding circuit is a prior art known to those skilled in the art and will not be described in detail here.

[0062] It should be noted that the embodiments of the present invention are not only applicable to digital signal processing of programmable gain amplifiers, operational amplifiers, temperature sensors and analog-to-digital converters themselves, but also to the technology of eliminating offset errors through software programs, and have strong adaptability (with complete hardware resources, software calibration can also be selected according to needs). In addition, the embodiments of the present invention only exemplify some amplifiers and sensors, and the output data of other amplifiers and sensors can also be calibrated, which cannot be regarded as a limitation of the present invention.

[0063] The offset error calibration circuit of the embodiment of the present invention only needs to design a programmable conversion channel to conveniently calibrate the module to be calibrated without complicated operations, thus greatly simplifying the operation process.

[0064] In addition, it should be noted that the data streams in the embodiments of the present invention are all expressed in the form of a bus. Taking 8 bits as an example, an 8-bit bus actually consists of 8 lines.

[0065] The calibration value management module can select and output target trimming data from multiple sets of initial trimming data according to the channel control signal in the effective state and the calibration control signal, and then calibrate to obtain calibration data according to the conversion result and the target trimming data. The offset error calibration circuit of the embodiment of the present invention is calibrated in a full hardware manner, which can improve calibration efficiency and reduce complexity and cost of use.

[0066] Embodiment 2.

[0067] refer to Figure 3 This embodiment provides an offset error calibration method, which is applied to the offset error calibration circuit of the first aspect embodiment, including: In response to the adjustment instruction, an analog signal and N channel control signals are generated; the states of the channel control signals include a valid state and an invalid state, one of the N channel control signals is in a valid state, and the rest are in an invalid state; In some embodiments of the present invention, the channel control signals corresponding to the four conversion channels of the analog-to-digital converter and programmable gain amplifier, the analog-to-digital converter and operational amplifier, the analog-to-digital converter and temperature sensor, and the analog-to-digital converter itself are channel control signal 1, channel control signal 2, channel control signal 3, and channel control signal 4, respectively.

[0068] If the conversion results of the analog-to-digital converter and the programmable gain amplifier need to be calibrated, the output channel control signal 1 is in a valid state, and the other channel control signals are in an invalid state. At this time, the analog signal will be connected to the input end of the programmable gain amplifier; if the conversion results of the analog-to-digital converter and the operational amplifier need to be calibrated, the output channel control signal 2 is in a valid state, and the other channel control signals are in an invalid state. At this time, the analog signal will be connected to the input end of the operational amplifier; if the conversion results of the analog-to-digital converter and the temperature sensor need to be calibrated, the output channel control signal 3 is in a valid state, and the other channel control signals are in an invalid state. At this time, the analog signal will be connected to the input end of the temperature sensor; if the conversion results of the analog-to-digital converter itself need to be calibrated, the output channel control signal 4 is in a valid state, and the other channel control signals are in an invalid state. At this time, the analog signal will be connected to the input end of the analog-to-digital converter itself; If the conversion results of the analog-to-digital converter and the programmable gain amplifier need to be calibrated, the output channel control signal 1 is high, and the channel control signal 2, the channel control signal 3 and the channel control signal 4 are all low. At this time, the analog signal will be connected to the input end of the programmable gain amplifier; if the conversion results of the analog-to-digital converter and the operational amplifier need to be calibrated, the output channel control signal 2 is high, and the channel control signal 1, the channel control signal 3 and the channel control signal 4 are all low. At this time, the analog signal will be connected to the input end of the operational amplifier; if the conversion results of the analog-to-digital converter and the temperature sensor need to be calibrated, the output channel control signal 3 is high, and the channel control signal 1, the channel control signal 2 and the channel control signal 4 are all low. At this time, the analog signal will be connected to the input end of the temperature sensor; if the conversion result of the analog-to-digital converter itself needs to be calibrated, the output channel control signal 4 is high, and the channel control signal 1, the channel control signal 2 and the channel control signal 3 are all low. At this time, the analog signal will be connected to the input end of the analog-to-digital converter itself; When the channel control signal is at a low level, it indicates an invalid state, and when the channel control signal is at a high level, it indicates a valid state.

[0069] Input the analog signal to the conversion channel corresponding to the channel control signal in the valid state to obtain a conversion result before adjustment, and the conversion result is used to output to the calibration module; Selecting target trimming value data from multiple groups of initial trimming values ​​stored in the trimming register module I2 through the calibration value management module I3 according to the channel control signal and the calibration control signal in the effective state; The calibration value management module I3 includes a calibration control register, N decoding selectors, N channel selectors and N logic decoding units; the logic decoding unit is connected to the calibration control register and the decoding selector, and is used to convert the value of the calibration control register into a calibration control signal; the decoding selector controls the opening and closing of the switch in the decoding signal control end to select the channel control signal output of the valid state according to the calibration control signal output by the logic decoding unit connected to it; the channel selector has a channel selection output end, a channel selection input end and a channel signal control end, the channel selection input end is used to connect with the sub-register in the trimming register module I2, the channel signal control end is connected to the decoding selector, and the channel selection output end is connected to the calibration module, and is used when a certain channel control signal is in a valid state and the signal end of the channel signal control end of the corresponding channel selector is in a valid state, at this time, the initial trimming data of the sub-register in the trimming register connected to the channel selection input end of the channel selector is used as the target trimming data; the signal end state of the channel signal control end includes a valid state and an invalid state; The calibration control signal includes: “00”, “01”, “10” and “11”.

[0070] When a channel control signal is in a valid state and the channel signal control terminal of the corresponding channel selector is in a valid state, the switch terminal of the channel signal control terminal of the channel selector is closed, and at this time, the initial trimming data of the sub-register in the trimming register module I2 connected to the channel selection input terminal of the channel selector is used as the target trimming data; The target adjustment data is obtained through the following steps: When the channel control signal 1 is in a valid state and the first logic decoding unit inputs "00", the ADC+PGA initial trimming data is used as the target trimming data; When the channel control signal 2 is in a valid state and the second logic decoding unit inputs "01", the ADC+OPA initial trimming data is used as the target trimming data; When the channel control signal 3 is in a valid state and the third logic decoding unit inputs "10", the ADC+temperature sensor initial trimming data is used as the target trimming data; When the channel control signal 4 is in a valid state and the fourth logic decoding unit inputs "11", the initial trimming data of the ADC itself is used as the target trimming data; Calibrate according to the conversion result and the target adjustment value data to obtain calibration data; In some embodiments of the present invention, the calibration data is obtained by the following steps: Get conversion results and target adjustment data; Add the conversion result and the target trim data to obtain the calibration data.

[0071] It should be noted that the working principle of the adding circuit I4 is a prior art known to those skilled in the art and will not be described in detail herein.

[0072] The offset error calibration circuit and method described in this embodiment are applicable to DSPs using built-in or external PGA, OPA, temperature sensor and ADC. These devices can complete the calibration of all data before leaving the factory (DSPs with built-in modules to be calibrated can write corresponding calibration data to the storage area before leaving the factory) or after leaving the factory (DSPs with external modules to be calibrated can have the customer write corresponding calibration data to the storage area after leaving the factory according to batch test results).

[0073] A one-to-one correspondence is established between the module to be calibrated, the input channel of the ADC, and the trimming value, and then the trimming value of a module is sent to the calibration buffer register through the input channel selection signal of the ADC. When the ADC switches the input channel, the input channel selection signal will also change accordingly, so this process can be automated without any human intervention.

[0074] By using the calibration value management module I3 on ​​the DSP chip, the corresponding relationship between different ADC channels and trimming values ​​can be flexibly changed. Therefore, when the type of module to be calibrated connected to the ADC channel changes, it is only necessary to change the corresponding relationship between different ADC channels and trimming values ​​to re-establish the mapping relationship of "trimming value-ADC channel-module to be calibrated".

[0075] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: 1. Strong flexibility: This embodiment can automatically select different calibration data according to actual needs by flexibly binding the selection bit of the calibration data and the ADC channel selection bit (as shown in the I3 module), thereby improving the flexibility and efficiency of calibration.

[0076] 2. Comprehensiveness: This embodiment can not only calibrate ADC+PGA, ADC+OPA, ADC+temperature sensor, but also calibrate the offset error of modules such as the ADC itself, thereby achieving more comprehensive calibration.

[0077] 3. Strong adaptability: This embodiment is not only applicable to DSPs with built-in PGA, OPA, temperature sensor and ADC, but also to DSPs with external modules to be calibrated, which use software programs to eliminate offset errors. It has strong adaptability (with complete hardware resources, customers can also calibrate through software according to their own needs).

[0078] 4. Simplified operation: This embodiment designs a programmable calibration control register, which can conveniently perform offset error calibration of different modules without complicated operations, greatly simplifying the operation process.

[0079] 5. Reduce costs: This embodiment can not only reduce additional offset errors caused by errors, environment and other factors, but also avoid the need to redesign and adjust the main program due to different types of development boards, thereby reducing the complexity and cost of use.

[0080] In addition, an embodiment of the present invention further provides a control device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and the memory may be connected via a bus or other means.

[0081] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0082] The non-transient software program and instructions required to implement the offset error calibration method of the above embodiment are stored in the memory, and when executed by the processor, the offset error calibration method of the above embodiment is executed.

[0083] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0084] In addition, an embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by a processor or controller, for example, by the processor of the above embodiment, so that the above processor can execute the offset error calibration method in the above embodiment.

[0085] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as a microprocessor, such as a central processing unit, a digital signal processor, or software executed by a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An offset error calibration circuit, characterized in that: Including analog-to-digital conversion module, adjustment register module, calibration value management module and calibration module: An analog-to-digital conversion module, used for outputting a conversion result; the analog-to-digital conversion module has N conversion channels; A trimming storage module, used for storing N groups of initial trimming data; A calibration value management module is connected to the analog-to-digital conversion module and the trimming register module respectively, and is used to receive N channel control signals, and select target trimming value data from the trimming register module according to the channel control signals and output them to the calibration module; the state of the channel control signal includes a valid state and an invalid state, and only one of the N channel control signals is in a valid state, and the rest are in an invalid state; The calibration module is connected to the analog-to-digital conversion module and the calibration value management module respectively, and is used to perform calibration according to the conversion result and the target adjustment value data to obtain calibration data.

2. The offset error calibration circuit according to claim 1, characterized in that , The calibration value management module includes a calibration control register, N logic decoding units, N decoding selectors and N channel selectors; the logic decoding unit is connected to the calibration control register and the decoding selector, and is used to convert the value of the calibration control register into a calibration control signal; the decoding selector controls the opening and closing of the switch in the decoding signal control end to select the channel control signal output in the valid state according to the calibration control signal output by the logic decoding unit connected to it; the channel selector has a channel selection output end, a channel selection input end and a channel signal control end, the channel selection input end is used to connect with the sub-register in the trimming register module, the channel signal control end is connected to the decoding selector, and the channel selection output end is connected to the calibration module, and is used for when a certain channel control signal is in a valid state and the signal end of the channel signal control end corresponding to the channel selector is in a valid state, at this time, the initial trimming data of the sub-register in the trimming register connected to the channel selection input end of the channel selector is used as the target trimming data; the signal end state of the channel signal control end includes a valid state and an invalid state.

3. The offset error calibration circuit according to claim 2, characterized in that: The trimming register module includes: an ADC+PGA trimming register for storing ADC+PGA initial trimming data; an ADC+OPA trimming register for storing ADC+OPA initial trimming data; an ADC+temperature sensor trimming register for storing ADC+temperature sensor initial trimming data; and an ADC own trimming register for storing ADC own initial trimming data.

4. The offset error calibration circuit according to claim 3, characterized in that: The calibration control register is an 8-bit register; the logic decoding unit is a 2-4 decoder; the calibration value management module includes a first logic decoding unit, a second logic decoding unit, a third logic decoding unit and a fourth logic decoding unit; bit [7:6] of the calibration control register corresponds to bit [1:0] of the fourth logic decoding unit; bit [5:4] of the calibration control register corresponds to bit [1:0] of the third logic decoding unit; bit [3:2] of the calibration control register corresponds to bit [1:0] of the second logic decoding unit; bit [1:0] of the calibration control register corresponds to bit [1:0] of the first logic decoding unit.

5. The offset error calibration circuit according to claim 4, characterized in that: The decoding selector includes a first decoding signal control terminal, a second decoding signal control terminal, a third decoding signal control terminal and a fourth decoding signal control terminal; the calibration value management module includes a first channel selector, a second channel selector, a third channel selector and a fourth channel selector; The first channel selector is connected to the ADC+PGA trimming register; the second channel selector is connected to the ADC+OPA trimming register; the third channel selector is connected to the ADC+temperature sensor trimming register; and the fourth channel selector is connected to the ADC trimming register itself.

6. The offset error calibration circuit according to claim 1, characterized in that: The analog-to-digital conversion module is used to respond to the adjustment instruction, generate an analog signal and N channel control signals, and has N different conversion channels corresponding to the N channel control signals one by one. The conversion channel corresponding to the channel control signal in the valid state is used to access the analog signal, and the analog signal is converted to obtain the conversion result before adjustment.

7. The offset error calibration circuit according to claim 1, characterized in that: The analog-to-digital conversion module includes a built-in analog-to-digital converter, a programmable gain amplifier, an operational amplifier and a temperature sensor; N is a positive integer greater than or equal to 4; The analog-to-digital converter has a conversion result output terminal, a first analog-to-digital conversion input terminal, a second analog-to-digital conversion input terminal, a third analog-to-digital conversion input terminal and a fourth analog-to-digital conversion input terminal, and the conversion result output terminal is connected to the calibration module; The first analog-to-digital conversion input terminal is connected to a programmable gain amplifier, the second analog-to-digital conversion input terminal is connected to an operational amplifier, and the third analog-to-digital conversion input terminal is connected to a temperature sensor; Among them, the analog-to-digital converter and the programmable gain amplifier, the analog-to-digital converter and the operational amplifier, the analog-to-digital converter and the temperature sensor and the analog-to-digital converter itself constitute four conversion channels respectively; the channel control signals corresponding to the four conversion channels of the analog-to-digital converter and the programmable gain amplifier, the analog-to-digital converter and the operational amplifier, the analog-to-digital converter and the temperature sensor and the analog-to-digital converter itself are channel control signal 1, channel control signal 2, channel control signal 3 and channel control signal 4 respectively.

8. The offset error calibration circuit according to claim 5, characterized in that: The calibration control signal includes: "00", "01", "10" and "11"; When the channel control signal 1 is in a valid state and the first logic decoding unit inputs "00", the channel signal control terminal signal end of the first channel selector is in a valid state, and the channel signal control terminal switch end of the first channel selector is closed, and the ADC+PGA initial trimming data stored in the ADC+PGA trimming register is selected as the target trimming data; When the channel control signal 2 is in a valid state and the second logic decoding unit inputs "01", the channel signal control terminal signal end of the second channel selector is in a valid state, and the channel signal control terminal switch end of the second channel selector is closed. At this time, the ADC+OPA initial trimming data stored in the ADC+OPA trimming register is selected as the target trimming data; When the channel control signal 3 is in a valid state and the third logic decoding unit inputs "10", the channel signal control terminal signal end of the third channel selector is in a valid state, and the channel signal control terminal switch end of the third channel selector is closed, and the ADC+temperature sensor initial trimming data stored in the ADC+temperature sensor trimming register is selected as the target trimming data; When the channel control signal 4 is in a valid state and the fourth logic decoding unit inputs "11", the channel signal control terminal signal end of the fourth channel selector is in a valid state, and the channel signal control terminal switch end of the fourth channel selector is closed. At this time, the ADC's own initial trimming data stored in the ADC's own trimming register is selected as the target trimming data.

9. The offset error calibration circuit according to claim 1, characterized in that: The calibration module includes an adding circuit and a trimmed result register; The adding circuit has a first adding input terminal, a second adding input terminal and an adding output terminal, the first adding input terminal is connected to the analog-to-digital conversion module, the second adding input terminal is connected to the output terminal of the calibration value management module, and the adding output terminal is used to output the calibration data after the conversion result before adjustment and the target adjustment data are added; The adjusted result register is connected to the output end of the adding circuit and is used to store calibration data.

10. An offset error calibration method, based on the offset error calibration circuit according to any one of claims 1 to 9, characterized in that: The method comprises the following steps: In response to the adjustment instruction, an analog signal and N channel control signals are generated; the states of the channel control signals include a valid state and an invalid state, and only one of the N channel control signals is in a valid state, and the rest are in an invalid state; Input the analog signal to the conversion channel corresponding to the channel control signal in the valid state to obtain a conversion result before adjustment, and the conversion result is used to output to the calibration module; Selecting target trimming value data from a plurality of groups of initial trimming values ​​stored in a trimming register module through a calibration value management module according to a channel control signal and a calibration control signal in a valid state; Calibration is performed according to the conversion result and the target adjustment value data to obtain calibration data.

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