Deep trench manufacturing method, semiconductor structure, chip and circuit

Abstract

The invention provides a deep trench manufacturing method, a semiconductor structure, a chip and a circuit, and relates to the technical field of semiconductors. The manufacturing method comprises the following steps: forming a hard mask layer with an etching window on the upper surface of a substrate; performing at least one time of substrate etching on the substrate by using the etching window to form a target deep trench; the step of etching the substrate comprises the following steps of: performing ion implantation on the substrate for multiple times through the etching window to form a modified region; the design size of the modification area is the same as that of the sub-target groove; the ion implantation angle is gradually increased; etching the modified region to form a sub-target groove; if the depth of the sub-target groove is smaller than that of the target deep groove, next substrate etching is carried out; the etching strength of the substrate is gradually increased; and if the depth of the sub-target groove is equal to the depth of the target deep groove, taking the sub-target groove as the target deep groove. According to the invention, the groove wall inclination of the deep groove can be reduced, the etching uniformity of the deep groove is improved, the morphology of the deep groove is improved, and the performance and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a deep trench manufacturing method, a semiconductor structure, a chip and a circuit. Background Art

[0002] Deep trenches (whose height-to-width ratio is usually greater than 4) are widely used in the field of semiconductor integrated circuits, for example, in the manufacturing processes of high voltage (HV) devices, image sensors (CMOS contact image sensor, CIS) devices and Bi-CMOS devices (i.e., complementary metal oxide semiconductor (CMOS) devices and bipolar junction transistor (BJT) devices integrated on the same chip).

[0003] In the deep trench etching process, due to the long time and deep etching depth of the deep trench etching process, the masking layer will be damaged and its morphology will change due to the action of etching ions during the etching process, resulting in the tilting of the groove wall of the etched deep groove. The difference between the bottom width and the top width of the deep trench gradually increases with time, affecting product performance.

[0004] Therefore, how to improve the uniformity of deep trench etching is a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of the technical problems of the inclination of the groove wall and poor etching uniformity of the deep groove formed in the prior art, the present invention provides a deep groove manufacturing method, a semiconductor structure, a chip and a circuit. The deep groove manufacturing method can reduce the inclination of the groove wall of the deep groove, reduce the difference between the bottom width and the top width of the deep groove, improve the etching uniformity of the deep groove, improve the morphology of the deep groove, and enhance the device performance and reliability.

[0006] To achieve the above-mentioned purpose, the first aspect of the present invention provides a deep trench manufacturing method, which includes: providing a substrate, and forming a hard mask layer with an etching window on the upper surface of the substrate; using the etching window of the hard mask layer to perform at least one substrate etching on the substrate to form a target deep trench; wherein each substrate etching step includes: performing multiple ion implantations on the substrate through the etching window of the hard mask layer to form a modified area; wherein the size of the modified area is the same as the design size of the sub-target trench to be formed by the substrate etching; and the angle of the next ion implantation is greater than the angle of the previous ion implantation. degree; using an etching process to remove the modified area to form a sub-target groove of the substrate etching; if it is determined that the depth of the sub-target groove formed by the substrate etching is less than the depth of the target deep groove, performing the next substrate etching; wherein the etching intensity used to remove the modified area by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified area by the etching process during the previous substrate etching; if it is determined that the depth of the sub-target groove formed by the substrate etching is equal to the depth of the target deep groove, stopping the substrate etching; and using the groove formed by the substrate etching as the target deep groove.

[0007] Furthermore, the hard mask layer having an etching window is formed on the upper surface of the substrate, comprising: sequentially forming a liner layer, an initial hard mask layer and a patterned layer on the upper surface of the substrate; forming an etching window in the patterned layer; using the patterned layer as a mask, etching the initial hard mask layer through the etching window of the patterned layer to form a hard mask layer having an etching window.

[0008] Furthermore, before performing at least one substrate etching on the substrate through the etching window of the hard mask layer, the method further includes: etching the substrate through the etching window of the hard mask layer to obtain an initial groove; wherein the depth of the initial groove is less than the depth of the target deep groove; performing at least one substrate etching on the substrate at the bottom of the initial groove through the etching window of the hard mask layer to form the target deep groove.

[0009] Furthermore, the depth of the initial groove is between 0.3um and 5um.

[0010] Furthermore, the method of performing multiple ion implantation on the substrate through the etching window of the hard mask layer to form the modified area includes: performing at least three ion implantation on the substrate through the etching window of the hard mask layer to form the modified area; wherein the angle of the first ion implantation is 0°, the angle of the second ion implantation is 5°, and the angle of the third ion implantation is 10°.

[0011] Furthermore, the energy of ion implantation is between 1Kev and 5000Kev, and the ion implantation dose is between 10 12 cm -2 -10 15 cm-2 .

[0012] Further, the ion implanted elements include one or more of germanium, silicon and arsenic.

[0013] Furthermore, the modified area is removed by a dry etching process; the etching gases used in the dry etching process include CHF3, HBr and Ar; wherein the flow rate of CHF3 is between 10sccm-1000sccm, the flow rate of HBr is between 10sccm-1000sccm, and the flow rate of Ar is between 10sccm-1000sccm.

[0014] Furthermore, the modified area is removed by wet etching process; the etching solution used in the wet etching process includes tetramethylammonium hydroxide solution; wherein the volume percentage of the tetramethylammonium hydroxide solution is between 10% and 80%; and the wet etching temperature is between 20° C. and 80° C.

[0015] Furthermore, the aspect ratio of the target deep trench is between 10:1 and 30:1.

[0016] A second aspect of the present invention provides a semiconductor structure, wherein the semiconductor structure comprises a target deep trench formed by the deep trench manufacturing method described above.

[0017] A third aspect of the present invention provides a chip, which includes the semiconductor structure described above.

[0018] A fourth aspect of the present invention provides a circuit, which includes the semiconductor structure described above.

[0019] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

[0020] The deep groove manufacturing method of the present invention first forms a hard mask layer with an etching window on the upper surface of the substrate, and then uses the etching window to perform at least one substrate etching on the substrate to form a target deep groove. Each step of substrate etching includes: ion implantation into the substrate through the etching window of the hard mask layer to form a modified area, and the design size of the modified area is equal to the design size of the sub-target groove to be formed by the substrate etching. The modified area is removed by an etching process to form a sub-target groove of the substrate etching. If the depth of the sub-target groove formed by the substrate etching is less than the depth of the target deep groove, the next substrate etching is cyclically performed. If the depth of the sub-target groove formed by the substrate etching is equal to the depth of the target deep groove, the etching is stopped, and the groove formed by the substrate etching is used as the target deep groove. Through the present invention, the groove wall inclination of the deep groove can be reduced, the gap between the bottom width and the top width of the deep groove can be reduced, the etching uniformity of the deep groove can be improved, the morphology of the deep groove can be improved, and the device performance and reliability can be improved.

[0021] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0023] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0024] Figure 1 It is a schematic diagram of the structure of the deep trench formed in the prior art;

[0025] Figure 2 A schematic diagram of the structure of a patterned layer and an initial hard mask layer formed in a deep trench manufacturing method provided in an embodiment of the present invention;

[0026] Figure 3 A schematic structural diagram of a hard mask layer and an etching window formed in a deep trench manufacturing method provided in an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of the structure of an initial trench formed in a deep trench manufacturing method provided in an embodiment of the present invention;

[0028] Figure 5 A schematic structural diagram of a first modified region formed in a deep trench manufacturing method provided in an embodiment of the present invention;

[0029] Figure 6 A schematic structural diagram of a first sub-target groove formed in the deep groove manufacturing method provided in an embodiment of the present invention;

[0030] Figure 7 A schematic structural diagram of a second modified region formed in a deep trench manufacturing method provided in an embodiment of the present invention;

[0031] Figure 8 A schematic structural diagram of a second sub-target groove formed in the deep groove manufacturing method provided in an embodiment of the present invention;

[0032] Fig. 9 A flow chart of a deep trench manufacturing method provided by an embodiment of the present invention.

[0033] Description of Reference Numerals

[0034] 100-substrate; 101-oxide layer; 102-deep groove; 103-patterning layer; 200-substrate; 201-pad layer; 202-initial hard mask layer; 203-patterning layer; 204-hard mask layer; 205-etching window; 206-initial groove; 207-first modified area; 208-first sub-target groove; 209-second modified area; 210-second sub-target groove. DETAILED DESCRIPTION

[0035] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0036] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0037] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.

[0038] As the background technology, the performance of the existing semiconductor structure is poor.

[0039] Please refer to Figure 1 , providing a substrate 100; forming an oxide layer 101 on the surface of the substrate 100; forming a patterned layer 103 on the surface of the oxide layer 101; using the patterned layer 103 as a mask, etching the oxide layer 101 and a portion of the thickness of the substrate 100 to form a deep trench 102 in the substrate 100.

[0040] However, during the formation of the semiconductor structure, the deep trench 102 is usually etched by plasma dry etching. Due to the directionality of plasma etching, the etching ability of the trench sidewall is weak, and the trench sidewall is tilted. Since the deep trench 102 is deep, as the etching depth and etching time increase, the gap between the bottom dimension d2 (Bottom CD) and the top dimension d1 (Top CD) of the deep trench 102 becomes larger and larger, thereby reducing the quality of the deep trench finally formed.

[0041] On this basis, the present invention provides a method for manufacturing a deep groove, providing a substrate, forming a hard mask layer with an etching window on the surface of the substrate, and then using the etching window to perform substrate etching on the substrate at least once to form a target deep groove. Each time the substrate is etched, ions are implanted into the substrate through the etching window of the hard mask layer according to the design size of the sub-target groove to be formed by the substrate etching to form a modified area. The substrate structure is destroyed by ion implantation, so that when the modified area is removed by an etching process, the modified area is more easily etched, and only the modified area is etched without etching the substrate. The sub-target groove formed in this way matches its design size, and the groove wall will not be tilted, which can reduce the difference between the bottom width and the top width of the deep groove, improve the etching uniformity of the deep groove, improve the morphology of the deep groove, and enhance the device performance and reliability.

[0042] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0043] Please refer to Fig. 9 In a first aspect, an embodiment of the present invention provides a deep trench manufacturing method, the method comprising: S101: providing a substrate 200, and forming a hard mask layer 204 having an etching window 205 on the upper surface of the substrate 200; S102: performing at least one substrate etching on the substrate 200 using the etching window 205 of the hard mask layer 204 to form a target deep trench; wherein each substrate etching step comprises: performing multiple ion implantations on the substrate 200 through the etching window 205 of the hard mask layer 204 to form a modified area; wherein the size of the modified area is the same as the design size of the sub-target trench to be formed by the substrate etching; and the next ion implantation step comprises: performing multiple ion implantations on the substrate 200 through the etching window 205 of the hard mask layer 204 to form a modified area. The angle of ion implantation is greater than the angle of the previous ion implantation; the modified area is removed by an etching process to form a sub-target groove of the substrate etching; if it is determined that the depth of the sub-target groove formed by the substrate etching is less than the depth of the target deep groove, the next substrate etching is performed; wherein the etching intensity used to remove the modified area by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified area by the etching process during the previous substrate etching; if it is determined that the depth of the sub-target groove formed by the substrate etching is equal to the depth of the target deep groove, the substrate etching is stopped; and the groove formed by the substrate etching is used as the target deep groove.

[0044] First, step S101 is performed: providing a substrate 200 , and forming a hard mask layer 204 having an etching window 205 on the upper surface of the substrate 200 .

[0045] Specifically, in the embodiment of the present invention, there is provided Figure 2The substrate 200 shown is made of silicon; in other embodiments, the substrate 200 may be made of germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate 200 may be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Then, a hard mask layer 204 having an etching window 205 is formed on the upper surface of the substrate 200.

[0046] Furthermore, the hard mask layer 204 having an etching window 205 is formed on the upper surface of the substrate 200, comprising: sequentially forming a liner layer 201, an initial hard mask layer 202 and a patterned layer 203 on the upper surface of the substrate 200; forming an etching window in the patterned layer 203; using the patterned layer 203 as a mask, etching the initial hard mask layer 202 through the etching window of the patterned layer 203 to form a hard mask layer 204 having an etching window 205.

[0047] Specifically, in the embodiment of the present invention, a liner layer 201 is formed on the upper surface of the substrate 200. In this embodiment, the liner layer 201 is a single-layer structure. In other embodiments, the liner layer 201 is also a stacked structure. In this embodiment, the material of the liner layer 201 is silicon oxide. In other embodiments, the material of the liner layer 201 can also be a combination of silicon oxynitride and silicon oxide.

[0048] In this embodiment, the formation method of the liner layer 201 is a thermal oxidation growth process. The thermal oxidation process is carried out in a thermal oxidation furnace tube, and the silicon exposed on the surface will be oxidized into silicon oxide. Preferably, the thermal oxidation needs to adopt a dry oxygen process, and the oxidation temperature is greater than 1050°C, wherein the thickness of the grown silicon oxide is controlled by controlling the time of the thermal oxidation process. In other embodiments, the formation method of the liner layer 201 can also be a chemical vapor deposition process, an atomic layer deposition process, or a physical vapor deposition process.

[0049] Next, an initial hard mask layer 202 is formed on the upper surface of the liner layer 201. In the present embodiment, the material of the initial hard mask layer 202 is silicon nitride. In other embodiments, the material of the initial hard mask layer 202 may also be one or a combination of silicon carbide, silicon oxynitride, silicon oxide, and silicon nitride. In the present embodiment, the initial hard mask layer 202 is a single-layer structure. In other embodiments, the initial hard mask layer 202 may also be a multi-layer structure, such as a combination of multi-layer silicon oxide and silicon nitride. In the present embodiment, the initial hard mask layer 202 is formed by a chemical vapor deposition process. In other embodiments, the initial hard mask layer 202 may be formed by a physical vapor deposition process or an atomic layer deposition process. When the initial hard mask layer 202 is formed by the atomic layer deposition process, the precursor gas used in the atomic layer deposition process includes a mixed gas of SiH2Cl2 and NH3, the flow rate of the mixed gas is between 1500sccm-4000sccm, the pressure is between 1mtorr-10mtorr, the deposition temperature is between 200℃-600℃, and the number of depositions is between 30 times-100 times.

[0050] Next, a patterned layer 203 is formed on the surface of the initial hard mask layer 202. The material of the patterned layer 203 is photoresist. The patterned layer 203 is exposed and developed to form an etching window. The initial hard mask layer 202 is etched through the etching window of the patterned layer 203 using the patterned layer 203 as a mask, and a dry etching process is used to form the following. Figure 3 The hard mask layer 204 with the etching window 205 is shown. The etching gases used in the dry etching include: CF4 gas and CHF3 gas, the flow rate of CF4 gas is between 8sccm-500sccm, the flow rate of CHF3 gas is between 30sccm-200sccm, the chamber pressure is between 10mtorr-2000mtorr, the source RF power is between 100W-1300W, the bias voltage is between 80V-500V, and the time is between 4 seconds-500 seconds. Finally, the liner layer 201 is etched to expose the substrate 200.

[0051] Then, step S102 is performed: the substrate 200 is etched at least once using the etching window 205 of the hard mask layer 204 to form a target deep groove; wherein each step of substrate etching includes: performing multiple ion implantations on the substrate 200 through the etching window 205 of the hard mask layer 204 to form a modified area; wherein the size of the modified area is the same as the design size of the sub-target groove to be formed by the substrate etching; the angle of the next ion implantation is greater than the angle of the previous ion implantation; and the modified area is removed by an etching process to form the sub-target groove of the substrate etching. Sub-target grooves are etched by substrate; if it is determined that the depth of the sub-target grooves formed by the substrate etching is less than the depth of the target deep groove, the next substrate etching is performed; wherein, the etching intensity used to remove the modified area by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified area by the etching process during the previous substrate etching; if it is determined that the depth of the sub-target grooves formed by the substrate etching is equal to the depth of the target deep groove, the substrate etching is stopped; and the groove formed by the substrate etching is used as the target deep groove.

[0052] Furthermore, before performing at least one substrate etching on the substrate 200 using the etching window 205 of the hard mask layer 204, the method also includes: etching the substrate 200 through the etching window 205 of the hard mask layer 204 to obtain an initial groove 206; wherein the depth of the initial groove 206 is less than the depth of the target deep groove; performing at least one substrate etching on the substrate 200 at the bottom of the initial groove 206 through the etching window 205 of the hard mask layer 204 to form the target deep groove.

[0053] Furthermore, the depth of the initial groove 206 is between 0.3um and 5um.

[0054] Furthermore, the method of performing multiple ion implantation on the substrate through the etching window of the hard mask layer to form the modified area includes: performing at least three ion implantation on the substrate through the etching window of the hard mask layer to form the modified area; wherein the angle of the first ion implantation is 0°, the angle of the second ion implantation is 5°, and the angle of the third ion implantation is 10°.

[0055] Furthermore, the energy of ion implantation is between 1Kev and 5000Kev, and the ion implantation dose is between 10 12 cm -2 -10 15 cm -2 .

[0056] Further, the ion implanted elements include one or more of germanium, silicon and arsenic.

[0057] Furthermore, the modified area is removed by a dry etching process; the etching gases used in the dry etching process include CHF3, HBr and Ar; wherein the flow rate of CHF3 is between 10sccm-1000sccm, the flow rate of HBr is between 10sccm-1000sccm, and the flow rate of Ar is between 10sccm-1000sccm.

[0058] Furthermore, the modified area is removed by wet etching process; the etching solution used in the wet etching process includes tetramethylammonium hydroxide solution; wherein the volume percentage of the tetramethylammonium hydroxide solution is between 10% and 80%; and the wet etching temperature is between 20° C. and 80° C.

[0059] Furthermore, the aspect ratio of the target deep trench is between 10:1 and 30:1.

[0060] Specifically, in the embodiment of the present invention, multiple ion implantation is performed on the substrate 200 through the etching window 205 of the hard mask layer 204 to form a target deep groove. If the depth of the target deep groove is small, substrate etching is performed once; if the depth of the target deep groove is large, substrate etching is performed multiple times. The process of substrate etching is as follows: according to the depth and width of the sub-target groove to be formed by the substrate etching, the substrate is implanted with ions multiple times to obtain a corresponding modified area, the size of the modified area is the same as the design size of the sub-target groove to be formed by the substrate etching, and then the modified area is removed by etching to obtain the sub-target groove. If the depth of the sub-target groove reaches the depth of the target deep groove, the substrate etching is stopped, and the groove formed by the substrate etching is used as the target deep groove. If the depth of the sub-target groove does not reach the depth of the target deep groove, the substrate etching is continued until the depth of the formed sub-target groove reaches the depth of the target deep groove.

[0061] In this embodiment, at least three ion implantations are performed on the substrate 200, the first ion implantation angle is 0°, the second ion implantation angle is 5°, and the third ion implantation angle is 10°. The increase in the ion implantation angle each time can ensure the uniformity of the ion implantation in the modified area, which helps to make the wall of the deep trench finally formed vertical.

[0062] Since the modified area has been ion implanted, the substrate structure in the modified area is destroyed. Under the same etching conditions, the etching rate of the modified area is greater than the etching rate of the nearby substrate 200. When etching the modified area, the nearby substrate 200 will not be etched away. The size of the sub-target groove formed each time is the same as the designed size, and the morphology will not change. Therefore, the size of the target deep groove finally formed is also the same as the designed size, which can reduce the inclination of the groove wall of the deep groove, reduce the difference between the bottom width and the top width of the deep groove, improve the etching uniformity of the deep groove, improve the morphology of the deep groove, and enhance the device performance and reliability.

[0063] Furthermore, if the etched trench depth is shallow, the sidewall of the shallow trench will not be tilted. In this embodiment, before forming the modified area, a shallow trench etching process can be performed first, and the substrate 200 can be etched through the etching window 205 of the hard mask layer 204 to obtain the following: Figure 4 The initial groove 206 shown has a depth of 0.3um-5um, and then substrate etching is performed on the basis of the initial groove 206. In this way, shallow trench etching can replace part of the substrate etching, reduce the complex process flow of ion implantation and then etching during substrate etching, improve the efficiency of deep groove formation, and reduce costs.

[0064] The initial groove 206 can be formed by a dry etching process, and the etching gases used in the dry etching process include CHF3, HBr and Ar; wherein the flow rate of CHF3 is between 10sccm-1000sccm, the flow rate of HBr is between 10sccm-1000sccm, and the flow rate of Ar is between 10sccm-1000sccm.

[0065] The initial trench 206 can be formed by a wet etching process, wherein the etching solution used in the wet etching process includes a tetramethylammonium hydroxide solution; wherein the volume percentage of the tetramethylammonium hydroxide solution is between 10% and 80%; and the wet etching temperature is between 20° C. and 80° C.

[0066] In a possible implementation, if the depth of the target deep trench is small, a substrate etching can be performed on the basis of the initial trench 206. According to the design size of the first sub-target trench 208 to be formed by the substrate etching (i.e., the target deep trench design size), ion implantation is performed on the substrate 200 to obtain the following: Figure 5 The first modified area 207 shown in the figure has a depth equal to the depth of the sub-target groove to be formed by etching the substrate, and a width equal to the width of the sub-target groove to be formed by etching the substrate. The ion implanted elements include one or more of germanium, silicon and arsenic. The energy of the ion implantation is between 1Kev and 5000Kev, and the ion implantation dose is between 10 12 cm -2 -10 15 cm -2 .

[0067] Next, the first modified region 207 is removed by etching to obtain Figure 6 The first sub-target groove 208 is shown, and the first sub-target groove 208 is used as a target deep groove.

[0068] In this embodiment, the modified area is removed by dry etching process, the etching gas used in the dry etching process includes CHF3, HBr and Ar, the flow rate of CHF3 is between 10sccm-1000sccm, the flow rate of HBr is between 10sccm-1000sccm, and the flow rate of Ar is between 10sccm-1000sccm. Further, the modified area is removed by wet etching process, the etching solution used in the wet etching process includes tetramethylammonium hydroxide solution, the volume percentage of tetramethylammonium hydroxide solution is between 10%-80%; the wet etching temperature is between 20℃-80℃.

[0069] In another possible implementation, if the depth of the target deep trench is large, multiple substrate etchings can be performed on the basis of the first sub-target trench 208. According to the depth and width of the second sub-target trench 210 to be formed by the second substrate etching, ion implantation is performed on the substrate 200 at the bottom of the first sub-target trench 208 to obtain the following: Figure 7 The second modified area 209 shown in FIG. 1 is a second modified area 209, the depth of which is equal to the depth of the second sub-target groove 210 to be formed by the second substrate etching, and the width of which is equal to the width of the second sub-target groove 210 to be formed by the second substrate etching. Next, the second modified area 209 is removed by etching to obtain the following: Figure 8 The second sub-target groove 210 shown. If the depth of the second sub-target groove 210 reaches the depth of the target deep groove, the substrate etching is stopped and the second sub-target groove 210 is used as the target deep groove. If the depth of the second sub-target groove 210 does not reach the depth of the target deep groove, the next substrate etching is continued until the depth of the formed sub-target groove reaches the depth of the target deep groove. The etching intensity used to remove the modified area by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified area by the etching process during the previous substrate etching, which can enhance the bottom etching ability and improve the problem of groove wall inclination.

[0070] The depth-to-width ratio of the target deep trench formed by the method of the present invention is between 10:1-30:1, the inclination angle of the side wall is between 85°-90°, the difference between the top dimension (D) and the bottom dimension (d) of the target deep trench is between 0.1um-1um, the top dimension of the target deep trench is between 0.3um-5um, and the bottom dimension of the target deep trench is between 0.2um-5um. It can be seen that the present invention can reduce the inclination of the groove wall of the deep trench, reduce the difference between the bottom width and the top width of the deep trench, improve the etching uniformity of the deep trench, improve the morphology of the deep trench, and enhance the device performance and reliability.

[0071] A second aspect of the present invention provides a semiconductor structure, wherein the semiconductor structure comprises a target deep trench formed by the deep trench manufacturing method described above.

[0072] A third aspect of the present invention provides a chip, which includes the semiconductor structure described above.

[0073] A fourth aspect of the present invention provides a circuit, which includes the semiconductor structure described above.

[0074] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0075] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0076] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A deep trench manufacturing method, characterized in that: The deep trench manufacturing method comprises: Providing a substrate, and forming a hard mask layer having an etching window on the upper surface of the substrate; The substrate is etched at least once using the etching window of the hard mask layer to form a target deep trench; wherein each substrate etching step includes: Performing multiple ion implantation on the substrate through the etching window of the hard mask layer to form a modified area; wherein the size of the modified area is the same as the design size of the sub-target groove to be formed by etching the substrate; and the angle of the next ion implantation is greater than the angle of the previous ion implantation; Using an etching process to remove the modified area, forming a sub-target groove of the substrate etching; If it is determined that the depth of the sub-target groove formed by the substrate etching is less than the depth of the target deep groove, the next substrate etching is performed; wherein the etching intensity used to remove the modified area by the etching process during the next substrate etching is greater than the etching intensity used to remove the modified area by the etching process during the previous substrate etching; If it is determined that the depth of the sub-target groove formed by the secondary substrate etching is equal to the depth of the target deep groove, stopping the secondary substrate etching; A trench formed by etching a substrate is used as the target deep trench.

2. The deep trench manufacturing method according to claim 1, characterized in that: The step of forming a hard mask layer having an etching window on the upper surface of the substrate comprises: forming a liner layer, an initial hard mask layer and a patterning layer in sequence on the upper surface of the substrate; forming an etching window in the patterned layer; The patterned layer is used as a mask, and the initial hard mask layer is etched through the etching window of the patterned layer to form a hard mask layer with an etching window.

3. The deep trench manufacturing method according to claim 1, characterized in that: Before performing at least one substrate etching on the substrate using the etching window of the hard mask layer, the method further includes: Etching the substrate through the etching window of the hard mask layer to obtain an initial groove; wherein the depth of the initial groove is less than the depth of the target deep groove; The substrate at the bottom of the initial trench is etched at least once through the etching window of the hard mask layer to form the target deep trench.

4. The deep trench manufacturing method according to claim 3, characterized in that: The depth of the initial groove is between 0.3um and 5um.

5. The deep trench manufacturing method according to claim 1, characterized in that: The method of performing multiple ion implantation on the substrate through the etching window of the hard mask layer to form a modified area includes: Ion implantation is performed at least three times on the substrate through the etching window of the hard mask layer to form a modified area; wherein the angle of the first ion implantation is 0°, the angle of the second ion implantation is 5°, and the angle of the third ion implantation is 10°.

6. The deep trench manufacturing method according to claim 1, characterized in that: The energy of ion implantation is between 1Kev and 5000Kev, and the ion implantation dose is between 10 12 cm -2 -10 15 cm -2 .

7. The deep trench manufacturing method according to claim 1, characterized in that: The elements implanted by ions include one or more of germanium, silicon and arsenic.

8. The deep trench manufacturing method according to claim 1, characterized in that: The modified area is removed by dry etching process; the etching gas used in the dry etching process includes CHF3, HBr and Ar; wherein, the flow rate of CHF3 is between 10sccm-1000sccm, the flow rate of HBr is between 10sccm-1000sccm, and the flow rate of Ar is between 10sccm-1000sccm.

9. The deep trench manufacturing method according to claim 1, characterized in that: The modified area is removed by wet etching process; the etching solution used in the wet etching process includes tetramethylammonium hydroxide solution; wherein the volume percentage of the tetramethylammonium hydroxide solution is between 10% and 80%; and the wet etching temperature is between 20° C. and 80° C.

10. The deep trench manufacturing method according to claim 1, characterized in that: The target deep trench has a depth-to-width ratio between 10:1 and 30:

1.

11. A semiconductor structure, characterized in that: The semiconductor structure includes a target deep trench formed by the deep trench manufacturing method according to any one of claims 1 to 10.

12. A chip, characterized in that: The chip comprises the semiconductor structure according to claim 11.

13. A circuit, characterized in that: The circuit comprises the semiconductor structure of claim 11.

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