DFE simplified parallel implementation circuit and method

Abstract

The invention provides a DFE simplified parallel implementation circuit and method, and belongs to the technical field of high-speed optical communication, the DFE simplified parallel implementation circuit comprises a forward feedback equalizer FFE, a decision feedback equalizer DFE, a decision device and a control module, and further comprises a pre-decision circuit module, the forward feedback equalizer FFE, the pre-decision circuit module, the decision feedback equalizer DFE and the decision device are connected in sequence, and the control module is connected with the pre-decision circuit module. The output of the decision device is simultaneously used as the input of the pre-decision circuit module for connection, and the decision feedback equalizer is connected with the control module. According to the invention, for each PAM4 symbol, the original one-out-of-four preprocessing is changed into one-out-of-two preprocessing, so that the implementation complexity of the DFE parallel architecture is simplified, resources are reduced, and the time sequence pressure is relieved. Meanwhile, for N tap DFE, the number of preprocessing operations is reduced from 4N to 2N, the implementation complexity is greatly reduced, and more tap DFE can be realized under the same resource.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-speed optical communication, and in particular relates to a DFE simplified parallel implementation circuit and method. Background Art

[0002] Serializer and Deserializer (SerDes) technology is mainly used to convert between parallel data and serial data in high-speed communication systems. SerDes systems usually transmit through a controlled impedance transmission line between the transmitter and the receiver. SerDes systems include parallel-to-serial and serial-to-parallel data conversion, impedance matching circuits, and clock data recovery functions.

[0003] In high-speed SerDes systems, due to the non-ideal characteristics of the channel, the signal will be severely damaged, so it is necessary to introduce equalization technology to offset the non-ideal effects of the channel. The common equalization technology at the transmitter is to add a feed forward equalizer (FFE) with a fixed tap coefficient to pre-distort the signal. The equalization function at the receiver is similar to that at the transmitter, and usually requires a combination of multiple equalization modules such as a continuous time linear equalizer (CTLE), a receiver FFE, and a decision feedback equalizer (DFE).

[0004] In high-speed transmission, a parallel architecture is usually used to increase the data processing speed. Since the DFE feedback branch has very high timing requirements, special design is often required in the parallel implementation process. In order to achieve parallel processing of DFE, the existing technology usually pre-processes all possible 4 decision values ​​of PAM4 by multiplication, addition, and judgment to obtain 4 output decision values, and obtains accurate decision values ​​through 4-choice 1 recursion. However, this algorithm is based on the method of exchanging area for time. The operation that originally only needs to be calculated once needs to be calculated 4 times at the same time, which consumes more resources. By using more resources in exchange for time, parallel processing can be achieved. Summary of the invention

[0005] The purpose of the present invention is to provide a DFE simplified parallel implementation circuit and method to solve the technical problem of using more resources to exchange time in the parallel implementation process proposed in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions: A DFE simplified parallel implementation circuit includes a feed-forward equalizer FFE, a decision feedback equalizer DFE, a decision maker, and a control module. It also includes a pre-decision circuit module. The feed-forward equalizer FFE, the pre-decision circuit module, the decision feedback equalizer DFE, and the decision maker are connected in sequence. The output of the decision maker is simultaneously connected as the input of the pre-decision circuit module. The decision feedback equalizer is connected to the control module.

[0007] Further, the ideal values v0, v1, v2, v3 obtained by convergence in the decision maker respectively correspond to the decision values -3, -1, 1, 3 corresponding to the 4 signal levels 00, 01, 10, 11 of the PAM4 signal. By comparing the input signal x i (n) with v1 and v2, it is decided into one of three regions. Two most likely decision values in each region are selected as the input for the next stage for preprocessing, and one of the two output results of the preprocessing is selected by recursive selection based on the final decision value.

[0008] Further, when the input signal x i (n) ≥ v2, the actual output is 3, and the output of the preselected decision value 3 is selected for the (i + 1)-th path. When the actual output is 1, -1, -3, the output of the preselected decision value 1 is selected for the (i + 1)-th path; when the input signal v1 < x i (n) < v2, the actual output is 3, 1, and the output of the preselected decision value 1 is selected for the (i + 1)-th path. When the actual output is -1, -3, the output of the preselected decision value -1 is selected for the (i + 1)-th path; when the input signal x i (n) ≤ v1, the actual output is 3, 1, -1, and the output of the preselected decision value -1 is selected for the (i + 1)-th path. When the actual output is -3, the output of the preselected decision value -3 is selected for the (i + 1)-th path.

[0009] Another object of the present invention provides a DFE simplified parallel implementation method. Based on the above DFE simplified parallel implementation circuit, first start the feed-forward equalizer FFE and the decision maker. After the coefficients of the feed-forward equalizer FFE and the decision maker converge, then start the pre-decision circuit module and the decision feedback equalizer DFE. Wait until the coefficients of the decision feedback equalizer DFE converge through an adaptive algorithm. After convergence, the system works normally and reports the coefficients of the decision feedback equalizer DFE to the control module at regular intervals.

[0010] The present invention has the following beneficial effects: 1. Perform simple pre-decision on the input data of the DFE, select the two most likely decision values from the original four decision values to replace, and finally select the final output after a one-in-two recursive selection. This greatly simplifies the parallel implementation architecture of the DFE. Because the possibility of input is reduced, the processing complexity is also reduced, and at the same time, the resource occupation can be reduced.

[0011] 2. After the FFE and the ideal level of the decision maker converge, the DFE is turned on. The pre-decision is classified by the ideal value converged by the decision maker. Since the ideal value fluctuates within a small range after convergence and is relatively stable, this feedback loop does not have high timing requirements, thereby alleviating timing pressure.

[0012] 3. After pre-determination, there are only two pre-processing results. All four possibilities are mapped to two alternative results according to the principle of proximity. Finally, one of the two is selected after the output decision value of the previous symbol is obtained, which minimizes the occurrence of bit errors and improves the accuracy of data transmission.

[0013] 4. For N-tap DFE, by analogy, each tap selects the two most likely decision values ​​for input preprocessing, and the number of preprocessing operations required is 4. N Reduced to 2 N , greatly reducing the implementation complexity, more tap DFEs can be implemented with the same resources, improving the performance and flexibility of the system.

[0014] 5. Check the coefficient of DFE at intervals. If the coefficient is too large, report it to the control module. The control module will prompt the risk and handle it by uniformly coordinating the allocation of balancing capacity of multiple balancing modules in the system. This can ensure the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0016] Figure 1 The structure diagram of the digital equalizer at the receiving end of the SerDes system in the prior art; Figure 2 A schematic diagram of a circuit for implementing a DFE in parallel in the prior art; FIG3 (a) is a structural diagram of each pre-processing circuit of a DFE parallel implementation circuit in the prior art; FIG3( b ) is a structural diagram of a 4-choice-1 recursive circuit of a DFE parallel implementation circuit in the prior art; Figure 4 The structure diagram of the simplified parallel implementation circuit of DFE of the present invention; Figure 5 A schematic diagram of a circuit for implementing pre-determination of the present invention; FIG6 (a) is a structural diagram of each pre-processing circuit of the simplified parallel implementation circuit of DFE of the present invention; FIG6( b ) is a structural diagram of a 2-choose-1 recursive circuit of a simplified parallel implementation circuit of DFE according to the present invention; Figure 7 The figure is a flow chart of a simplified parallel implementation method of DFE of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] Four-level pulse amplitude modulation (PAM4) technology is usually used in high-speed SerDes systems. Four different signal levels are used to represent 00, 01, 10, and 11, and 2 bits of information can be transmitted per cycle, while the traditional two-level non-return-to-zero (NRZ) signal technology can only transmit 1 bit of information per cycle. Therefore, at the same baud rate, the bit rate of PAM4 is twice that of the NRZ signal, which makes PAM4 more efficient and cost-effective in high-speed data communications.

[0019] At the receiving end of a high-speed SerDes system, digital domain equalization usually uses a joint equalization of a feed forward equalizer (FFE) and a decision feedback equalizer (DFE). The structure is as follows: Figure 1 As shown in Figure 2. Since the input of the current symbol of the DFE is the decision value of the output of the previous symbol, as shown in Figure 2. Figure 2 As shown, in parallel implementation, the multiplication, addition and judgment of each path need to be completed sequentially. The delay required for these processes is too long to meet the timing requirements of parallel implementation.

[0020] In high-speed transmission, a parallel architecture is usually used to increase the data processing speed. Since the DFE feedback branch has very high timing requirements, special design is often required in the parallel implementation process. By using more resources in exchange for time, parallel processing can be achieved. In order to achieve parallel processing of DFE, the prior art usually pre-processes all possible 4 decision values ​​of PAM4 by multiplication, addition, and judgment in advance to obtain 4 output decision values, and obtains accurate decision values ​​through 4-to-1 recursion, as shown in Figure 3. Since the operations that require more time are completed in advance, the final 4-to-1 calculation takes relatively less time and can be completed within 1 beat. However, this algorithm is based on the method of exchanging area for time. The operation that originally only needs to be calculated once needs to be calculated 4 times at the same time, which consumes more resources. Since the parallel implementation is more complicated, the resources required for each additional tap are multiplied by 4. In high-speed SerDes systems, 1-tap DFE is usually used.

[0021] The present invention is based on a high-speed SerDes system including FFE and DFE, and optimizes the parallel implementation of DFE during PAM4 modulation. For the commonly used receiving end FFE and DFE joint equalization solution, FFE shares part of the equalization task, and the coefficient of DFE can be controlled not to be particularly large, that is, the input signal is unlikely to deviate too far from the ideal value.

[0022] See also Figure 4-7 As shown, a DFE simplified parallel implementation circuit includes a feed forward equalizer (FFE), a decision feedback equalizer (DFE), a decision device and a control module, and also includes a pre-decision circuit module. The feed forward equalizer, the pre-decision circuit module, the decision feedback equalizer, and the decision device are connected in sequence, and the output of the decision device is also connected as the input of the pre-decision circuit module, and the decision feedback equalizer is connected to the control module. The structural diagram of the DFE simplified parallel implementation circuit of the present invention is shown in FIG. Figure 4 shown.

[0023] The pre-decision circuit is as follows: Figure 5 As shown. Among them, x i (n) is the DFE input data of the nth parallel path, s i (n,1) and s i (n,2) are the two most likely decision values ​​selected by the pre-decision of the i-th path of the n-th beat. The ideal level obtained by the convergence of the decision device uses the pre-decision circuit module to select the two most likely decision values ​​of each symbol as the DFE filter input of the next symbol. At the same time, the DFE coefficient is reported to the control module once every period of time.

[0024] The four signal levels of the PAM4 signal, 00, 01, 10, and 11, correspond to the decision values ​​-3, -1, 1, and 3, respectively, which correspond to the ideal values ​​v0, v1, v2, and v3 obtained by convergence in the decision device, respectively. Table 1 shows the mapping relationship of the pre-decision circuit module. By comparing the input signal with v1 and v2, one of the three regions is determined. Two most likely decision values ​​are selected in each region as the input of the next channel for preprocessing. One of the two output results of the preprocessing is recursively selected through the final decision value. Since v1 and v2 fluctuate slightly around the optimal value after convergence, this feedback branch does not have high requirements on timing. As shown in Figure 6, w(n) is the DFE coefficient of the nth beat, y i (n,1) and y i (n,2) are the two decision values ​​of the preprocessing output of the nth beat and the ith path, z i (n) is the output decision value obtained by recursion in the i-th path of the n-th beat.

[0025] Due to the pre-determination, each path only needs to pre-process two possible decision values, and finally perform a 2-to-1 result recursion, which greatly reduces the required computing resources.

[0026] Table 1 Pre-determination circuit module mapping relationship

[0027] Figure 7 The flowchart of the simplified parallel implementation method of DFE of the present invention is shown. First, the FFE and the decision device are started, and after the coefficients of the FFE and the decision device converge, the pre-decision circuit module and the DFE are started, and the DFE coefficient converges through the adaptive algorithm. After convergence, the system works normally and reports the DFE coefficient to the control module at intervals. By monitoring whether the DFE coefficient is too large, it is judged whether there is a risk of bit error, so that the control module can coordinate the cooperation of each equalization module as a whole.

[0028] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well.

Claims

1. A DFE simplified parallel implementation circuit, comprising a forward feedback equalizer FFE, a decision feedback equalizer DFE, a decision device and a control module, characterized in that: The invention also includes a pre-decision circuit module, wherein the forward feedback equalizer FFE, the pre-decision circuit module, the decision feedback equalizer DFE, and the decision device are connected in sequence, and the output of the decision device is also connected as the input of the pre-decision circuit module. The decision feedback equalizer is connected to the control module, and the ideal values ​​v0, v1, v2, and v3 obtained by convergence in the decision device correspond to the decision values ​​-3, -1, 1, and 3 corresponding to the four signal levels 00, 01, 10, and 11 of the PAM4 signal, respectively. i (n) is compared with v1 and v2, and a decision is made in one of the three regions. Two most likely decision values ​​are selected from each region as the input of the next path for preprocessing. One of the two output results of the preprocessing is recursively selected through the final decision value.

2. The DFE simplified parallel implementation circuit according to claim 1, characterized in that: When the input signal x i (n) ≥ v2, the actual output is 3, and the output of the (i + 1)-th path selects the preselected decision value of 3. The actual outputs are 1, -1, -3, and the output of the (i + 1)-th path selects the preselected decision value of 1; when the input signal v1 < x i (n) < v2, the actual outputs are 3, 1, and the output of the (i + 1)-th path selects the preselected decision value of 1. The actual outputs are -1, -3, and the output of the (i + 1)-th path selects the preselected decision value of -1; when the input signal x i (n) ≤ v1, the actual outputs are 3, 1, -1, and the output of the (i + 1)-th path selects the preselected decision value of -1. The actual output is -3, and the output of the (i + 1)-th path selects the preselected decision value of -3.

3. A DFE simplified parallel implementation method, based on the DFE simplified parallel implementation circuit according to claim 1 or 2, characterized in that: First, the forward feedback equalizer FFE and the decision device are started, and after the coefficients of the forward feedback equalizer FFE and the decision device converge, the pre-decision circuit module and the decision feedback equalizer DFE are started, and the decision feedback equalizer DFE coefficients converge through an adaptive algorithm. After convergence, the system works normally and reports the decision feedback equalizer DFE coefficients to the control module at intervals.

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