A method for implementing a virtual GPU based on a vectorized instruction set

Abstract

The present invention discloses a method for implementing a virtual GPU based on a vectorized instruction set, which is used to construct a virtual GPU accelerator card in a CPU processor to enable virtual heterogeneous accelerated computing on a processor platform. The method includes: constructing a virtual GPU thread operating environment based on scalable vector instructions in the CPU, wherein each scalar computing unit in the vectorized computing unit serves as a parallel computing core of the virtual GPU, and each virtual GPU parallel core has an independent stack space as a local storage space; and a virtual GPU task manager creates a task block space required for the virtual GPU thread and manages the operation of the virtual GPU task. The system constructs a GPU-like parallel computing mode by utilizing the parallel execution capability of the CPU scalable vector instructions, thereby constructing a virtual GPU and providing GPU use in an environment without GPU hardware.

Description

Technical Field

[0001] The present invention relates to the field of computer processing technology, and in particular to a method for implementing a virtual GPU based on a vectorized instruction set. Background Art

[0002] With the rapid development of information technology, especially the increasing demand for high-performance computing such as artificial intelligence, big data analysis, and deep learning, graphics processing units (GPUs) have become key hardware for accelerating complex computing tasks with their powerful parallel computing capabilities. However, traditional GPUs have some limitations in high-performance computing, such as high power consumption, high cost, and large size, which are particularly prominent in resource-constrained embedded systems and mobile devices.

[0003] CPU processors are widely used in mobile devices, embedded systems and IoT devices due to their versatility, high performance and good scalability. In order to make up for the shortcomings of computing performance, CPU processors usually add dedicated computing acceleration instructions, such as the early MMX and subsequent AVX instructions of X86, as well as Neon, SVE and other computing acceleration instructions provided in ARM processors. The early vectorized computing acceleration instructions usually perform completely consistent operations on all data, while the later scalable vectorized instructions provide a certain degree of flexible and elastic processing capabilities. For example, the SVE (Scalable Vector Extension) instruction set in the ARM processor, as a scalable vector computing extension, provides a mask type prediction register for independent operation control of different data bits, supports operations on part of the vectorized data, and supports memory read and write access to non-continuous addresses; the AVX512 instruction set of the X86 processor also provides similar functional features.

[0004] Vectorized instructions provide powerful computing power. At the same time, scalable vectorized instructions also provide rich fine-grained computing and data access control capabilities. From the hardware capability perspective, they provide computing power similar to that of GPU CUDA Core, where each Core has the same instructions but different data. However, the application of vectorized instructions in the existing technology is mainly data parallel computing, and the independent enable control of its data units in the vectorized instruction set has not been fully utilized to imitate the GPU's CUDA Core computing mode to build a virtual GPU, thereby achieving high-performance computing on an embedded platform.

[0005] Therefore, there is an urgent need for an innovative method based on the vectorized instruction set of the CPU processor, which can efficiently simulate the parallel computing mode of the GPU on an embedded platform without a GPU to meet the needs of high-performance computing while reducing power consumption and cost. Summary of the invention

[0006] In view of the deficiencies in the prior art, an object of the present invention is to provide a method for implementing a virtual GPU based on a vectorized instruction set.

[0007] The objective of the present invention is achieved through the following technical solution: a method for implementing a virtual GPU based on a vectorized instruction set, comprising:

[0008] By using the CPU vectorized instruction's ability to process data in parallel, the CPU vectorized instruction SIMD operation mode is used to simulate the behavior mode of multi-core SIMT parallel data processing in the GPU. The vectorized mask register is used to finely control the data processing in each vector to simulate the behavior mode of independent judgment and branch jump of each GPU core.

[0009] The virtual GPU structure includes: a physical CPU supporting scalable vectorized instructions, a virtual GPU task manager, a virtual GPU thread task block space, a virtual GPU runtime library, a virtual GPU static program, a virtual GPU task compilation tool, and a virtual GPU thread;

[0010] The physical CPU supporting scalable vectorized instructions includes a general vector register for storing general computing data, a vector mask register for controlling whether each scalar in a vector is operated, and a vector computing engine for executing data in the general vector register;

[0011] The virtual GPU task manager is used to manage virtual GPU tasks, including creating task block spaces required by virtual GPU threads, and creating and running virtual GPU threads; when running virtual GPU threads, synchronously passing virtual GPU task block space address information to the virtual GPU threads;

[0012] The virtual GPU thread task block space is associated with a virtual GPU thread in a one-to-one correspondence, and is used for storage and access of private data of each virtual GPU thread during its operation, including private input parameters passed to the virtual GPU thread from the outside, global variables private to the virtual GPU thread, and dynamic program stacks during the operation of the virtual GPU thread;

[0013] The virtual GPU task compilation tool is used to compile user GPU programs, adapt to the vectorized instruction running and jump mode in the physical CPU, and support data transfer between the virtual GPU task manager and the virtual GPU thread.

[0014] Furthermore, the physical CPU supporting scalable vectorized instructions includes:

[0015] A vector register, used to store data to be processed, wherein the data is data of any type, including address type data and calculation type data;

[0016] A vector mask register, used for operation control, wherein the mask register contains a flag bit having the same number of data as that stored in the vector register, and is used to mark whether the corresponding data in the vector register participates in the calculation execution;

[0017] A vector computing engine is used to perform parallel operations on the data in the vector register, wherein the parallel operations include data access and data computing. During the parallel operations, the vector computing engine skips the operations on the data that does not need to be processed according to the value of the flag bit in the mask register.

[0018] Furthermore, the virtual GPU thread task block space includes:

[0019] The virtual GPU thread task block space is a memory space for storing data, and is used to store data related to the virtual GPU thread task;

[0020] Each virtual GPU thread task block space corresponds to a virtual GPU thread task;

[0021] The virtual GPU thread task block spaces corresponding to different parallel thread tasks of the same virtual GPU program have the same memory data space structure, which is represented by the same space size and the same data arrangement method, but have different base addresses and specific stored data values.

[0022] The virtual GPU thread task block space is used to store statically allocated data, and does not include data storage space dynamically requested during task execution.

[0023] Furthermore, the virtual GPU thread task block space is used to store statically allocated data, specifically: the static allocation method is a space allocation method of the storage location determined during the compilation process of the virtual GPU program, including all global variables of the virtual GPU thread task corresponding to the virtual GPU thread task block space, parameter data passed in when the virtual GPU thread task is started, and stack data during the operation of the virtual GPU thread task.

[0024] Furthermore, the virtual GPU thread includes:

[0025] Logically corresponds to a computing thread running on a GPU core;

[0026] In terms of computation execution, a scalar unit in the CPU vectorized instruction is used as the actual computation execution carrier;

[0027] In operation scheduling management, CPU software threads are used as scheduling operation objects.

[0028] Furthermore, the CPU software thread is used as the scheduling operation object in the operation scheduling management, including:

[0029] Controlling the execution of the virtual GPU thread by scheduling the CPU software thread to run or not;

[0030] A CPU software thread contains multiple virtual GPU threads. The virtual GPU threads in the same CPU software thread can be uniformly scheduled for execution or suspended.

[0031] Furthermore, the virtual GPU task manager is used to create all task block spaces for each virtual GPU thread, and configure and start the virtual GPU thread tasks, specifically:

[0032] Create a task block space for each virtual GPU thread according to the total number of GPU task threads required;

[0033] According to the number of virtual GPU threads contained in each CPU thread, manage and organize the base address information of the task block space corresponding to the virtual GPU threads contained in the CPU thread;

[0034] Organize corresponding data according to the data required for the virtual GPU thread to run, and pass the corresponding data as parameters to the CPU thread when creating the CPU thread;

[0035] Determine the number of CPU threads that need to be created and run based on the total number of virtual GPU threads required.

[0036] Furthermore, the corresponding data includes:

[0037] Virtual GPU thread task dimension information, including the size of each dimension;

[0038] The ID information of the virtual GPU thread, that is, the position of the virtual GPU thread in the overall virtual GPU thread task;

[0039] The base address of the task block space corresponding to the virtual GPU thread;

[0040] Input parameters passed by external tasks to the virtual GPU thread tasks.

[0041] Furthermore, the virtual GPU task compilation tool is specifically used to:

[0042] Organize the data access, calculation and jump control of the virtual GPU program in the form of scalable vectorized instructions;

[0043] Determine the number of virtual GPU threads in a single CPU thread according to the number and performance of scalable vectorized instruction computing engines, scalable vectorized general vector registers, and scalable vectorized mask registers in the physical CPU;

[0044] Provide key information required for the operation of the virtual GPU thread to the outside, including the minimum size requirement of the virtual GPU thread task block space and the format of the data that needs to be externally filled in the virtual GPU task.

[0045] The present invention also provides a device for implementing a virtual GPU based on a vectorized instruction set, comprising one or more processors for implementing the method for implementing a virtual GPU based on a vectorized instruction set.

[0046] The beneficial effects of the present invention are:

[0047] 1. Low hardware cost: No additional GPU hardware is required, which reduces the overall cost of the system and is particularly suitable for resource-constrained embedded systems and mobile devices.

[0048] 2. High flexibility: The capabilities of virtual GPUs are highly flexible and can dynamically adjust task scheduling and resource allocation according to different computing tasks and system requirements to improve computing efficiency.

[0049] 3. Efficient parallel computing: By making full use of the vector processing capabilities and dynamic scalability of the scalable vectorized instruction set, parallel computing similar to traditional GPUs is achieved, meeting the needs of high-performance computing.

[0050] 4. Convenient software development: The GPU-like computing operation mode allows software development to be carried out in a CUDA-like manner, making it convenient for developers with CUDA development experience to quickly develop software.

[0051] 5. Wide applicability: The present invention is applicable to various resource-constrained application scenarios, such as mobile devices, embedded systems, Internet of Things devices, etc., expanding the application scope of high-performance computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0053] Figure 1 A schematic diagram of the architecture system of the solution of the present invention;

[0054] Figure 2 A schematic diagram of the virtual GPU structure of the solution of the present invention;

[0055] Figure 3 A schematic diagram of the relationship between the physical CPU, CPU thread, virtual GPU thread, and task block space;

[0056] Figure 4 It is a schematic diagram of the structure of the virtual GPU thread task block space;

[0057] Figure 5 The figure is a schematic diagram of the change process of the valid bits of the mask register during the branch processing of the virtual GPU thread task. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0059] like Figure 1 As shown, an implementation method of a virtual GPU based on a vectorized instruction set provided by an embodiment of the present invention includes:

[0060] The CPU vectorized instruction can process data in parallel by using its ability to do vectorized instructions. The CPU vectorized instruction SIMD operation mode is used to simulate the behavior of multi-core SIMT parallel data processing in the GPU. The vectorized mask register is used to finely control the data processing in each vector to simulate the behavior of independent judgment and branch jump of each GPU core.

[0061] The virtual GPU structure includes: a physical CPU supporting scalable vectorized instructions, a virtual GPU task manager, a virtual GPU thread task block space, a virtual GPU runtime library, a virtual GPU static program, a virtual GPU task compilation tool, and a virtual GPU thread.

[0062] The physical CPU that can support scalable vectorized instructions needs to include general vector registers that store general computing data, vector mask registers that control whether each scalar in the vector is operated, and a vector computing engine that executes the data in the general vector registers. The basic computing capability of the virtual GPU is provided by the parallel processing computing capability of the vectorized registers.

[0063] The virtual GPU thread is a virtual abstraction based on the vectorized computing resources in the physical CPU. From the perspective of hardware entities, each virtual GPU thread is composed of a scalar unit in the physical CPU vectorization module. The general vector register, vector mask register and a scalar unit in the vector computing engine together constitute the storage and execution entity of a virtual GPU thread. Figure 2As shown in the figure; from the perspective of software tasks, virtual GPU thread tasks are carried, run and scheduled by CPU threads. Each CPU thread carries several virtual GPU threads, which is equivalent to thread bundles in general GPU software development. The scheduling of virtual GPU threads uses CPU threads as the minimum granularity. The number of virtual GPU threads that can be carried by the same CPU thread is determined by the width and number of vectorized resources in the physical CPU and the compiler.

[0064] The virtual GPU task block space is a piece of memory space associated with a virtual GPU thread in a one-to-one correspondence, and is used for storing and accessing private data of each virtual GPU thread during its operation. Figure 3 As shown, the relationship between the virtual GPU task block space and the virtual GPU thread as well as the CPU thread and the CPU core is maintained during the life cycle of the virtual GPU computing task. A fixed corresponding relationship is maintained between the virtual GPU thread task block space and the virtual GPU thread. Regardless of whether the virtual GPU thread is scheduled to run on the physical CPU core, the virtual GPU thread task block exists in the system memory. In terms of data types, the virtual GPU thread task block space includes private input parameters passed to the virtual GPU thread from the outside, global variables private to the virtual GPU thread, and dynamic program stacks during the running of the virtual GPU thread. In the same GPU task, the task block spaces of different virtual GPU threads have the same size and structural layout. The only differences are the base address of the task block space and the specific data values ​​stored therein. In terms of the spatial composition structure of the virtual GPU thread task block space, the task data memory space block includes the task variable space and the task stack space, as shown in Figure 4 As shown; the variable layout in the task variable space is static, and its storage position remains unchanged during the task execution life cycle. The variable layout in the task stack space is dynamic, and the number and position of the variable data therein will change synchronously with the execution of the task.

[0065] The virtual GPU task manager is mainly used to manage virtual GPU tasks, including creating the task block space required for virtual GPU threads, and creating and running virtual GPU threads. Before running, the virtual GPU task manager needs to create a task block space for each virtual GPU thread, and assign necessary data in the task block space according to the overall GPU task and environment; when running a virtual GPU thread, the virtual GPU task manager needs to synchronously pass the virtual GPU task block space address information to the virtual GPU thread.

[0066] The virtual GPU task compiler tool mainly compiles user GPU programs, adapts to the vectorized instruction running and jump mode in the physical CPU, and supports data transfer between the virtual GPU task manager and the virtual GPU thread. During the virtual GPU program compilation process, the compiler needs to determine the number of virtual GPU threads contained in each CPU thread according to the number of vectorized resources in the physical CPU, as well as the processing and control of the vectorized mask register value of the virtual GPU task during the branch execution process.

[0067] The following takes the SVE instruction set and CPU processor resources under the ARM platform as an example to describe the construction and operation method and process of the virtual GPU on its processor.

[0068] In the ARM processor SVE instruction, the general vector registers are Z0-Z31 registers, and the register width is determined by the chip implementer; the mask registers that control the operation are P0-P15 registers, also known as prediction registers. When performing data access operations, the ARM processor provides Gather-Load and Scatter-store operations. For example, the LD1SB instruction can load byte data based on discrete address values ​​in general vector registers; when performing data access and calculation operations, the ARM processor supports controlling the non-execution of several channels in parallel operations based on prediction registers. For example, LD1SB can support controlling whether the load operation of different data channels is performed based on prediction registers, and the ADD instruction supports controlling whether to perform addition operations on data in different data channels in vector registers based on prediction registers.

[0069] During the calculation and data access process, the parallelized virtual GPU core is a channel between the vectorized register and the execution engine. For example, for 64-bit data, it is each 64-bit data storage space in the vectorized register and each 64-bit data processing module in the execution engine.

[0070] Each task uses an independent memory space to store its own data. Access to the data in the task requires the use of the gater-load and scatter-store capabilities provided by the ARM processor. When the task is initialized and loaded, the task loading module allocates an independent memory space for each task, selects the address value with the smallest address value among the base addresses of each task space as the task space address reference, and then calculates the offset of each task space base address relative to this task space address reference, and saves this offset and the aforementioned task space base address value and task space address reference value as parallel task attributes in the task control block.

[0071] When the parallel task is ready for scheduling and execution, the system selects the subtask to be executed, and then uses a general scalar register Xn to load and store the task space address reference value of this parallel task, and then uses the vectorized register Zn to load the offset of the task space base address of the subtask to be executed relative to the task space address reference value. Subsequent access to each subtask space will be based on this Xn and Zn, plus the offset of the specific variable in the task space for access. For example, for a variable with an offset of k in the task space, the access process is: use a scalar instruction to add Xn and offset k and store it back to the Xn register, then set all channels of the prediction register Pn to 1 to validate the loading operation of each vectorized channel, and then use the vectorized load instruction LD1x with scalar offset to read the variable at the offset k position of each task. In the LD1x instruction, the Xn and Zn registers are used as the base scalar value and the offset vector value respectively, and the previously set Pn prediction register is used to validate the loading action. For example, the instruction to read a 64-bit integer value is LD1D.

[0072] During sequential execution, each subtask loads the required data into the vectorized register in parallel. For the private data of each subtask, the above Xn and Zn register methods are used to load the data of each task memory space in parallel. For the global shared variables, all channels in the vectorized register Zn are set to the address value of the global shared variable, and then the vectorized load instruction LD1x is used to load the global shared variable into each subtask. After the data of each subtask is loaded into the vectorized register, the calculation instructions, such as the ADD instruction, are used in parallel to perform parallel processing operations on the data. When the data needs to be written back to the memory after the processing operation, the operation method is similar to the previous data loading, except that the ST1x instruction is used for storage. During sequential execution, each subtask uses the prediction register Pn that has been assigned valid values ​​for all channels to perform effective processing operations on all subtasks.

[0073] When executing a branch, it is necessary to use a branch condition judgment statement to determine whether the branch of each subtask is established or not, and store the judgment result in the vectorized prediction register Pn. Then, the Pn register is used to control the order of executing the branch logic of the subtasks whose judgment conditions are established. When entering another branch, it is necessary to invert the value of the prediction register Pn and use the Pn register to execute instructions to execute the branch logic of the subtask whose judgment conditions are not established before. For example, for if-else branch type statements, at the if judgment statement, after each subtask calculates the logical value to be judged, the vectorized CMP instruction is used to parallelize the judgment result of the if condition of each subtask, and the CMP judgment result is assigned to the prediction register Pn, and then the instructions after the if judgment are executed sequentially. During execution, all calculation processing instructions use the Pn register as a control register, so that the execution engine only calculates and processes the vector data channel with a valid if judgment result in the previous step, so as to realize the branch execution of the subtask whose if judgment logic is true; when the subtask executes the current if branch and needs to execute the else branch, the execution engine needs to negate all the values ​​of the Pn register, and the execution engine only calculates and processes the vector data channel with a false if judgment result in the previous step, so as to realize the non-if branch of the subtask whose if judgment logic is false, that is, the execution of the else branch. In order to improve versatility and performance, the compiler of the task program can control the location of the program branch when compiling the program to ensure that the logic code of all else branches is at the end of the if branch, so as to realize the sequential execution of the logic of the if and else branches without additional address jumps.

[0074] The above branch execution processing method flow only contains one layer of if-else mode. If there is nested if-else statements, or if it contains Loop loop logic at the same time, the branch processing logic needs to be slightly adjusted. When it contains nested if-else or contains if-else branches and Loop loop statements at the same time, the system needs to record the valid subtask domain range during the current execution, that is, the subtask object set currently being processed. Note that the subtask set currently being processed is not equal to the subtask whose value in the current prediction register is a valid bit, but the subtask involved in the current calculation code block, including both the subtask whose value in the current prediction register is valid and the subtask whose value in the prediction register needs to be set to valid when the else branch is executed later; for non-valid subtasks, the corresponding bits in the prediction register Pn are all invalid when the current code block is executed. When the system is initially executed, the valid subtask domain is all subtasks. When the execution engine executes the code backward, if it encounters an if-type judgment statement, the system needs to first push the valid value of the current prediction register Pn into the task domain stack to record the current valid sub-task domain range, and then execute the judgment statement to update the prediction register Pn value; when subsequently executing the else branch corresponding to the current if, the system needs to take out the top value in the task domain stack as the current valid task domain range value, and then invert the prediction register Pn value within this valid sub-task domain range to execute the subtask that needs to execute the else branch; when the else branch is executed, the system pops the top value in the task domain stack and assigns it to the prediction register Pn as the subtask execution control when the subsequent code is executed. If a Loop-type loop statement instruction is encountered during code execution, before starting the Loop loop, the current prediction register Pn value is pushed into the task domain stack, and then the condition is judged and the Pn register value is modified. When the loop body completes this execution and needs to execute a forward jump instruction to start the next loop, the value of the Pn register and the task domain stack are not modified. The forward jump instruction also needs to jump to the start position of the current Loop loop and push Pn into the back of the task domain stack instruction so as not to affect the task domain stack; if the new valid subtask domain corresponding to the forward jump instruction is empty, that is, there is no need for a subtask to execute the loop, the system pops the top value of the task domain stack and assigns it to the prediction register Pn value, and executes subsequent instructions. Figure 5 The figure shows an example of how the prediction register Pn and task domain range change with code execution in the case of two levels of branch nesting. During the running process, as the code branch nesting enters and exits, the task domain stack content also needs to be pushed and popped accordingly.

[0075] An embodiment of the present invention further provides a device for implementing a virtual GPU based on a vectorized instruction set, comprising one or more processors for implementing the method for implementing a virtual GPU based on a vectorized instruction set.

[0076] The implementation process of the functions and effects of each unit in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0077] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of the present invention. Ordinary technicians in this field can understand and implement it without paying creative work.

[0078] Those skilled in the art will readily appreciate other embodiments of the present application after considering the description and practicing the contents disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application. The description and examples are intended to be exemplary only.

[0079] It should be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A method for implementing a virtual GPU based on a vectorized instruction set, characterized in that: include: By using the CPU vectorized instruction's ability to process data in parallel, the CPU vectorized instruction SIMD operation mode is used to simulate the behavior mode of multi-core SIMT parallel data processing in the GPU. The vectorized mask register is used to finely control the data processing in each vector to simulate the behavior mode of independent judgment and branch jump of each GPU core. The virtual GPU structure includes: a physical CPU supporting scalable vectorized instructions, a virtual GPU task manager, a virtual GPU thread task block space, a virtual GPU runtime library, a virtual GPU static program, a virtual GPU task compilation tool, and a virtual GPU thread; The physical CPU supporting scalable vectorized instructions includes a general vector register for storing general computing data, a vector mask register for controlling whether each scalar in a vector is operated, and a vector computing engine for executing data in the general vector register; The virtual GPU task manager is used to manage virtual GPU tasks, including creating task block spaces required by virtual GPU threads, and creating and running virtual GPU threads; when running virtual GPU threads, synchronously passing virtual GPU task block space address information to the virtual GPU threads; The virtual GPU thread task block space is associated with a virtual GPU thread in a one-to-one correspondence, and is used for storage and access of private data during the operation of each virtual GPU thread, including private input parameters passed to the virtual GPU thread from the outside, global variables private to the virtual GPU thread, and dynamic program stacks during the operation of the virtual GPU thread; The virtual GPU task compilation tool is used to compile user GPU programs, adapt to the vectorized instruction running and jump mode in the physical CPU, and support data transfer between the virtual GPU task manager and the virtual GPU thread.

2. The method for implementing a virtual GPU based on a vectorized instruction set according to claim 1, characterized in that: The physical CPU supporting scalable vectorized instructions includes: A vector register, used to store data to be processed, wherein the data is data of any type, including address type data and calculation type data; A vector mask register, used for operation control, wherein the vector mask register contains a flag bit having the same number of data stored in the vector register, and is used to mark whether the corresponding data in the vector register participates in the calculation execution; A vector computing engine is used to perform parallel operations on the data in the vector register, wherein the parallel operations include data access and data computing. During the parallel operations, the vector computing engine skips the operations on the data that does not need to be processed according to the value of the flag bit in the vector mask register.

3. The method for implementing a virtual GPU based on a vectorized instruction set according to claim 1, characterized in that: The virtual GPU thread task block space includes: The virtual GPU thread task block space is a memory space for storing data, and is used to store data related to the virtual GPU thread task; Each virtual GPU thread task block space corresponds to a virtual GPU thread task; The virtual GPU thread task block spaces corresponding to different parallel thread tasks of the same virtual GPU program have the same memory data space structure, which is represented by the same space size and the same data arrangement method, but have different base addresses and specific stored data values. The virtual GPU thread task block space is used to store statically allocated data, and does not include data storage space dynamically requested during task execution.

4. The method for implementing a virtual GPU based on a vectorized instruction set according to claim 3, characterized in that: The virtual GPU thread task block space is used to store statically allocated data, specifically: the static allocation method is the space allocation method of the storage location determined during the compilation process of the virtual GPU program, including all global variables of the virtual GPU thread task corresponding to the virtual GPU thread task block space, parameter data passed in when the virtual GPU thread task is started, and stack data during the operation of the virtual GPU thread task.

5. The method for implementing a virtual GPU based on a vectorized instruction set according to claim 1, characterized in that: The virtual GPU thread includes: Logically corresponds to a computing thread running on a GPU core; In terms of computation execution, a scalar unit in the CPU vectorized instruction is used as the actual computation execution carrier; In operation scheduling management, CPU software threads are used as scheduling operation objects.

6. The method for implementing a virtual GPU based on a vectorized instruction set according to claim 5, characterized in that: The CPU software thread is used as the scheduling operation object in the operation scheduling management, including: Controlling the execution of the virtual GPU thread by scheduling the CPU software thread to run or not; A CPU software thread contains multiple virtual GPU threads. The virtual GPU threads in the same CPU software thread can be uniformly scheduled for execution or suspended.

7. The method for implementing a virtual GPU based on a vectorized instruction set according to claim 1, characterized in that: The virtual GPU task manager is used to create all task block spaces for each virtual GPU thread, and configure and start the virtual GPU thread tasks, specifically: Create a task block space for each virtual GPU thread according to the total number of GPU task threads required; According to the number of virtual GPU threads contained in each CPU thread, manage and organize the base address information of the task block space corresponding to the virtual GPU threads contained in the CPU thread; Organize corresponding data according to the data required for the virtual GPU thread to run, and pass the corresponding data as parameters to the CPU thread when creating the CPU thread; Determine the number of CPU threads that need to be created and run based on the total number of virtual GPU threads required.

8. The method for implementing a virtual GPU based on a vectorized instruction set according to claim 7, characterized in that: The corresponding data include: Virtual GPU thread task dimension information, including the size of each dimension; ID information of the virtual GPU thread; The base address of the task block space corresponding to the virtual GPU thread; Input parameters passed by external tasks to the virtual GPU thread tasks.

9. The method for implementing a virtual GPU based on a vectorized instruction set according to claim 1, characterized in that: The virtual GPU task compilation tool is specifically used for: Organize the data access, calculation and jump control of the virtual GPU program in the form of scalable vectorized instructions; Determine the number of virtual GPU threads in a single CPU thread according to the number and performance of scalable vectorized instruction computing engines, scalable vectorized general vector registers, and scalable vectorized mask registers in the physical CPU; Provide key information required for the operation of the virtual GPU thread to the outside, including the minimum size requirement of the virtual GPU thread task block space and the format of the data that needs to be externally filled in the virtual GPU task.

10. A device for implementing a virtual GPU based on a vectorized instruction set, characterized in that: It comprises one or more processors, and is used to implement a method for implementing a virtual GPU based on a vectorized instruction set as described in any one of claims 1-9.

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