Layered memory page management method and system based on random dynamic access memory and heterogeneous memory

Abstract

The invention discloses a hierarchical memory page management method and system based on a random dynamic access memory and a heterogeneous memory. The hierarchical memory page management method comprises the following steps: defining the random dynamic access memory as the uppermost layer; all the heterogeneous memories are divided into corresponding hierarchies; calculating a comprehensive performance index of each hierarchy, and determining a hierarchy sequence; and dynamically determining the upgrade or degradation of the page according to the access frequency of the page and the comprehensive performance index of the hierarchy to which the heterogeneous memory belongs based on a preset intelligent page migration algorithm by taking the maximum system performance gain as a target, thereby completing the hierarchical memory page management. All the heterogeneous memories are divided into the corresponding hierarchies to facilitate management of the operating system, the heterogeneous memories with different performances are fully and reasonably utilized, after the hierarchies of the heterogeneous memories are divided, movement of the memory data among the different memory hierarchies is optimized by the preset algorithm, and the memory data can be effectively and effectively utilized under the condition that the influence on the system performance is not large. And the memory data is placed at a proper position, so that the performance gain is maximized.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory page management, and in particular relates to a hierarchical memory page management method and system based on random dynamic access memory and heterogeneous memory. Background Art

[0002] In recent years, the emergence of various new heterogeneous memories has improved the performance crisis caused by the traditional DRAM memory, which was originally stretched to its limits. However, an important issue is that, in terms of hardware, heterogeneous memory has become a reality and even commercially available (such as NVM, etc.), but the use of heterogeneous memory in software is relatively primitive, that is, using heterogeneous memory as another NUMA node, but this is not the best practice for heterogeneous memory, because it does not have a corresponding computing node, and its performance characteristics are not suitable for treating it as the memory of a NUMA node. At present, memory hierarchical management mechanisms have emerged (such as TPP, Nomad, etc.), but these management mechanisms only optimize the application running memory (anonymous memory), and do not optimize the I / O performance that really affects system performance. Summary of the invention

[0003] In view of the above problems, the present invention proposes a hierarchical memory page management method and system based on random dynamic access memory and heterogeneous memory. The present invention divides all heterogeneous memories into corresponding levels for the convenience of operating system management, and makes full and reasonable use of heterogeneous memories with different performances. After dividing the heterogeneous memory levels, the movement of memory data between different memory levels is optimized by a preset algorithm. The memory data is placed in a suitable position without much impact on system performance, thereby maximizing performance gain.

[0004] In order to achieve the above technical objectives and the above technical effects, the present invention is implemented through the following technical solutions:

[0005] In a first aspect, the present invention provides a hierarchical memory page management method based on random dynamic access memory and heterogeneous memory, comprising:

[0006] Define the random dynamic access memory as the uppermost layer;

[0007] Based on the preset hierarchical indicators, all heterogeneous memories are divided into corresponding levels;

[0008] Calculate the comprehensive performance indicators of each level and determine the level order;

[0009] With the goal of maximizing system performance gain, based on the preset intelligent page migration algorithm, the upgrade or downgrade of the page is dynamically determined according to the page access frequency and the comprehensive performance indicators of the layer to which the heterogeneous memory belongs, thus completing the hierarchical memory page management.

[0010] In conjunction with the first aspect, optionally, the hierarchical indicators include: hardware implementation technology, hardware connection mode and hardware performance indicators;

[0011] When the hardware implementation technology and hardware connection methods of two heterogeneous memories are the same, and their hardware performance indicators meet the preset requirements, they are classified into the same level;

[0012] The hardware performance indicators include throughput and latency. When comparing hardware performance indicators, the following are specifically included:

[0013] For two heterogeneous memories in different regions, when the throughput difference and access latency between the two are both smaller than the corresponding thresholds, the two are classified into the same level.

[0014] In combination with the first aspect, optionally, the comprehensive performance index of each level is calculated by the following formula:

[0015] ;

[0016] in, For level Comprehensive performance indicators; are the weight factors of the sub-item performance indicators respectively; Level Standardized values ​​of sub-item performance indicators;

[0017] The level Standardized values ​​of sub-item performance indicators Calculated by the following formula:

[0018]

[0019] in, For the The sample mean of the sub-item performance indicators, , For the Level Item performance indicators, , is the total number of levels;

[0020]

[0021] in, For the The sample standard deviation of the sub-item performance indicators;

[0022] ;

[0023] in, For level No. Standardized values ​​of performance indicators of each item;

[0024] The hierarchical order is determined by:

[0025] The levels are sorted according to the size of the comprehensive performance indicators of each level. The larger the comprehensive performance indicator, the higher the level it is in.

[0026] In combination with the first aspect, optionally, the random dynamic access memory and the heterogeneous memory are uniformly managed using pages, wherein pages are downgraded in the random dynamic access memory in an LRU manner, or upgraded and downgraded in the current heterogeneous memory; the random dynamic access memory has a waiting area, and each heterogeneous memory has two waiting areas for page upgrades and page downgrades, each waiting area has queues equal to the number of CPU cores, and pages that need to be migrated will first be placed in the queue of the CPU core corresponding to the waiting area to wait for operation.

[0027] In combination with the first aspect, optionally, if the memory in the current level is insufficient, the page is downgraded, specifically including:

[0028] By approximating the least recently used method, the coldest page in the current tier that has not yet entered the waiting area is marked as waiting for demotion;

[0029] Send pages marked as waiting for demotion to a specific waiting area;

[0030] According to the CPU core currently processing the downgrade process, the page pointer is moved to the queue of the corresponding CPU core. If the page currently in the waiting area is accessed, it is removed from the waiting area and placed at the head of the LRU list of the current level.

[0031] When the queue to which a CPU core belongs is full, or the number of free pages at the current level is less than the preset percentage of the memory at the current level, the corresponding CPU core will start to perform batch page downgrades, including: the CPU core copies all pages in the queue to the next level. If the pages are modified at this time, the pages at the current level and the pages at the next level are changed synchronously.

[0032] In combination with the first aspect, optionally, the CPU core copies all pages in the queue to the next level, and if a page therein is modified at this time, the page of the current level and the page of the next level are synchronously modified, including the following steps:

[0033] The CPU core corresponding to the queue allocates free memory of the corresponding size in the target layer. If the target layer does not have the corresponding number of free pages, the migration is suspended and the memory recycling thread is actively awakened to wait for the free memory size of the target layer to be larger than the preset percentage of the current layer memory.

[0034] The CPU core corresponding to the queue copies the pages in the queue to the new level in batches. During the copying process, the page table entries of the copied pages are marked as read-only. After the copying is completed, the current page is marked with a locked status bit and the Present bit in the page table entry is cleared.

[0035] The operating system updates the page table entries, maps the virtual addresses to the new physical pages, and executes the translation lookaside buffer to ensure that the page table caches of all CPU cores are synchronized with the new page tables;

[0036] After the page is copied, the page address indicated in the page table cache is changed to the corresponding page address in the next level;

[0037] Unlock the page.

[0038] Mark old pages in the current level as invalid.

[0039] In combination with the first aspect, optionally, the memory recovery thread is a process located in the operating system kernel, which exists in the kernel when the operating system starts. When the memory in a certain layer is insufficient, the process switches from a sleep state to an active state, and begins to downgrade pages on the layer with insufficient free space from the current level to the next level, or moves them out of the heterogeneous memory.

[0040] In combination with the first aspect, optionally, the process of executing the downgrade of the page also includes:

[0041] The page that is accessed and entered into the memory for the first time is moved out of the random dynamic access memory, and the access information is recorded in the random dynamic access memory;

[0042] The hierarchical memory page management method further includes:

[0043] The re-return distance is used to determine whether the page should re-enter the random dynamic access memory or the appropriate level of heterogeneous memory when the page is accessed next time. The re-return distance describes how many times a page is accessed within the time interval after it is removed from the random dynamic access memory and accessed again. The access counter is used to count global events to predict the access distance of a page. The access distance is called the page age. When describing the distance a page moves to the end in the LRU list, it is necessary to count the number of pages added to the LRU list before the page position. As long as a page is no longer accessed, the LRU algorithm ensures that each page inserted in front of the LRU list will move the page back one position.

[0044] The factors affecting the page age include: (1) newly accessed pages. If all levels are regarded as an LRU list in order, the newly accessed page is inserted into the head of the LRU list of the random dynamic access memory, and the current page is regarded as moving back one position; (2) upgraded pages, including the pages accessed in the LRU list of the current level and the upgraded pages in the next level;

[0045] When the page is accessed again, the above-mentioned re-return distance is used to determine whether the page needs to enter the next level of memory or be evicted again when it leaves the random dynamic access memory next time; if the re-return distance of the page during the evicted stage is less than the sum of the sizes of all memories except the random dynamic access memory, then it is necessary for the page to enter the next level of memory when it leaves the random dynamic access memory next time; otherwise, it will be evicted from the memory again.

[0046] In combination with the first aspect, optionally, the page upgrade refers to migrating a page from a heterogeneous memory to a heterogeneous memory or random dynamic access memory at a higher level than the page; when the number of page accesses reaches a certain threshold within a certain time range, the page upgrade is performed, specifically including the following steps:

[0047] If the number of visits to a page reaches the threshold, the page will be placed in the upgrade queue of the CPU core corresponding to the waiting area; when the number of pages in the upgrade list reaches a certain number, these pages will be moved to the memory of the previous level at one time; among them, the page age used to record the visit information will be cleared when the page is upgraded, so that the re-return distance can be recalculated the next time it is returned, and the visit counts of other pages that have not been upgraded are also updated regularly;

[0048] The re-return distance describes how many times a page is accessed within a time interval after being removed from the random dynamic access memory and then accessed again, and uses an access counter to count global events to predict the access distance of a page, and the access distance is called page age;

[0049] The factors affecting the page age include: (1) newly accessed pages. If all levels are regarded as an LRU list in order, the newly accessed page is inserted into the head of the LRU list of the random dynamic access memory, and the current page is regarded as moving backward by one position; (2) upgraded pages, including the pages accessed in the LRU list of the current level and the upgraded pages in the next level.

[0050] In a second aspect, the present invention provides a hierarchical memory page management system based on random dynamic access memory and heterogeneous memory, including a storage medium and a processor;

[0051] The storage medium is used to store instructions;

[0052] The processor is configured to operate according to the instructions to execute the method according to any one of the first aspects.

[0053] Compared with the prior art, the present invention has the following beneficial effects:

[0054] The present invention divides all heterogeneous memories into corresponding levels for easy management by the operating system, and makes full and reasonable use of heterogeneous memories with different performances. After dividing the heterogeneous memory levels, the movement of memory data between different memory levels is optimized by a preset algorithm, and the memory data is placed in a suitable position without much impact on system performance, thereby maximizing performance gains.

[0055] The present invention utilizes the file system page cache mechanism of the operating system, and expands the file system page cache to heterogeneous memory (such as NVM, CXL memory) while retaining the anonymous memory hierarchical management mechanism, and is supplemented by a variety of optimizations and algorithms to ensure superior performance.

[0056] The present invention is mainly applicable to the operating system level, ensuring the compatibility of upper-layer applications. No modification is required for heterogeneous memory, and applications can also benefit from the performance improvement brought by heterogeneous memory when using system calls to perform a large number of I / O operations. Current work mainly focuses on anonymous memory, and its focus is mainly on the running memory of applications. But in fact, the performance levels such as read and write speed and latency required by the running memory of applications may far exceed the performance indicators of heterogeneous memory. Therefore, a better way to utilize heterogeneous memory is to use it for the page cache part of the file system.

[0057] In terms of memory layout, the present invention has three hyperparameters when dividing the memory hierarchy: ) can be specified to flexibly adjust the tiering strategy according to the characteristics of the system load and the system's sensitivity to performance impact. In memory page migration, a configurable threshold is used to determine the indicator for page promotion, retaining the possibility of performance tuning based on the type of system load. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor, among which:

[0059] Figure 1 The present invention is a schematic diagram of a hierarchical memory page management method based on random dynamic access memory and heterogeneous memory according to an embodiment of the present invention.

[0060] Figure 2 A schematic diagram of a memory layered architecture according to an embodiment of the present invention, wherein the performance relationship is obtained based on market data research, and the actual performance level may be different from this;

[0061] Figure 3 The present invention provides a page eviction mechanism based on the CLOCK algorithm according to an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0064] The implementation of the present invention is based on the following premises:

[0065] 1. The access mode of heterogeneous memory is the same as that of random dynamic access memory (hereinafter referred to as DRAM), such as accessing row size, memory data organized by bit, and accessing data by address. In other words, heterogeneous memory and DRAM should be able to exchange and migrate data in some way with the intervention of the CPU. At the same time, the basic unit of heterogeneous memory management space in the operating system should be the same as DRAM, organized as pages.

[0066] 2. Heterogeneous memory and DRAM need to be supported and accessible by the operating system at the same time. In other words, heterogeneous memory and DRAM are online and accessible at the same time.

[0067] 3. The hardware performance of the heterogeneous memory used is worse than that of DRAM. Existing heterogeneous memories (such as NVM, CXL, etc.) all meet this premise.

[0068] In the specific implementation process, data exchange between DRAM and heterogeneous memory is realized through hardware interface adapters (such as QPI, UPI, CCIX, CXL and other protocols or interface buses). The adapter is responsible for handling the communication protocol and data format conversion between different memory types. In hardware, there is no need to implement any specific strategy, just to ensure that data can be exchanged normally between all memories and the operating system supports the use of such exchange.

[0069] Example 1

[0070] The embodiment of the present invention provides a hierarchical memory page management method based on random dynamic access memory and heterogeneous memory, including two parts: memory hierarchical organization structure and memory page operation. Figure 1 As shown, the specific steps include:

[0071] (1) Define random dynamic access memory as the top layer;

[0072] (2) Based on the preset hierarchical indicators, all heterogeneous memories are divided into corresponding levels;

[0073] (3) Calculate the comprehensive performance indicators of each level and determine the level order;

[0074] (4) With the goal of maximizing system performance gain, based on a preset intelligent page migration algorithm, the upgrade or downgrade of a page is dynamically determined according to the page access frequency and the comprehensive performance indicators of the heterogeneous memory layer to which it belongs, thus completing hierarchical memory page management.

[0075] The hierarchical memory page management method in the embodiment of the present invention divides all heterogeneous memories into corresponding levels for the convenience of operating system management, and makes full and reasonable use of heterogeneous memories with different performances. After the heterogeneous memory levels are divided, the movement of memory data between different memory levels is optimized by a preset algorithm, and the memory data is placed in a suitable position without much impact on system performance, thereby maximizing performance gains.

[0076] In a specific implementation of the embodiment of the present invention, the hierarchical indicators include: hardware implementation technology, hardware connection mode and hardware performance indicators;

[0077] When the hardware implementation technology and hardware connection methods of two heterogeneous memories are the same, and their hardware performance indicators meet the preset requirements, they are classified into the same level;

[0078] The hardware performance indicators include throughput and latency. When comparing hardware performance indicators, the following are specifically included:

[0079] For two heterogeneous memories in different regions, when the difference in their throughput and latency are both smaller than the corresponding thresholds, they are classified into the same level.

[0080] In a specific implementation of the embodiment of the present invention, the comprehensive performance index of each level is calculated by the following formula:

[0081] ;

[0082] in, For level Comprehensive performance indicators; are the weight factors of the sub-item performance indicators respectively; Level Standardized values ​​of sub-item performance indicators;

[0083] The level Standardized values ​​of sub-item performance indicators Calculated by the following formula:

[0084]

[0085] in, For the The sample mean of the sub-item performance indicators, , For the Level Item performance indicators, , is the total number of levels;

[0086]

[0087] in, For the The sample standard deviation of the sub-item performance indicators;

[0088] ;

[0089] in, For level No. Standardized values ​​of performance indicators of each item;

[0090] The hierarchical order is determined by:

[0091] The levels are sorted according to the size of the comprehensive performance index of each level. The larger the comprehensive performance index, the higher the level it is in. In the specific implementation process, the operating system (Linux, UNIX, BSD, Windows, etc.) needs to expand its memory management module to support pages of different sizes (such as 4KB, 2MB, 1GB, etc.), use the memory tiering algorithm designed by the present invention, and implement the LRU management mechanism of the page.

[0092] In a specific implementation of the embodiment of the present invention, the random dynamic access memory and the heterogeneous memory are uniformly managed using pages, wherein the page is downgraded in the random dynamic access memory in an LRU manner, or upgraded and downgraded in the current heterogeneous memory; the random dynamic access memory has a waiting area, and each heterogeneous memory has two waiting areas, (i.e. Figure 1 The waiting zone in the waiting area is used for page upgrade and page downgrade. Each waiting area has a waiting area queue equal to the number of CPU cores. The page that needs to be migrated will first be placed in the waiting area queue of the CPU corresponding to the waiting area to wait for operation.

[0093] In a specific implementation of the embodiment of the present invention, if the memory in the current level is insufficient, the page is downgraded, specifically including:

[0094] By approximating the least recently used method, the coldest page in the inner layer of the current level that has not yet entered the waiting area is marked as waiting for demotion;

[0095] Send pages marked as waiting for demotion to a specific waiting area;

[0096] According to the CPU core currently processing the downgrade process, the page pointer is moved to the waiting area queue of the corresponding CPU core. If the page currently in the waiting area is accessed, it is removed from the waiting area and placed in the LRU list of the current level (i.e. Figure 1The head of the Memory LRU List in the Memory LRU List;

[0097] When the queue to which a CPU core belongs is full, or the number of free pages at the current level is less than the preset percentage of the memory at the current level, the corresponding CPU core will start to perform batch page downgrades, including: the CPU core copies all pages in the queue to the next level. If the pages are modified at this time, the pages at the current level and the pages at the next level are changed synchronously.

[0098] In a specific implementation of the embodiment of the present invention, the CPU core copies all pages in the queue to the next level. If a page in the queue is modified at this time, the page of the current level and the page of the next level are synchronously modified, including the following steps:

[0099] The CPU core corresponding to the queue allocates free memory of the corresponding size in the target layer. If the target layer does not have the corresponding number of free pages, the migration is suspended and the memory recycling thread is actively awakened to wait for the free memory size of the target layer to be larger than the preset percentage of the current layer memory.

[0100] The CPU core corresponding to the queue copies the pages in the queue to the new level in batches. During the copying process, the page table entries of the copied pages are marked as read-only. After the copying is completed, the current page is marked with a locked status bit and the Present bit in the page table entry is cleared.

[0101] The operating system updates the page table entries, maps the virtual addresses to the new physical pages, and executes the translation lookaside buffer to ensure that the page table caches of all CPU cores are synchronized with the new page tables;

[0102] After the page is copied, the page address indicated in the page table cache is changed to the corresponding page address in the next level;

[0103] Unlock the page.

[0104] Mark old pages in the current level as invalid.

[0105] In a specific implementation of an embodiment of the present invention, the memory recovery thread is a process located in the operating system kernel, and exists in the kernel when the operating system is started. When the memory in a certain layer is insufficient, the process switches from a sleep state to an active state, and begins to downgrade pages on the layer with insufficient free space from the current level to the next level, or moves them out of the heterogeneous memory.

[0106] In a specific implementation of the embodiment of the present invention, the process of executing page downgrade further includes:

[0107] The page that is accessed and entered into the memory for the first time is moved out of the random dynamic access memory, and the access information is recorded in the random dynamic access memory;

[0108] The hierarchical memory page management method further includes:

[0109] The re-entry distance is used to determine whether the page should re-enter the random dynamic access memory or the appropriate level of heterogeneous memory when the page is accessed next time. The re-entry distance describes how many times a page is accessed within a time interval after it is removed from the random dynamic access memory and accessed again. The access distance of a page is predicted by using access counters to count global events. The access distance is called the page age. In order to describe the distance a page moves toward the end in the LRU list, it is necessary to count the number of pages added to the LRU list before the page position. Before the page is accessed next time, the LRU algorithm ensures that each page inserted in front of the LRU list will move the page back one position.

[0110] (1) Newly accessed pages. If all levels are regarded as an LRU list in order, the newly accessed page is inserted into the head of the LRU list of the random dynamic access memory, and the current page is regarded as moving back one position; (2) Upgraded pages, including the pages accessed in the LRU list of the current level and the upgraded pages in the next level;

[0111] When the page is accessed again, it is determined based on the above re-return distance whether the page needs to enter the next level of memory or be evicted again when it leaves the random dynamic access memory next time; if so, the re-return distance of the page in the evicted stage is less than the sum of the sizes of all memories except the random dynamic access memory, then it is necessary for the page to enter the next level of memory when it leaves the random dynamic access memory next time; otherwise, it is evicted from the memory again.

[0112] In a specific implementation of the embodiment of the present invention, the page upgrade refers to migrating a page from a heterogeneous memory to a heterogeneous memory or random dynamic access memory at a higher level than the heterogeneous memory; when the number of page accesses reaches a certain threshold within a certain time range, the page upgrade is executed, which specifically includes the following steps:

[0113] If the number of visits to a page reaches the threshold, the page will be placed in the upgrade queue of the CPU corresponding to the waiting area; when the number of pages in the upgrade list reaches a certain number, these pages will be moved to the memory of the previous level at one time; among them, the page age used to record the visit information will be cleared when the page is upgraded, so that the re-return distance can be recalculated the next time it is returned, and the visit counts of other pages that have not been promoted are also updated regularly;

[0114] The re-return distance describes how many times a page is accessed within the time interval after it is removed from the random dynamic access memory and then accessed again, and uses an access counter to count global events to predict the access distance of a page. The access distance is called the page age. When describing the distance a page moves toward the end of the LRU list, it is necessary to count the number of pages added to the LRU list before the page position. As long as a page is no longer accessed, the LRU algorithm ensures that each page inserted in front of the LRU list will move the page back one position.

[0115] (1) Newly accessed pages. If all levels are regarded as an LRU list in order, the newly accessed pages are inserted into the head of the LRU list of the random dynamic access memory, and the current page is regarded as moving one position backward; (2) Upgraded pages, including the pages accessed in the LRU list of the current level and the upgraded pages in the next level.

[0116] The hierarchical memory page management method based on random dynamic access memory and heterogeneous memory in the embodiment of the present invention is described in detail below in conjunction with a specific implementation.

[0117] (1) Setting up a hierarchical memory organization structure

[0118] Organize memory into a hierarchical structure, such as Figure 2 As shown in the figure, DRAM, as the memory with the highest performance, is located at the highest level of the memory hierarchy, while the rest of the heterogeneous memory (such as NVM, CXL memory, etc.) is located below DRAM. The hierarchical division between heterogeneous memories is based on device type and device distance, and the device throughput and latency are used as the basis for the hierarchical order. The specific steps include:

[0119] a. Classification based on the hardware implementation technology of heterogeneous memory. For different hardware implementations, for example, NVM uses 3D XPoint technology, while HBM memory uses HBM technology, so the two cannot be classified into the same level.

[0120] b. Classification based on the hardware connection method of heterogeneous memory. For different hardware connection methods, for example, NVM memory and CXL memory, which are both made with 3D XPoint technology, cannot be classified into the same level because the way they are connected to the processor and the bus they use are different. The specific reason is: the connection between NVM and the processor is through the memory bus of the memory controller, and each NVM and DRAM is directly connected to the memory controller. CXL memory is connected to the processor through the PCI-e bus. Depending on the topology of the PCI-e bus, the bus may be shared memory between CXLs or each CXL memory may have independent bandwidth.

[0121] c. Classification based on the performance indicators of heterogeneous memory. Classification is based on the hardware performance indicators (throughput and latency) of different areas. For example, if the transmission latency of the remote memory is larger than that of the near memory (more than 50ns) or the memory bandwidth difference is more than 1000MB / s, the remote CXL memory and the near CXL memory cannot be considered as the same level. Only when the two are within the above difference threshold can they be called the same level.

[0122] In the specific implementation process, in addition to the division based on hardware implementation technology and connection methods, customized hierarchical division can also be considered based on the memory usage scenarios (such as databases, big data analysis, etc.).

[0123] (2) Hierarchical sorting of heterogeneous memory

[0124] Once the hierarchy is confirmed, the hierarchical relationship needs to be confirmed. In the embodiment of the present invention, an algorithm is used for sorting.

[0125] Define a set of performance indicator factors ,The performance indicators that need to be considered at each level of heterogeneous memory are capacity , Throughput and access delay .when hour, Indicates Tier capacity indicator; when hour, Indicates The throughput indicator of the layer; when hour, Indicates For example, in our system, the capacity of the NVM is measured , throughput , access delay .

[0126] After completing the definition and evaluation of the performance indicators of all heterogeneous memory levels, normalize the performance indicator factors of each level. The specific method is:

[0127] For each performance indicator factor in each layer :

[0128] Calculate performance index factors The sample mean of and the sample standard deviation .

[0129]

[0130]

[0131] in, For the The sample mean of the sub-item performance indicators, , For the Level Item performance indicators, , is the total number of levels; For the The sample standard deviation of the sub-item performance indicators;

[0132] Computational level No. The standardized values ​​of the performance indicators of each level are: As the normalized performance indicator of this level, the specific calculation formula is:

[0133] ;

[0134] In the formula, For level No. The standardized value of the sub-item performance indicator.

[0135] In the specific implementation process, a set of weight factors are defined ,satisfy The number of weighting factors should be equal to the number of performance indicators considered. Currently, the weighting factor capacity , Throughput and delay The weight factor can be adjusted according to the actual scenario. The current strategy is to manually set the weight factor to , , The weights here can be tuned based on the specific performance preferences of the system. For example, in a latency-sensitive system, The proportion of throughput can be appropriately increased; in throughput-sensitive systems, the throughput As for capacity, its impact on performance is actually more complicated. Generally speaking, the better the throughput and latency indicators, the higher the unit cost and the smaller the capacity. In fact, regardless of whether the system cost is considered, the memory with higher performance indicators should be placed at the top of the hierarchy. In the specific implementation process, the thresholds of performance indicators (such as access latency, throughput, etc.) can be adjusted according to the specific hardware performance and system requirements.

[0136] Calculate the comprehensive performance index: For each level of memory, calculate its final comprehensive performance index based on its normalized performance index and the corresponding weight factor .in,

[0137] ;

[0138] In the formula, For level Comprehensive performance indicators; are the weight factors of the sub-item performance indicators respectively; Level Standardized values ​​of sub-item performance indicators.

[0139] Finally, the comprehensive performance indicators of all heterogeneous memory levels Sort. The higher ones are located above the hierarchy.

[0140] In addition, if there are different memories in the same level, the order of memory usage can be arbitrarily determined within the level. Each memory in the same level will only migrate data when data enters or leaves the level (when data is transferred in or out, the memory location where the data is stored is determined based on the used capacity of different memories in the level), and memory data will not be migrated within the level.

[0141] (3) Defining data structures in heterogeneous memory

[0142] Heterogeneous memory and DRAM are uniformly managed in the form of pages, including ordinary pages and large pages such as 4KB pages, 2MB pages, and 1GB pages. Among them, pages are downgraded in random dynamic access memory in the LRU manner, or upgraded and downgraded in the current heterogeneous memory. The random dynamic access memory has only one waiting area for downgrade operations; each layer of heterogeneous memory has two waiting areas, which are used for page upgrades and page downgrades respectively. Among them, each waiting area has queues equal to the number of CPU cores, and the pages that need to be migrated will first be placed in the queue of the CPU core corresponding to the waiting area to wait for operations. In the specific implementation process, the size of the page can be parameterized according to the needs of the system to adapt to different application scenarios.

[0143] (4) Page operations between memory levels

[0144] Once the hierarchical relationship between memories is formed, the operations and algorithms for data migration between memories are established.

[0145] When a page is accessed for the first time, it will be placed in the page cache of the operating system. If a page has not been accessed for a period of time, a new page will be placed in the page cache, and the unaccessed page will be removed from the page cache due to limited memory space. Since the page cache of the operating system is extended in the embodiment of the present invention, when a page cannot be placed in the system memory (DRAM), other locations (heterogeneous memory) can be considered.

[0146] In addition, if the original operating system double linked lists (Active List and Inactive List) are used, it will also be quite difficult. The original page cache mechanism uses the method of modifying pointers when processing page location modifications, and the physical location (physical address) of the original data has not changed. However, the premise of this solution is that the pages exist in the same hardware storage medium, or the status of these storage devices is the same. But contrary to expectations, the performance of heterogeneous memory is somewhat different from that of DRAM. If DRAM and heterogeneous memory are directly mixed, the memory performance will be seriously degraded due to the mutual dependence of memory data.

[0147] Therefore, in order to properly treat heterogeneous memory and DRAM differently, it is necessary to consider page migration between heterogeneous memory and DRAM. There are two types of page migration: page promotion and page demotion. Page promotion refers to migrating a page from heterogeneous memory to DRAM, while page demotion refers to migrating a page from DRAM to heterogeneous memory. The overall goal of page migration is to place hotter data on faster DRAM and cooler data on slower heterogeneous memory. Although the migration operation will result in data movement overhead, the purpose is to place the page in the appropriate location to increase cache capacity, thereby promoting overall performance improvement.

[0148] (4.1) Page Demotion

[0149] (4.1.1) Bulk, per-CPU page downgrade

[0150] When the upper memory is sufficient, no page needs to be demoted, because according to the above memory hierarchical organization structure, the performance of the upper memory is better than that of the lower memory. Only when the upper memory is insufficient, the cold page in the upper memory needs to be demoted to the next level page.

[0151] a. Before the downgrade operation begins, the downgraded page needs to enter a specific waiting area. First, Figure 3As shown, through the method of approximate least recently used (Approximate LRU) (i.e., CLOCK algorithm), the coldest page in the current level that has not yet entered the waiting area (the page that needs to be downgraded scanned by the CLOCK algorithm) is marked as waiting for downgrade, and the page marked as waiting for downgrade is sent to a specific waiting area, and according to the CPU core currently processing the downgrade process, the page pointer is moved to the queue of the corresponding CPU core (one CPU core manages one queue). In addition, if the page currently in the waiting area is accessed, it is removed from the waiting area again and placed at the head of the LRU list of the current level. The present invention performs page selection based on the CLOCK algorithm to determine which pages need to be downgraded. At the same time, the independence of the CPU is used to reduce the synchronization overhead of page migration. In the specific implementation process, in addition to the CLOCK algorithm, other page replacement algorithms, such as LRU, FIFO, etc., can be considered, and the most appropriate algorithm is selected according to the specific needs and performance characteristics of the system.

[0152] b. When the queue to which a CPU core belongs is full, or the number of free pages at the current level reaches the low watermark (that is, the number of free pages at the current level is less than the preset percentage of the memory at the current level), the corresponding CPU core (or all queues) will start to perform batch page downgrades. First, the CPU core copies all pages in the queue to the next level. If a page is modified at this time (the CPU core marks the page as dirty), the page at the current level and the page at the next level will be changed synchronously. The external manifestation of "modification" is that a flag corresponding to the page is set to Dirty. The modification here refers to the substantial change to the page data. After the change is completed, the system will automatically set the page flag to dirty (the operation marked as dirty is the original operation of the system, not the innovation of the present invention, but this feature is used here to determine whether the page has changed compared to before the copy). The specific algorithm is as follows.

[0153] a) First, the CPU corresponding to the queue allocates the corresponding amount of free memory in the target layer. If the target layer does not have the corresponding number of free pages, the migration is suspended, the memory recycling thread is actively awakened, and the target layer's free memory size increases to the low watermark again (that is, greater than the preset percentage of the current layer's memory).

[0154] b) Then, the CPU corresponding to the queue copies the pages in the queue to the new memory level in batches. During the copying process, the page table entries (PTE) are marked as read-only. After the copying is completed, the lock status bit of the current page is marked and the Present bit in the page table entry (PTE) is cleared. The above operations are atomic.

[0155] c) The operating system updates the PTE (Page Table Entry), maps the virtual address to the new physical page, and performs a TLB Shootdown (Translation Lookaside Buffer, used to convert the virtual address (VA) to the physical address (PA)) to ensure that the new page tables of the TLBs of all CPUs are synchronized.

[0156] e) After the page is copied, the page address indicated in the cache TLB is changed to the corresponding page address in the next level.

[0157] f) Unlock the page.

[0158] g) Finally, mark the old pages in the current level as invalid.

[0159] This page demotion is more efficient due to the use of batch and CPU-independent demotion methods.

[0160] (4.1.2) Selective page downgrade mechanism

[0161] In order to prevent the demotion of useless pages, a selective demotion mechanism is introduced.

[0162] According to the 20-80 rule, a page that is accessed and enters the cache for the first time is unlikely to be accessed again. Therefore, when such a page is about to be moved out of DRAM for the first time, it will no longer enter the next memory level, but will be directly evicted from the memory and the access information will be recorded in the DRAM as a shadow entry. After that, we can use the re-entry distance to determine the location where the page should re-enter the cache when it is accessed next time.

[0163] The re-return distance is actually the number of pages accessed, describing how many times a page is accessed within the time interval between when a page is removed from the cache and then accessed again (re-returned). We use a counter to count global events to predict the access distance of a page, which is called page age. In order to describe the distance a page moves toward the end of the LRU list, it is necessary to count the number of pages added to the LRU list before the page position. As long as a page is no longer accessed, the LRU algorithm ensures that each page inserted in front of the LRU list will move the page back one position.

[0164] For ease of understanding, assume that the page is still in memory, and we call it a Pseudo Page. The page does not actually exist in memory, and all that is needed is that the page moves with the LRU. Therefore, we can conclude that there are two types of pages that can cause the Pseudo Page position to move backward: (1) Newly accessed pages, which are inserted into the head of the DRAM LRU list. If all memory levels are viewed as an LRU list in order, the PseudoPage at this time actually moves one position backward; (2) Upgraded pages, which include pages accessed in the current level LRU and upgraded pages in the next level.

[0165] When a page is accessed again, we can decide whether the page needs to enter the next level of memory or be evicted again based on the above re-return distance when it leaves DRAM next time. If the re-return distance of the page during the eviction phase is less than the sum of the sizes of all memories (except DRAM), then it is necessary for the page to enter the next level of memory the next time it leaves DRAM; otherwise, it will be evicted from memory again.

[0166] The page downgrade algorithm is as follows:

[0167] Global variable definition:

[0168] global_age_cnt: records the global age count, which is used to determine the usage of the page.

[0169] shadow_entry: used to store the age information of each page.

[0170] Processing of page reaching the end (PAGEARRIVETAIL):

[0171] When a page first reaches the tail of the DRAM page cache, the algorithm checks the next destination for the page.

[0172] If the next destination of the page is the heterogeneous page cache (HMEM), the page is marked as ready for demotion to the heterogeneous page cache.

[0173] If not, the page is marked as ready for eviction from the page cache.

[0174] Finally, update the page's age in shadow_entry to the current global age count.

[0175] Page fault handling (PAGEFAULT):

[0176] When a page fault occurs, the algorithm calculates the page fault distance of the page, which is the current global age count minus the age of the page.

[0177] If the page fault distance is less than or equal to the size of the heterogeneous page cache, the page is targeted to the heterogeneous page cache.

[0178] Otherwise, the page's target is set to NULL, indicating that it will not be migrated.

[0179] (4.2) Page upgrade

[0180] The process of page upgrade is the same as that of page downgrade, but the process of judging the pages to be upgraded and downgraded is slightly different. Since the overhead of page migration is large and the capacity of the upper-level memory is generally smaller than the current-level memory, it is necessary to carefully consider the pages that need to be upgraded. Only pages whose page access times reach a certain threshold within a certain time range are allowed to be promoted. In the specific implementation process, the certain threshold can be defined as 4 in combination with the restrictions of the system pages and the experience of testing.

[0181] If the number of visits to a page reaches the threshold, the page will be placed in the upgrade queue of the CPU corresponding to the waiting area; when the number of pages in the upgrade list reaches a certain number, these pages will be moved to the upper-level memory at one time; among them, the age information in the shadow entry used to record the visit information when the page is upgraded will be cleared to enable the re-return distance to be recalculated the next time it is returned, and the number of visits to the remaining pages that have not been promoted will also be updated regularly.

[0182] The page upgrade algorithm is as follows:

[0183] Global variable definition: Define several global variables, including access threshold (access_threshold), page promotion vector (promote_page_vec), promotion threshold (promote_threshold), and shadow entry (shadow_entry).

[0184] Procedure MARKPAGEACCESSED(page):

[0185] Receives a page as input.

[0186] Increase the access count (access_cnt) of the page by 1, but not exceeding the access threshold.

[0187] Checks whether the location of the page is in high performance memory (HMEM) and whether the access count reaches the access threshold.

[0188] If the page is not in the promoted page vector, and the size of the promoted page vector is less than or equal to the promotion threshold, the page is added to the promoted page vector.

[0189] If the size of the promoted page vector has reached the promotion threshold, the corresponding logic is executed.

[0190] End the process.

[0191] (4.3) Page Eviction

[0192] Use memory recycling thread to implement page eviction:

[0193] The memory recycling thread is a process located in the operating system kernel. It exists in the kernel when the operating system starts. When the memory in a certain memory level is insufficient (reaching the low water mark, refer to the above modification here), the process switches from the sleep state (also known as the suspended state) to the active state, and begins to downgrade the pages on the memory level with insufficient free space from the current page level to the next memory level, or moves them out of the heterogeneous memory.

[0194] In the embodiment of the present invention, the access counter is updated in such a way that the garbage collection thread is woken up at a fixed time, and the thread traverses all pages and subtracts 1 from the access counter of each page.

[0195] In a specific implementation process, the triggering condition for page upgrade may be based on the access mode of the page. For example, an access mode identifier may be set to determine whether an upgrade is required based on the access mode of the page.

[0196] Example 2

[0197] Based on the same inventive concept as that of Example 1, the present invention provides a hierarchical memory page management system based on random dynamic access memory and heterogeneous memory, including a storage medium and a processor;

[0198] The storage medium is used to store instructions;

[0199] The processor is configured to operate according to the instructions to execute the method according to any one of the embodiments 1.

[0200] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0201] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0202] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0203] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0204] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

[0205] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A hierarchical memory page management method based on random dynamic access memory and heterogeneous memory, characterized in that: include: Define the random dynamic access memory as the uppermost layer; Based on the preset hierarchical indicators, all heterogeneous memories are divided into corresponding levels; Calculate the comprehensive performance indicators of each level and determine the level order; With the goal of maximizing system performance gain, based on a preset intelligent page migration algorithm, the upgrade or downgrade of a page is dynamically determined according to the page access frequency and the comprehensive performance indicators of the heterogeneous memory layer to which it belongs, thus completing hierarchical memory page management.

2. The hierarchical memory page management method based on random dynamic access memory and heterogeneous memory according to claim 1, characterized in that: The hierarchical indicators include: hardware implementation technology, hardware connection mode and hardware performance indicators; When the hardware implementation technology and hardware connection methods of two heterogeneous memories are the same, and their hardware performance indicators meet the preset requirements, they are classified into the same level; The hardware performance indicators include throughput and latency. When comparing hardware performance indicators, the following are specifically included: For two heterogeneous memories in different regions, when the throughput difference and access latency between the two are both smaller than the corresponding thresholds, the two are classified into the same level.

3. The hierarchical memory page management method based on random dynamic access memory and heterogeneous memory according to claim 1, characterized in that: The comprehensive performance index of each level is calculated by the following formula: ； in, For level Comprehensive performance indicators; are the weight factors of the sub-item performance indicators respectively; Level Standardized values ​​of sub-item performance indicators; The level Standardized values ​​of sub-item performance indicators Calculated by the following formula: ； in, For the The sample mean of the sub-item performance indicators, , For the Level Item performance indicators, , is the total number of levels; ； in, For the The sample standard deviation of the sub-item performance indicators; ； in, For level No. Standardized values ​​of performance indicators of each item; The hierarchical order is determined by: The levels are sorted according to the size of the comprehensive performance indicators of each level. The larger the comprehensive performance indicator, the higher the level it is in.

4. The hierarchical memory page management method based on random dynamic access memory and heterogeneous memory according to claim 1, characterized in that: The random dynamic access memory and the heterogeneous memory are uniformly managed in a page manner, wherein the page is downgraded in the random dynamic access memory in an LRU manner, or upgraded and downgraded in the current heterogeneous memory; the random dynamic access memory has a waiting area, and each heterogeneous memory has two waiting areas for page upgrade and page downgrade, each waiting area has a queue equal to the number of CPU cores, and the page to be migrated will first be placed in the queue of the CPU core corresponding to the waiting area to wait for operation.

5. The hierarchical memory page management method based on random dynamic access memory and heterogeneous memory according to claim 1 or 4, characterized in that: If there is insufficient memory in the current level, the page is downgraded, including: By approximating the least recently used method, the coldest page in the current tier that has not yet entered the waiting area is marked as waiting for demotion; Send pages marked as waiting for demotion to a specific waiting area; According to the CPU core currently processing the downgrade process, the page pointer is moved to the queue of the corresponding CPU core. If the page currently in the waiting area is accessed, it is removed from the waiting area and placed at the head of the LRU list of the current level. When the queue to which a CPU core belongs is full, or the number of free pages at the current level is less than the preset percentage of the memory at the current level, the corresponding CPU core will start to perform batch page downgrades, including: the CPU core copies all pages in the queue to the next level. If the pages are modified at this time, the pages at the current level and the pages at the next level are changed synchronously.

6. The hierarchical memory page management method based on random dynamic access memory and heterogeneous memory according to claim 5, characterized in that: The CPU core copies all pages in the queue to the next level. If a page is modified at this time, the page of the current level and the page of the next level are changed synchronously, including the following steps: The CPU core corresponding to the queue allocates free memory of the corresponding size in the target layer. If the target layer does not have the corresponding number of free pages, the migration is suspended and the memory recycling thread is actively awakened to wait for the free memory size of the target layer to be larger than the preset percentage of the current layer memory. The CPU core corresponding to the queue copies the pages in the queue to the new level in batches. During the copying process, the page table entries of the copied pages are marked as read-only. After the copying is completed, the current page is marked with a locked status bit and the Present bit in the page table entry is cleared. The operating system updates the page table entries, maps the virtual addresses to the new physical pages, and executes the translation lookaside buffer to ensure that the page table caches of all CPU cores are synchronized with the new page tables; After the page is copied, the page address indicated in the page table cache is changed to the corresponding page address in the next level; Unlock the page. Mark old pages in the current level as invalid.

7. The hierarchical memory page method based on random dynamic access memory and heterogeneous memory according to claim 6, characterized in that: The memory recovery thread is a process located in the operating system kernel and exists in the kernel when the operating system starts. When the memory in a certain layer is insufficient, the process switches from a sleep state to an active state and begins to downgrade pages on the layer with insufficient free space from the current layer to the next layer, or moves them out of the heterogeneous memory.

8. The hierarchical memory page management method based on random dynamic access memory and heterogeneous memory according to claim 6, characterized in that: The process of performing page downgrade also includes: The page that is accessed and entered into the memory for the first time is moved out of the random dynamic access memory, and the access information is recorded in the random dynamic access memory; The hierarchical memory page management method further includes: The re-return distance is used to determine whether the page should re-enter the random dynamic access memory or the appropriate level of heterogeneous memory when the page is accessed next time. The re-return distance describes how many times a page is accessed within the time interval after it is removed from the random dynamic access memory and accessed again. The access counter is used to count global events to predict the access distance of a page. The access distance is called the page age. When describing the distance a page moves to the end in the LRU list, it is necessary to count the number of pages added to the LRU list before the page position. As long as a page is no longer accessed, the LRU algorithm ensures that each page inserted in front of the LRU list will move the page back one position. The factors affecting the page age include: (1) newly accessed pages. If all levels are regarded as an LRU list in order, the newly accessed page is inserted into the head of the LRU list of the random dynamic access memory, and the current page is regarded as moving back one position; (2) upgraded pages, including the pages accessed in the LRU list of the current level and the upgraded pages in the next level; When the page is accessed again, the above-mentioned re-return distance is used to determine whether the page needs to enter the next level of memory or be evicted again when it leaves the random dynamic access memory next time; if the re-return distance of the page during the evicted stage is less than the sum of the sizes of all memories except the random dynamic access memory, then it is necessary for the page to enter the next level of memory when it leaves the random dynamic access memory next time; otherwise, it will be evicted from the memory again.

9. A hierarchical memory page management device based on random dynamic access memory and heterogeneous memory according to claim 1 or 4, characterized in that: Page promotion refers to migrating a page from heterogeneous memory to a higher-level heterogeneous memory or random dynamic access memory; When the number of page visits reaches a certain threshold within a certain time range, the page upgrade is executed, which includes the following steps: If the number of visits to a page reaches the threshold, the page will be placed in the upgrade queue of the CPU core corresponding to the waiting area; when the number of pages in the upgrade list reaches a certain number, these pages will be moved to the memory of the previous level at one time; among them, the page age used to record the visit information will be cleared when the page is upgraded, so that the re-return distance can be recalculated the next time it is returned, and the visit counts of other pages that have not been upgraded are also updated regularly; The re-return distance describes how many times a page is accessed within a time interval after being removed from the random dynamic access memory and then accessed again, and uses an access counter to count global events to predict the access distance of a page, and the access distance is called page age; The factors affecting the page age include: (1) newly accessed pages. If all levels are regarded as an LRU list in order, the newly accessed page is inserted into the head of the LRU list of the random dynamic access memory, and the current page is regarded as moving backward by one position; (2) upgraded pages, including the pages accessed in the LRU list of the current level and the upgraded pages in the next level.

10. A hierarchical memory page management system based on random dynamic access memory and heterogeneous memory, characterized in that: including storage media and processors; The storage medium is used to store instructions; The processor is configured to operate according to the instructions to perform the method according to any one of claims 1-9.

Images