A virtualized nested translation method, system and readable medium

Abstract

The present invention relates to a virtualization nested translation method, system and readable medium, comprising receiving a virtual address translation request, judging the address translation mode of the virtual address translation request, and determining the virtual address type; selecting a corresponding translation cache according to the determined virtual address type; performing address translation in a multi-level translation cache in a parallel or serial search mode under the selected translation cache to obtain a search result; judging whether the search result hits a leaf item of a page table; if the search result hits a leaf item, returning a corresponding physical address to complete the translation; if the leaf item is not hit, performing a page table traversal to obtain a physical address. The method can improve the speed of virtualization nested translation, reduce redundant virtual addresses of a translation cache and redundant PTEs of a translation path cache under a single technical condition, and improve the translation delay from a virtual address to a physical address in memory virtualization or peripheral virtualization.

Description

Technical Field

[0001] The present invention relates to the field of processor design, and in particular to a virtualized nested translation method, system and readable medium. Background Art

[0002] As the demand for memory capacity in computer systems continues to grow, paging technology has become an indispensable technology in modern processor architectures. It simplifies memory management by virtualizing physical memory, allowing programs to use memory ranges that exceed the actual physical memory capacity. Many processor architectures introduce a memory management unit (MMU), which is a hardware component responsible for translating virtual addresses into physical addresses. These address translation relationships are stored in a page table called a multi-level unidirectional tree structure, and page table translation involves decomposing the virtual address into a multi-level page table index, using the corresponding level of page table index number and base address to find the page table entry level by level, and finally calculating the physical address.

[0003] However, in a system that supports virtualization, since the physical memory view of the guest operating system (Guest OS) is different from that of the host operating system (Host OS), a second-level address translation is required in the virtualization scenario to convert the guest physical address (GPA) to the host physical address (HPA). Nested Paging technology allows the Guest OS to control its own page table without the intervention of the hypervisor, thereby improving the memory management efficiency in the virtualization scenario, but also increasing the number of memory accesses. If the guest page table has m levels and the host page table has n levels, then nested translation requires at most mn+m+n memory accesses. Usually, in order to increase the address translation speed, the MMU can store the translated address mapping in the TLB (Translation Look-aside Buffer), and a TLB hit can avoid page table traversal. However, as the memory capacity of the CPU continues to increase, there are more and more applications with poor temporal locality and spatial locality, resulting in a low hit rate of the TLB that only caches the end-to-end mapping of virtual addresses to physical addresses, and the penalty of TLB misses is further increased.

[0004] Modern processors cache page table entries (PTEs) through page table caches, translation caches, or translation path caches to reduce the number of memory traversals of the page table for TLB misses and reduce the penalty for TLB misses. These caches can cache PTEs at different page table levels. The page table cache uses the physical address of the PTE in memory to mark it. PTEs from different levels are mixed and stored in the same cache. The cache lines are indexed by the physical address. The address translation of this scheme needs to be serially queried according to the page table structure, and it takes a relatively long time to complete a nested translation. The translation cache uses part of the virtual address for marking, and the caches of virtual address tags of different lengths can be stored separately. Therefore, using this marking scheme, all lookups can be performed independently of each other. Finally, the entry that matches the longest tag of the virtual address is selected because it allows the page table traversal to skip most levels of the page table. The translation path cache uses the full content of the virtual address for marking, and caches all levels of PTE traversed in each translation path into the same cache line, so that a single cache line contains the complete translation path.

[0005] Currently, for virtualized nested translation scenarios, the Page table cache needs to perform serial queries according to the page table structure, resulting in a large translation delay. When the Translation cache has many page table levels, a large amount of redundant virtual address information will be cached in the tag part. On the other hand, if the high-order index locality of the accessed virtual address is good and the low-order index locality is poor, the Translation path cache will cache a large number of high-level page table PTEs, resulting in a large amount of redundant PTE information in the cache lines of the Translation path cache. Summary of the invention

[0006] The present invention provides a virtualized nested translation method, system and readable medium, the purpose of which is to improve the problem of large address translation delay and large amount of cached redundant information in a virtualized nested translation scenario.

[0007] To achieve the above object, the first aspect of the present invention provides a virtualized nested translation method, comprising the following steps:

[0008] receiving a virtual address translation request, determining an address translation mode of the virtual address translation request, and determining a virtual address type;

[0009] According to the determined virtual address type, a corresponding translation cache is selected;

[0010] Under the selected translation cache, performing address translation in the multi-level translation cache in a parallel or serial search mode to obtain a search result;

[0011] Analyze the search results to determine whether the search results hit the leaf item of the page table;

[0012] If the search result hits a leaf item, the corresponding physical address is returned to complete the translation;

[0013] If a leaf entry is not hit, a page table walk is performed to obtain the physical address.

[0014] Furthermore, the virtual address type is determined according to the following rules:

[0015] The address translation modes include iosatp.mode mode and iohgatp.mode mode;

[0016] When both the iosatp.mode mode and the iohgatp.mode mode are not pure physical modes, determining that the requested virtual address type is a client virtual address, and sending the request to the stage one translation buffer unit for stage one translation;

[0017] When the iosatp.mode mode is the pure physical mode and the iohgatp.mode mode is the non-pure physical mode, determining that the requested virtual address type is a client physical address, and sending the request to the stage two translation cache arbitration unit to wait for stage two translation;

[0018] When the iosatp.mode mode is non-pure physical mode and the iohgatp.mode mode is pure physical mode, it is determined that the requested virtual address type is a host virtual address, and the request is sent to the stage one translation buffer unit to wait for stage one translation.

[0019] Furthermore, the multi-level translation cache includes: a stage one translation cache and a stage two translation cache, wherein the stage one translation cache includes a third-level cache, a second-level cache, and a cache unit merged by a first-level cache and a zero-level cache, the third-level cache is used to cache third-level page table entries, the second-level cache is used to cache second-level page table entries, and the merged cache unit is used to cache first-level page table entries and zero-level page table entries at the same time.

[0020] Furthermore, in the parallel search mode, the third-level cache, the second-level cache, and the merged cache unit of the stage one translation cache perform searches simultaneously, and send the search results to the stage one translation result selection unit.

[0021] Furthermore, in the multi-level translation cache search result, if the search result hits the leaf item of the page table, it is further determined whether the current translation request involves nested translation:

[0022] If the current translation request does not involve nested translation, the final translation is completed directly and the physical address is returned;

[0023] If the current translation request involves nested translation, a search request is initiated to the next translation stage for further address translation;

[0024] If the search result does not hit the leaf entry of the page table, the page table traversal unit accesses the memory to complete the page table traversal and fills the traversal result back into the corresponding translation cache.

[0025] Furthermore, after the page table traversal unit accesses the memory and completes the page table traversal, it initiates a backfill request to the translation cache backfill unit according to the page table traversal result, and the backfill unit selects the cache level that needs to be backfilled.

[0026] Further, the translation cache backfill unit selects to backfill the result into the third level cache, the second level cache or the merged cache unit of the stage one translation cache or the stage two translation cache according to the level completed by the page table traversal unit.

[0027] Furthermore, the method also includes performing an invalidation operation on outdated information in the translation cache in the address translation mode, wherein the invalidation operation is performed by the translation cache invalidation unit receiving an invalidation request and sending the invalidation request to the corresponding cache level to clear outdated page table information.

[0028] If the address translation mode is client virtual address or host virtual address, then the lookup stage one translation cache is selected;

[0029] Determine whether a leaf page table entry is hit in the stage 1 translation cache;

[0030] If the leaf page table entry is not hit, traverse the stage 1 page table and complete the stage 1 translation;

[0031] Determine whether it is a nested translation. If it is a nested translation, initiate a request to the translation cache arbitration unit in stage 2, otherwise terminate the translation;

[0032] If the virtual address type is a client physical address, a request is made to the stage 2 translation cache arbitration unit;

[0033] Determine whether the leaf page table entry is hit in the stage 2 translation cache;

[0034] If the leaf page table entry is not hit, the stage 2 translation is completed by traversing the stage 2 page table;

[0035] During the page table traversal, if the stage one page table entry is obtained, the stage two translation cache is accessed to complete the stage two translation.

[0036] Furthermore, in the phase 1 translation cache search or phase 2 translation cache search, the page table entry caches at various levels are read in parallel, including:

[0037] If the lookup request is in SV48 address translation mode, the page table entries at levels 0, 1, 2, and 3 in the stage 1 translation cache are read in parallel;

[0038] If the lookup request is in SV39 address translation mode, the page table entries at levels 0, 1, and 2 in the stage 1 translation cache are read in parallel;

[0039] A judgment is made based on the hit result of the stage 1 translation cache search. If the search directly hits the 0th level page table entry in the stage 1 translation cache, the stage 1 translation is completed.

[0040] Otherwise, determine whether the leaf page table entry at level 1 is hit. If so, the translation of stage 1 is completed.

[0041] Otherwise, determine whether the leaf page table entry at level 2 is hit. If so, the translation of stage 1 is completed.

[0042] Otherwise, determine whether the leaf page table entry at level 3 is hit. If so, the translation of stage 1 is completed.

[0043] Otherwise, the request traverses the page table in stage one.

[0044] Further, the page table entry caches of each level of the stage 1 translation cache or the stage 2 translation cache are selected to be searched serially, including:

[0045] If the lookup request is in SV48 address translation mode, read the first and zeroth level caches to obtain the page table entries of levels 1 and 0;

[0046] If it is a hit, the leaf item is judged. If it is a leaf item, the translation of stage 1 is completed;

[0047] If the search for the first and zeroth level caches hits but misses the leaf entry, the page table is traversed;

[0048] If the search of the first and zero-level caches does not hit, start searching the second-level cache to obtain the second-level page table entry;

[0049] Determine whether the second-level cache is hit. If the leaf item of the second level is hit, the translation of stage 1 is completed;

[0050] If the second-level leaf entry is not hit, the page table is traversed;

[0051] If the search for the second-level cache does not hit, the SV39 address translation mode is determined. If it is the SV39 address translation mode, the page table is traversed;

[0052] If it is SV48 address translation mode, the third-level cache is searched to obtain the third-level page table entry;

[0053] If the third-level cache is not hit, the page table is traversed;

[0054] If the third-level cache is hit, determine whether the leaf item of the third level is hit. If the leaf item is hit, the translation of stage 1 is completed;

[0055] If the leaf item at level 3 is not hit, the translation is wrong and the translation ends.

[0056] Furthermore, the stage one translation cache includes four levels of cache: level 0, level 1, level 2, and level 3, and the tags of each level cache contain PSCID, GSCID, and the index of the corresponding level; the stage two translation cache includes three levels of cache: level 0, level 1, level 2, and level 3, and the tags of each level cache contain GSCID and the index of the corresponding level.

[0057] To achieve the above object, the second aspect of the present invention provides a virtualized nested translation system, comprising the following modules:

[0058] A request receiving module, used for receiving a virtual address translation request, determining an address translation mode of the virtual address translation request, and determining a virtual address type;

[0059] A cache selection module, used for selecting a corresponding translation cache according to the determined virtual address type;

[0060] A cache search execution module is used to perform address translation in a multi-level translation cache in a parallel or serial search mode under a selected translation cache to obtain a search result;

[0061] A hit determination module is used to analyze the search result and determine whether the search result hits the leaf item of the page table;

[0062] The address return module returns the corresponding physical address if the search result hits the leaf item, completing the translation;

[0063] The page table traversal module, if the leaf entry is not hit, performs a page table traversal to obtain the physical address.

[0064] To achieve the above objective, the third aspect of the present invention provides a computer-readable medium, on which computer instructions are stored. When the computer instructions are executed by a processor, the processor executes the method.

[0065] Beneficial effects of the present invention:

[0066] Compared with the prior art, the virtualization nested translation method, system and readable medium provided by the present invention significantly improve the translation delay and cache efficiency problems in a virtualized environment by optimizing the address translation process and cache management. First, by accurately judging the virtual address type (client virtual address, client physical address or host virtual address) of the memory access request, the method ensures that each translation is directly directed to the most relevant translation cache stage, reducing unnecessary cache queries. Secondly, the introduction of parallel and serial search modes allows the system to select the optimal search strategy according to the current cache state and the urgency of the translation request, greatly improving the search efficiency. In addition, for requests that search for leaf items that miss, the system reduces the number of accesses to physical memory through an efficient page table traversal mechanism. At the same time, the intelligent backfill and cache update strategies effectively reduce the redundant information in the cache, thereby improving the overall translation performance and system response speed. These optimization measures directly target the bottleneck problem in traditional virtualization nested translation, achieving a significant reduction in delay and an improvement in cache utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments.

[0068] Figure 1 It is an overall flow chart of the cache system disclosed in the embodiment of the present invention.

[0069] Figure 2 It is a flowchart of an optional TCS1 parallel search mode disclosed in an embodiment of the present invention.

[0070] Figure 3 It is a flow chart of an optional TCS1 serial search mode disclosed in an embodiment of the present invention.

[0071] Figure 4 It is a schematic diagram of the RISC-V architecture SV48 address translation mode disclosed in an embodiment of the present invention.

[0072] Figure 5 It is a schematic diagram of the nested translation of the RISC-V architecture SV48 address translation mode and the SV48x4 address translation mode disclosed in an embodiment of the present invention.

[0073] Figure 6 It is a schematic diagram of cache contents of a stage one translation cache applicable to a RISC-V architecture that can support SV39 and SV48 address translation modes disclosed in an embodiment of the present invention.

[0074] Figure 7It is a schematic diagram of cache contents of a stage two translation cache applicable to a RISC-V architecture and supporting SV39x4 and SV48x4 address translation modes disclosed in an embodiment of the present invention.

[0075] Figure 8 It is a schematic diagram of a cache system combining a Translation cache and a Translation path cache disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0076] like Figure 1 As shown, the present invention provides a virtualization nested translation method, which combines Translationcache with Translation path cache, improves the speed of virtualization nested translation, reduces the redundant virtual addresses cached by Translation cache and the redundant PTEs cached by Translation path cache under a single technical condition, and improves the translation delay from virtual address to physical address in memory virtualization or peripheral virtualization; the method specifically comprises:

[0077] Step S100: receiving a virtual address translation request, determining an address translation mode of the virtual address translation request, and determining a virtual address type;

[0078] In step S100, a request is received and its address translation mode is analyzed. The address translation mode may be a guest virtual address (GVA), a guest physical address (GPA), or a host virtual address (HVA).

[0079] Guest Virtual Address (GVA): Usually refers to the virtual address managed at the guest operating system level, which needs to be converted into the corresponding guest physical address or direct physical address.

[0080] Guest Physical Address (GPA): In a virtualized environment, the address of the guest (or virtual machine)'s physical memory. These addresses need to be further mapped to the host's physical address space.

[0081] Host Virtual Address (HVA): These are virtual addresses used by the hypervisor or host operating system, which also need to be translated into actual physical addresses.

[0082] By analyzing the address translation mode in the request, it is determined which layer of address space the translation request is for, which determines how the subsequent translation process will be performed. For example, if it is GVA, it involves the address translation inside the virtual machine, if it is GPA, it involves the address mapping from the virtual machine to the host, and HVA usually directly involves the address translation inside the host.

[0083] Step S200: selecting a corresponding translation cache according to the determined virtual address type;

[0084] Based on the previously determined address translation mode, the corresponding translation cache is selected to perform the address translation. This step is the preparation stage for the specific translation operation, in which the system determines whether to use the stage one or stage two translation cache, or a combination of the two, depending on the virtual address (client virtual address, client physical address, or host virtual address). For example, if the requested address is a GVA, the stage one translation cache is first used to convert the GVA to a GPA, and then the stage two translation cache is used to map the GPA to the actual host physical address (HPA). Each stage of the cache system is configured with cache units that adapt to different levels of page tables to speed up the address translation process and reduce the number of accesses to the actual memory page table.

[0085] Step S300, in the selected translation cache, performing address translation in the multi-level translation cache in a parallel or serial search mode to obtain a search result;

[0086] The parallel search mode allows the system to search multiple cache levels simultaneously to quickly determine the address translation, while the serial search mode visits each cache level in sequence. The result of the search will determine whether further page table traversal is required or whether the final physical address has been obtained, thus affecting the efficiency and response time of the entire translation process.

[0087] Step S400, analyzing the search result to determine whether the search result hits a leaf item of the page table;

[0088] Step S500: If the search result hits a leaf item, the corresponding physical address is returned to complete the translation;

[0089] Step S600: If the leaf entry is not hit, perform a page table traversal to obtain the physical address.

[0090] The leaf item is an entry in the page table that directly contains the physical address. Its hit means that the physical address can be directly returned without further page table traversal, which greatly speeds up the translation process. If the search result hits the leaf item, it goes directly to step S500 to complete the address translation and return the result; if the leaf item is not hit, an additional page table traversal operation (step S600) is required to resolve the correct physical address (GPA or HPA).

[0091] During the address translation process, determining whether the lookup result hits a leaf entry of a page table involves checking specific flags or fields in the cache system or the page table traversal result. The leaf entry of a page table directly contains physical address information rather than a further page table pointer, so the system evaluates the properties of the returned page table entry (PTE), such as the valid bit and type field. If a PTE is marked as valid and there is no pointer to the next level page table, it is considered to hit a leaf entry.

[0092] In a translation request involving virtual address to physical address translation, the process includes at least two stages (stage one and stage two), each of which contains at least three levels of page table cache. Stage one handles the translation from guest virtual address (GVA) to guest physical address (GPA), while stage two handles the translation from guest physical address to host physical address (HPA). The three-level page table cache in each stage corresponds to different page table levels, such as L1, L2, and L3, and each level of cache is designed to speed up the access and lookup of page table entries at the corresponding level. This hierarchical cache structure enables the address translation process to resolve virtual addresses faster, because each cache level can perform lookup operations in parallel or independently, effectively reducing the number of times the actual memory page table is accessed, thereby improving the efficiency and response speed of the translation.

[0093] When determining the address translation mode, taking the RISC-V architecture as an example, according to the requested virtual memory translation mode, i.e., iosatp.mode and iohgatp.mode, it is determined whether the requested virtual address type (IOVA) is GVA, GPA or host virtual address (HVA). If both iosatp.mode and iohgatp.mode are not bare mode (Bare-mode), it indicates that the requested IOVA is GVA, and the request will be sent to the stage one translation buffer unit (TCS1 BUF) by the translation cache selection unit (TC REQ SEL), indicating that the stage one translation needs to be performed first; if iosatp.mode is Bare-mode and iohgatp.mode is not bare mode (Bare-mode), it indicates that the requested IOVA is GPA, and the request will be sent to the stage two translation buffer arbitration unit (TCS2 ARB) by the translation cache selection unit (TC REQ SEL), and then wait for the stage two translation; if iosatp.mode is not Bare-mode and iohgatp.mode is Bare-mode, it indicates that the requested IOVA is HVA, and the request will be sent to the stage one translation buffer unit (TCS1 BUF) by the translation cache selection unit (TC REQSEL), waiting for the stage one translation.

[0094] It is understandable that in a virtualized environment, the operating system and hardware use specific modes (such as the address translation modes specified by IOSAT.Mode and IOHGATP.Mode) to handle the translation of memory addresses. The "Bare-mode" here is a specific setting, such as pure physical mode or non-pure physical mode, which means that the address translation process is direct without any additional levels or complex translations. When both "IOSATP.Mode and IOHGATP.Mode" are not bare modes, in this case, the address is not directly mapped to physical memory, but is first regarded as a virtual address (GVA, i.e. Guest Virtual Address). Therefore, if these two mode settings indicate that it is not a direct mapping mode, the processed memory address is considered to be a virtual address from the virtual machine, rather than a direct physical memory address.

[0095] When the virtual address type is a guest virtual address (GVA), the request is sent to the stage 1 translation buffer (TCS1 BUF) for stage 1 translation. When the virtual address type is a host virtual address (HVA), the request is also sent to the stage 1 translation buffer (TCS1 BUF) to wait for stage 1 translation.

[0096] If the virtual address type is a guest physical address (GPA), the request is sent by the translation cache select unit (TC REQSEL) to the stage two translation cache arbitration unit (TCS2 ARB) to wait for stage two translation.

[0097] In step S300, the multi-level translation cache includes: a stage 1 translation cache and a stage 2 translation cache, wherein the stage 1 translation cache specifically processes the conversion from GVA to GPA, and the stage 2 translation cache processes the conversion from GPA to the final physical address (HPA). This hierarchical structure allows the system to efficiently manage different types of address translation requirements.

[0098] Among them, the internal structure of the stage one translation cache includes four different levels of cache, namely: a third-level cache, a second-level cache, a first-level cache and a zero-level cache, each level being used to cache corresponding page table entries; for example, the third-level cache is used to cache third-level page table entries (such as large areas), the second-level cache is used to cache second-level page table entries (such as medium-sized areas), and the first-level and zero-level caches are used to cache first-level and zero-level page table entries (such as small areas).

[0099] It should be noted that the cache system includes: a translation cache selection unit (TC REQ SEL), a stage one translation buffer unit (TCS1 BUF), a stage one translation cache backfill unit (TCS1 FILL), a stage one translation cache invalidation unit (TCS1INVD), a stage one translation third-level cache (TCS1 L3), a stage one translation second-level cache (TCS1 L2), a stage one translation first and zero-level cache (TCS1 L1L0), a stage one translation result selection unit (TCS1 LKUP SEL), a stage two translation cache (TCS2), a stage two translation cache arbitration unit (TCS2 ARB), a stage two translation buffer unit (TCS2 BUF), a stage two translation result selection unit (TCS2 LKUP SEL), a stage two translation cache backfill unit (TCS2 FILL), a stage two translation cache invalidation unit (TCS2 INVD), a stage two translation third-level cache (TCS2 L3), a stage two translation second-level cache (TCS2 L2), a stage two translation first and zero-level cache (TCS2 L1L0), stage two translation cache (TCS2).

[0100] In parallel search mode, each level of cache in the stage one translation cache (TCS1) will search simultaneously, and then send the search results to a result selection unit to select the best result. For example, the stage one translation third level cache (TCS1L3), the stage one translation second level cache (TCS1 L2), and the stage one translation first and zero level cache (TCS1 L1L0) will search simultaneously and send the search results to the stage one translation result selection unit (TCS1 LKUP SEL).

[0101] The stage one translation buffer unit (TCS1 BUF) is used to buffer the request sent from the translation buffer selection unit (TC REQSEL) to the stage one translation buffer (TCS1). When the stage one translation buffer (TCS1) is idle and the stage one translation buffer unit (TCS1 BUF) has buffered the search request of the stage one translation buffer (TCS1), the stage one translation buffer unit (TCS1 BUF) will initiate a search request to the stage one translation buffer (TCS1). The existence of the stage one translation buffer unit (TCS1 BUF) allows the next request buffered in the stage one translation buffer unit (TCS1BUF) to continue the query of the stage one translation buffer (TCS1) when the stage one translation buffer (TCS1) search misses.

[0102] It can be understood that the function of the stage one translation buffer unit (TCS1 BUF) is to receive and save these requests. When the stage one translation cache (TCS1) is ready to receive requests, the stage one translation buffer unit (TCS1 BUF) will send the saved requests. If the stage one translation cache is busy processing a request and cannot process new requests immediately, the stage one translation buffer unit (TCS1 BUF) will temporarily save these new requests until the stage one translation cache is free.

[0103] In the processing of the search request of the stage one translation cache (TCS1), each search request of the stage one translation cache (TCS1) only involves the query of the page table entry (PTE) cache of different page table levels in the stage one translation cache (TCS1) in the parallel search mode or the serial search mode. Among them, the stage one translation third level cache (TCS1 L3) is used to cache the third level PTE of the stage one page table, and the search of the cache may directly hit the 512GB leaf page or the third level non-leaf page. The stage one translation second level cache (TCS1 L2) is used to cache the second level page table entry of the stage one page table, and the search of the cache may directly hit the 1GB leaf page or the second level non-leaf page. The stage one translation first and zero level cache (TCS1L1L0), each cache line of which caches the translation path of the first and zero level page tables of the stage one once, and the search of the cache may directly hit the 2MB, 4KB leaf page or the first level non-leaf page.

[0104] It is understandable how a multi-level cache system is utilized to speed up lookups when processing virtual address translation to physical address. This process involves three different levels of cache in the stage one translation cache (TCS1): level 3, level 2, and levels 1 and 0.

[0105] The cache of the Stage 1 Translation Level 3 Cache (TCS1 L3) stores the Level 3 Page Table Entries (PTEs). A page table entry is a data structure used by the memory management unit to map virtual addresses to physical addresses. The Level 3 cache can directly hit the 512GB "leaf pages" or the non-leaf pages of the Level 3. Leaf pages are the final entries in the page table that directly point to physical memory addresses, while non-leaf pages contain pointers to the next level of page tables.

[0106] The Stage 1 Translation Level 2 Cache (TCS1 L2) is one level smaller than the Stage 1 Translation Level 3 Cache (TCS1 L3).

[0107] The stage one translation level 1 and level 0 cache (TCS1 L1L0) cache covers the translation paths of the first and zero level page tables, that is, the lowest two levels of page table entries.

[0108] These three levels of cache work together, and both parallel search mode (searching multiple levels simultaneously to quickly determine the location of data) and serial search mode (searching one level after another until the data is found) involve only a single query to each level of cache.

[0109] How parallel search mode works:

[0110] like Figure 2 , Figure 3 As shown in the figure, in the mode of parallel search stage one translation third level cache (TCS1 L3), stage one translation second level cache (TCS1 L2), and stage one translation first and zero level cache (TCS1 L1L0), the following steps describe how the cache system handles multiple levels of PTE (page table entry) lookup requests:

[0111] When a lookup request is issued, the Stage 1 Translation Level 3 Cache (TCS1 L3), Stage 1 Translation Level 2 Cache (TCS1 L2), and Stage 1 Translation Level 1 and Level 0 Cache (TCS1 L1L0) operate simultaneously to read the tags in their respective caches.

[0112] Each level of cache (TCS1 L3, TCS1 L2, TCS1 L1L0) sends the search result, including whether it hits and the corresponding data, to the stage one translation result selection unit (TCS1 LKUP SEL).

[0113] The stage 1 translation result selection unit (TCS1 LKUP SEL) receives the search hit results from multiple cache levels. At this time, TCS1 LKUP SEL selects the most appropriate result according to specific priority rules:

[0114] Prefer leaf items: If a leaf item is hit in one level of cache, that result will be preferred. Prefer results that require the fewest memory accesses: Typically, this means choosing results that hit in L0 or L1.

[0115] If no L1 cache hits the leaf entry, the system will request the stage 1 page table traversal unit to perform further translation to continue looking for the required PTE information.

[0116] If the current search result does not hit a leaf item and further translation is required by the page table traversal unit, this process will not block subsequent search requests. If the search result hits a leaf item, the next step is determined based on whether the request requires nested translation:

[0117] Directly return PA (physical address): If nested translation is not required, the stage 1 translation cache (TCS1) can directly return the final physical address. Initiate a search request to the stage 2 translation cache (TCS2): If further translation is required, a search request will continue to be initiated to the stage 2 translation cache (TCS2).

[0118] Working principle of TCS1 FILL:

[0119] When the search phase 1 translation cache (TCS1) does not hit the leaf PTE of the phase 1 translation page table, the translation needs to be completed through the phase 1 page table traversal unit. This process includes the following steps:

[0120] When the lookup in the stage one translation cache (TCS1) misses a leaf PTE, the translation is done by accessing memory with the help of the stage one page table walk unit.

[0121] If the stage 1 page table walk unit successfully completes the stage 1 translation, it initiates a fill request to the stage 1 translation cache fill unit (TCS1 FILL).

[0122] The stage 1 translation cache backfill unit (TCS1 FILL) needs to decide which cache levels to backfill, for example:

[0123] Three-level page table translation mode: If the three-level page table is traversed, only the stage one translation second level cache (TCS1 L2) and the stage one translation first and zero level cache (TCS1 L1L0) are backfilled.

[0124] L1 and L0 page table translation mode: If the L1 and L0 page tables are traversed, only the stage 1 translation first and level 0 caches (TCS1 L1L0) are backfilled.

[0125] The phase one translation cache backfill unit (TCS1 FILL) is not only responsible for selecting which levels of cache to backfill, but also directly returns the translation results of phase one, thus avoiding repeated queries of the phase one translation cache (TCS1).

[0126] In this embodiment, the cache system not only includes lookup and backfill operations, but also needs to be invalidated to avoid using outdated information when the software changes the configuration of the page table entry or address translation mode. The stage one translation cache invalidation unit (TCS1 INVD) and the stage two cache invalidation unit (TCS2 INVD) will receive the invalidation request. These units will select the cache level that needs to be invalidated according to the request and issue the corresponding operation to ensure that the outdated page table information in TCS1 L3, TCS1 L2, TCS1 L1L0, TCS2 L3, TCS2 L2 and TCS2 L1L0 is correctly cleared.

[0127] In the virtualized nested translation scenario, after the stage 1 translation cache (TCS1) completes the stage 1 translation and obtains the global physical address (GPA), it will initiate a query request to the stage 2 translation cache arbitration unit (TCS2 ARB). The stage 2 translation cache arbitration unit (TCS2 ARB) is responsible for arbitrating search requests from different request sources, including the translation cache selection unit (TCREQ SEL), the stage 1 translation cache (TCS1), and other request sources that may involve stage 2 translation, such as the request generated when the stage 1 page table traversal unit performs the translation from the client physical address (GPA) to the final physical address (HPA) during the nested translation process.

[0128] The stage 2 translation buffer unit (TCS2 BUF) is used to buffer the requests from the stage 2 translation cache arbitration unit (TCS2ARB) to the stage 2 translation cache (TCS2). When the stage 2 translation cache (TCS2) is idle and the stage 2 translation buffer unit (TCS2 BUF) has buffered the search request of the stage 2 translation cache (TCS2), the stage 2 translation buffer unit (TCS2 BUF) will initiate a search request to the stage 2 translation cache (TCS2). The existence of the stage 2 translation buffer unit (TCS2 BUF) ensures that the second-level cache system can effectively process and coordinate multiple search requests, especially when the cache system is busy.

[0129] The third-level cache of stage 2 translation (TCS2 L3) is used to cache the third-level page table entries of the stage 2 page table. The cache may directly hit the 512GB leaf page or the third-level non-leaf page; the second-level cache of stage 2 translation (TCS2 L2) is used to cache the second-level page table entries. The cache may directly hit the 1GB leaf page or the second-level non-leaf page. The first and zero-level cache of stage 2 translation (TCS2 L1L0) caches the translation path of the first and zero-level page tables of stage 2 once per cache line. The cache may directly hit the 2MB, 4KB leaf page or the first-level non-leaf page. These cache levels work together to provide an efficient hierarchical cache mechanism to speed up the address translation process.

[0130] How the parallel search phase 2 cache works:

[0131] When searching the Stage 2 Translation Level 3 Cache (TCS2 L3), Stage 2 Translation Level 2 Cache (TCS2 L2), and Stage 2 Translation Level 1 and Level 0 Cache (TCS2 L1L0) in parallel, these caches will send the search hit results and hit data information to the Stage 2 Translation Result Selection Unit (TCS2 LKUP SEL) in parallel. The Stage 2 Translation Result Selection Unit (TCS2 LKUP SEL) may receive results that hit multiple levels of cache at the same time. At this time, the Stage 2 Translation Result Selection Unit (TCS2 LKUP SEL) will give priority to the content that hits the leaf item or the result that requires the least memory access. If the leaf item is not hit, the Stage 2 Page Table Traversal Unit needs to be requested for further translation. The Stage 2 Page Table Traversal Unit will not block the next Stage 2 Translation Cache (TCS2) search request buffered in the Stage 2 Translation Buffer Unit (TCS2 BUF) during the translation process. If the leaf item is hit, the Stage 2 translation is completed directly and the physical address (PA) is returned.

[0132] How the Phase 2 Backfill Unit (TCS2 FILL) works:

[0133] When the query of the stage 2 translation cache (TCS2) misses a leaf PTE, the stage 2 page table traversal unit will complete the translation, and then initiate a backfill request to the stage 2 backfill unit (TCS2 FILL). The stage 2 backfill unit (TCS2FILL) unit will select which cache levels of the stage 2 translation cache (TCS2) (such as TCS2 L3, TCS2 L2, and TCS2L1L0) to backfill, and directly return the stage 2 translation result to avoid repeated queries of the stage 2 translation cache (TCS2). This process ensures that when the cache system misses, efficient translation performance can still be maintained through an appropriate backfill mechanism.

[0134] In view of the virtualization nested translation scenario, this embodiment designs a stage one page table cache and a stage two page table cache respectively, allowing mixed translation of different address translation modes in virtualization and non-virtualization scenarios; by dividing the virtual address into a third-level virtual page number (VPN3), a second-level virtual page number (VPN2), a first-level virtual page number (VPN1) and a zero-level virtual page number (VPN0) according to the page table index level, using a combination of different virtual page numbers as a label, independently caching the PTEs of each page table level of stage one and stage two, allowing parallel search of caches at different page table levels, thereby improving the query speed; the caches of the L3 page table and the L2 page table are cached in a translation cache manner, and the L1 page table and the L0 page table are cached in a translationpath cache manner, thereby reducing the cache of redundant information.

[0135] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0136] See also Figure 4 , Figure 4 It is a schematic diagram of the SV48 address translation mode of the RISC-V architecture disclosed in an embodiment of the present invention. Taking the RISC-V architecture as an example, consider a standard SV48 page table traversal, and a physical address will be generated at each stage of the traversal. In the first step, the physical page number PPN of the IOSATP register is used as the base address, VPN3=VA[47:39] is used as the index, and the PTE of the S1L3 page table is read; then, the PPN of the PTE of S1L3 is used as the base address, VPN2=VA[38:30] is used as the index, and the PTE of the S1L2 page table is read; then, the PPN of the PTE of S1L2 is used as the base address, VPN1=VA[29:21] is used as the index, and the PTE of the S1L1 page table is read; then, the PPN of the PTE of S1L0 is used as the base address, VPN0=VA[20:12] is used as the index, and the PTE of the S1L0 page table is read. The page table entries read before reading the S1L0 page table are likely to be leaf pages. In this case, a large page will be obtained. If a large page is found, the translation can be terminated and the physical address can be obtained. Therefore, by caching the page table translated in stage 1 at different levels, and each level can cache the leaf PTE of the corresponding level page table and the non-leaf PTE, it is allowed to skip some or all page table traversal steps when searching the translation cache, so as to improve the performance of address translation.

[0137] Figure 5This is a schematic diagram of nested translation of the SV48 address translation mode and the SV48x4 address translation mode of the RISC-V architecture disclosed in an embodiment of the present invention. During the SV48 and SV48x4 nested translation process, if neither the phase 1 translation nor the phase 2 translation involves finding a large page, the memory access traversal PTE will be performed at the maximum number of times. First, the PPN of IOSATP is a GPA. After the first complete stage 2 translation, HPA is obtained. Then, the HPA is used as the base address and VPN3 is used as the offset to read S1L3PTE. The PPN in S1L3 PTE is a GPA, which cannot directly read the stage 1 page table PTE. Therefore, the second complete stage 2 translation is required to obtain HPA. Then, the HPA is used as the base address and VPN2 is used to read S1L2 PTE. Similarly, the PPN of S1L0 PTE read by stage 1 translation is still a GPA. When S1L0 PTE is obtained by memory access, it means that the complete stage 1 translation is completed. However, the last stage 2 translation is still required to translate the GPA obtained by stage 1 translation into HPA. At this point, after 24 memory accesses, a complete SV48 and SV48x4 nested translation is completed. In fact, in the process of nested translation, whether stage 1 translation or stage 2 translation, it is possible to directly find the large page. At this time, the corresponding stage 1 translation or stage 2 translation is completed, and the number of nested translation memory accesses is reduced. The above shows that in the virtualized nested translation scenario, the number of address translation times increases several times. In the embodiment of the present invention, TCS1 caches the leaf PTE and non-leaf PTE of the stage one translation to allow the translation of stage one to be skipped to the greatest extent. If the search TCS1 hits the leaf PTE, then TCS2 needs to be queried. Therefore, in the best case, the virtualized nested translation queries TCS1 once and TCS2 once to obtain the physical address PA.

[0138] Figure 6The present invention discloses a RISC-V architecture that can support the SV39 address translation mode and the SV48 address translation mode in the first stage of the translation cache content diagram. The translation cache includes three independent caches, namely TCS1 L3, TCS1 L2 and TCS1 L1L0. Among them, the TCS1 L1L0 cache uses the process address space identifier (Process Address Space Identifier, PSCID), the guest soft-context identifier (Guest soft-context identifier, GSCID) and the complete virtual address page number as tags, and uses the search path of the L1 PTE and L0 PTE also marked in the first stage as data for caching. Compared with the separated L1 PTE and L0 PTE translation caches, the cache reduces the redundant caching of the virtual address page number of the tag part. TCS1 L2 uses PSCID, GSCID and the stage one page table L3-L2 index as the tag cache PTE2, and TCS1 L3 uses PSCID, GSCID and the stage one page table L3 index as the tag cache PTE3. The translation cache is compatible with the SV39 and SV48 address translation modes of the RISC-V architecture, caching the mapping and intermediate content of the stage one translation from GVA to GPA or HVA to HPA.

[0139] Figure 7 It is a schematic diagram of the content of the phase 2 translation cache of the RISC-V architecture disclosed in the embodiment of the present invention, which can support the SV39x4 and SV48x4 address translation modes. The translation cache includes three independent caches, namely TCS2 L3, TCS2 L2 and TCS1 L1L0. Among them, the TCS2 L1L0 cache uses GSCID and the complete GPA page number as tags, and caches the path of the phase 2 translation L1 PTE and L0 PTE as data, TCS2 L2 uses GSCID and the phase 2 page table L3-L2 index as the tag cache PTE2, and TCS2 L3 uses GSCID and the phase 2 page table L3 index as the tag cache PTE3. The translation cache can be compatible with the SV39x4 and SV48x4 address translation modes of the RISC-V architecture, and caches the mapping and intermediate content of the phase 2 translation of GVA to HPA.

[0140] Figure 8A schematic diagram of a cache system combining a Translation cache and a Translation path cache disclosed in an embodiment of the present invention. The system mainly includes the following contents: translation cache selection unit (TC REQ SEL), stage one translation buffer unit (TCS1 BUF), stage one translation cache backfill unit (TCS1 FILL), stage one translation cache invalidation unit (TCS1 INVD), stage one translation third-level cache (TCS1 L3), stage one translation second-level cache (TCS1 L2), stage one translation first zero-level cache (TCS1 L1L0), stage one translation result selection unit (TCS1 LKUP SEL), stage one translation cache (TCS1), stage two translation cache arbitration unit (TCS2 ARB), stage two translation buffer unit (TCS2BUF), stage two translation result selection unit (TCS2 LKUP SEL), stage two translation cache backfill unit (TCS2 FILL), stage two translation cache invalidation unit (TCS2 INVD), stage two translation third-level cache (TCS2 L3), stage two translation second-level cache (TCS2 L2), stage two translation first zero-level cache (TCS2 L1L0), stage two translation cache (TCS2). The cache system can perform translation in three-level page table address translation mode or four-level page table address translation mode in parallel in virtualized scenarios or non-virtualized scenarios. Usually, the TC REQ SEL unit identifies the virtualized scenario or non-virtualized scenario to determine whether the request should be translated by TCS1 or TCS2. In TCS1 and TCS2, the cache levels to be read are selected according to the address translation mode, which reduces the reading of unnecessary cache blocks and reduces power consumption. Figure 6 The translation cache flow chart disclosed in the embodiment of the present invention. When the translation cache receives a search request, it will first pass through TC REQ SEL to determine whether the search request is GVA, GPA or HPA. If the search request is GVA or HVA, TCS1 is selected for search, and then it is determined whether the search TCS1 hits the leaf PTE. If the leaf PTE is not hit, the stage one page table is traversed to complete the stage one translation. If the stage one translation is completed, it is determined whether it is a nested translation. If it is a nested translation, a request is initiated to the TCS2 request arbitration unit, otherwise, the translation is terminated. If the search request is GPA, the translation cache selection unit initiates a request to the TCS2 request arbitration unit, and TCS2 is searched after arbitration. If the search hits the leaf PTE, it indicates that the stage two translation is completed. If the leaf PTE is not hit, the stage two translation is completed by traversing the stage two page table. Usually, in order to speed up the traversal of the stage one page table in the nested translation scenario, during the page table traversal process, if the stage one page table PTE is obtained, all translations involving the stage two can access TCS2 to quickly complete the stage two translation.

[0141] In order to improve the translation speed in the virtualized nested translation scenario, the PTE caches at various levels can be read in parallel during the TCS1 or TCS2 search stage. Figure 7 It is a flowchart of an optional TCS1 parallel search mode disclosed in an embodiment of the present invention. This embodiment is explained by taking the parallel search mode of the translation cache of the SV48 and SV39 address translation modes of the RISC-V architecture as an example. First, if the search request is the SV48 address translation mode, then the three caches TCS1 L1L0, TCS1 L2 and TCS1 L3 in TCS1 are read in parallel at the same time. If the address translation mode of the search request is the SV39 address translation mode, then TCS1 L1L0 and TCS1 L2 are searched in parallel at the same time. After the search is completed, it will be judged according to the hit result of the TCS1 search. If the search directly hits the L0 PTE of TCS1 L1L0, it indicates that the stage 1 translation is completed and a 4KB page is obtained; otherwise, it is judged whether the L1 leaf PTE of TCS1 L1L0 is hit. If it is hit, it indicates that the stage 1 translation is completed and a 2MB page is obtained; otherwise, it is judged whether the leaf PTE of TCS1 L2 is hit. If it is hit, it indicates that the stage 1 translation is completed and a 1GB page is obtained; otherwise, it is judged whether the leaf PTE of TCS1 L3 is hit. If it is hit, it indicates that the stage 1 translation is completed and a 512GB page is obtained. Otherwise, it is requested to traverse the page table of stage 1. If the result of the TCS1 search indicates that the leaf PTE of stage 1 is hit, it indicates that the complete stage 1 translation is completed, and then the stage 2 translation can be performed or the translation result can be directly returned.

[0142] Generally, in order to further improve the power consumption of the translation cache, you can also choose to serially search the PTE cache of each level of TCS1 or TCS2, and you can choose to read the lower-level PTE cache first to match the virtual address with the maximum bit width, so as to allow more memory accesses to be skipped when hitting the lower-level PTE cache. If the lower-level PTE cache is not hit, then initiate a search for the higher-level PTE cache. Figure 8It is an optional TCS1 serial search process disclosed in an embodiment of the present invention. This embodiment is illustrated by taking the serial search mode of the translation cache of the SV48 and SV39 address translation modes of the RISC-V architecture as an example. First, if the search request is in SV48 address translation mode, then TCS1 L1L0 is read first. If it hits, the leaf item is judged. If it is a leaf item, the stage one translation is completed; if the search for TCS1 L1L0 hits but the leaf item of TCS1 L1L0 is not hit, then the page table traversal begins; if the search for TCS1 L1L0 does not hit, start searching TCS2 L2, and then determine whether TCS1 L2 is hit. If the leaf item of TCS1 L2 is hit, the stage one translation is completed; if the leaf item is not hit, the page table traversal begins; if the search for TCS1 L2 does not hit, the SV39 address translation mode is judged. If it is SV39 mode, the page table traversal begins; if it is SV48 mode, search TCS1 L3 to determine whether TCS1 L3 is hit. If TCS1 L3 is hit and the leaf item is hit, the stage one translation is completed; if TCS1 is hit L3, but the leaf item is not hit, the translation is wrong and the translation ends; if TCS1 L3 is not hit, the page table traversal begins, and after completing the translation of stage 1, it continues to search TCS2 or returns the translation result, and the address translation ends.

[0143] The present invention also provides a virtualized nested translation system, comprising the following modules:

[0144] A request receiving module, used for receiving a virtual address translation request, determining an address translation mode of the virtual address translation request, and determining a virtual address type;

[0145] A cache selection module, used for selecting a corresponding translation cache according to the determined virtual address type;

[0146] A cache search execution module is used to perform address translation in a multi-level translation cache in a parallel or serial search mode under a selected translation cache to obtain a search result;

[0147] A hit determination module is used to analyze the search result and determine whether the search result hits the leaf item of the page table;

[0148] The address return module returns the corresponding physical address if the search result hits the leaf item, completing the translation;

[0149] The page table traversal module, if the leaf entry is not hit, performs a page table traversal to obtain the physical address.

[0150] Preferably, the present invention further provides a computer-readable medium, on which computer instructions are stored, and when the computer instructions are executed by a processor, the processor executes the method.

[0151] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0152] One or more embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A virtualized nested translation method, characterized in that: The steps include: receiving a virtual address translation request, determining an address translation mode of the virtual address translation request, and determining a virtual address type; According to the determined virtual address type, the corresponding translation cache is selected, where: The translation cache includes a cache unit for storing multi-level page table entries; The multi-level translation cache includes a stage one translation cache and a stage two translation cache, wherein the stage one translation cache includes a third-level cache, a second-level cache, and a cache unit merged by a first-level cache and a zero-level cache, the third-level cache is used to cache third-level page table entries, the second-level cache is used to cache second-level page table entries, and the merged cache unit is used to cache first-level page table entries and zero-level page table entries at the same time; Under the selected translation cache, address translation is performed in the multi-level translation cache in a parallel or serial search mode to obtain a search result, where: In the parallel search mode, the third level cache, the second level cache, and the merged cache unit of the stage one translation cache simultaneously search and send the search results to the stage one translation result selection unit; The serial search mode refers to searching in the order of the levels of the multi-level translation cache, starting from the lowest level cache. If there is a miss, the second level cache and the third level cache are searched upwards in sequence until the corresponding page table entry is found. Analyze the search results to determine whether the search results hit the leaf item of the page table; If the search result hits a leaf item, the corresponding physical address is returned to complete the translation; If a leaf entry is not hit, a page table walk is performed to obtain the physical address.

2. The virtualized nested translation method according to claim 1, characterized in that: The virtual address type is determined according to the following rules: The address translation modes include iosatp.mode mode and iohgatp.mode mode; When both the iosatp.mode mode and the iohgatp.mode mode are not pure physical modes, determining that the requested virtual address type is a client virtual address, and sending the request to the stage one translation buffer unit for stage one translation; When the iosatp.mode mode is the pure physical mode and the iohgatp.mode mode is the non-pure physical mode, determining that the requested virtual address type is a client physical address, and sending the request to the stage two translation cache arbitration unit to wait for stage two translation; When the iosatp.mode mode is non-pure physical mode and the iohgatp.mode mode is pure physical mode, it is determined that the requested virtual address type is a host virtual address, and the request is sent to the stage one translation buffer unit to wait for stage one translation.

3. The virtualized nested translation method according to claim 1, characterized in that: In the multi-level translation cache search results, if the search result hits the leaf item of the page table, it is further determined whether the current translation request involves nested translation: If the current translation request does not involve nested translation, the final translation is completed directly and the physical address is returned; If the current translation request involves nested translation, a search request is initiated to the next translation stage for further address translation; If the search result does not hit the leaf entry of the page table, the page table traversal unit accesses the memory to complete the page table traversal and fills the traversal result back into the corresponding translation cache.

4. The virtualized nested translation method according to claim 3, characterized in that: After the page table traversal unit accesses the memory and completes the page table traversal, it initiates a backfill request to the translation cache backfill unit according to the page table traversal result, and the backfill unit selects the cache level that needs to be backfilled.

5. The virtualized nested translation method according to claim 4, characterized in that: The translation cache backfill unit selects to backfill the result into the third-level cache, the second-level cache or the merged cache unit of the stage one translation cache or the stage two translation cache according to the level completed by the page table traversal unit.

6. The virtualized nested translation method according to claim 1, characterized in that: The method further includes performing an invalidation operation on obsolete information in the translation cache in the address translation mode, wherein the invalidation operation is performed by a translation cache invalidation unit receiving an invalidation request and sending the invalidation request to a corresponding cache level to clear obsolete page table information.

7. A virtualized nested translation system, characterized in that: Includes the following modules: A request receiving module, used for receiving a virtual address translation request, determining an address translation mode of the virtual address translation request, and determining a virtual address type; The cache selection module is used to select a corresponding translation cache according to the determined virtual address type, wherein: The translation cache includes a cache unit for storing multi-level page table entries; The multi-level translation cache includes a stage one translation cache and a stage two translation cache, wherein the stage one translation cache includes a third-level cache, a second-level cache, and a cache unit merged by a first-level cache and a zero-level cache, the third-level cache is used to cache third-level page table entries, the second-level cache is used to cache second-level page table entries, and the merged cache unit is used to cache first-level page table entries and zero-level page table entries at the same time; The cache search execution module is used to perform address translation in the multi-level translation cache in a parallel or serial search mode under the selected translation cache to obtain a search result, wherein: In the parallel search mode, the third level cache, the second level cache, and the merged cache unit of the stage one translation cache simultaneously search and send the search results to the stage one translation result selection unit; The serial search mode refers to searching in the order of the levels of the multi-level translation cache, starting from the lowest level cache. If there is a miss, the second level cache and the third level cache are searched upwards in sequence until the corresponding page table entry is found. A hit determination module is used to analyze the search result and determine whether the search result hits the leaf item of the page table; The address return module returns the corresponding physical address if the search result hits the leaf item, completing the translation; The page table traversal module, if the leaf entry is not hit, performs a page table traversal to obtain the physical address.

8. A computer-readable medium, characterized in that The computer readable medium stores computer instructions, which, when executed by a processor, cause the processor to execute the method according to any one of claims 1 to 6.

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