On-chip automatic calibration system for local oscillator leakage and I / Q imbalance

Abstract

The invention discloses an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance. The on-chip automatic calibration system comprises a first part circuit used as a frequency mixer, a second part circuit used as a local oscillator leakage and image frequency detection circuit and a third part circuit used as a digital control circuit, local oscillator leakage and image frequency signals of an output port of a transmitter are detected through a self-mixing method, local oscillator leakage and I / Q imbalance detection is achieved, and an on-chip digital circuit is used for automatically adjusting output current of a current type DAC in a transconductance stage of a mixer according to a detection result. Automatic calibration of on-chip integrated local oscillator leakage and I / Q imbalance is realized.

Description

Technical Field

[0001] The invention relates to the technical field of power electronic design, and in particular to an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance. Background Art

[0002] In a frequency conversion transmitter, local oscillator leakage and I / Q imbalance are two of the most important indicators. Excessive local oscillator leakage and I / Q imbalance will affect the constellation diagram of the transmitted signal, causing the constellation diagram to shift horizontally or vertically. Therefore, when designing a transmitter, it is necessary to focus on reducing local oscillator leakage and I / Q imbalance. The local oscillator leakage and I / Q imbalance can be improved by optimizing the selection of mixer transistor size and the symmetry of the layout. The main factor of local oscillator leakage is the inconsistency of the current in the two differential paths inside the transconductance stage I or Q path. The main reason for I / Q imbalance is the inconsistency of the overall current between the transconductance stage I and Q paths. The local oscillator leakage and I / Q imbalance can be improved by adjusting the bias voltage of each transconductance of the actual chip mixer.

[0003] The traditional method of calibrating transmitter local oscillator leakage and I / Q imbalance is to read the local oscillator leakage and image frequency signal output by the transmitter through a vector network analyzer, and manually adjust the mixer transconductance stage bias voltage to minimize the output local oscillator leakage and image frequency signal. This method requires expensive instruments, takes a long time to calibrate, and the environment inside the chip may change after the chip has been running for a period of time, and the original calibration result is no longer the optimal value. Summary of the invention

[0004] Technical purpose: In view of the three key issues in the prior art, namely local oscillator leakage, I / Q imbalance, and inability to accurately and automatically calibrate on chip, the present invention discloses an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance. On the basis of the traditional frequency converter, a local oscillator leakage and I / Q imbalance calibration circuit is added, and a broadband local oscillator leakage and image frequency signal detection circuit and an on-chip digital control circuit are added to realize signal reading and automatic calibration without the need for external instruments and manual adjustment.

[0005] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0006] An on-chip automatic calibration system for local oscillator leakage and I / Q imbalance includes a first circuit section 1000 used as a mixer, a second circuit section 2000 used as a local oscillator leakage and image frequency detection circuit, and a third circuit section 3000 used as a digital control circuit; The first circuit 1000 includes an I, Q mixer composed of two Gilbert units, the input of which is an externally provided orthogonal intermediate frequency signal, including IF_I+, IF_I-, IF_Q+, IF_Q-, and an orthogonal local oscillator signal, including LO_I+, LO_I-, LO_Q+, LO_Q-; the output is a radio frequency differential signal, including RF+ and RF-; the radio frequency differential signal is amplified by a power amplifier and coupled to a single-ended radio frequency signal RF at the radio frequency output end of the transmitter; the positive and negative transconductance stages of the I, Q mixer are respectively controlled by current-type DACs, so that local oscillator leakage and I / Q imbalance can be calibrated; The second circuit 2000 is used to detect the local oscillator leakage and image frequency of the single-ended radio frequency signal RF, and finally convert the local oscillator leakage and image frequency signals into digital signals proportional to their power; the digital signals are input to the third circuit 3000; The output end of the third circuit 3000 is connected to the current-type DAC in the first circuit 1000, and is used to obtain the current local oscillator leakage and image frequency by reading the digital signal generated by the second circuit 2000, thereby using the traversal method to find the IDAC output that minimizes the local oscillator leakage and image frequency.

[0007] Beneficial effects: The present invention detects the local oscillator leakage and image frequency signals at the transmitter output port by a self-mixing method, thereby realizing the detection of local oscillator leakage and I / Q imbalance, and uses an on-chip digital circuit to automatically adjust the output current of the current-type DAC in the mixer transconductance stage according to the detection results, thereby realizing automatic calibration of the on-chip integrated local oscillator leakage and I / Q imbalance. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance provided in an embodiment of the present application; Figure 2 A schematic diagram of the first circuit structure of an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance provided in an embodiment of the present application; Figure 3 A schematic diagram of the second part of the structure of an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance provided in an embodiment of the present application; Figure 4 A control logic diagram of the third part of an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance provided in an embodiment of the present application; Figure 5 LO leakage suppression test result diagram of a transmitter with an on-chip automatic calibration system for LO leakage and I / Q imbalance; Figure 6Figure 1 is a graph of image rejection test results for a transmitter with an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0010] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0011] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0012] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0013] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0014] Some implementation methods of the present application are described in detail below in conjunction with the accompanying drawings.

[0015] Example As attached Figure 1 As shown, an on-chip automatic calibration system for local oscillator leakage and I / Q imbalance of this embodiment is applicable to a transmitter, and includes a first circuit 1000 used as a mixer, a second circuit 2000 used as a local oscillator leakage and image frequency detection circuit, and a third circuit 3000 used as a digital control circuit; The first circuit 1000 includes an I, Q mixer composed of two Gilbert units, the input of which is an externally provided orthogonal intermediate frequency signal, including IF_I+, IF_I-, IF_Q+, IF_Q-, and an orthogonal local oscillator signal, including LO_I+, LO_I-, LO_Q+, LO_Q-; the output is a radio frequency differential signal, including RF+ and RF-; the radio frequency differential signal is amplified by a power amplifier and coupled to a single-ended radio frequency signal RF at the radio frequency output end of the transmitter; the positive and negative transconductance stages of the I, Q mixer are respectively controlled by current-type DACs, so that the local oscillator leakage and I / Q imbalance can be calibrated; The second circuit 2000 is used to detect the local oscillator leakage and image frequency of the single-ended radio frequency signal RF, and finally convert the local oscillator leakage and image frequency signals into digital signals proportional to their power; the digital signals are input to the third circuit 3000; The output end of the third circuit 3000 is connected to the current-type DAC in the first circuit 1000, and is used to obtain the current local oscillator leakage and image frequency by reading the digital signal generated by the second circuit 2000, thereby using the traversal method to find the IDAC output that minimizes the local oscillator leakage and image frequency.

[0016] like Figure 2 As shown, the first part of the circuit 1000 includes an I-channel mixer switch stage, an I-channel mixer transconductance stage and a series inductor between the two stages constituting an I mixer, a Q-channel mixer switch stage, a Q-channel mixer transconductance stage and a series inductor between the two stages constituting a Q mixer, a current-type DAC for controlling four mixers connected to the I-channel mixer transconductance stage and the Q-channel mixer transconductance stage, and a transconductance stage bias resistor connected to the I-channel mixer transconductance stage and the Q-channel mixer transconductance stage; the I mixer and the Q mixer have the same structure; The I-channel mixer switch stage is connected to the I-channel mixer transconductance stage through a series inductor, and the Q-channel mixer switch stage is connected to the Q-channel mixer transconductance stage through a series inductor. The input signal of the I-channel mixer switch stage is LOI+ and LOI-; the input signal of the Q-channel mixer switch stage is LOQ+ and LOQ-; LOI+, LOI-, LOQ+ and LOQ- are orthogonal local oscillator signals; the mixer output signal, that is, the output signal of the first part of the circuit 1000 is RF+ and RF-, that is, the radio frequency differential output signal; the input signal connected to the I-channel mixer transconductance stage is IF_I+ and IF_I-, and the input signal connected to the Q-channel mixer transconductance stage is IF_Q+ and IF_Q-; IF_I+, IF_I-, IF_Q+ and IF_Q- are orthogonal local oscillator signals after buffering and amplification; Wherein, the I-channel mixer switch stage, as a switch stage of a Gilbert unit, includes a first transistor 1021, a second transistor 1022, a third transistor 1023, and a fourth transistor 1024; the source electrodes of the first transistor 1021 and the second transistor 1022 are connected, and the source electrodes of the third transistor 1023 and the fourth transistor 1024 are connected; the drain electrodes of the first transistor 1021 and the third transistor 1023 are connected, and the drain electrodes of the second transistor 1022 and the fourth transistor 1024 are connected, serving as the output end of the I-channel mixer, the gate electrodes of the first transistor 1021 and the fourth transistor 1024 are connected, serving as the positive input end of the local oscillation signal I, the input signal LO_I+, and the gate electrodes of the second transistor 1022 and the third transistor 1023 are connected, serving as the negative input end of the local oscillation signal I, the input signal LO_I-; Similarly, the Q-channel mixer switch stage, as a switch stage of a Gilbert unit, includes a fifth transistor 1025, a sixth transistor 1026, a seventh transistor 1027, and an eighth transistor 1028; the source electrodes of the fifth transistor 1025 and the sixth transistor 1026 are connected, and the source electrodes of the seventh transistor 1027 and the eighth transistor 1028 are connected; the drain electrodes of the fifth transistor 1025 and the seventh transistor 1027 are connected, and the drain electrodes of the sixth transistor 1026 and the eighth transistor 1028 are connected, serving as the output end of the Q-channel mixer; the gate electrodes of the fifth transistor 1025 and the eighth transistor 1028 are connected, serving as the positive input end of the local oscillator signal Q-channel, the input signal LO_Q+, and the gate electrodes of the sixth transistor 1026 and the seventh transistor 1027 are connected, serving as the negative input end of the local oscillator signal Q-channel, the input signal LO_Q-; After the output ends of the I mixer and the Q mixer are connected, the remaining sidebands are canceled and the sidebands are added to obtain single sideband output, output signals RF+ and RF-, that is, RF differential output signals.

[0017] The I-channel mixer transconductance stage includes a ninth transistor 1002, a tenth transistor 1004, an eleventh transistor 1005, and a twelfth transistor 1007; the Q-channel mixer transconductance stage includes a thirteenth transistor 1010, a fourteenth transistor 1012, a fifteenth transistor 1013, and a sixteenth transistor 1015; the current-mode DAC controlling the four-channel mixer includes a first IDAC 1001, a second IDAC 1008, a third IDAC 1009, and a fourth IDAC 1016; and the transconductance stage bias resistor includes a first resistor 1003, a second resistor 1006, a third resistor 1011, and a fourth resistor 1014; A total of four positive and negative transconductance stages of the I and Q mixers are controlled by current-type DACs respectively, so that local oscillator leakage and I / Q imbalance can be calibrated. The ninth transistor 1002, the twelfth transistor 1007, the thirteenth transistor 1010, and the sixteenth transistor 1015 constitute a current mirror of the transconductance stage. The gates of all transistors in the current mirror are connected to the drains, and the sources are grounded. The drain of the ninth transistor 1002 is connected to the first IDAC 1001, the drain of the twelfth transistor 1007 is connected to the second IDAC 1008, the drain of the thirteenth transistor 1010 is connected to the third IDAC 1009, and the drain of the sixteenth transistor 1015 is connected to the fourth IDAC 1016. Each IDAC can be controlled by a digital circuit, that is, the third part of the circuit 3000 to control the output size of the current, and the control amplitude is 60μA. The present invention uses a current-type DAC at the bias of the four transconductances of the mixer to control the size of the four currents, so that local oscillator leakage and I / Q imbalance can be calibrated.

[0018] The gate of the ninth transistor 1002 in the transconductance stage of the mixer of path I is connected to the gate of the tenth transistor 1004 through the first resistor 1003, the gate of the eleventh transistor 1005 is connected to the gate of the twelfth transistor 1007 through the second resistor 1006, the sources of the tenth transistor 1004 and the eleventh transistor 1005 are grounded, the gate of the thirteenth transistor 1010 in the transconductance stage of the mixer of path Q is connected to the gate of the fourteenth transistor 1012 through the third resistor 1011, the gate of the fifteenth transistor 1013 is connected to the gate of the sixteenth transistor 1015 through the fourth resistor 1014, and the sources of the fourteenth transistor 1012 and the fifteenth transistor 1013 are grounded.

[0019] The series inductance between the mixer switch stage and the transconductance stage includes a first inductor 1017, a second inductor 1018, a third inductor 1019, and a fourth inductor 1020; the drain of the tenth transistor 1004 in the I-channel mixer transconductance stage is connected to the source of the first transistor 1021 and the second transistor 1022 in the I-channel mixer switch stage through the first inductor 1017, and the drain of the eleventh transistor 1005 in the I-channel mixer transconductance stage is connected to the source of the third transistor 1021 and the second transistor 1022 in the I-channel mixer switch stage through the first inductor 1017. 3 and the source of the fourth transistor 1024 are connected through the second inductor 1018, the drain of the fourteenth transistor 1012 in the Q-channel mixer transconductance stage and the source of the fifth transistor 1025 and the sixth transistor 1026 in the Q-channel mixer switch stage are connected through the third inductor 1019, and the drain of the fifteenth transistor 1013 in the Q-channel mixer transconductance stage and the source of the seventh transistor 1027 and the eighth transistor 1028 in the Q-channel mixer switch stage are connected through the fourth inductor 1020.

[0020] Among them, the first transistor 1021, the second transistor 1022, the third transistor 1023, the fourth transistor 1024, the fifth transistor 1025, the sixth transistor 1026, the seventh transistor 1027, and the eighth transistor 1028 have the same size, the ninth transistor 1002, the twelfth transistor 1007, the thirteenth transistor 1010, and the sixteenth transistor 1015 have the same size, and the tenth transistor 1004, the eleventh transistor 1005, the fourteenth transistor 1012, and the fifteenth transistor 1013 have the same size; the first IDAC 1001, the second IDAC 1008, the third IDAC 1009, and the fourth IDAC 1016 have the same current output range; the first resistor 1003, the second resistor 1006, the third resistor 1011, and the fourth resistor 1014 have the same resistance value; the first inductor 1017, the second inductor 1018, the third inductor 1019, and the fourth inductor 1020 have the same inductance value.

[0021] like Figure 3 As shown, the second circuit 2000 includes an input coupling transformer 2100, a self-mixer 2200, a low-pass filter 2300, a voltage amplifier 2400, an envelope detector 2500 and an ADC 2600; the input coupling transformer 2100 is the first-stage input, the self-mixer 2200, the low-pass filter 2300, the voltage amplifier 2400 and the envelope detector 2500 are sequentially cascaded, and the two outputs of the envelope detector 2500 are respectively connected to the two inputs of the ADC 2600, and finally the local oscillator leakage and the image frequency signal are converted into a digital signal proportional to the power thereof; the digital signal is input to the third circuit 3000; The input coupling transformer 2100 is formed by coupling the primary coil and the secondary coil, realizing the T-model function composed of the series and parallel inductors, reducing the chip area, and realizing the function of coupling the transmitter output signal RF to the second circuit 2000 without affecting the transmission power. The self-mixer 2200 is a first-stage self-mixer, including a seventeenth transistor 2203, an eighteenth transistor 2204, a nineteenth transistor 2207, a twentieth transistor 2208, a fifth resistor 2201, a sixth resistor 2202, a seventh resistor 2209, an eighth resistor 2210, a ninth resistor 2211, a first capacitor 2205, and a second capacitor 2206. The input terminals of the self-mixer 2200 are IN+ and IN-, and the output terminal is OUT. The drain of the seventeenth transistor 2203 is connected to the source of the nineteenth transistor 2207, the drain of the eighteenth transistor 2204 is connected to the source of the twentieth transistor 2208, the gate of the seventeenth transistor 2203 is connected to the positive input terminal IN+, the gate of the eighteenth transistor 2204 is connected to the negative input terminal IN-, the sources of the seventeenth transistor 2203 and the eighteenth transistor 2204 are grounded, the gates of the nineteenth transistor 2207 and the twentieth transistor 2208 are connected to the bias voltage Vb2, the drains of the nineteenth transistor 2207 and the twentieth transistor 2208 are connected to the output terminal OUT, and the output terminal O UT is connected to the power supply through the fifth resistor 2201, the output terminal OUT is connected to the gate of the seventeenth transistor 2203 by connecting the seventh resistor 2209 and the first capacitor 2205 in series to form a negative feedback, the output terminal OUT is connected to the gate of the eighteenth transistor 2204 by connecting the eighth resistor 2210 and the second capacitor 2206 in series to form a negative feedback, the gate of the seventeenth transistor 2203 is connected to the bias voltage Vb1 through the fifth resistor 2201, the gate of the eighteenth transistor 2204 is connected to the bias voltage Vb1 through the sixth resistor 2202, and the output terminal OUT is connected to the input terminal of the low-pass filter 2300; The seventeenth transistor 2203 has the same size as the eighteenth transistor 2204, the nineteenth transistor 2207 has the same size as the twentieth transistor 2208, the fifth resistor 2201 has the same resistance value as the sixth resistor 2202, the seventh resistor 2209 has the same resistance value as the eighth resistor 2210, and the first capacitor 2205 has the same capacitance value as the second capacitor 2206; The self-mixer 2200 mixes the RF, LO leakage and image frequency signals coupled from the input coupling transformer 2100, and outputs components such as 1x IF, 2x IF, RF and RF third harmonic, wherein 1x IF is the product of mixing RF and LO leakage, and 2x IF is the product of mixing RF and image frequency, which respectively represent the magnitude of LO leakage and image frequency in the original signal; The low-pass filter 2300 is a first-stage low-pass filter, including a fifth inductor 2301, a third capacitor 2302, and a fourth capacitor 2303. The input end of the low-pass filter is IN, and the output end is OUT. The fifth inductor 2301 is connected in parallel with the third capacitor 2302, one end of which is connected to IN and the other end of which is connected to OUT. The fourth capacitor 2303 has one end connected to OUT and the other end connected to the ground. The output end OUT is connected to the input end of the voltage amplifier 2400. The low-pass filter 2300 is used to filter the signal with a frequency higher than twice the intermediate frequency output from the mixer 2200. The voltage amplifier 2400 is a two-stage voltage amplifier, including a twenty-first transistor 2402, a twenty-second transistor 2403, a twenty-third transistor 2412, a twenty-fourth transistor 2411, a fifth capacitor 2401, a sixth capacitor 2407, a seventh capacitor 2408, an eighth capacitor 2410, a ninth capacitor 2414, a sixth inductor 2404, a seventh inductor 2406, a tenth resistor 2405, an eleventh resistor 2409, a twelfth resistor 2413, and a thirteenth resistor 2415. The input end of the voltage amplifier 2400 is IN, and the output end is OUT. The gate of the twenty-first transistor 2402 is connected to the input terminal IN through the fifth capacitor 2401, the source of the twenty-first transistor 2402 is grounded, the gate of the twenty-first transistor 2402 is connected to the voltage bias Vb1, the drain of the twenty-first transistor 2402 is connected to the source of the twenty-second transistor 2403, the gate of the twenty-second transistor 2403 is connected to the bias voltage Vb2, the drain of the twenty-second transistor 2403 is connected to the power supply by connecting the sixth inductor 2404 and the tenth resistor 2405 in series in sequence, the seventh inductor 2406 is connected in parallel with the sixth capacitor 2407, one end of the inductor 2406 is connected to the drain of the twenty-second transistor 2403, and the other end is connected to the gate of the twenty-third transistor 2412 through the eighth capacitor 2410, the drain of the twenty-second transistor 2403 is connected to the gate of the twenty-first transistor 2402 by connecting the seventh capacitor 2408, the eleventh resistor 2409 and the gate of the twenty-first transistor 2402 in series in sequence. The sixth inductor 2404 and the seventh inductor 2406 are coupled to each other; one end of the sixth inductor 2404 away from the power supply and one end of the seventh inductor 2406 connected to the drain of the twenty-second transistor 2403 are the same-named ends; the drain of the twenty-third transistor 2412 is connected to the source of the twenty-fourth transistor 2411, the gate of the twenty-third transistor 2412 is connected to the bias voltage Vb3, the source of the twenty-third transistor 2412 is grounded, the gate of the twenty-fourth transistor 2411 is connected to the bias voltage Vb4, the drain of the twenty-fourth transistor 2411 is connected to the power supply through the twelfth resistor 2413, the drain of the twenty-fourth transistor 2411 is connected to the output end OUT, the output end OUT is connected to the gate of the twenty-third transistor 2412 through the ninth capacitor 2414 and the thirteenth resistor 2415 connected in series in sequence, and the output end OUT is connected to the input end of the envelope detector 2500; The voltage amplifier 2400 is used to perform voltage amplification on the single intermediate frequency and double intermediate frequency signals output from the mixer 2200, and filter out interference components above the double intermediate frequency. The low-pass filter 2300 and the voltage amplifier 2400 work together to filter out interference components above the double intermediate frequency more thoroughly.

[0022] The envelope detector 2500 is a first-stage envelope detector, including a twenty-fifth transistor 2503, a twenty-sixth transistor 2504, a twenty-seventh transistor 2508, a twenty-eighth transistor 2509, a twenty-ninth transistor 2510, a thirtieth transistor 2513, a thirty-first transistor 2514, a tenth capacitor 2501, an eleventh capacitor 2506, a twelfth capacitor 2512, a thirteenth capacitor 2515, a fourteenth capacitor 2507, a fourteenth resistor 2502, a fifteenth resistor 2505, and a sixteenth resistor 2511, the input end of the envelope detector is IN, and the output ends are OUT1 and OUT2; The gate of the twenty-fifth transistor 2503 is connected to the input terminal IN through the tenth capacitor 2501, the gate of the twenty-fifth transistor 2503 is connected to the bias voltage Vb1 through the fourteenth resistor 2502, the source of the twenty-fifth transistor 2503 is grounded, the gate of the twenty-sixth transistor 2504 is connected to the ground through the eleventh capacitor 2506, the gate of the twenty-sixth transistor 2504 is connected to the bias voltage Vb1 through the fifteenth resistor 2505, the drain of the twenty-fifth transistor 2503 is connected to the drain of the twenty-sixth transistor 2504, the drain of the twenty-ninth transistor 2510, and the output terminal OUT2, the output terminal OUT2 is grounded through the fourteenth capacitor 2507, the drain of the twenty-ninth transistor 2510 is grounded through the twelfth capacitor 2512, the source of the twenty-ninth transistor 2510 is connected to the power supply, the gate of the twenty-ninth transistor 2510 is connected to the gate of the twenty-eighth transistor 2509, and the The gate of the twenty-eighth transistor 2509 is connected to its own drain, the source of the twenty-eighth transistor 2509 is connected to the power supply, the drain of the twenty-eighth transistor 2509 is connected to the drain of the twenty-seventh transistor 2508, the gate of the twenty-seventh transistor 2508 is connected to the bias voltage Vb2, the source of the twenty-seventh transistor 2508 is grounded, the drain of the twenty-ninth transistor 2510 is connected to the gate of the thirtieth transistor 2513 through the sixteenth resistor 2511, the source of the thirtieth transistor 2513 is connected to the power supply, the drain of the thirtieth transistor 2513 is connected to the drain of the thirty-first transistor 2514 and the output terminal OUT1, the gate of the thirty-first transistor 2514 is connected to the bias voltage Vb3, the source of the thirty-first transistor 2514 is grounded, the output terminal OUT1 is connected to the ground through the thirteenth capacitor 2515, and the output terminal OUT1 and the output terminal OUT2 are connected to the first-stage ADC2600; The twenty-fifth transistor 2503 and the twenty-sixth transistor 2504 have the same size, the fourteenth resistor 2502 and the fifteenth resistor 2505 have the same resistance value, and the tenth capacitor 2501 and the eleventh capacitor 2506 have the same capacitance value.

[0023] The envelope detector 2500 is used to convert the single intermediate frequency and double intermediate frequency signals into DC components, wherein the level output by the output terminal OUT1 is positively correlated with the voltage of the input signal, and its change is more sensitive when the input signal voltage is small; the level output by the output terminal OUT2 is negatively correlated with the voltage of the input signal, and its change is more sensitive when the input signal voltage is large; the difference between the results of the output terminal OUT1 and the output terminal OUT2 is positively correlated with the input signal voltage, and the change at each voltage is more sensitive than that of the single output terminal OUT1 or the output terminal OUT2, which can represent the power size of the transmitter local oscillator leakage and the image frequency component; The ADC2600 includes two DC level input ports, a digital control port for switching the read port, and a digital bus output port. The two DC level input ports are respectively connected to the output terminal OUT1 and the output terminal OUT2 of the envelope detector 2500, and the digital bus output port is connected to the third circuit 3000. The level range of the ADC sampling is 0-1V, and the sampling accuracy is 10 bits. ADC2600 converts the input DC level into a digital signal and outputs it to the third circuit 3000 through the bus, so that the digital control circuit can obtain the power of the transmitter local oscillator leakage and the image frequency component and perform automatic calibration accordingly.

[0024] The local oscillator leakage and image frequency generated by the I / Q mixer are coupled at the output end of the transmitter as RF signals and input into the detection circuit. The local oscillator and image frequency are converted into one and two intermediate frequencies respectively through the self-mixer, and then converted into DC level after filtering and amplification. After ADC sampling, they are transmitted to the third circuit.

[0025] The third circuit 3000 is a digital control circuit automatically generated by Verilog code, including a digital bus input port, a calibration signal input port, a calibration end signal output port, and four digital bus output ports. The digital bus output ports are respectively connected to the first IDAC1001, the second IDAC1008, the third IDAC1009, and the fourth IDAC1016, and are used to control the current output by the DAC; The signal flow process of this embodiment is as follows: The first circuit 1000 has an input of an externally provided orthogonal intermediate frequency signal, including IF_I+, IF_I-, IF_Q+, IF_Q-, and an orthogonal local oscillator signal, including LO_I+, LO_I-, LO_Q+, LO_Q-; the output is an RF differential signal, including RF+ and RF-; after being amplified by a power amplifier, the RF differential signal is converted into a single-ended RF signal RF at the RF output port; the second circuit 2000 has an input of an RF signal RF, and an output of a digital bus signal; the third circuit 3000 has an input including a digital bus signal from the second circuit 2000 and a calibration start signal, and outputs a calibration end signal and four digital bus outputs, and the digital bus outputs are respectively connected to the first IDAC1001, the second IDAC1008, the third IDAC1009, and the fourth IDAC1016 in the first circuit 1000, thereby forming a closed-loop control loop.

[0026] The local oscillator leakage and I / Q imbalance calibration process of this embodiment is as follows: due to differences in chip manufacturing processes, the sizes of the transconductance stage transistors, namely the tenth transistor 1004, the eleventh transistor 1005, the fourteenth transistor 1012, and the fifteenth transistor 1013, may be different, which leads to an imbalance in the DC current of the transconductance stage transistors. The imbalance in the current of the transconductance stage transistors will cause the local oscillator signal or the mirror frequency at the output port to be unable to completely offset, and the output amplitude of the local oscillator signal or the mirror frequency with a large current is large, thereby generating a large local oscillator leakage or mirror frequency. In the present invention, the output current of the current-type DAC is controlled, and then the current sizes of the four channels are changed, so that the DC current of the transconductance stage transistors is restored to balance, thereby realizing the calibration of the local oscillator leakage and I / Q imbalance. In order to realize on-chip automation of the calibration process, the present invention adds a local oscillator leakage and image frequency detection circuit at the transmitter output port, converts the components to be detected into digital signals and outputs them to the on-chip digital control circuit. After receiving the calibration start signal, the digital control circuit obtains the IDAC control code when the local oscillator leakage and image frequency are minimized by traversal, thereby realizing the calibration of local oscillator leakage and I / Q imbalance.

[0027] like Figure 4 As shown, the control logic of the third circuit 3000 of the system of the present invention includes a main process and a sub-process 3100. When the automatic calibration starts, the system is first in state 3001, and the third circuit 3000 receives the calibration signal from the calibration signal input port and enters the sub-process 3100a; in the sub-process 3100a, the system calibrates the local oscillator leakage of the I channel, that is, calibrates the first IDAC1001, wherein the steps of 3100a are consistent with 3100, and the modified IDAC register is the control register corresponding to the first IDAC1001, and after completion, enters the sub-process 3100b; In sub-process 3100, the circuit first enters state 3101, sets the control register value of the corresponding IDAC to 0, then enters state 3102, adds 1 to the register value, and then enters state 3103. The third part of the circuit reads the values ​​of output terminal OUT1 and output terminal OUT2 read by ADC2600 through the digital bus input port, and calculates the value of OUT1-OUT2, and then enters state 3104. If the value of OUT1-OUT2 is less than the previous reading at this time, the minimum value is stored, and behavior 3105 is triggered to store the current register value. After state 3104 ends, it enters state 3106 to determine whether the register value reaches the upper limit. If it does not reach the upper limit, it returns to state 3102. If it has reached the upper limit, it enters 3107 to set the register to the best bias value obtained in the loop, and ends sub-process 3100. In sub-process 3100b, the system calibrates the local oscillator leakage of the Q path, that is, calibrates the fourth IDAC1016, wherein the steps of 3100b are consistent with 3100, and the modified IDAC register is the control register corresponding to the fourth IDAC1016, and after completion, it enters sub-process 310c; In sub-process 3100c, the circuit calibrates the imbalance of the I and Q paths, that is, the first IDAC1001 and the second IDAC1008 are calibrated at the same time. At this time, the state 3102 in the sub-process changes to adding 1 to the register values ​​controlling the first IDAC1001 and the second IDAC1008 at the same time, that is, keeping the difference between the two registers constant. The state 3106 in the sub-process changes to judging whether the value of the first IDAC1001 or the second IDAC1008 register reaches the upper limit. If one of them reaches it, the state 3107 is entered. The remaining steps are the same. After completion, the state 3002 is entered. In state 3002, since the calibration of local oscillator leakage and the calibration of I / Q imbalance will affect each other, it is necessary to determine whether the value of the current register is the same as the value of the previous register. If they are not the same, it means that the calibration has not converged, and enter state 3003. If they are the same, it means that the calibration has converged, and enter state 3004; in state 3003, determine whether the upper limit of the number of iterations is reached. If not, return to state 3100a. If it has been reached, enter state 3004; in state 3004, the circuit sends a calibration end signal through the calibration signal input port to complete the automatic calibration; The digital control circuit realizes automatic local oscillator leakage and I / Q imbalance calibration by automatically traversing the register value that controls the IDAC output current and combining the digital signal input by the detection circuit.

[0028] The present invention adopts an I / Q mixing architecture, and has two mixers, an I-channel mixer and a Q-channel mixer. The I-channel mixer and the Q-channel mixer are respectively input with orthogonal intermediate frequency signals and orthogonal local oscillator signals. The I-channel mixer and the Q-channel mixer obtain two sidebands, one of which has the same phase and the other has an opposite phase. Finally, the required sideband is retained and the remaining sideband is offset, thereby realizing single-sideband up-conversion. The mixer output matching network realizes the selection of the sideband. Specifically, the sideband can be switched by changing the connection mode of the I-channel mixer and the Q-channel mixer output: the positive end of the I-channel output is connected to the positive end of the Q-channel output, and the negative end is connected to the negative end, so that the upper sideband is selected; the positive end of the I-channel output is connected to the negative end of the Q-channel output, and the negative end is connected to the positive end, so that the lower sideband is selected.

[0029] The present invention adds a local oscillator leakage and I / Q imbalance calibration circuit on the basis of a traditional frequency converter, that is, includes the first part of the circuit of the current-type DAC, and adds a broadband local oscillator leakage and image frequency signal detection circuit and an on-chip digital control circuit, so as to realize signal reading and automatic calibration without the need for external instruments, such as an external vector network analyzer, and manual adjustment; the local oscillator leakage and image frequency signal output by the transmitter are detected by the on-chip circuit, and the bias voltage of the mixer transconductance stage is automatically adjusted to the optimal value through the on-chip digital control circuit, which can save a lot of costs in the case of mass production of chips, and can also be calibrated at any time when the whole machine is put into use to maintain the optimal state.

[0030] like Figure 5 As shown in the figure, this is a schematic diagram of the comparison of the situation before and after the local oscillator leakage suppression calibration in this example test. The horizontal axis in the figure is the intermediate frequency, and the vertical axis is the local oscillator leakage suppression ratio. Figure 5 It can be seen that in the range of 2.4-7.5GHz for intermediate frequency signals, the local oscillator leakage suppression of the transmitter is improved by at least 20dBc after automatic calibration. In the required RF frequency range, the local oscillator leakage suppression ratio of the transmitter is greater than 40dBc.

[0031] like Figure 6 As shown in the figure, this is a comparison diagram of the situation before and after the image frequency suppression calibration in this example test. Figure 6 The horizontal axis is the intermediate frequency, and the vertical axis is the image frequency suppression ratio. Figure 6 It can be seen that in the range of 2.4-7.5GHz for the intermediate frequency signal, the image frequency suppression of the transmitter is improved by at least 8dBc after automatic calibration. In the required RF frequency range, the image frequency suppression ratio of the transmitter is greater than 40dBc.

[0032] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0033] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. An on-chip automatic calibration system for local oscillator leakage and I / Q imbalance, characterized in that: It comprises a first circuit section (1000) used as a mixer, a second circuit section (2000) used as a local oscillator leakage and image frequency detection circuit, and a third circuit section (3000) used as a digital control circuit; The first circuit (1000) comprises an I, Q mixer composed of two Gilbert units, the input of which is an externally provided orthogonal intermediate frequency signal, including IF_I+, IF_I-, IF_Q+, IF_Q-, and an orthogonal local oscillator signal, including LO_I+, LO_I-, LO_Q+, LO_Q-; The output is a radio frequency differential signal, including RF+ and RF-; after being amplified by the power amplifier, the radio frequency differential signal is coupled to a single-ended radio frequency signal RF at the radio frequency output end of the transmitter; The positive and negative transconductance stages of the I and Q mixers are controlled by current-mode DACs, respectively, so that local oscillator leakage and I / Q imbalance can be calibrated. The second circuit (2000) is used to perform local oscillator leakage and image frequency detection on the single-ended radio frequency signal RF, and finally convert the local oscillator leakage and image frequency signals into digital signals proportional to their power; the digital signals are input into the third circuit (3000); The output end of the third circuit (3000) is connected to the current-type DAC in the first circuit (1000) and is used to obtain the current local oscillator leakage and image frequency by reading the digital signal generated by the second circuit (2000), thereby using a traversal method to find the IDAC output that minimizes the local oscillator leakage and image frequency.

2. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 1, characterized in that: The first circuit (1000) comprises an I-channel mixer switch stage, an I-channel mixer transconductance stage and a series inductor between the two stages constituting an I mixer, a Q-channel mixer switch stage, a Q-channel mixer transconductance stage and a series inductor between the two stages constituting a Q mixer, a current-type DAC for controlling a four-channel mixer connected to the I-channel mixer transconductance stage and the Q-channel mixer transconductance stage, and a transconductance stage bias resistor connected to the I-channel mixer transconductance stage and the Q-channel mixer transconductance stage; The I-channel mixer switch stage is connected to the I-channel mixer transconductance stage through a series inductor, and the Q-channel mixer switch stage is connected to the Q-channel mixer transconductance stage through a series inductor. The input signal of the I-channel mixer switch stage is LOI+ and LOI-; the input signal of the Q-channel mixer switch stage is LOQ+ and LOQ-; LOI+, LOI-, LOQ+ and LOQ- are orthogonal local oscillator signals; the mixer output signal is RF+ and RF-, that is, the RF differential output signal; the input signal connected to the I-channel mixer transconductance stage is IF_I+ and IF_I-, and the input signal connected to the Q-channel mixer transconductance stage is IF_Q+ and IF_Q-; IF_I+, IF_I-, IF_Q+ and IF_Q- are orthogonal local oscillator signals after buffering and amplification.

3. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 2, characterized in that: The I-channel mixer switch stage, as a switch stage of a Gilbert unit, comprises a first transistor (1021), a second transistor (1022), a third transistor (1023), and a fourth transistor (1024); the source electrodes of the first transistor (1021) and the second transistor (1022) are connected, the source electrodes of the third transistor (1023) and the fourth transistor (1024) are connected, the drain electrodes of the first transistor (1021) and the third transistor (1023) are connected, the drain electrodes of the second transistor (1022) and the fourth transistor (1024) are connected, serving as the output end of the I-channel mixer, the gate electrodes of the first transistor (1021) and the fourth transistor (1024) are connected, serving as the positive input end of the local oscillator signal I-channel, the input signal LO_I+, the gate electrodes of the second transistor (1022) and the third transistor (1023) are connected, serving as the negative input end of the local oscillator signal I-channel, the input signal LO_I-; A Q-channel mixer switch stage, as a switch stage of a Gilbert unit, comprises a fifth transistor (1025), a sixth transistor (1026), a seventh transistor (1027), and an eighth transistor (1028); the source electrodes of the fifth transistor (1025) and the sixth transistor (1026) are connected, the source electrodes of the seventh transistor (1027) and the eighth transistor (1028) are connected, the drain electrodes of the fifth transistor (1025) and the seventh transistor (1027) are connected, the drain electrodes of the sixth transistor (1026) and the eighth transistor (1028) are connected, serving as the output end of the Q-channel mixer, the gate electrodes of the fifth transistor (1025) and the eighth transistor (1028) are connected, serving as the positive input end of the local oscillator signal Q-channel, the input signal LO_Q+, the gate electrodes of the sixth transistor (1026) and the seventh transistor (1027) are connected, serving as the negative input end of the local oscillator signal Q-channel, the input signal LO_Q-; The first transistor (1021), the second transistor (1022), the third transistor (1023), the fourth transistor (1024), the fifth transistor (1025), the sixth transistor (1026), the seventh transistor (1027), and the eighth transistor (1028) have the same size.

4. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 2, characterized in that: The I-channel mixer transconductance stage comprises a ninth transistor (1002), a tenth transistor (1004), an eleventh transistor (1005), and a twelfth transistor (1007); the Q-channel mixer transconductance stage comprises a thirteenth transistor (1010), a fourteenth transistor (1012), a fifteenth transistor (1013), and a sixteenth transistor (1015); the current-type DAC for controlling the four-channel mixer comprises a first IDAC (1001), a second IDAC (1008), a third IDAC (1009), and a fourth IDAC (1016); and the transconductance stage bias resistor comprises a first resistor (1003), a second resistor (1006), a third resistor (1011), and a fourth resistor (1014); The ninth transistor (1002), the twelfth transistor (1007), the thirteenth transistor (1010), and the sixteenth transistor (1015) have the same size; the tenth transistor (1004), the eleventh transistor (1005), the fourteenth transistor (1012), and the fifteenth transistor (1013) have the same size; the first IDAC (1001), the second IDAC (1008), the third IDAC (1009), and the fourth IDAC (1016) have the same current output range; the first resistor (1003), the second resistor (1006), the third resistor (1011), and the fourth resistor (1014) have the same resistance value; A total of four positive and negative transconductance stages of the I and Q mixers are controlled by current-type DACs, respectively, so that local oscillator leakage and I / Q imbalance can be calibrated. The ninth transistor (1002), the twelfth transistor (1007), the thirteenth transistor (1010), and the sixteenth transistor (1015) form a current mirror of the transconductance stage, and the gate is connected to the drain. The drain of the ninth transistor (1002) is connected to the first IDAC (1001), the drain of the twelfth transistor (1007) is connected to the second IDAC (1008), the drain of the thirteenth transistor (1010) is connected to the third IDAC (1009), and the drain of the sixteenth transistor (1015) is connected to the fourth IDAC (1016). Each IDAC can be controlled by a digital circuit to control the output current, and the control amplitude is 60μA. The gate of the ninth transistor (1002) in the I-channel mixer transconductance stage is connected to the gate of the tenth transistor (1004) through a first resistor (1003), the gate of the eleventh transistor (1005) is connected to the gate of the twelfth transistor (1007) through a second resistor (1006), the sources of the tenth transistor (1004) and the eleventh transistor (1005) are grounded, the gate of the thirteenth transistor (1010) in the Q-channel mixer transconductance stage is connected to the gate of the fourteenth transistor (1012) through a third resistor (1011), the gate of the fifteenth transistor (1013) is connected to the gate of the sixteenth transistor (1015) through a fourth resistor (1014), and the sources of the fourteenth transistor (1012) and the fifteenth transistor (1013) are grounded.

5. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 4, characterized in that: The series inductance between the mixer switch stage and the transconductance stage comprises a first inductance (1017), a second inductance (1018), a third inductance (1019), and a fourth inductance (1020), wherein the first inductance (1017), the second inductance (1018), the third inductance (1019), and the fourth inductance (1020) have the same inductance value; the drain of the tenth transistor (1004) in the I-channel mixer transconductance stage is connected to the source of the first transistor (1021) and the second transistor (1022) in the switch stage via the first inductance (1017); the eleventh transistor (1004) in the transconductance stage is connected to the source of the first transistor (1021) and the second transistor (1022) in the transconductance stage via the first inductance (1017); The drain of the transistor (1005) is connected to the source of the third transistor (1023) and the fourth transistor (1024) in the switch stage through a second inductor (1018), the drain of the fourteenth transistor (1012) in the Q-channel mixer transconductance stage is connected to the source of the fifth transistor (1025) and the sixth transistor (1026) in the switch stage through a third inductor (1019), and the drain of the fifteenth transistor (1013) in the transconductance stage is connected to the source of the seventh transistor (1027) and the eighth transistor (1028) in the switch stage through a fourth inductor (1020).

6. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 1, characterized in that: The second circuit (2000) comprises an input coupling transformer (2100), a self-mixer (2200), a low-pass filter (2300), a voltage amplifier (2400), an envelope detector (2500) and an ADC (2600); the input coupling transformer (2100) is the first-stage input, the self-mixer (2200), the low-pass filter (2300), the voltage amplifier (2400) and the envelope detector (2500) are sequentially cascaded, and the two outputs of the envelope detector (2500) are respectively connected to the two inputs of the ADC (2600), and finally the local oscillator leakage and the image frequency signal are converted into a digital signal proportional to the power thereof.

7. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The self-mixer (2200) comprises a seventeenth transistor (2203), an eighteenth transistor (2204), a nineteenth transistor (2207), a twentieth transistor (2208), a fifth resistor (2201), a sixth resistor (2202), a seventh resistor (2209), an eighth resistor (2210), a ninth resistor (2211), a first capacitor (2205), and a second capacitor (2206); the input terminals of the self-mixer are IN+ and IN-, and the output terminal is OUT; The drain of the seventeenth transistor (2203) is connected to the source of the nineteenth transistor (2207), the drain of the eighteenth transistor (2204) is connected to the source of the twentieth transistor (2208), the gate of the seventeenth transistor (2203) is connected to the positive input terminal IN+, the gate of the eighteenth transistor (2204) is connected to the negative input terminal IN-, the sources of the seventeenth transistor (2203) and the eighteenth transistor (2204) are grounded, the gates of the nineteenth transistor (2207) and the twentieth transistor (2208) are connected to the bias voltage Vb2, the drains of the nineteenth transistor (2207) and the twentieth transistor (2208) are connected to the output terminal OUT, the output terminal is connected to the power supply through the fifth resistor (2201), and the output terminal is connected to the gate of the seventeenth transistor (2203) by connecting the seventh resistor (2209) and the first capacitor (2205) in series in sequence to form a negative The output terminal is connected to the gate of the eighteenth transistor (2204) in series to form negative feedback, the gate of the seventeenth transistor (2203) is connected to the bias voltage Vb1 through the fifth resistor (2201), the gate of the eighteenth transistor (2204) is connected to the bias voltage Vb1 through the sixth resistor (2202), and the output terminal OUT is connected to the input terminal of the low-pass filter (2300); the seventeenth transistor (2203) and the eighteenth transistor (2204) have the same size, the nineteenth transistor (2207) and the twentieth transistor (2208) have the same size, the fifth resistor (2201) and the sixth resistor (2202) have the same resistance value, the seventh resistor (2209) and the eighth resistor (2210) have the same resistance value, and the first capacitor (2205) and the second capacitor (2206) have the same capacitance value.

8. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The low-pass filter (2300) comprises a fifth inductor (2301), a third capacitor (2302), and a fourth capacitor (2303); the input end of the low-pass filter is IN, and the output end is OUT; wherein the fifth inductor (2301) is connected in parallel with the third capacitor (2302), one end of which is connected to IN, and the other end of which is connected to OUT; the fourth capacitor (2303) has one end connected to OUT, and the other end connected to ground; and the output end OUT is connected to the input end of the voltage amplifier (2400).

9. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The voltage amplifier (2400) comprises a twenty-first transistor (2402), a twenty-second transistor (2403), a twenty-third transistor (2412), a twenty-fourth transistor (2411), a fifth capacitor (2401), a sixth capacitor (2407), a seventh capacitor (2408), an eighth capacitor (2410), a ninth capacitor (2414), a sixth inductor (2404), a seventh inductor (2406), a tenth resistor (2405), an eleventh resistor (2409), a twelfth resistor (2413), and a thirteenth resistor (2415); an input terminal of the voltage amplifier is IN, and an output terminal is OUT; The gate of the twenty-first transistor (2402) is connected to the input terminal IN through the fifth capacitor (2401), the source of the twenty-first transistor (2402) is grounded, the gate of the twenty-first transistor (2402) is connected to the voltage bias Vb1, the drain of the twenty-first transistor (2402) is connected to the source of the twenty-second transistor (2403), the gate of the twenty-second transistor (2403) is connected to the bias voltage Vb2, the drain of the twenty-second transistor (2403) is connected to the power supply through the sixth inductor (2404) and the tenth resistor (2405) connected in series in sequence, the seventh inductor (2406) is connected in parallel with the sixth capacitor (2407), one end of the seventh inductor (2406) is connected to the drain of the twenty-second transistor (2403), and the other end is connected to the gate of the twenty-third transistor (2412) through the eighth capacitor (2410), the drain of the twenty-second transistor (2403) is connected to the seventh capacitor (2404) and the tenth resistor (2405) connected in series in sequence, 8), the eleventh resistor (2409) is connected to the gate of the twenty-first transistor (2402), the sixth inductor (2404) and the seventh inductor (2406) are coupled to each other, the drain of the twenty-third transistor (2412) is connected to the source of the twenty-fourth transistor (2411), the gate of the twenty-third transistor (2412) is connected to the bias voltage Vb3, the source of the twenty-third transistor (2412) is grounded, the gate of the twenty-fourth transistor (2411) is connected to the bias voltage Vb4, the drain of the twenty-fourth transistor (2411) is connected to the power supply through the twelfth resistor (2413), the drain of the twenty-fourth transistor (2411) is connected to the output terminal OUT, the output terminal OUT is connected to the gate of the twenty-third transistor (2412) through the ninth capacitor (2414) and the thirteenth resistor (2415) connected in series in sequence, and the output terminal OUT is connected to the input terminal of the envelope detector (2500).

10. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The envelope detector (2500) comprises a twenty-fifth transistor (2503), a twenty-sixth transistor (2504), a twenty-seventh transistor (2508), a twenty-eighth transistor (2509), a twenty-ninth transistor (2510), a thirtieth transistor (2513), a thirty-first transistor (2514), a tenth capacitor (2501), an eleventh capacitor (2506), a twelfth capacitor (2512), a thirteenth capacitor (2515), a fourteenth capacitor (2507), a fourteenth resistor (2502), a fifteenth resistor (2505), and a sixteenth resistor (2511); the input end of the envelope detector is IN, and the output ends are OUT1 and OUT2; The gate of the twenty-fifth transistor (2503) is connected to the input terminal IN through the tenth capacitor (2501), the gate of the twenty-fifth transistor (2503) is connected to the bias voltage Vb1 through the fourteenth resistor (2502), the source of the twenty-fifth transistor (2503) is grounded, the gate of the twenty-sixth transistor (2504) is connected to the ground through the eleventh capacitor (2506), the gate of the twenty-sixth transistor (2504) is connected to the bias voltage Vb1 through the fifteenth resistor (2505), the drain of the twenty-fifth transistor (2503) is connected to the twenty-sixth transistor (2504). The drain of the body tube (2504), the drain of the twenty-ninth transistor (2510) and the output terminal OUT2 are connected, the output terminal OUT2 is connected to the ground through the fourteenth capacitor (2507), the drain of the twenty-ninth transistor (2510) is connected to the ground through the twelfth capacitor (2512), the source of the twenty-ninth transistor (2510) is connected to the power supply, the gate of the twenty-ninth transistor (2510) is connected to the gate of the twenty-eighth transistor (2509), the gate of the twenty-eighth transistor (2509) is connected to its own drain, and the gate of the twenty-eighth transistor (2509) is connected to the gate of the twenty-eighth transistor (2509). The source is connected to the power supply, the drain of the twenty-eighth transistor (2509) is connected to the drain of the twenty-seventh transistor (2508), the gate of the twenty-seventh transistor (2508) is connected to the bias voltage Vb2, the source of the twenty-seventh transistor (2508) is grounded, the drain of the twenty-ninth transistor (2510) is connected to the gate of the thirtieth transistor (2513) through the sixteenth resistor (2511), the source of the thirtieth transistor (2513) is connected to the power supply, the drain of the thirtieth transistor (2513) is connected to the drain of the thirty-first transistor (2514) and the output terminal OUT1 is connected, the gate of the thirty-first transistor (2514) is connected to the bias voltage Vb3, the source of the thirty-first transistor (2514) is grounded, the output terminal OUT1 is connected to the ground through the thirteenth capacitor (2515), and the output terminals OUT1 and OUT2 are connected to the ADC (2600); the twenty-fifth transistor (2503) and the twenty-sixth transistor (2504) have the same size, the fourteenth resistor (2502) and the fifteenth resistor (2505) have the same resistance value, and the tenth capacitor (2501) and the eleventh capacitor (2506) have the same capacitance value.

11. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 6, characterized in that: The ADC (2600) comprises two DC level input ports, a digital control port for switching a reading port, and a digital bus output port, the two DC level input ports are respectively connected to an output terminal OUT1 and an output terminal OUT2 of the envelope detector (2500), and the digital bus output port is connected to a third circuit (3000).

12. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 1, characterized in that: The third circuit (3000) is a digital control circuit, comprising a digital bus input port, a calibration signal input port, a calibration end signal output port, and four digital bus output ports, wherein the digital bus output ports are respectively connected to the current-type DACs in the first circuit (1000), namely, the first IDAC (1001), the second IDAC (1008), the third IDAC (1009), and the fourth IDAC (1016), and are used to control the current output by the DACs; The control logic of the third part of the circuit (3000) includes a main process and a sub-process (3100). When the automatic calibration starts, the system is first in state 3001, receives the calibration signal from the calibration signal input port, and enters sub-process 3100 (a); in sub-process 3100 (a), the circuit calibrates the first IDAC (1001), wherein the steps of 3100 (a) are consistent with 3100, and the modified IDAC register is the control register corresponding to the first IDAC (1001), and after completion, enters sub-process 3100 (b); in sub-process 3100 (b), the circuit calibrates the fourth IDAC (1016), wherein the steps of 3100 (b) are consistent with 3100, and the modified IDAC register is the control register corresponding to the fourth IDAC (1016), and after completion, enters sub-process 3100 (c); in sub-process 3100 (c), the circuit calibrates the first IDAC (1001) and the second IDAC (10 08) calibration is performed simultaneously, at this time, the state 3102 in the sub-process is changed to simultaneously add 1 to the register values ​​controlling the first IDAC (1001) and the second IDAC (1008), that is, keep the difference between the two registers constant, and the state 3106 in the sub-process is changed to determine whether the value of the first IDAC (1001) or the second IDAC (1008) register has reached the upper limit, if one of them has reached it, it enters state 3107, and the remaining steps are the same, and after the end, it enters state 3002; in state 3002, it is determined whether the value of the current register is the same as the value of the register in the previous round, if not, it enters state 3003, if the same, it enters state 3004; in state 3003, it is determined whether the upper limit of the number of iterations has been reached, if not, it returns to state 3100 (a), if it has been reached, it enters state 3004; in state 3004, the circuit sends a calibration end signal through the calibration signal input port to complete the automatic calibration.

13. The on-chip automatic calibration system for local oscillator leakage and I / Q imbalance according to claim 12, characterized in that: In sub-process 3100, the circuit first enters state 3101, sets the control register value of the corresponding IDAC to 0, then enters state 3102, adds 1 to the register value, and then enters state 3103, reads the values ​​of OUT1 and OUT2 read by the ADC through the digital bus input port, and calculates the value of OUT1-OUT2, and then enters state 3104. If the value of OUT1-OUT2 is less than the previous reading at this time, the minimum value is stored, and behavior 3105 is triggered to store the current register value. After state 3104 ends, enter state 3106 to determine whether the register value has reached the upper limit. If it has not reached the upper limit, return to state 3102. If it has reached the upper limit, enter 3107, set the register to the optimal bias value obtained in the loop, and end sub-process 3100.

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