Photoelectric conversion device and electronic equipment

Abstract

The invention relates to the technical field of photoelectric sensors, and discloses a photoelectric conversion device and electronic equipment, the photoelectric conversion device comprises an SPAD device, a quenching module, a counting module, a time analog conversion module and a data processing module; when the count value is not greater than the preset value, the data processing module uses the count value to represent the ambient light intensity; and when the count value is greater than the preset value, calculating the average voltage corresponding to the average value of the pulse widths of the electric signals in the whole exposure period according to the accumulated value of the analog voltage, and representing the ambient light intensity by using the average voltage. According to the invention, the counting module is firstly used for counting the number of photons received by the SPAD device, and when the counting value reaches a set value, the time analog conversion module is switched to represent the ambient light intensity, so that the dynamic range of photon detection is expanded without increasing power consumption, the photons can be detected when the light intensity is relatively low or relatively high, and the detection efficiency is improved. And the condition of inaccurate counting caused by saturation of the counter due to increase of the light intensity is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of photoelectric imaging sensors, and in particular to a photoelectric conversion device and an electronic device. Background Art

[0002] The SPAD device (Single Photon Avalanche Diode) in the photoelectric imaging sensor usually adopts a passive quenching method, such as Figure 1 As shown, when the SPAD device 201 detects a photon, avalanche multiplication occurs. Since the resistance of the quenching device 202 is much larger than the resistance of the SPAD device 201 during avalanche, the VC point begins to discharge, causing the VC voltage to drop. When the VC voltage is lower than the judgment threshold, the VO voltage begins to rise.

[0003] like Figure 2 and Figure 3 As shown, from time t0 to time t1, a voltage difference "VH-VL" is applied to Figure 1 The SPAD device 201 in. At time t1, when a photon is incident on the SPAD device 201, avalanche multiplication occurs in the SPAD device 201, so that the avalanche multiplication current flows in the quenching element 202, causing the voltage of VC to drop. If the voltage drop amount further increases, and the voltage difference applied to the SPAD device 201 becomes smaller, the avalanche multiplication of the SPAD device 201 stops at time t2, and the voltage level at point VC does not drop more than a predetermined value. Then, between time t2 and time t3, current flows from the voltage VL to VC to form a voltage drop, and at time t3, the potential level at point VC is statically stabilized to the original potential level. At this time, in the case where the output waveform at point VC exceeds the threshold, the output waveform is shaped by the waveform shaping unit 210 and output to VO as a signal, at which point VO is finally output in the form of a pulse voltage (such as Figure 3 If the VO point is connected to a counter, photon counting can be performed, that is, the number of pulse voltages can be recorded.

[0004] like Figure 5 As shown in FIG. 1 , under low light intensity, there are only 3 photons. When the SPAD device 201 receives 3 photons, the counter counts three pulses accordingly. Figure 6 As shown in the figure, under high light intensity, although about 20 photons are incident, only 3 pulses are counted, and the count value is small. Although there are continuous photon irradiation, the VC point voltage is continuously lower than the threshold voltage, and VO does not generate a pulse signal. It can be seen that during the high level period of each clock cycle of the clock signal, only the first triggered photon can be responded, so the count value is less than the actual number of photons. Therefore, Figure 4As shown, after the light intensity reaches a certain value, the value represented by the count value will decrease, and the count value and the light intensity value cannot correspond one to one. In this case, the SPAD device cannot obtain the correct count value, and the count value of the counter is easily saturated, making it impossible to count subsequent photons.

[0005] Currently, in strong light environments, the dynamic range of SPAD is usually increased by increasing the number of bits and clock frequency of the counter, but this method will significantly increase the power consumption of the photoelectric sensor chip, which is not conducive to the development of SPAD image sensors. Summary of the invention

[0006] In view of the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a photoelectric conversion device and an electronic device to solve the problem of inaccurate counting values ​​of the existing photoelectric sensors in a strong light environment.

[0007] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0008] A photoelectric conversion device, comprising a SPAD device, a quenching module, a counting module, a time analog conversion module and a data processing module;

[0009] The quenching module is used to switch the working state according to the clock signal. When the quenching module is in the conducting state, the SPAD device is charged to the power supply voltage. When the quenching module is in the non-conducting state, the SPAD device waits for receiving a photon trigger.

[0010] The SPAD device is used to generate an electrical signal pulse according to the photon signal received for the first time in each clock cycle during the exposure period;

[0011] The counting module is used to count the number of the electrical signal pulses output by the SPAD device to obtain a count value;

[0012] The time analog conversion module is used to convert the pulse width values ​​of the electrical signal pulses in all clock cycles into the cumulative value of the analog voltage;

[0013] The data processing module is used to use the count value to characterize the ambient light intensity when the count value is not greater than the preset value; and is used to calculate the average voltage corresponding to the average value of the pulse width of the electrical signal pulse during the entire exposure period based on the accumulated value of the analog voltage when the count value is greater than the preset value, and use the average voltage to characterize the ambient light intensity.

[0014] In the photoelectric conversion device, the preset value is smaller than the maximum value of the counter.

[0015] In the photoelectric conversion device, during the high level period of the clock signal, when the SPAD device receives a photon signal, the electrical signal pulse is at a high level;

[0016] The pulse width of the electrical signal pulse is the time length between the first time point when the SPAD device is first triggered by a photon in each clock cycle and the second time point of the falling edge of the clock signal.

[0017] In the photoelectric conversion device, the proportion of the high level of the clock signal to the clock period is at least 80%.

[0018] In the photoelectric conversion device, the time analog conversion module includes a first PMOS tube, a first NMOS tube, a second NMOS tube and a first capacitor, the gate of the first PMOS tube is connected to an external bias power supply, the source of the first PMOS tube is connected to a power supply terminal, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the gate of the first NMOS tube is connected to the output terminal of the SPAD device, the source of the first NMOS tube is connected to one end of the first capacitor, the input terminal of the data processing module and the drain of the second NMOS tube, the source of the second NMOS tube and the other end of the first capacitor are grounded, and the gate of the second NMOS tube is connected to the first external control terminal;

[0019] The external bias power supply controls the first PMOS tube to be continuously turned on to provide charging current for the first capacitor; when exposure starts, when the SPAD device receives photons, the output of the SPAD device controls the first NMOS tube to be turned on to charge the first capacitor, and the second NMOS tube is disconnected at this time; when exposure ends, the output of the SPAD device controls the first NMOS tube to be turned off, and the second NMOS tube is turned on to release the charge of the first capacitor, waiting for the next exposure.

[0020] In the photoelectric conversion device, the average value of the pulse width of the electrical signal pulse during the entire exposure period is calculated according to the accumulated value of the analog voltage, specifically including:

[0021] The change value of the voltage of the first capacitor before and after exposure is divided by the number of electrical signal pulses to obtain the average voltage of the analog voltage corresponding to the pulse width of the electrical signal pulse.

[0022] In the photoelectric conversion device, the time analog conversion module includes: a D trigger, an inverter, a buffer, a second PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second capacitor and a third capacitor. The input end of the D trigger is connected to the output end of the SPAD device, the clock pulse input end of the D trigger is connected to the trigger clock, the output end of the D trigger is connected to the gate of the third NMOS tube, the input end of the inverter and the input end of the buffer, the output end of the inverter is connected to the reset end of the D trigger, the output end of the buffer is connected to the gate of the fifth NMOS tube, the gate of the second PMOS tube is connected to the second external control end, the source of the second PMOS tube is connected to the power supply end, the drain of the second PMOS tube is connected to the drain of the third NMOS tube and one end of the second capacitor, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the third external control end, the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube and one end of the third capacitor, and the source of the fifth NMOS tube, the other end of the second capacitor and the other end of the third capacitor are all grounded;

[0023] The clock frequency of the trigger clock is n times that of the clock signal. Before the exposure starts, the second external control terminal controls the second PMOS tube to be turned on, and the power supply of the power supply terminal charges the second capacitor;

[0024] After the exposure starts, the fourth NMOS tube is turned on, and the second external control terminal controls the second PMOS tube to be turned off. When the electrical signal pulse is at a high level, each time the rising edge of the trigger clock occurs, the D trigger outputs a high level signal to turn on the third NMOS tube. At this time, the charge of the second capacitor is discharged to the third capacitor through the third NMOS tube and the fourth NMOS tube, and the fifth NMOS tube is turned off. The high level signal output by the D trigger passes through the inverter and serves as a reset signal of the D trigger. The output of the D trigger is reset to a low level signal to turn off the third NMOS tube. At this time, the fifth NMOS tube is turned on, and the charge of the third capacitor is discharged to the ground. During the exposure period, the charge on the second capacitor will be continuously discharged according to the high level of the electrical signal pulse.

[0025] In the photoelectric conversion device, the clock frequency of the trigger clock is 5 times that of the clock signal. When the electrical signal pulse is at a high level, the trigger clock has 1-4 rising edges, causing the third NMOS tube to be turned on 1-4 times.

[0026] In the photoelectric conversion device, the capacitance of the second capacitor is M times that of the third capacitor, and M is greater than the number of the electrical signal pulses during the exposure period.

[0027] In the photoelectric conversion device, the average value of the pulse width of the electrical signal pulse during the entire exposure period is calculated according to the accumulated value of the analog voltage, specifically including:

[0028] The change value of the second capacitor voltage before and after exposure is divided by a coefficient to obtain an average value of the pulse width of the electrical signal pulse; the coefficient is related to the number of the electrical signal pulses and the clock frequency of the trigger clock is a multiple of the clock signal.

[0029] The present invention also provides an electronic device, characterized in that it comprises the photoelectric conversion device as described above.

[0030] Compared with the prior art, the photoelectric conversion device and electronic device provided by the present invention first use a counting module to count the number of photons received by the SPAD device, and when the count value reaches a set value, switch to a time analog conversion module to characterize the ambient light intensity. This achieves the expansion of the dynamic range of photon detection without increasing power consumption, so that photons can be detected when the light intensity is low or high, avoiding the situation where the counter is saturated due to the increase in light intensity, resulting in inaccurate counting. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A circuit diagram of a photoelectric sensor in the prior art.

[0032] Figure 2 The figure is a schematic diagram of the voltage waveform at the VC point when the SPAD device in the photoelectric sensor of the prior art avalanches.

[0033] Figure 3 The figure is a schematic diagram of the voltage waveform at the VO point when the SPAD device in the photoelectric sensor of the prior art avalanches.

[0034] Figure 4 Schematic diagram of light intensity.

[0035] Figure 5 The schematic diagram of the counting of photons received by the SPAD device of the prior art photoelectric sensor under low light intensity is shown.

[0036] Figure 6 The schematic diagram of the counting of photons received by the SPAD device of the prior art photoelectric sensor under strong light intensity is shown.

[0037] Figure 7 This is a structural block diagram of the photoelectric conversion device provided by the present invention.

[0038] Figure 8 This is a schematic diagram of the waveform correspondence of the clock signal, electrical signal pulse, count value, and pulse width value output by the time analog conversion module in the photoelectric conversion device provided by the present invention.

[0039] Fig. 9The photoelectric conversion device provided by the present invention respectively uses a counting module and a time analog conversion module to represent a waveform diagram of light intensity.

[0040] Fig.10 A circuit diagram of an embodiment of a time analog conversion module in a photoelectric conversion device provided by the present invention.

[0041] Fig.11 for Fig.10 Schematic diagram of the voltage waveforms of VO and VC1.

[0042] Fig.12 This is a circuit diagram of another embodiment of the time analog conversion module in the photoelectric conversion device provided by the present invention.

[0043] Fig.13 for Fig.12 Medium VO, V TRG 、V Dis Schematic diagram of the voltage waveform of VC2.

[0044] Description of Reference Numerals

[0045] SPAD device 11, quenching module 12, counting module 13, time analog conversion module 14, data processing module 15, first PMOS tube Q1, first NMOS tube Q2, second NMOS tube Q3, first capacitor C1, D trigger U1, inverter INVT, buffer A1, second PMOS tube Q4, third NMOS tube Q5, fourth NMOS tube Q6, fifth NMOS tube Q7, second capacitor C2, third capacitor C3 DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0047] See also Figure 7 The photoelectric conversion device provided by the present invention mainly includes a SPAD device 11, a quenching module 12, a counting module 13, a time analog conversion module 14 and a data processing module 15. The cathode of the SPAD device 11 is connected to a power supply end (such as a VDD power supply) and an input end of a logic module through the quenching module 12, and the anode of the SPAD device 11 is grounded; an external clock source is connected to another input end of the logic module and connected to the clock pulse input end STOP of the time analog conversion module 14. The output end of the logic module is connected to the input end of the counting module 13 and the control input end START of the time analog conversion module 14. The output end of the counting module 13 and the output end of the time analog conversion module 14 are connected to the input end of the data processing module 15.

[0048] The quenching module 12 is used to switch the working state according to the clock signal. When the quenching module 12 is in the conducting state, the SPAD device 11 is charged to the power supply voltage (i.e., the voltage VDD at the power supply end). When the quenching module 12 is in the non-conducting state, the SPAD device 11 waits for receiving a photon trigger. In one embodiment, the quenching module is a PMOS tube.

[0049] The SPAD device 11 is used to generate an electrical signal pulse VO according to the photon signal received for the first time in each clock cycle during the exposure period.

[0050] In one embodiment, the logic module is as follows Figure 7 As shown, an AND gate with an inverted input terminal is shown, the cathode voltage of the SPAD is recorded as VC, and the clock signal clk_R and VC are input to the AND gate. When a photon is incident on the SPAD, the value of VC changes from a high level to a low level. In this case, when the clock signal clk_R is at a high level, the output VO of the logic module becomes a high level. Then, when the clock signal clk_R changes from a high level to a low level, the output VO of the logic module changes to a low level, thereby generating an output signal, that is, an electrical signal pulse VO.

[0051] The counting module 13 is used to count the number of the electrical signal pulses VO output by the SPAD device 11 to obtain a count value. The counting module 13 is a counter used in existing SPAD image sensors, which is a prior art and will not be described in detail here.

[0052] The time analog conversion module 14 is used to convert the pulse width Ti (such as Figure 8 and converts it into the analog voltage cumulative value Vn. Figure 8 In the photoelectric conversion device of the present invention, the pulse width value of the electrical signal pulse VO is represented as a time signal, that is, the duration of the high level of the electrical signal pulse VO in one cycle.

[0053] The data processing module 15 is used to use the count value to characterize the ambient light intensity when the count value is not greater than the preset value; and is used to calculate the average value of the pulse width of the electrical signal pulse VO during the entire exposure period based on the accumulated value Vn of the analog voltage when the count value is greater than the preset value, convert the average value of the pulse width into an average voltage Vi, and use the average voltage Vi to characterize the ambient light intensity.

[0054] The present invention uses a counting module 13 to count the number of photons received by the SPAD device 11 first, and when the count value reaches a set value, it switches to the time analog conversion module 14 to characterize the ambient light intensity, thereby expanding the dynamic range of ambient light intensity detection without increasing power consumption, that is, the photoelectric conversion device can characterize the light intensity value under weak light and strong light. That is, when the count value is not greater than the preset value (that is, when the light intensity is low), the counting module 13 counts, and when the count value is greater than the preset value, the time analog conversion module 14 characterizes the ambient light intensity by the average value of the electrical signal pulses during the entire exposure period. The combination of the two methods can obtain a larger dynamic range with low power consumption.

[0055] like Fig. 9 As shown, in Fig. 9 The medium dynamic range DR1 is characterized by the count value (counter) provided by the counting module 13. However, when the light intensity reaches a certain value, the counting module 13 is saturated, i.e., the count is full. The present invention switches to the time analog conversion module 14 before the counting module is saturated. Fig. 9 The dynamic range DR2 in the time analog conversion module 14 is characterized by the analog voltage value output. Fig. 9 It can be seen that the dynamic range of SPAD detection of photons can be increased by combining the counting module 13 and the time analog conversion module 14. In weak light, the counting value of the counting module is used to represent the light intensity to ensure accuracy, while in strong light, the analog voltage output by the time analog conversion module is used to represent the light intensity to expand the detection range.

[0056] In an optional embodiment, the preset value is less than the maximum value of the counter. For example, the maximum count value of the counting module 13 can be 1024, and the preset value can be 1000. When the count value of the counter reaches 1000, the data processing module calculates the voltage value Vi corresponding to the average value of the pulse width of the electrical signal pulse VO during the entire exposure period according to the cumulative value Vn of the analog voltage of the time analog conversion module 14, and outputs Vi to represent the ambient light intensity, thereby expanding the dynamic range of photon detection without increasing power consumption, that is, the ambient light intensity can be detected when the light intensity is large or small.

[0057] like Figure 8 As shown, in the time analog conversion module 14, within one cycle of the clock signal, when the clock signal is at a high level, when the SPAD device 11 receives the first photon signal, the electrical signal pulse VO output by the time analog conversion module 14 changes from a low level to a high level; the pulse width value Ti of the electrical signal pulse VO is the time length between the first time point when the SPAD device 11 is first triggered by a photon to the second time point of the falling edge of the clock signal in each clock cycle.

[0058] However, it is not accurate to use only the electrical signal pulse VO within one clock cycle to characterize the light intensity. When one exposure is completed, it is necessary to obtain the pulse width value T1-Tn corresponding to the high level period of the electrical signal pulse VO_1-VO_n of the entire clock cycle during the exposure period, and then obtain the average value of the pulse width during the high level period of the electrical signal pulse VO by averaging. The stronger the light, the greater the average pulse width. The average pulse width reflects the light intensity, so the voltage corresponding to the average pulse width is linearly related to the light intensity. By calculating the voltage corresponding to the average pulse width, the light intensity value can be obtained.

[0059] In an optional embodiment, the high level of the clock signal provided by the clock source accounts for at least 80% of the clock cycle. For example, in one clock cycle, the high level accounts for 90% and the low level accounts for only 10%. The high level time is made as long as possible to receive more photons and improve the counting accuracy.

[0060] See also Fig.10 and Fig.11 In one optional embodiment of the photoelectric conversion device of the present invention, the time analog conversion module 14 includes a first PMOS tube Q1, a first NMOS tube Q2, a second NMOS tube Q3 and a first capacitor C1. When the gate of the first PMOS tube Q1 is at a low level, the MOS tube is turned on. When the gates of the first NMOS tube Q2 and the second NMOS tube Q3 are at a high level, the MOS tube is turned on.

[0061] The gate of the first PMOS tube Q1 is connected to the external bias power supply Vbias, the source of the first PMOS tube Q1 is connected to the power supply terminal VDD, the drain of the first PMOS tube Q1 is connected to the drain of the first NMOS tube Q2, the gate of the first NMOS tube Q2 is connected to the output end of the SPAD device 11, the source of the first NMOS tube Q2 is connected to one end of the first capacitor C1, the input end of the data processing module 15 and the drain of the second NMOS tube Q3, the source of the second NMOS tube Q3 and the other end of the first capacitor C1 are grounded, and the gate of the second NMOS tube Q3 is connected to the first external control terminal VR. Among them, the external bias power supply Vbias and the first external control terminal VR can be provided by a chip or a switch, and the provision method is not a protection point of the present invention and is not described in detail here.

[0062] If a photon reaches the SPAD device 11 during the high level period of clk_R, when the SPAD device 11 receives the photon, the first NMOS tube Q2 is turned on and the second NMOS tube Q3 is turned off to charge the first capacitor C1. When the exposure is completed, the second NMOS tube Q3 is turned on and the first NMOS tube Q2 is turned off to release the charge of the first capacitor C1, waiting for the next exposure.

[0063] In this embodiment, the first PMOS tube Q1 is used to provide a charging current for the first capacitor C1. During the exposure period, the first PMOS tube Q1 is continuously turned on to provide a charging current for the first capacitor C1. The first PMOS tube is controlled to be continuously turned on by an external bias power supply Vbias, and the magnitude of the charging current can be controlled, which is recorded as I. The first NMOS tube Q2 and the second NMOS tube Q3 both act as switches. Whether the first NMOS tube Q2 is turned on is controlled by the high and low level states of the electrical signal pulse VO. When the electrical signal pulse VO is at a high level, the first NMOS tube Q2 is turned on, and the current I at each turn-on is used to charge the first capacitor C1. The second NMOS tube Q3 is disconnected when the SPAD is normally exposed. When the exposure is over, the second NMOS tube Q3 is turned on to release the charge on the first capacitor C1 and wait for the next exposure. By charging and discharging the first capacitor C1 multiple times, more photons can be counted.

[0064] Exposure starts. When the SPAD device receives photons, the output of the SPAD device controls the first NMOS tube Q2 to turn on, thereby charging the first capacitor C1. At this time, the second NMOS tube Q3 is disconnected. When the SPAD device does not receive photons, the output of the SPAD device controls the first NMOS tube Q2 to turn off. At this time, the second NMOS Q3 is turned on to release the charge of the first capacitor C1, waiting for the next exposure.

[0065] In this embodiment, the average value of the pulse width of the electrical signal pulse VO during the entire exposure period is calculated based on the accumulated value Vn of the analog voltage, specifically including: dividing the change value of the voltage of the first capacitor C1 before and after exposure by the number of electrical signal pulses VO, to obtain the average voltage of the analog voltage corresponding to the pulse width of the electrical signal pulse VO, and used to characterize the ambient light intensity, wherein the pulse width is linearly related to the analog voltage, and the analog voltage is linearly related to the light intensity.

[0066] However, in this embodiment, the capacitance of the first capacitor C1 needs to be very large, and the charging current needs to be very small, so that the amount of charge charged each time is smaller, that is, Q1=C1V=It. In this way, during the entire exposure period, when the electrical signal pulse VO outputs a pulse, the first capacitor C1 can be charged, and it will not be fully charged quickly, otherwise it will affect the stability of the ambient light intensity measurement. However, the larger the capacitance of the capacitor, the larger the volume of the capacitor, which makes the capacitor occupy a large space, does not meet the requirements of the miniaturization development of the photoelectric conversion device, and increases the cost.

[0067] from Fig.11It can be seen that as the number of photons received per clock increases, the voltage of VC1 gradually increases, but VC1 only increases to VDD at most. If VDD is 1.1v / 3.3v / 2.5v, in order to prevent VC1 from increasing too quickly, the capacitance of the first capacitor C1 must be increased. The increase in capacitance will increase the chip area and the cost of the photoelectric sensor.

[0068] In another optional embodiment of the photoelectric conversion device of the present invention, please refer to Fig.12 and Fig.13 The time analog conversion module 14 includes: a D trigger U1, an inverter INVT, a buffer A1, a second PMOS tube Q4, a third NMOS tube Q5, a fourth NMOS tube Q6, a fifth NMOS tube Q7, a second capacitor C2 and a third capacitor C3. When the gate of the second PMOS tube Q4 is low level and turned on, and when the gates of the third NMOS tube Q5, the fourth NMOS tube Q6 and the fifth NMOS tube Q7 are high level, the MOS tubes are turned on.

[0069] The input end of the D flip-flop U1 is connected to the output end of the SPAD device 11, the clock pulse input end of the D flip-flop U1 (the clock pulse input end STOP of the time analog conversion module 14) is connected to the trigger clock, the output end of the D flip-flop U1 is connected to the gate of the third NMOS tube Q5, the input end of the inverter INVT and the input end of the buffer A1, the output end of the inverter INVT is connected to the reset end of the D flip-flop U1, the output end of the buffer A1 is connected to the gate of the fifth NMOS tube Q7, the gate of the second PMOS tube Q4 is connected to the second external control Terminal RSTB1, the source of the second PMOS tube Q4 is connected to the power supply terminal VDD, the drain of the second PMOS tube Q4 is connected to the drain of the third NMOS tube Q5 and one end of the second capacitor C2, the source of the third NMOS tube Q5 is connected to the drain of the fourth NMOS tube Q6, the gate of the fourth NMOS tube Q6 is connected to the third external control terminal Vb, the source of the fourth NMOS tube Q6 is connected to the drain of the fifth NMOS tube Q7 and one end of the third capacitor C3, the source of the fifth NMOS tube Q7, the other end of the second capacitor C2, and the other end of the third capacitor C3 are all grounded. Among them, the second external control terminal RSTB1 and the third external control terminal Vb can be provided by a chip or a switch, and the provision method is not a protection point of the present invention and is not described in detail here.

[0070] The clock frequency of the trigger clock is n times the clock signal. Before the exposure starts, the second external control terminal RSTB1 controls the second PMOS tube Q4 to turn on, and the power supply terminal VDD charges the second capacitor C2 to wait for exposure. After the exposure starts, the fourth NMOS tube Q6 is turned on, and the second external control terminal RSTB1 controls the second PMOS tube Q4 to turn off. When the electrical signal pulse is at a high level, each time the trigger clock rises, the trigger outputs a high-level signal to turn on the third NMOS tube Q5. At this time, the charge of the second capacitor C2 is discharged to the third capacitor C3 through the third NMOS tube Q5 and the fourth NMOS tube Q6, and the fifth NMOS tube Q7 is disconnected; the high-level signal output by the D trigger passes through the inverter INVT as the reset signal of the D trigger U1, so that the output of the D trigger is reset to a low-level signal to disconnect the third MOS tube Q5. Due to the effect of the delay device, the fifth NMOS tube Q7 is turned on at this time, and the charge of the third capacitor C3 is discharged to the ground. During the exposure period, the charge on the second capacitor C2 will be continuously discharged according to the high level of the electrical signal pulse.

[0071] In this embodiment, the average value of the pulse width of the electrical signal pulse VO during the entire exposure period is calculated based on the accumulated value Vn of the analog voltage, specifically including: dividing the change value of the voltage of the second capacitor C2 before and after exposure by a coefficient to obtain the average value of the pulse width of the electrical signal pulse VO; the coefficient is related to the number of the electrical signal pulses and the clock frequency of the trigger clock is a multiple of the clock signal.

[0072] In specific implementation, the clock frequency of the trigger clock ck2 is n times of the clock signal. Under the premise of the same clock source, the clock frequency can be changed to n times by using a frequency multiplier, a phase-locked loop, a resonator, etc. as the trigger clock ck2. In this embodiment, ck2 is used as the clock of the D flip-flop U1, the electrical signal pulse VO is used as the input signal of the D flip-flop U1, and the output VTRG of the D flip-flop U1 is used as the control signal of whether the third NMOS tube Q5 is turned on. Before the exposure starts, the signal RSTB1 controls the second PMOS tube Q4 to turn on, and the VDD power supply charges the second capacitor C2, waiting for the exposure to start.

[0073] After the exposure starts, RSTB1 is at a low level to control the second PMOS tube Q4 to turn off and stop charging the second capacitor C2. When the electrical signal pulse VO is at a high level and each time ck2 rises, the V output by the D trigger U1 TRG The signal becomes high level to turn on the third NMOS tube Q5, and after passing through the inverter INVT, it serves as the reset signal of the D flip-flop U1. TRG The signal is reset to a low level to disconnect the third NMOS tube Q5; therefore, at V TRG When the signal is at a high level, the third NMOS transistor Q5 is turned on, and when the signal is at a low level, the third NMOS transistor Q5 is turned off.

[0074] During the exposure period, the fourth NMOS tube Q6 is always in the on state. When the third NMOS tube Q5 is on, the fifth NMOS tube Q7 is off, and the charge on the second capacitor C2 is discharged to the third capacitor C3 through the third NMOS tube Q5 and the fourth NMOS tube Q6. When the third NMOS tube Q5 is off, the fifth NMOS tube Q7 is on, so that the charge on the third capacitor C3 is discharged to the ground through the fifth NMOS tube Q7.

[0075] During the exposure period, the charge on the second capacitor C2 is continuously discharged according to the pulse of the electrical signal pulse VO, so that the second capacitor C2 and the third capacitor C3 do not need capacitors with too large capacitance.

[0076] In an optional embodiment, the clock frequency of the trigger clock is 5 times that of the clock signal, that is, n is 5. In one cycle of the clock signal, when the electrical signal pulse is at a high level, the trigger clock has 1-4 rising edges, so that the third NMOS tube Q5 is turned on 1-4 times. Fig.13 As shown, in one clock cycle, when the clock signal is at a high level, the trigger clock has four clock rising edges, so that the third NMOS transistor Q5 and the fifth NMOS transistor Q7 can be turned on three times.

[0077] Furthermore, the capacitance of the second capacitor C2 is M times that of the third capacitor C3, and M is greater than the number of the electrical signal pulses VO during the exposure period.

[0078] In another optional embodiment of the present invention, Fig.12 , the voltage VC2 on the second capacitor C2 indirectly reflects the cumulative value of the pulse width of the electrical signal pulse VO; in one cycle of the clock signal, the electrical signal pulse VO is at a high level, ck2 has 1-4 rising edges, so the third NMOS tube Q5 is turned on 1-4 times, and the second capacitor C2 will discharge 1-4 times of charge, but the time of each discharge is very short, so during the exposure period, the second capacitor C2 can always discharge the charge according to the high pulse of the electrical signal pulse VO, but it will not be discharged quickly. The charge discharged each time is determined by the third capacitor C3 and the voltage on the third capacitor C3, achieving a more precise control of the voltage VC2 drop, and the voltage VC2 gradually decreases, and during the exposure period, there is always a voltage on the second capacitor C2, and it does not drop to 0 quickly, so that a more accurate ambient light intensity can be obtained during the exposure period.

[0079] according to Fig.12 and Fig.13, the charge Q2 on the second capacitor C2 is C2*VDD, and the voltage V3 on the third capacitor C3 is Vb-Vgs(Q6). Therefore, the charge Q3 charged each time by the third capacitor C3 is C3*V3. Therefore, each time the third NMOS tube Q5 is turned on, the charge discharged from the third NMOS tube Q5 is determined by the third capacitor C3, that is, Q2 / Q3=K*C2 / C3=the number of Vtrg pulses=M. The value of M indicates how many times the VTRG pulse signal can be discharged from the second capacitor C2. Therefore, this embodiment focuses on the value of M and no longer focuses on the absolute value of the second capacitor C2, thereby reducing the area of ​​the second capacitor C2.

[0080] The present invention further provides an electronic device, which includes the above-mentioned photoelectric conversion device. The electronic device may be a scanner. Since the photoelectric conversion device has been described in detail above, it will not be described again here.

[0081] In summary, the present invention adopts a method of first using a counting module to count the number of photons received by the SPAD device, and when the count value reaches a set value, switching to a time analog conversion module to characterize the ambient light intensity, thereby expanding the dynamic range of photon detection without increasing power consumption, so that photons can be detected when the light intensity is low or high, avoiding the situation where the counter is saturated due to the increase in light intensity and causing inaccurate counting.

[0082] At the same time, the present invention does not need to increase the number of bits and clock frequency of the counter, so that the photoelectric conversion device can be small in size, low in power consumption, and low in product cost. When the light intensity is low, a counting module is used for counting. When the counting module is close to saturation, a time analog conversion module is used to characterize the ambient light intensity, thereby ensuring the working efficiency of the photoelectric conversion device and enabling it to maintain good performance under different lighting conditions.

[0083] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of the present invention, and all these changes or substitutions should fall within the protection scope of the claims attached to the present invention.

Claims

1. A photoelectric conversion device, characterized in that: It includes a SPAD device, a quenching module, a counting module, a time analog conversion module and a data processing module; The quenching module is used to switch the working state according to the clock signal. When the quenching module is in the conducting state, the SPAD device is charged to the power supply voltage. When the quenching module is in the non-conducting state, the SPAD device waits for receiving a photon trigger. The SPAD device is used to generate an electrical signal pulse according to the photon signal received for the first time in each clock cycle during the exposure period; The counting module is used to count the number of the electrical signal pulses output by the SPAD device to obtain a count value; The time analog conversion module is used to convert the pulse width values ​​of the electrical signal pulses in all clock cycles into the cumulative value of the analog voltage; The data processing module is used to use the count value to represent the ambient light intensity when the count value is not greater than a preset value; And when the count value is greater than a preset value, the average voltage corresponding to the average value of the pulse width of the electrical signal pulse during the entire exposure period is calculated according to the accumulated value of the analog voltage, and the average voltage is used to characterize the ambient light intensity.

2. The photoelectric conversion device according to claim 1, characterized in that: The preset value is smaller than the maximum value of the counter.

3. The photoelectric conversion device according to claim 1, characterized in that: During the high level period of the clock signal, when the SPAD device receives a photon signal, the electrical signal pulse is at a high level; The pulse width of the electrical signal pulse is the time length between the first time point when the SPAD device is first triggered by a photon in each clock cycle and the second time point of the falling edge of the clock signal.

4. The photoelectric conversion device according to claim 1, characterized in that: The proportion of the high level of the clock signal to the clock period is at least 80%.

5. The photoelectric conversion device according to claim 1, characterized in that: The time analog conversion module includes a first PMOS tube, a first NMOS tube, a second NMOS tube and a first capacitor, the gate of the first PMOS tube is connected to an external bias power supply, the source of the first PMOS tube is connected to a power supply terminal, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the gate of the first NMOS tube is connected to the output terminal of the SPAD device, the source of the first NMOS tube is connected to one end of the first capacitor, the input terminal of the data processing module and the drain of the second NMOS tube, the source of the second NMOS tube and the other end of the first capacitor are grounded, and the gate of the second NMOS tube is connected to the first external control terminal; The external bias power supply controls the first PMOS tube to be continuously turned on to provide charging current for the first capacitor; when exposure starts, when the SPAD device receives photons, the output of the SPAD device controls the first NMOS tube to be turned on to charge the first capacitor, and the second NMOS tube is disconnected at this time; when exposure ends, the output of the SPAD device controls the first NMOS tube to be turned off, and the second NMOS tube is turned on to release the charge of the first capacitor, waiting for the next exposure.

6. The photoelectric conversion device according to claim 5, characterized in that: Calculating the average voltage corresponding to the average value of the pulse width of the electrical signal pulses during the entire exposure period according to the accumulated value of the analog voltage, specifically includes: The change value of the voltage of the first capacitor before and after exposure is divided by the number of electrical signal pulses to obtain an average voltage corresponding to the average value of the pulse width of the electrical signal pulses.

7. The photoelectric conversion device according to claim 1, characterized in that: The time analog conversion module includes: a D trigger, an inverter, a buffer, a second PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second capacitor and a third capacitor, the input end of the D trigger is connected to the output end of the SPAD device, the clock pulse input end of the D trigger is connected to the trigger clock, the output end of the D trigger is connected to the gate of the third NMOS tube, the input end of the inverter and the input end of the buffer, the output end of the inverter is connected to the reset end of the D trigger, the output end of the buffer is connected to the gate of the fifth NMOS tube, the gate of the second PMOS tube is connected to the second external control end, the source of the second PMOS tube is connected to the power supply end, the drain of the second PMOS tube is connected to the drain of the third NMOS tube and one end of the second capacitor, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the third external control end, the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube and one end of the third capacitor, the source of the fifth NMOS tube, the other end of the second capacitor and the other end of the third capacitor are all grounded; The clock frequency of the trigger clock is n times that of the clock signal. Before the exposure starts, the second external control terminal controls the second PMOS tube to be turned on, and the power supply of the power supply terminal charges the second capacitor; After the exposure starts, the fourth NMOS tube is turned on, and the second external control terminal controls the second PMOS tube to be turned off. When the electrical signal pulse is at a high level, each time the rising edge of the trigger clock occurs, the D trigger outputs a high level signal to turn on the third NMOS tube. At this time, the charge of the second capacitor is discharged to the third capacitor through the third NMOS tube and the fourth NMOS tube, and the fifth NMOS tube is turned off. The high level signal output by the D trigger passes through the inverter and serves as a reset signal of the D trigger. The output of the D trigger is reset to a low level signal to turn off the third NMOS tube. At this time, the fifth NMOS tube is turned on, and the charge of the third capacitor is discharged to the ground. During the exposure period, the charge on the second capacitor will be continuously discharged according to the high level of the electrical signal pulse.

8. The photoelectric conversion device according to claim 7, characterized in that: The clock frequency of the trigger clock is 5 times that of the clock signal. Within one cycle of the clock signal, when the electrical signal pulse is at a high level, the trigger clock has 1-4 rising edges, causing the third NMOS tube to be turned on 1-4 times.

9. The photoelectric conversion device according to claim 7, characterized in that: The capacitance of the second capacitor is M times that of the third capacitor, and M is greater than the number of the electrical signal pulses during the exposure period.

10. The photoelectric conversion device according to claim 7, characterized in that: Calculating the average value of the pulse width of the electrical signal pulse during the entire exposure period according to the accumulated value of the analog voltage, specifically including: The change value of the second capacitor voltage before and after exposure is divided by a coefficient to obtain an average value of the pulse width of the electrical signal pulse; the coefficient is related to the number of the electrical signal pulses and the clock frequency of the trigger clock is a multiple of the clock signal.

11. An electronic device, characterized in that: Comprising the photoelectric conversion device according to any one of claims 1 to 10.

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