Software and hardware decoupling brain-like computing compiling method and device and compiling framework

Abstract

The invention relates to the technical field of brain-like computing compiling, in particular to a software and hardware decoupling brain-like computing compiling method and device and a compiling framework. The method comprises the following steps: converting a to-be-compiled brain-like computing application into a first intermediate expression, wherein the first intermediate expression is used for being identified by a compiled framework; converting the first intermediate expression into a second intermediate expression, wherein the abstraction level of the second intermediate expression is lower than that of the first intermediate expression; and converting the second intermediate expression into an underlying hardware expression, wherein the underlying hardware expression is used for generating a parameter file running on target hardware. According to the method provided by the embodiment of the invention, based on the design idea of software and hardware decoupling, the brain-like computing application is hierarchically reduced to the underlying hardware expression by using the multi-layer intermediate expression, and efficient support for different types of applications is realized.

Description

Technical Field

[0001] The present disclosure relates to the field of brain-like computing compilation technology, and in particular to a software-hardware decoupled brain-like computing compilation method, device, and compilation framework. Background Art

[0002] With the rapid development of artificial intelligence technology, brain-like computing, as an important research direction of the next generation of artificial intelligence, has shown great potential and application prospects. As one of the major development directions of the post-Moore era architecture, brain-like computing hardware has significant advantages in dealing with problems in specific fields. In particular, Spiking Neural Network (SNN), as the core computing paradigm of brain-like computing, is considered to be one of the key technologies to promote the development of artificial intelligence.

[0003] However, how to efficiently run various brain-inspired computing applications on the developed architecture or chip remains a technical challenge. Currently, teams developing brain-inspired computing models and algorithms are faced with the challenge of achieving efficient computing on different brain-inspired chips. The provision and convenient use of efficient computing power are crucial to the development of algorithms, which has been proven in the development of deep learning.

[0004] At present, there is no universal compilation framework for various types of brain-like computing chips. Most of the current compilation software is designed for specific hardware. Although it can achieve good performance on the target architecture, this design limits the reusability of software modules, interoperability and composability between tool chains, and increases the cost of developing new chip compilers. For different types of brain-like computing applications, their computing characteristics vary greatly, making it difficult to efficiently support diverse application requirements. These problems limit the widespread application and rapid development of brain-like computing technology. Summary of the invention

[0005] In view of this, the present disclosure proposes a brain-like computing compilation method, device and compilation framework with software and hardware decoupling, which can improve the operating efficiency and compatibility of brain-like computing applications on different hardware platforms.

[0006] According to one aspect of the present disclosure, a method for brain-like computing compilation with software-hardware decoupling is provided, the method comprising:

[0007] Converting the brain-like computing application to be compiled into a first intermediate expression, where the first intermediate expression is used to be recognized by a compilation framework;

[0008] converting the first intermediate expression into a second intermediate expression, wherein the abstraction level of the second intermediate expression is lower than the abstraction level of the first intermediate expression;

[0009] The second intermediate expression is converted into an underlying hardware expression, where the underlying hardware expression is used to generate a parameter file running on target hardware.

[0010] In a possible implementation, converting the first intermediate expression into a second intermediate expression includes:

[0011] The first intermediate expression is converted into the second intermediate expression according to the operator attributes of the brain-like computing application provided by the first intermediate expression, wherein the operator attributes are used to indicate the storage format of the neuron's pulses and / or the storage format of the neuron's synapses.

[0012] In another possible implementation, the storage format of the pulse includes: a dense storage format or a sparse storage format; and / or,

[0013] The storage format of the synapse includes: one of a dense storage format, a compressed sparse row (Compressed Sparse Row, CSR) storage format, and an expanded compressed sparse row (Expanded Compressed Sparse Row, ECSR) storage format, and the ECSR format is used to indicate that synapses with different delays are stored in the same CSR matrix.

[0014] In another possible implementation, the brain-like computing application includes operators and operator attributes, the operators include at least one of a neuron update operator, a synaptic propagation operator, a neuron definition operator, and a synapse definition operator, and the operator attributes include format attributes and / or delay attributes, the format attributes are used to indicate whether the operator is sparse, and the delay attributes are used to indicate whether the operator has a delay.

[0015] In another possible implementation manner, the synaptic propagation operator is converted into a bottom-level operator in the process of converting the second intermediate expression into the bottom-level hardware expression.

[0016] In another possible implementation, the method further includes:

[0017] When there are multiple operators in the brain-inspired computing application that meet a preset merging condition, merging the multiple operators;

[0018] The preset merging condition includes that the operator types of the multiple operators are the same.

[0019] In another possible implementation, the method further includes:

[0020] In the intermediate expression conversion process, for each input operator, a corresponding output operator is determined according to a preset conversion model, and the abstract level of the output operator is lower than the abstract level of the input operator;

[0021] The preset conversion model is used to indicate the mapping relationship between the preset input operator and the output operator.

[0022] According to another aspect of the present disclosure, a brain-like computing compilation device with software and hardware decoupling is provided, the device comprising:

[0023] A first conversion module, configured to convert the brain-inspired computing application to be compiled into a first intermediate expression, where the first intermediate expression is used to be recognized by a compilation framework;

[0024] a second conversion module, configured to convert the first intermediate expression into a second intermediate expression, wherein the abstraction level of the second intermediate expression is lower than the abstraction level of the first intermediate expression;

[0025] The third conversion module is used to convert the second intermediate expression into an underlying hardware expression, where the underlying hardware expression is used to generate a parameter file running on target hardware.

[0026] In a possible implementation manner, the second conversion module is further configured to:

[0027] The first intermediate expression is converted into the second intermediate expression according to the operator attributes of the brain-like computing application provided by the first intermediate expression, wherein the operator attributes are used to indicate the storage format of the neuron's pulses and / or the storage format of the neuron's synapses.

[0028] In another possible implementation, the storage format of the pulse includes: a dense storage format or a sparse storage format; and / or,

[0029] The storage format of the synapse includes: one of a dense storage format, a CSR storage format, and an ECSR storage format, and the ECSR format is used to indicate that synapses with different delays are stored in the same CSR matrix.

[0030] In another possible implementation, the brain-like computing application includes operators and operator attributes, the operators include at least one of a neuron update operator, a synaptic propagation operator, a neuron definition operator, and a synapse definition operator, and the operator attributes include format attributes and / or delay attributes, the format attributes are used to indicate whether the operator is sparse, and the delay attributes are used to indicate whether the operator has a delay.

[0031] In another possible implementation manner, the synaptic propagation operator is converted into a bottom-level operator in the process of converting the second intermediate expression into the bottom-level hardware expression.

[0032] In another possible implementation, the device further includes: a merging module, configured to:

[0033] When there are multiple operators in the brain-inspired computing application that meet a preset merging condition, merging the multiple operators;

[0034] The preset merging condition includes that the operator types of the multiple operators are the same.

[0035] In another possible implementation, the apparatus further includes: a determining module, configured to:

[0036] In the intermediate expression conversion process, for each input operator, a corresponding output operator is determined according to a preset conversion model, and the abstract level of the output operator is lower than the abstract level of the input operator;

[0037] The preset conversion model is used to indicate the mapping relationship between the preset input operator and the output operator.

[0038] According to another aspect of the present disclosure, a brain-like computing compilation device with software and hardware decoupling is provided, the device comprising:

[0039] processor;

[0040] a memory for storing processor-executable instructions;

[0041] Wherein, the processor is configured to implement the above method when executing the instructions stored in the memory.

[0042] According to another aspect of the present disclosure, a brain-like computing compilation framework with software-hardware decoupling is provided, and the compilation framework is used to implement the above method.

[0043] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0044] According to another aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0045] The disclosed embodiment proposes a brain-like computing compilation method with software-hardware decoupling, which converts the brain-like computing application to be compiled into a first intermediate expression, which is used to be recognized by the compilation framework, converts the first intermediate expression into a second intermediate expression, and the abstract level of the second intermediate expression is lower than the abstract level of the first intermediate expression, and converts the second intermediate expression into a bottom-level hardware expression, which is used to generate a parameter file running on the target hardware; that is, the method is based on the design concept of software-hardware decoupling, uses multi-level intermediate representation (MLIR), and hierarchically descends the brain-like computing application to the bottom-level hardware primitives, thereby achieving efficient support for different types of applications, and can effectively solve the problem of low running efficiency of brain-like computing applications on different hardware platforms in related technologies, improve the reusability, interoperability and composability of compilers, reduce the cost of developing new chip compilers, and accelerate the development and application of brain-like computing technology.

[0046] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0048] Figure 1 A schematic diagram showing an application scenario provided by an exemplary embodiment of the present disclosure is shown.

[0049] Figure 2 A flowchart of a method for brain-like computing compilation with software-hardware decoupling provided by an exemplary embodiment of the present disclosure is shown.

[0050] Figure 3 A schematic diagram of a compilation framework provided by an exemplary embodiment of the present disclosure is shown.

[0051] Figure 4 A schematic diagram of user-defined data provided by an exemplary embodiment of the present disclosure is shown.

[0052] Figure 5 A schematic diagram of the structure of a brain-like computing compilation device with software and hardware decoupling provided by an exemplary embodiment of the present disclosure is shown.

[0053] Figure 6 It is a block diagram of a device for executing a software-hardware decoupled brain-like computing compilation method according to an exemplary embodiment. DETAILED DESCRIPTION

[0054] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0055] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0056] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0057] Brain-like computing compilation software is used to transform various brain-like computing applications into executable forms that can efficiently drive brain-like computing chips with different architectures. This is also conducive to uniting research forces in various fields to form a good R&D ecosystem, such as applying new discoveries in the field of neurology to the field of AI, or widely and efficiently applying the latest (brain-like) computing chips to help new algorithms evolve and be applied quickly.

[0058] At present, there is still a blank of universal compilation framework for various brain-like computing chips. The brain-like computing compilation framework is a compilation infrastructure (English: compiler infrastructure) that is not targeted at specific hardware. Through flexible multi-level internal architecture, intermediate representation and interface, it can be extended to support a variety of brain-like computing applications and brain-like computing chips. This is different from the current compilation software for specific brain-like chips. The latter can achieve good performance on the target architecture, but the interfaces between each software module and layer are oriented to the target chip, which limits the reusability of software modules, interoperability and composability between tool chains, and the cost of developing new chip compilers is high.

[0059] At present, compilers or SNN simulation frameworks for brain-like chips are set up for various brain-like computing applications. Among them, compilers for brain-like chips mainly depend on target chips. For example, chips based on emerging neuromorphic devices complete synaptic processing and / or neuron computing in the form of analog circuits. The above-mentioned many brain-like chips generally come with their own tool chain software, the core part of which is the compiler. The compiler is one of the key components of the basic software for brain-like computing, but it is currently mainly custom-designed for target chips. This limits the reusability of software modules, the interoperability and composability between tool chains, and the cost of developing new chip compilers is high.

[0060] SNN simulation frameworks are often developed for CPUs and general-purpose GPUs, such as Spikingjelly and Nest. Spikingjelly is a simulator based on Pytorch, and it implements automatic differentiation, gradient substitution, parallel acceleration, etc.; it currently also supports the deployment of spiking neural network applications on different brain-like chips. Nest is a spiking neural network simulator developed in python. NEST mainly supports the simulation of the nervous system and supports spike-timing dependent plasticity (STDP) training.

[0061] For brain-like computing applications, the computing characteristics of different applications vary greatly, and it is difficult to efficiently support different types of applications. For current spiking neural network simulation tools, they are usually optimized for different applications. For example, NEST focuses on supporting examples of computational neurology, and SpikingJelly focuses on supporting deep spiking neural network (DSNN) applications. This leads to inconvenience and low efficiency in using the simulation framework.

[0062] That is to say, there are the following technical problems in the relevant technology: First, the application computing characteristics span a large range. From the perspective of computing and data access characteristics, the span is large and complex - from DSNNs with intensive computing and (relatively) regular data access, to applications characterized by sparse event-triggered computing and irregular data access (such as simulations of biological neural networks derived from neuroscience), and the latter's rich spatiotemporal neural dynamics characteristics give this computing model greater room for optimization. Second, the chip architecture spans a large range. Since there is currently no widely accepted technical route for brain-like computing chips, the span of the microarchitecture is also large, from the mature traditional von Neumann architecture to the data flow architecture based on emerging neuromorphic devices, and there are various hybrid architectures between the two ends, such as Tianji chips, Loihi, GaBAN, etc. Moreover, the granularity of the hardware primitives provided by the chip is very different. For example, the SpiNNaker chip based on the traditional von Neumann architecture uses the ARM soft core as the computing core and provides the traditional general instruction set as a fine-grained hardware and software interface, while many brain-like chips (such as TrueNorth, BrainScaleS, etc.) expose the hardware functions of the neuron model granularity as a coarse-grained interface. There are also storage and computing integrated chips based on emerging non-volatile devices that use the crossbar structure as the main computing body, that is, directly use a certain scale of dot product calculation as a hardware primitive. This requires the implementation of a unified compilation framework with high resource reuse on these chips with different architectures to improve development efficiency (English: productivity), and at the same time, it is necessary to be able to flexibly combine compilation optimization methods of different levels to achieve high performance (English: performance portability) on different backends for different applications.

[0063] Therefore, the disclosed embodiment designs a set of brain-like computing compilation methods that decouple software and hardware, and hierarchically descends brain-like computing applications (such as pulse neural network applications) to the underlying hardware primitives through multiple layers of intermediate expressions. This not only supports different types of applications, but also allows the brain-like computing compilation method to start development from the intermediate layer when new brain-like computing hardware is proposed, reusing the general optimization in brain-like computing compilation.

[0064] It should be noted that the compilation framework provided in the embodiment of the present disclosure is mainly for developers of brain-like chips and brain-like application development tools, while the compiler or simulator is for application developers. That is to say, the compilation framework of the embodiment of the present disclosure is intended to provide efficient tools for developers of brain-like chips and brain-like application development tools, who are responsible for using this compilation framework to more efficiently generate new compilers for target hardware. This framework helps them convert brain-like computing applications described in high-level languages ​​into parameter files that can be executed by target hardware. In contrast, compilers or simulators focus more on the needs of application developers, who use these compilers or simulators to run and test specific applications. Unlike traditional SNN simulators or compilers, the compilation framework of multi-layer intermediate expressions used in the embodiment of the present disclosure facilitates the development of new compilation backends, supports the use of operator attributes to describe the characteristics of brain-like computing applications, supports partial reduction of brain-like computing applications during compilation, and reuses compiler optimization, that is, the compilation framework allows the compilation process from the first intermediate expression to the second intermediate expression to be reused to a certain extent between different hardware backends, which reduces the workload of developing optimizations for each hardware separately, allowing different hardware backends to reuse the same intermediate optimization steps, improving the efficiency of the compiler, and possibly improving cross-platform performance.

[0065] Figure 1 A schematic diagram of an application scenario provided by an exemplary embodiment of the present disclosure is shown. The application scenario includes a brain-like computing application 11, a compiler 12, and target hardware 13.

[0066] Brain-like computing applications 11 refer to computing applications that simulate the structure and function of human brain neuron networks. This application usually involves a large number of neurons and synaptic connections, as well as complex dynamic behaviors. In order to realize this application, specific programming languages ​​and tools are needed to describe the structure and function of neural networks. Brain-like computing applications are neural network applications, and the neural network can be SNN, DSNN or biological pulse neural network. Among them, SNN is an artificial neural network modeled based on the pulse behavior of neurons, which can imitate the mechanism of information exchange and transmission of neurons in the human brain through discrete action potentials. DSNN is an extension of SNN, which simulates more complex neural activities through a multi-layer network structure. DSNN is mainly used to complete artificial intelligence (AI) tasks. Biological pulse neural networks focus more on starting from a biological perspective, trying to simulate the physiological structure and function of the human brain more realistically, and biological pulse neural network simulation is used for biological simulation calculations.

[0067] The compiler 12 is a tool that converts high-level language code into machine language code. In brain-like computing compilation, the compiler 12 is a bridge connecting the brain-like computing application 11 and the target hardware 13. The core function of the compiler 12 is to convert the brain-like computing application 11 written in a high-level language into a format that the target hardware 13 can understand and execute.

[0068] The target hardware 13 refers to the actual physical device that runs the brain-like computing application 11. In brain-like computing compilation, the target hardware 13 is usually a dedicated hardware platform with a large number of parallel processing units and a high-speed interconnect network. These hardware platforms can efficiently simulate the dynamic behavior of neural networks and provide sufficient computing power and storage space to support the operation of large-scale neural networks. The target hardware 13 can be a brain-like computing chip. For example, the target hardware is a general-purpose graphics processing unit (GPGPU).

[0069] The functions involved in this application scenario include but are not limited to the following: 1. Receiving brain-like computing applications 11: The compiler 12 receives brain-like computing application codes written in high-level languages ​​(such as Python, C++, etc.). These codes usually contain information such as neural network models, algorithm descriptions, and parameter configurations. 2. Generating intermediate representations: The compiler 12 converts application codes written in high-level languages ​​into multiple intermediate representations, and hierarchically descends brain-like computing applications to hardware-based primitives through multiple layers of intermediate expressions. These intermediate representations are closer to machine languages, but still maintain a certain degree of abstraction to facilitate subsequent optimization and conversion. 3. Optimization and conversion: At the intermediate representation level, the compiler 12 implements various optimization strategies to improve the efficiency and performance of the final execution. 4. Mapping to brain-like computing chips: The compiler 12 further converts the optimized intermediate representation into the underlying hardware expression of the target hardware. 5. Generate executable files: Finally, the compiler 12 generates parameter files that can be run on the target hardware, that is, executable files. These files contain all the necessary information required to configure and control the target hardware. 6. Loading and execution: The generated parameter files are loaded onto the target hardware and executed by the target hardware to complete specific computing tasks.

[0070] The compiler 12 is used to execute the software-hardware decoupled brain-like computing compilation method provided in the embodiment of the present disclosure, that is, the compiler 12 is used to convert the brain-like computing application to be compiled into a first intermediate expression, and the first intermediate expression is used to be recognized by the compilation framework; convert the first intermediate expression into a second intermediate expression, and the abstract level of the second intermediate expression is lower than the abstract level of the first intermediate expression; convert the second intermediate expression into an underlying hardware expression, and the underlying hardware expression is used to generate a parameter file running on the target hardware.

[0071] Below, several illustrative embodiments are used to further introduce the software-hardware decoupled brain-like computing compilation method provided by the embodiments of the present disclosure.

[0072] Please refer to Figure 2 , which shows a flowchart of a method for brain-like computing compilation with software and hardware decoupling provided by an exemplary embodiment of the present disclosure. This embodiment uses this method for Figure 1 The method is illustrated in the compiler shown in FIG.

[0073] Step 201: convert the brain-like computing application to be compiled into a first intermediate expression, where the first intermediate expression is used to be recognized by a compilation framework.

[0074] The purpose of converting brain-like computing applications (including operators and operator attributes) written in high-level languages ​​into the first intermediate expression is to enable the compilation framework to recognize and process this information. Optionally, this step may include the following: analyzing the operators and operator attributes in the brain-like computing application; generating the first intermediate expression according to the operators and operator attributes. In the compilation process, the intermediate representation (IR) is a representation of one or more abstract levels in the process of converting source code to target code. They are usually used in different stages of the compiler to facilitate optimization and code generation. The following is a glossary of the first intermediate expression: The first intermediate expression is also called a high-level intermediate expression. The first intermediate expression has a high level of abstraction, retains the high-level structure and semantics of the source code, and begins to approach the instruction set of the target machine. In brain-like computing applications, the first-level intermediate expression is a high-level instruction under the SNN dialect, such as snn.new_lif, which is used to initialize, assign values, and calculate neuron groups and synapses. They are abstract instructions that input and return operands, but have not yet been specific to the underlying hardware level.

[0075] Optionally, the brain-like computing application includes operators and operator attributes, the operator includes at least one of a neuron update operator, a synaptic propagation operator, a neuron definition operator, and a synapse definition operator, and the operator attribute includes a format attribute and / or a delay attribute, the format attribute is used to indicate whether the operator is sparse, and the delay attribute is used to indicate whether the operator has a delay. The following is a glossary of these operators and operator attributes:

[0076] 1. Neuron update operator: The neuron update operator is responsible for simulating the activities of biological neurons, including the processing and transmission of their electrical signals. Such operators are usually included in SNNs to describe how neurons modify their states based on input signals and generate output pulses.

[0077] 2. Synaptic propagation operator: Synaptic propagation operators simulate the connection between neurons, that is, the function of synapses. They define how signals are transmitted between neurons and how this transmission affects the activity of receiving neurons. Synaptic propagation operators are particularly important when implementing learning rules such as STDP. Optionally, the synaptic propagation operator is not converted in the process of converting the first intermediate expression to the second intermediate expression, but is converted into a low-level operator in the process of converting the second intermediate expression to the low-level hardware expression.

[0078] 3. Neuron definition operators: These operators are used to define and initialize the states and parameters of neurons. For example, setting the threshold of neurons, resetting characteristics, etc. These parameters are crucial for simulating the dynamic behavior of neurons.

[0079] 4. Synapse definition operator: The synapse definition operator describes the characteristics of the synapse, such as weight, delay, and synapse type (excitatory or inhibitory). These parameters determine the transmission effect and mode of neural signals.

[0080] 5. Format attribute: The format attribute is used to indicate whether the operator is sparse. In brain-like computing, many connections may not exist or be invalid. Sparse operators can effectively utilize this feature and only process existing connections, thereby reducing computing resource consumption and improving computing efficiency. The format attribute includes a first format value or a second format value. The first format value is used to indicate that the operator is sparse, and the second format value is used to indicate that the operator is dense.

[0081] 6. Delay attribute: The delay attribute is used to indicate whether an operator has a delay. In biological neural systems, delay in signal transmission is inevitable. Simulating this characteristic helps improve the biological rationality and accuracy of the model. The delay attribute includes a first delay value or a second delay value. The first delay value is used to indicate that the operator has no delay, and the second delay value is used to indicate that the operator has a delay.

[0082] In brain-like computing applications, operator merging is an important optimization method aimed at improving computing efficiency and reducing resource consumption. When there are multiple operators in a brain-like computing application that meet the preset merging conditions, the multiple operators can be merged, and they can be merged into a composite operator, thereby reducing the storage and transmission requirements of intermediate data. The preset merging conditions may include that the operator types of multiple operators are the same, or they can be merged based on conditions such as data dependencies between operators, parallelism of operator execution, and operator demand for resources. The embodiments of the present disclosure are not limited to this. It should be noted that operator merging can be performed in multiple links in the brain-like computing compilation process, that is, it can be performed when there is a need to merge operators in steps 201 to 203. Take the example of operator merging in the process of converting the brain-like computing application into the first intermediate expression in step 201, that is, when there are multiple operators in the brain-like computing application that meet the preset merging conditions, these operators can be merged first, and then the conversion is performed.

[0083] In order to describe a brain-like computing application, it is necessary to define the neuron model, the connection between neurons, the storage format of neuron pulses, and the storage format of neuron synapses. The following is an explanation of these data:

[0084] 1. Neuron model: defines the biological or mathematical behavior of neurons and is used to simulate the dynamic characteristics of neurons. Neuron models describe how neurons respond to input signals, and different models have different mathematical expressions and parameters.

[0085] 2. Connections between neurons: describes how neurons are connected through synapses, including the topological structure and functional characteristics of the connections. The connections between neurons define the architecture of the network, such as feedforward networks, convolutional networks, recurrent networks, etc.

[0086] 3. Pulse storage format: determines the way the pulse information is recorded, such as frequency coding, time coding, etc. Different storage formats will affect the data processing method and access efficiency. The storage format of the pulse includes: dense storage format or sparse storage format.

[0087] Dense storage format: Each neuron's spikes are stored separately, even if many values ​​are zero (inactive), they still take up the same space.

[0088] Sparse storage format: only non-zero elements (that is, actual pulses) are stored, saving storage space and improving processing efficiency.

[0089] 4. Synaptic storage format: describes the information about the connection strength between neurons, which usually exists in the form of a weight matrix. Synaptic storage formats include: dense storage format, CSR storage format, and ECSR storage format.

[0090] Dense storage format: Similar to the spike-like dense format, all synaptic weights are stored, regardless of whether their value is zero or not.

[0091] CSR storage format: An optimized sparse matrix storage format that stores only non-zero elements, reducing memory usage and increasing data access speed.

[0092] ECSR storage format: Based on this, further optimization can be performed to store synapses with different delays in the same CSR matrix, and synaptic data with delay differences can be managed more efficiently. The delay attribute corresponding to CSR is the first delay value, and the delay attribute corresponding to ECSR is the second delay value. The first delay value is used to indicate that there is no delay, and the second delay value is used to indicate that there is a delay. Optionally, for the GPGPU backend, a new data format called ECSR is implemented. This data structure is used to show that synapses with different delays are stored in the same CSR matrix, which can greatly reduce the sparsity of synapses with each delay and increase computational efficiency.

[0093] Step 202: convert the first intermediate expression into a second intermediate expression, where the abstraction level of the second intermediate expression is lower than the abstraction level of the first intermediate expression.

[0094] The abstraction level of the first intermediate expression is reduced to the second intermediate expression in order to further refine the representation of brain-like computing applications so that it can be more easily mapped to the underlying hardware.

[0095] The first intermediate expression usually maintains an abstract level close to the high-level source code to facilitate program analysis and optimization by the compiler. In brain-like computing, the first intermediate expression may contain high-level descriptions such as neuron models and connection methods. The second intermediate expression is an expression closer to the target machine, and its abstract level is lower than the first intermediate expression. This may involve directly mapping the specific implementation details of neurons and synapses to the instruction set or data structure executable by the target hardware. The second intermediate expression is also called a low-level intermediate expression, which is further optimized and converted on the basis of the first intermediate expression. The second intermediate expression has a lower level of abstraction than the first intermediate expression and is closer to the instruction set and specific hardware operations of the target machine. The second intermediate expression usually includes specific instructions and data structures, such as specific instructions including loop instructions, control instructions, some calculation instructions, etc., such as data structures including arrays, etc. In brain-like computing applications, the second intermediate expression refines the abstract instructions of the first intermediate expression, such as converting snn.new_lif to memref.alloc in the memref dialect, which is a memory allocation instruction closer to the hardware level, preparing for the final conversion to the underlying hardware expression.

[0096] Optionally, according to the operator attribute of the brain-like computing application provided by the first intermediate expression, the first intermediate expression is converted into a second intermediate expression, including: when the operator attribute is a first attribute value, the first intermediate expression is converted into a second intermediate expression in a first manner; when the operator attribute is a second attribute value, the first intermediate expression is converted into a second intermediate expression in a second manner, and the second manner is different from the first manner to generate different second-level intermediate expressions to increase computing efficiency. Among them, the operator attribute is used to indicate the storage format of the neuron's pulse and / or the storage format of the neuron's synapse. That is, according to the operator attribute, the storage format of the synapse and / or the storage format of the pulse used can be determined; the synapse and / or the pulse are stored in the memory, and different algorithms are used to calculate the synaptic propagation and neuron update process according to different storage formats. Schematically, the operator attribute includes a format attribute and a delay attribute. When the format attribute of the synapse indicates that the operator is dense, and the delay attribute indicates that the operator does not have a delay, a code is generated when the synapse is dense, and the weights are stored in a two-dimensional array. When the format attribute of the synapse indicates that the operator is sparse, and the delay attribute indicates that the operator does not have a delay, a CSR array is generated to store the weights, and the original weights are compressed to be stored in the CSR array. This embodiment of the disclosure is not limited to this.

[0097] Step 203: convert the second intermediate expression into an underlying hardware expression, where the underlying hardware expression is used to generate a parameter file running on the target hardware.

[0098] The second intermediate expression is converted into an underlying hardware expression, and the abstraction level of the underlying hardware expression is lower than that of the second intermediate expression, so as to generate a parameter file running on the target hardware. In this step of conversion, the underlying code will be generated and optimized according to the hardware characteristics. The synaptic propagation process will also be reduced to the underlying operator at this time. The reason for this design is that different hardwares are very different and the synaptic propagation algorithms used are also different. The purpose of this step is to map the brain-like computing application to specific hardware resources to achieve efficient operation. The underlying hardware expression can be a data structure related to the target hardware, such as an instruction set or a configuration file, that is, for instruction set architectures such as CPU and GPU, the corresponding instruction set assembly is generated, and for some mixed flow coarse-grained description architectures, the corresponding configuration file is generated. The underlying hardware expression is used to describe the execution mode of the brain-like computing application on the target hardware. The parameter file can be an executable file of the target hardware, and the parameter file can be a text file containing hardware configuration information, which is used to guide the operation of the brain-like computing application on the target hardware.

[0099] Optionally, the intermediate expression includes multiple operators, that is, the first intermediate expression, the second intermediate expression and the underlying hardware expression all include multiple operators. In the intermediate expression conversion process, for each input operator, the corresponding output operator is determined according to the preset conversion model, and the abstract level of the output operator is lower than the abstract level of the input operator. The preset conversion model is used to indicate the mapping relationship between the preset input operator and the output operator. The intermediate expression conversion process can be any one of the three steps above. In the process of converting the brain-like computing application to be compiled into the first intermediate expression, the input operator is the operator in the brain-like computing application, and the output operator is the operator in the first intermediate expression. In the process of converting the first intermediate expression into the second intermediate expression, the input operator is the operator in the first intermediate expression, and the output operator is the operator in the second intermediate expression. In the process of converting the second intermediate expression into the underlying hardware expression, the input operator is the operator in the second intermediate expression, and the output operator is the operator in the underlying hardware expression.

[0100] After converting the second intermediate expression into the underlying hardware expression, the compiler converts the underlying hardware expression into assembly language (assembly language is a description method that can be directly recognized by hardware), and finally converts the assembly language into an executable file, that is, a parameter file that runs on the target hardware. The parameter file can be executed on the corresponding target hardware backend.

[0101] In summary, the disclosed embodiments propose a brain-like computing compilation method with software and hardware decoupling, which converts the brain-like computing application to be compiled into a first intermediate expression, which is used to be recognized by the compilation framework, converts the first intermediate expression into a second intermediate expression, and the abstract level of the second intermediate expression is lower than the abstract level of the first intermediate expression, and converts the second intermediate expression into a bottom-level hardware expression, which is used to generate a parameter file running on the target hardware; that is, the method is based on the design idea of ​​software and hardware decoupling, uses multiple layers of intermediate expressions, and hierarchically reduces the brain-like computing application to the bottom-level hardware primitives, thereby achieving efficient support for different types of applications, and can effectively solve the problem of low running efficiency of brain-like computing applications on different hardware platforms in related technologies, improve the reusability, interoperability and composability of the compiler, reduce the development difficulty and workload of brain-like chip compilers, and improve the running efficiency of brain-like applications (through brain-like compilation optimization).

[0102] The compilation framework provided by the embodiments of the present disclosure is based on the design concept of software-hardware decoupling, and uses multi-layer intermediate expressions to divide the compilation framework of brain-like computing into three layers: description layer, intermediate layer, and hardware layer, so as to better achieve the effect of software-hardware decoupling. Multi-layer intermediate expressions are a sub-project of the low-level virtual machine (LLVM) compilation infrastructure, which provides multiple dialects (English: Dialect), each dialect is a collection of operators and data structures in a specific field, and multi-layer intermediate expressions are easy to expand new dialects and convert to original dialects, so multi-layer intermediate expressions are often used as development tools for compilers in specific fields.

[0103] like Figure 3 As shown, the compilation framework includes a description layer, an intermediate layer, and a hardware layer, and the description layer, the intermediate layer, and the hardware layer correspond to the first intermediate expression, the second intermediate expression, and the bottom hardware expression, respectively. The conversion between the three is converted through the compilation flow (English: pass), that is, the compiler reduces the description layer expression (i.e., the first intermediate expression) to the intermediate layer expression (i.e., the second intermediate expression), and then to the hardware layer expression (i.e., the bottom hardware expression) by executing the compilation method, and finally converts it into an executable file (i.e., parameter file) of the target hardware backend. Among them, "%v" is a variable name, "snn.new_lif" is an operator, which belongs to the SNN dialect and is used to create or define an integral leaky neuron model (Leaky Integrate-and-Fire, LIF) neuron group, and the meaning of the entire expression of "%v=snn.new_lif" is to define the LIF neuron group in the SNN dialect and assign the reference of this neuron group to the variable "%v". In other expressions, "%p" is another variable name; "%s" is another variable name; "memref.alloc" is another operator, which belongs to the memref dialect in MLIR and is used to allocate space for variables in memory; "llvm.alloc" is another operator, which is an instruction in LLVM IR and is used to allocate memory space for local variables on the stack frame of the function. The meanings of other expressions are similar and will not be repeated here. Below, the compilation framework is further introduced.

[0104] 1. The compiler converts the brain-like computing application described in a high-level language written by the user into a language that can be recognized by the compilation framework). In order to make this step as simple as possible, the design of the description layer should be as close as possible to the expression of common brain-like computing simulation frameworks, such as close to the syntax of PyNN, which is a widely used SNN description language.

[0105] In order to describe a brain-like computing application, some target data needs to be defined, including the neuron model, the connection between neurons, the storage format of pulses, and the storage format of synapses. The simulation framework has some built-in neuron models for users to use directly (such as the common LIF, Izhikevich, IAF and other neuron models). Users need to specify a specific neuron and provide the hyperparameters of the neuron model (such as threshold voltage, resting voltage, etc.).

[0106] The connection method between neurons supports static synapses. The framework supports multiple methods of initializing static synapses, such as reading from files, or using one-to-one, many-to-many, and probabilistic connections similar to NEST.

[0107] Users can also specify the storage format of pulses and / or the storage format of synapses. Due to the large differences in brain-like computing applications, their computing characteristics are also very different. The sparsity of pulses and synapses varies greatly between different applications. The framework supports users to specify the storage format of pulses and synapses according to the computing characteristics of the problem, thereby improving the overall computing efficiency. The storage format of pulses and the storage format of synapses can be customized by users. The computing characteristics refer to the sparsity of synapses and pulses. Due to the large differences in the sparsity of synapses and pulses in different brain-like computing applications, dense or sparse storage formats may be used in the calculation process. Here, the compilation framework will determine the data structure of synapses and pulses to be used based on the operator properties provided by the user. Storage refers to storing pulses and synapses in memory, and using different algorithms to calculate synaptic propagation and neuron update processes according to different storage formats.

[0108] In general, brain-like computing applications described in high-level languages ​​are converted into inputs of the compilation framework. Therefore, the description layer has the following two characteristics: (1) flexibility in facilitating the conversion of upper-level applications; and (2) efficiency in facilitating subsequent optimization.

[0109] Optional, user-defined data diagram such as Figure 4 As shown, the data includes operators, data structures, operator attributes and compilation flows. Brain-like computing applications are applications described using operators, in which operator attributes are used in the definition of some operators (neuron update operator, synaptic propagation operator, neuron definition operator, synapse definition operator). Operator attributes are used to specify some additional information of the operator for subsequent optimization. The format attribute is used to indicate whether the operator is sparse, and the delay attribute is used to indicate whether the operator has a delay. Some brain-like computing applications have delayed synapses. Delayed synapses require a period of time after the pre-synaptic neuron is released before the post-synaptic neuron can receive them. Some brain-like computing applications have no delay in the synapses (or the delay is 1 time step), so the delay attribute is used to describe whether the synapses of the brain-like computing application have a delay.

[0110] 2. On the one hand, the middle layer needs to take over the description layer and transform the abstract operators of the description layer into specific algorithm implementations. On the other hand, it needs to take over the hardware layer downwards. Therefore, the primitives of this layer need to be supported by the underlying hardware so that they can run on the corresponding hardware platform.

[0111] During compilation, the compiler converts the first intermediate expression of the description layer into a second intermediate expression (IR) of a slightly lower level. At the same time, the intermediate layer also describes the actual computational process of the pulse neural network application. In the process of converting the abstract operators of the description layer into the intermediate layer, some operator properties of the description layer will guide the generation of specific intermediate codes. For example, the synaptic sparsity of different applications may be different, so dense / sparse matrices are required for storage. This requires the description layer to provide application features. In addition, since the synaptic propagation operator is usually a hot spot for the entire brain-like computing application, the conversion of the synaptic propagation operator is usually performed from the intermediate layer to the hardware layer.

[0112] Some operator attributes of the description layer will guide the generation of specific intermediate codes, including: checking the operator attributes corresponding to the input operator, for example, for the synaptic propagation definition operator, by obtaining the format attribute and delay attribute, when the format attribute indicates that the operator is dense, and the delay attribute indicates that the operator does not have a delay, the code for the dense synapse is generated, and the weights are stored in a two-dimensional array. When the format attribute indicates that the operator is sparse, and the delay attribute indicates that the operator does not have a delay, a CSR array is generated to store the weights, and the original weights are compressed to be stored in the CSR array. In addition, during the neuron update process, the storage form of the generated pulses will also be determined according to the format attributes of the pulses. For example, when the format attribute of the pulse indicates that the operator is dense, it is directly stored in the dense array in the form of 0 / 1. When the format attribute of the pulse indicates that the operator is sparse, only the neuron identifier (Identifier, id) with a value of 1 is stored.

[0113] In general, most operators in the description layer are converted to specific second intermediate expressions, leaving a small number of hot operators waiting for subsequent conversion. During the conversion from the description layer to the intermediate layer, the compiler will optimize according to the properties of the description layer. Hot operators are the operators that take the longest time in the application. In brain-like computing applications, hot operators are usually synaptic propagation operators. During the conversion from the first intermediate expression to the second intermediate expression, the synaptic propagation operator will not decrease, but will wait until the second intermediate expression is converted to the underlying hardware expression before being converted.

[0114] 3. The hardware layer takes over the middle layer and converts the second intermediate expression of the middle layer into the bottom hardware expression of the hardware layer. In this step of conversion, the bottom code will be generated and optimized according to the hardware characteristics. The synaptic propagation process will also be reduced to the bottom operator at this time. The reason for this design is that different hardware varies greatly and the synaptic propagation algorithms used are also different. After all operators are converted into bottom-level hardware expressions, the compiler converts them again, converts them into assembly language, and finally converts them into executable files to be executed on the corresponding hardware backend.

[0115] The intermediate expressions of different layers are converted through compilation flow. Optionally, the disclosed embodiment implements two compilation flows, the first one is the merge flow (English: MergePass) of the automatic neuron group, and the other one is the descending flow (English: LowerPass). The descending flow is the compilation stage that converts the intermediate expressions of three different levels. The merge flow can be an optimization stage in the process of converting the brain-like computing application to the first intermediate expression. After the merge flow, the neuron group will be merged to increase the computing efficiency, while the brain-like computing application still uses the first intermediate expression.

[0116] The merge flow is an optimization flow that traverses all operators of brain-like computing applications, finds all neuron definition operators, and determines whether neuron definition operators can be merged (for example, the preset merging conditions include whether the types of neurons are the same). If they can be merged, all operators that use neuron groups need to be merged along the usage chain of neuron definition operators. It should be noted that operators that need to be merged can also be neuron update operators, synaptic propagation operators, etc., as well as operators and functions on these operator usage chains.

[0117] The descending flow involves the transformation of intermediate expressions at different levels. It is necessary to define what kind of transformation this compilation flow needs to perform, and define the input and output operator sets of this flow. The input and output operators can both be dialects. And define the transformation rules for all possible input operators of this flow. For each input operator, you need to design a descent method to map it to the output operator set. Later, when this compilation flow is executed, the compiler will gradually replace the original input operators according to the transformation rules. After matching the input operator, it will execute the transformation rules and replace it with the output operator set. Therefore, the most critical thing is to implement the replacement rules for each operator and use a lower-level operator combination to implement the functions of advanced and abstract operators.

[0118] The compilation framework provided by the embodiments of the present disclosure is applied on a variety of hardware platforms to achieve a significant improvement in operating efficiency. In an illustrative example, the compilation framework provided by the embodiments of the present disclosure shows excellent performance for target hardware including CPU, general-purpose GPU, ReRAM-based data flow brain-like chip, vector processing brain-like chip GaBAN II and brain-like Tianji chip. Among them, the code generated by the compilation framework on ReRAM-based data flow brain-like chip, GaBAN II and brain-like Tianji chip has an operating efficiency not lower than that of the code generated using the original tool chain. This shows that the compilation framework can effectively adapt to these specific hardware architectures and optimize code execution performance. For more common hardware platforms, such as CPU and general-purpose GPU, the compilation framework also performs well. Compared with the simulation framework NEST for SNN applications, the compilation framework achieves an average of 6.7 times acceleration on the CPU and an average of 5.1 times acceleration on the GPU. In addition, compared with the simulation framework SpikingJelly for DSNN applications, the compilation framework achieves an average of 7.6 times acceleration on the CPU and an average of 4.8 times acceleration on the GPU. These results show that the compilation framework provided by the embodiments of the present disclosure can significantly improve the running efficiency of the code, whether on traditional CPUs and GPUs or on specially designed brain-like chips. This cross-platform performance improvement demonstrates the wide applicability and optimization capabilities of the compilation framework, and provides strong support for brain-like computing applications on different hardware platforms.

[0119] In summary, unlike traditional SNN simulators or compilers, the disclosed embodiments use a compilation framework with multiple layers of intermediate expressions, support the use of operator attributes to describe the characteristics of brain-like computing applications, and support partial descent of brain-like computing applications during compilation, so that different hardware backends can reuse the same intermediate optimization. Reusing the same intermediate optimization mainly refers to the above-mentioned optimization of the merged stream and the descending stream. Different hardware backends can reuse the optimization of the merged stream and can partially reuse the optimization in the descending stream. Depending on the characteristics of the hardware backend, the descending stream has different optimizations for the traditional instruction set architecture, data flow architecture, and hybrid flow architecture. The new hardware backend can select different descending processes according to the characteristics of the hardware, thereby reusing different optimizations. The optimization of the merged stream is to merge the neuron groups, which increases the parallelism and memory access continuity of the neuron groups. The descending stream is optimized for multi-threading, vectorization, ECSR, etc. In addition, the disclosed embodiment provides a synaptic propagation algorithm for GPGPU and implements a new data format, namely ECSR, for the GPGPU backend. This data structure is used in the synaptic propagation process and is used to store synapses with different delays in the same CSR matrix. This can greatly reduce the sparsity of each delayed synapse and increase computing efficiency.

[0120] The following is an apparatus embodiment of the present disclosure. For parts not described in detail in the apparatus embodiment, reference may be made to the technical details disclosed in the above method embodiment.

[0121] Please refer to Figure 5 , which shows a schematic diagram of the structure of a brain-like computing compilation device with software and hardware decoupling provided by an exemplary embodiment of the present disclosure. The device can realize all or part of a computing device through software, hardware, or a combination of the two. The device includes: a first conversion module 51, a second conversion module 52, and a second conversion module 53.

[0122] A first conversion module 51, used to convert the brain-inspired computing application to be compiled into a first intermediate expression, where the first intermediate expression is used to be recognized by a compilation framework;

[0123] A second conversion module 52, configured to convert the first intermediate expression into a second intermediate expression, wherein the abstraction level of the second intermediate expression is lower than the abstraction level of the first intermediate expression;

[0124] The third conversion module 53 is used to convert the second intermediate expression into an underlying hardware expression, and the underlying hardware expression is used to generate a parameter file running on the target hardware.

[0125] In a possible implementation, the second conversion module 52 is further configured to:

[0126] The first intermediate expression is converted into a second intermediate expression according to operator properties of the brain-like computing application provided by the first intermediate expression, where the operator properties are used to indicate a storage format of a neuron's pulses and / or a storage format of a neuron's synapses.

[0127] In another possible implementation, the storage format of the pulses includes: a dense storage format or a sparse storage format; and / or,

[0128] The storage format of the synapse includes: one of a dense storage format, a CSR storage format, and an ECSR storage format. The ECSR format is used to indicate that synapses with different delays are stored in the same CSR matrix.

[0129] In another possible implementation, a brain-like computing application includes operators and operator attributes, where the operators include at least one of a neuron update operator, a synaptic propagation operator, a neuron definition operator, and a synapse definition operator; the operator attributes include format attributes and / or delay attributes, where the format attribute is used to indicate whether the operator is sparse, and the delay attribute is used to indicate whether the operator has a delay.

[0130] In another possible implementation manner, the synaptic propagation operator is converted into a bottom-level operator in the process of converting the second intermediate expression into the bottom-level hardware expression.

[0131] In another possible implementation, the device further includes: a merging module, configured to:

[0132] When there are multiple operators in the brain-like computing application that meet the preset merging conditions, the multiple operators are merged;

[0133] The preset merging condition includes that the operator types of the multiple operators are the same.

[0134] In another possible implementation, the device further includes: a determining module, configured to:

[0135] In the process of intermediate expression conversion, for each input operator, the corresponding output operator is determined according to the preset conversion model, and the abstract level of the output operator is lower than the abstract level of the input operator;

[0136] The preset conversion model is used to indicate the mapping relationship between the preset input operator and the output operator.

[0137] It should be noted that the device provided in the above embodiment only uses the division of the above-mentioned functional modules as an example to implement its functions. In practical applications, the above-mentioned functions can be assigned to different functional modules according to actual needs, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0138] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0139] The disclosed embodiments also provide a brain-like computing compilation framework with software and hardware decoupling, and the compilation framework is used to implement the above method.

[0140] The disclosed embodiments also provide a brain-like computing compilation device with software and hardware decoupling, the device comprising: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0141] The embodiment of the present disclosure also provides a non-volatile computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.

[0142] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of a computing device, the processor in the computing device executes the above method.

[0143] Figure 6 1 is a block diagram of an apparatus 1900 for executing a method for brain-like computing compilation with software and hardware decoupling according to an exemplary embodiment. For example, the apparatus 1900 may be provided as a server or a terminal device. Figure 6 , the apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions, such as an application, that can be executed by the processing component 1922. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0144] The device 1900 may also include a power supply component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input / output interface 1958 (I / O interface). The device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2000. TM , MacOS X TM , Unix TM ,Linux TM , FreeBSD TM or similar.

[0145] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the device 1900 to perform the above method.

[0146] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0147] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0148] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0149] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0150] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0151] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0152] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0153] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0154] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A brain-like computing compilation method with software and hardware decoupling, characterized in that: The method comprises: Converting the brain-like computing application to be compiled into a first intermediate expression, where the first intermediate expression is used to be recognized by a compilation framework; converting the first intermediate expression into a second intermediate expression, wherein the abstraction level of the second intermediate expression is lower than the abstraction level of the first intermediate expression; The second intermediate expression is converted into an underlying hardware expression, where the underlying hardware expression is used to generate a parameter file running on target hardware.

2. The method according to claim 1, characterized in that The converting the first intermediate expression into a second intermediate expression comprises: The first intermediate expression is converted into the second intermediate expression according to the operator attributes of the brain-like computing application provided by the first intermediate expression, wherein the operator attributes are used to indicate the storage format of the neuron's pulses and / or the storage format of the neuron's synapses.

3. The method according to claim 2, characterized in that The storage format of the pulses includes: a dense storage format or a sparse storage format; and / or, The storage format of the synapse includes: one of a dense storage format, a compressed sparse row CSR storage format, and an extended compressed sparse row ECSR storage format, and the ECSR format is used to indicate that synapses with different delays are stored in the same CSR matrix.

4. The method according to claim 1, characterized in that: The brain-like computing application includes operators and operator attributes, the operator includes at least one of a neuron update operator, a synaptic propagation operator, a neuron definition operator, and a synapse definition operator, the operator attributes include format attributes and / or delay attributes, the format attribute is used to indicate whether the operator is sparse, and the delay attribute is used to indicate whether the operator has a delay.

5. The method according to claim 4, characterized in that The synaptic propagation operator is converted into a low-level operator in the process of converting the second intermediate representation into the low-level hardware representation.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: When there are multiple operators in the brain-inspired computing application that meet a preset merging condition, merging the multiple operators; The preset merging condition includes that the operator types of the multiple operators are the same.

7. The method according to any one of claims 1 to 5, characterized in that The method further comprises: In the intermediate expression conversion process, for each input operator, a corresponding output operator is determined according to a preset conversion model, and the abstract level of the output operator is lower than the abstract level of the input operator; The preset conversion model is used to indicate the mapping relationship between the preset input operator and the output operator.

8. A brain-like computing compilation device with software and hardware decoupling, characterized in that: The device comprises: A first conversion module, configured to convert the brain-inspired computing application to be compiled into a first intermediate expression, where the first intermediate expression is used to be recognized by a compilation framework; a second conversion module, configured to convert the first intermediate expression into a second intermediate expression, wherein the abstraction level of the second intermediate expression is lower than the abstraction level of the first intermediate expression; The third conversion module is used to convert the second intermediate expression into an underlying hardware expression, where the underlying hardware expression is used to generate a parameter file running on target hardware.

9. A brain-like computing compilation device with software and hardware decoupling, characterized in that: The device comprises: processor; a memory for storing processor-executable instructions; The processor is configured to implement the method described in any one of claims 1 to 7 when executing the instructions stored in the memory.

10. A brain-like computing compilation framework with software and hardware decoupling, characterized in that: The compilation framework is used to implement the method described in any one of claims 1 to 7.

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