Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a substrate which is provided with a plurality of bit lines which are arranged at intervals; the spacing structures are located on the surface of the substrate, the spacing structures are located between the bit lines, and the spacing structures are located on the side faces of all the bit lines; the spacing structure comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer is located on the side face of the bit line, and the second dielectric layer is located between the first dielectric layer and the third dielectric layer; the relative dielectric constant of the material of the first dielectric layer is smaller than the relative dielectric constant of the material of the third dielectric layer. According to the semiconductor structure and the preparation method thereof provided by the embodiment of the invention, at least the parasitic capacitance between the bit line and the adjacent conductive structure can be improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the continuous development of integrated circuit technology and process technology, the characteristic size of transistor (MOS) devices has been continuously reduced in order to improve the integration of integrated circuits. At process nodes such as high dielectric metal gate (HKMG) and fin-type transistors (Finfet), a series of problems need to be faced while increasing the operating speed of MOS devices and reducing their power consumption.

[0003] In order to reduce the power consumption of MOS devices, those skilled in the art use metal wires as connecting media at multiple process nodes based on the advantage of low resistance of metal itself, which brings a series of problems. For example, short circuits between adjacent metal wires lead to chip failure; parasitic capacitance exists between adjacent metal wires. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the problem of parasitic capacitance between a bit line and an adjacent conductive structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate having a plurality of bit lines spaced apart; a spacing structure, the spacing structure being located on a surface of the substrate, the spacing structure being located between the bit lines, and the spacing structure being located on a side of each of the bit lines; the spacing structure comprising a first dielectric layer, a second dielectric layer, and a third dielectric layer, the first dielectric layer being located on a side of the bit line, the second dielectric layer being located between the first dielectric layer and the third dielectric layer, and the relative dielectric constant of a material of the first dielectric layer being smaller than the relative dielectric constant of a material of the third dielectric layer.

[0006] In some embodiments, the relative dielectric constant of the material of the first dielectric layer is less than or equal to 4.5.

[0007] In some embodiments, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

[0008] In some embodiments, a material of the first dielectric layer includes silicon oxycarbide.

[0009] In some embodiments, the method further includes: a nitride layer located between the bit line and the spacer structure.

[0010] In some embodiments, the first dielectric layer includes a first film layer and a second film layer, the first film layer is located between the second film layer and the bit line, and the oxygen content of the second film layer is greater than that of the first film layer.

[0011] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a method for preparing a semiconductor structure, comprising: providing a substrate having a plurality of bit lines arranged at intervals; forming a spacing structure, wherein the spacing structure is located on a surface of the substrate, the spacing structure is located between the bit lines, and the spacing structure is located on a side of each of the bit lines; the spacing structure comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer, the first dielectric layer is located on a side of the bit line, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and the relative dielectric constant of a material of the first dielectric layer is smaller than the relative dielectric constant of a material of the third dielectric layer.

[0012] In some embodiments, before forming the spacing structure, the method further includes: performing nitrogen doping treatment on the bit line to form a nitride layer, wherein the nitride layer covers the top surface and the side surface of the bit line; and the spacing structure is located on the side surface of the nitride layer.

[0013] In some embodiments, the nitrogen doping treatment includes a remote plasma nitriding process; the process parameters of the remote plasma nitriding process include: a radio frequency of 50W to 500W, a radio frequency angle of 70 to 110°, and a pressure of 20 to 40 Pa.

[0014] In some embodiments, the process steps for forming the first dielectric layer and the second dielectric layer include: forming a dielectric film, the dielectric film being located on the side of the bit line; forming a second dielectric layer, the second dielectric layer being located on the side of the dielectric film; wherein the reaction source gas for forming the second dielectric layer includes an oxidizing gas, the oxidizing gas oxidizes a portion of the dielectric film to form a second film layer, and the remaining dielectric film serves as the first film layer, the first film layer and the second film layer together constitute the first dielectric layer; the oxygen content of the second film layer is greater than the oxygen content of the first film layer; the process parameters for forming the second dielectric layer include: a reaction temperature of 270°C to 330°C.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] The semiconductor structure provided by the embodiment of the present disclosure includes a spacing structure, the spacing structure is located between adjacent bit lines, the spacing structure includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer is located on the side of the bit line, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and the relative dielectric constant of the material of the first dielectric layer is less than the relative dielectric constant of the material of the third dielectric layer. In this way, the parasitic capacitance between the bit line and the adjacent conductive structure can be reduced, and the conductive structure can include another bit line or storage node contact structure to reduce the risk of leakage current between the bit line and the bit line or between the bit line and the storage node contact structure, thereby improving the operation speed of the bit line and the storage node contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of a first cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0019] Figure 2 A schematic diagram of a second cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0020] Figures 3 to 11 A schematic diagram of the cross-sectional structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The semiconductor structure provided by the embodiment of the present disclosure includes a spacing structure, the spacing structure is located between adjacent bit lines, the spacing structure includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer is located on the side of the bit line, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and the relative dielectric constant of the material of the first dielectric layer is less than the relative dielectric constant of the material of the third dielectric layer. In this way, the parasitic capacitance between the bit line and the adjacent conductive structure can be reduced, and the conductive structure can include another bit line or storage node contact structure to reduce the risk of leakage current between the bit line and the bit line or between the bit line and the storage node contact structure, thereby improving the operation speed of the bit line and the storage node contact structure.

[0022] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0023] Figure 1 A schematic diagram of a first cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of a second cross-sectional structure of a semiconductor structure provided in an embodiment of the present disclosure.

[0024] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a semiconductor structure for reducing parasitic capacitance between a bit line and an adjacent conductive structure.

[0025] refer to Figure 1-2 The semiconductor structure includes: a substrate, on which a plurality of bit lines are arranged at intervals. The semiconductor structure includes: a spacing structure, the spacing structure is located on the surface of the substrate, the spacing structure is located between the bit lines, and the spacing structure is located on the side of each bit line; the spacing structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, the first dielectric layer is located on the side of the bit line, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and the relative dielectric constant of the material of the first dielectric layer is less than the relative dielectric constant of the material of the third dielectric layer.

[0026] In some embodiments, the material of the substrate 100 may be a semiconductor material, and the semiconductor material includes silicon, silicon germanium, or germanium. The substrate 100 contains a P-type doping element or an N-type doping element. The N-type doping element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type doping element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0027] In some embodiments, the substrate 100 has a plurality of active regions and an isolation structure 102 that separates each active region 101. The isolation structure 102 is used to separate each two active regions 101, thereby subsequently forming transistor structures.

[0028] In some embodiments, the material of the active region 101 may include a semiconductor material including silicon, silicon germanium, or germanium.

[0029] In some embodiments, the active region 101 and the substrate 100 may be prepared from the same original substrate, that is, the material of the active region 101 is the same as that of the substrate 100 .

[0030] In some embodiments, the active region 101 includes a channel region and doped regions located on both sides of the channel region. The doped regions serve as a source or a drain of the transistor structure. One of the doped regions is electrically connected to the bit line 110, and the other doped region is electrically connected to the capacitor structure.

[0031] In some embodiments, the isolation structure 102 may be a shallow trench isolation (STI) structure or an isolation structure formed of an isolation material. The isolation structure 102 may be a single-layer film layer or a multi-layer film layer.

[0032] In some embodiments, the material of the isolation structure 102 includes silicon oxide, silicon nitride, silicon carbonitride, or other materials with a high dielectric constant.

[0033] In some embodiments, the bit line 110 includes a stacked crystalline silicon layer 111 , a conductive layer 112 , and a dielectric layer 113 .

[0034] In some embodiments, the material of the crystalline silicon layer 111 may be any one or more of amorphous silicon, microcrystalline silicon or polycrystalline silicon. The material of the conductive layer 112 may be a metal such as tungsten, copper and silver. The metal itself has a low resistance, which is conducive to improving the conductivity of the bit line 110. The material of the dielectric layer 113 may be silicon oxide or silicon nitride.

[0035] In some embodiments, the bit line 110 further includes a first barrier layer, which is located between the active region 101 and the crystalline silicon layer 111; and a second barrier layer, which is located between the crystalline silicon layer 111 and the conductive layer 112. The first barrier layer is used to prevent element diffusion between the crystalline silicon layer 111 and the substrate 100, and the second barrier layer is used for ion diffusion between the conductive layer 112 and the crystalline silicon layer 111, while reducing the contact resistance of the bit line contact hole.

[0036] In some embodiments, the material of the first barrier layer may be any one or more of silicon nitride, silicon oxide or silicon carbide. In some embodiments, the material of the second barrier layer may be titanium nitride TiN, silicon nitride SiN, titanium nitride Ti2N2 and titanium nitride Ti3N4.

[0037] In some embodiments, the semiconductor structure further includes: a nitride layer 106, and the nitride layer 106 is located between the bit line 110 and the spacing structure 120. The bit line 110 includes multiple stacked film layers, and the performance and threshold values ​​of different film layers are different, so that the performance of the film layer covering the surface of the bit line 110 may be different, and then the performance of the first dielectric layer is poor, and the first dielectric layer cannot provide the functionality of reducing parasitic capacitance and supporting. The semiconductor structure includes a nitride layer 106, and the nitride layer 106 serves as a buffer dielectric layer between the bit line 110 and the spacing structure 120. The nitride layer 106 is used to buffer the threshold difference between different film layers in the bit line 110, thereby improving the performance of the first dielectric layer 121 and the contact performance between the first dielectric layer 121 and the bit line 110.

[0038] In some embodiments, the nitride layer 106 includes sub-layers corresponding to the film layers of the bit line. The nitride layer 106 is prepared by nitriding the film layers in the bit line 110 .

[0039] In some embodiments, the thickness of the nitride layer 106 is 0.3 nm to 0.7 nm. The thickness of the nitride layer 106 may be 0.3 nm to 0.42 nm, 0.42 nm to 0.51 nm, 0.51 nm to 0.63 nm, or 0.63 nm to 0.7 nm. The thickness of the nitride layer 106 may be 0.31 nm, 0.43 nm, 0.52 nm, 0.61 nm, or 0.68 nm.

[0040] The thickness of the nitride layer 106 within the above range or value can improve the impact of the threshold difference between the film layers of the bit line on the first dielectric layer 121, and reduce the impact on the performance of the film layer of the first dielectric layer 121. The thickness of the nitride layer 106 can also be used to reduce the impact of the nitridation process on the bit line 110 itself, thereby ensuring the electrical performance and contact performance of the bit line 110.

[0041] In some embodiments, the spacer structure 120 is used to isolate the bit lines 110 from each other or from the storage node contact structure.

[0042] In some embodiments, the relative dielectric constant of the material of the first dielectric layer 121 is less than or equal to 4.5. Thus, the relative dielectric constant of the material of the first dielectric layer 121 is small, which can reduce the dielectric constant of the spacing structure between the bit lines, thereby reducing the influence of the mutual parasitic capacitance between the bit lines 110 and the bit lines 110, and improving the response speed of the bit lines 110. Similarly, the relative dielectric constant of the material of the first dielectric layer 121 is small, which can reduce the parasitic capacitance between the bit lines 110 and the storage node contact structure.

[0043] It is worth noting that the relative permittivity (or dielectric constant) refers to the ratio of the original external electric field (in a vacuum) to the final electric field in the medium, which will generate induced charges and weaken the electric field when an external electric field is applied to the medium. The relative permittivity is also called the dielectric constant and is related to the frequency.

[0044] In some embodiments, the material of the first dielectric layer 121 includes silicon oxycarbide. Compared with silicon oxide, silicon oxycarbide has higher etching resistance and lower dielectric constant, thereby improving the etching resistance of the spacer structure, reducing the dielectric constant, and making the critical voltage distribution of the bit line more uniform.

[0045] In some embodiments, the material of the first dielectric layer 121 includes silicon boron carbon nitride. Since silicon boron carbon nitride has high strength and hardness, the first dielectric layer 121 formed by silicon boron carbon nitride also has high strength and hardness, and can withstand various stresses in subsequent processes, thereby avoiding lateral deformation of the bit line 110, making the structure of the bit line 110 relatively complete, and effectively avoiding the increase of parasitic capacitance between the bit line 110 and the storage node contact structure due to the increase of K value and the risk of short circuit between the bit line 110 and the storage node contact structure.

[0046] In some embodiments, the etching resistance of the first dielectric layer 121 is also related to the carbon content in the silicon oxycarbide layer. When the carbon content is above 50%, the etching resistance can be increased to at least above 90%.

[0047] In some embodiments, the carbon content of the first dielectric layer 121 is constant from the inside to the outside. In some embodiments, the carbon content in the first dielectric layer 121 changes in a gradient, and the carbon content gradually increases from the inner layer to the surface layer, thereby reducing the carbon doping amount while also meeting the requirement of improving corrosion resistance with a high carbon content in the surface layer.

[0048] In some embodiments, the thickness of the first dielectric layer 121 ranges from 2.0 nm to 4.0 nm. The thickness of the first dielectric layer 121 can be 2 nm to 2.5 nm, 2.5 nm to 3.1 nm, 3.1 nm to 3.63 nm, or 3.63 nm to 4 nm. The thickness of the first dielectric layer 121 can be 2.1 nm, 2.8 nm, 3.2 nm, 3.4 nm, or 4 nm.

[0049] The thickness of the first dielectric layer 121 is within any range or any value mentioned above, which can reduce the dielectric constant of the spacing structure 120, thereby effectively reducing the parasitic capacitance between the bit line 110 and the storage node contact structure. The thickness of the first dielectric layer 121 also allows for a portion of the thickness to be oxidized, thereby ensuring the dielectric constant of the spacing structure 120 to the greatest extent within a limited space.

[0050] In some embodiments, reference Figure 2 The first dielectric layer 121 includes a first film layer 108 and a second film layer 109 . The first film layer 108 is located between the second film layer 109 and the bit line 110 . The oxygen content of the second film layer 109 is greater than that of the first film layer 108 .

[0051] In some embodiments, the material of the second dielectric layer 122 includes silicon oxide. The thickness of the second dielectric layer 122 is 1.0 nm to 3.0 nm.

[0052] In some embodiments, the thickness of the first dielectric layer 121 is greater than the thickness of the second dielectric layer 122. The thickness of the first dielectric layer 121 is greater than the thickness of the second dielectric layer 122 to prevent the oxidation reaction from affecting the first dielectric layer 121, that is, the thickness of the first dielectric layer 121 is increased in a limited area, thereby ensuring that even if the oxidation reaction occurs, the remaining thickness of the first dielectric layer 121 is still large, thereby increasing the first dielectric layer 121 with sufficient thickness to reduce the parasitic capacitance between the bit line 110 and the storage node contact structure.

[0053] In some embodiments, the material of the third dielectric layer 123 is silicon nitride, and the thickness of the third dielectric layer 123 is 2.0-6.0 nm.

[0054] In some embodiments, the semiconductor structure also includes a storage node contact structure, which can be a capacitor structure. The storage node contact structure includes a capacitor contact layer 124 and a capacitor conductive layer 125. The capacitor contact layer 124 can be a polysilicon layer. The polysilicon layer can be doped with N-type doping elements or P-type doping elements. The doping elements can act as carriers, which can improve the migration and diffusion of carriers between the active area 101 and the storage node contact structure, which is beneficial to improving the conductivity of the active area 101 and the storage node contact structure, and at the same time can reduce the contact resistance of the storage node contact structure.

[0055] In some embodiments, the material of the capacitor conductive layer 125 is a metal such as tungsten, copper, and silver. The metal itself has a low resistance, which is beneficial to improving the conductivity of the storage node contact structure.

[0056] In some embodiments, the semiconductor structure further includes a metal silicide layer 104 , and the metal silicide layer 104 is used to reduce the contact resistance between the active region 101 and the bit line 110 .

[0057] In some embodiments, the semiconductor structure further includes a filling layer 107, and the filling layer 107 is located between the bit line 110 and the isolation structure 102. The material of the filling layer 107 includes silicon nitride.

[0058] The semiconductor structure provided in the embodiment of the present disclosure includes a spacing structure 120, the spacing structure 120 is located between adjacent bit lines 110, the spacing structure includes a first dielectric layer 121, a second dielectric layer 122 and a third dielectric layer 123, the first dielectric layer 121 is located on the side of the bit line, the second dielectric layer 122 is located between the first dielectric layer 121 and the third dielectric layer 123, and the relative dielectric constant of the material of the first dielectric layer 121 is less than the relative dielectric constant of the material of the third dielectric layer 123. In this way, the parasitic capacitance between the bit line 110 and the adjacent conductive structure can be reduced, and the conductive structure can include another bit line 110 or a storage node contact structure, reducing the risk of leakage current between the bit line 110 and the bit line 110 or the bit line 110 and the storage node contact structure, thereby improving the operation speed of the bit line 110 and the storage node contact structure.

[0059] Accordingly, according to some embodiments of the present disclosure, the embodiments of the present disclosure also provide a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided by the above embodiments. The technical features that are the same or corresponding to the above embodiments will not be elaborated here.

[0060] Figures 3 to 11 A schematic diagram of the cross-sectional structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure.

[0061] refer to Figure 3 The preparation method includes: providing a substrate 100, and the substrate 100 has a plurality of bit lines 110 arranged at intervals.

[0062] In some embodiments, the substrate 100 may be made of a semiconductor material and may contain a P-type doping element or an N-type doping element.

[0063] In some embodiments, the substrate 100 has a plurality of active regions 101 and an isolation structure 102 that separates each active region 101. The isolation structure 102 is used to separate each two active regions 101, thereby subsequently forming transistor structures.

[0064] In some embodiments, the material of the active region 101 may include a semiconductor material.

[0065] In some embodiments, the active region 101 and the substrate 100 may be prepared from the same original substrate, that is, the material of the active region 101 is the same as that of the substrate 100 .

[0066] In some embodiments, the active region 101 includes a channel region and doped regions located on both sides of the channel region. The doped regions serve as a source or a drain of the transistor structure.

[0067] In some embodiments, the isolation structure 102 may be a shallow trench isolation (STI) structure or an isolation structure formed of an isolation material. The isolation structure 102 may be a single-layer film layer or a multi-layer film layer.

[0068] In some embodiments, the material of the isolation structure 102 includes silicon oxide, silicon nitride, silicon carbonitride, or other materials with a high dielectric constant.

[0069] In some embodiments, the bit line 110 includes a stacked crystalline silicon layer 111 , a conductive layer 112 , and a dielectric layer 113 .

[0070] In some embodiments, the material of the crystalline silicon layer 111 may be any one or more of amorphous silicon, microcrystalline silicon or polycrystalline silicon. The material of the conductive layer 112 may be a metal such as tungsten, copper and silver. The metal itself has a low resistance, which is conducive to improving the conductivity of the bit line 110. The material of the dielectric layer 113 may be silicon oxide or silicon nitride.

[0071] In some embodiments, the bit line 110 further includes a first barrier layer, which is located between the active region 101 and the crystalline silicon layer 111; and a second barrier layer, which is located between the crystalline silicon layer 111 and the conductive layer 112. The first barrier layer is used to prevent element diffusion between the crystalline silicon layer 111 and the substrate 100, and the second barrier layer is used for ion diffusion between the conductive layer 112 and the crystalline silicon layer 111, while reducing the contact resistance of the bit line contact hole.

[0072] In some embodiments, the material of the first barrier layer may be any one or more of silicon nitride, silicon oxide or silicon carbide. In some embodiments, the material of the second barrier layer may be titanium nitride TiN, silicon nitride SiN, titanium nitride Ti2N2 and titanium nitride Ti3N4.

[0073] In some embodiments, the substrate 100 has a first groove 103 therein, and the bit line 110 is located in the first groove 103 and protrudes out of the first groove 103 .

[0074] In some embodiments, the semiconductor structure further includes a metal silicide layer 104 , and the metal silicide layer 104 is used to reduce the contact resistance between the active region 101 and the bit line 110 .

[0075] In some embodiments, the metal silicide layer 104 includes thin films such as TiSi 2 , CoSi 2 , and NiPtSi.

[0076] refer to Figure 4 and Figure 5 The preparation method includes: performing nitrogen doping treatment on the bit line 110 to form a nitride layer 106 , and the nitride layer 106 covers the top surface and the side surface of the bit line 110 .

[0077] In some embodiments, the nitriding treatment includes a remote plasma nitriding (RPN) process or a decoupled plasma nitriding (DPN) process using radio frequency to form the nitride layer 106 .

[0078] By performing nitriding treatment on the bit line 110, the electrical properties of the bit line 110 can be adjusted. For example, the side of the bit line 110 can obtain a higher dielectric constant, so that the threshold voltage of the transistor device can be smaller at the same thickness of the device oxide finally formed.

[0079] On the other hand, the nitride layer 106 serves as a buffer dielectric layer between the bit line 110 and the spacing structure to buffer the threshold difference between different film layers in the bit line 110, thereby improving the performance of the first dielectric layer formed subsequently and the contact performance between the first dielectric layer and the bit line 110.

[0080] It should be noted that Figure 5 As shown, the entire bit line is nitrided, that is, a nitride layer is formed on the exposed surface of the entire bit line; the nitride layer can also be formed only on the side of the bit line, which is not limited in the embodiments of the present disclosure.

[0081] When the bit line 110 is nitrided, a protective layer may be formed on the surface of the bit line, and the nitriding energy and the nitriding concentration may be adjusted to allow nitrogen ions to penetrate into the bit line 110. During the nitriding process, the protective layer may block some nitrogen ions to control the penetration depth of the nitrogen ions, thereby facilitating the control of the thickness of the nitride layer 106.

[0082] In some embodiments, a remote plasma nitriding process is used to form the nitride layer 106, and the process parameters of the plasma nitriding process include: a radio frequency of 50W to 500W, a radio frequency angle a of 70 to 110°, and a pressure of 20 to 40 Pa. The range of the radio frequency angle a is used to reduce damage to the bit line 110 caused by plasma, thereby preventing the bit line 110 from bending.

[0083] In some embodiments, the process parameters of the plasma nitriding process further include: a power supply ratio of 5% to 10%, which is used to reduce the amount of plasma attached to the bit line 110, thereby reducing damage to the bit line 110 caused by the plasma nitriding process.

[0084] It is worth noting that the power ratio refers to the time the power switch is turned on per unit time. For example, when the power ratio is 5%, the power is turned on for 5 seconds in a 100s period.

[0085] In some embodiments, the thickness of the nitride layer 106 is 0.3 nm to 0.7 nm. The thickness of the nitride layer 106 may be 0.3 nm to 0.42 nm, 0.42 nm to 0.51 nm, 0.51 nm to 0.63 nm, or 0.63 nm to 0.7 nm. The thickness of the nitride layer 106 may be 0.31 nm, 0.43 nm, 0.52 nm, 0.61 nm, or 0.68 nm.

[0086] In some embodiments, the nitride layer 106 includes sub-layers corresponding to the film layers of the bit line 110. The nitride layer 106 is prepared by performing a nitridation process on the film layers of the bit line 110.

[0087] refer to Figure 6 to Figure 11 The preparation method includes: forming a spacing structure 120, the spacing structure 120 is located on the surface of the substrate 100, the spacing structure 120 is located between the bit lines 110, and the spacing structure 120 is located on the side of each bit line 110; the spacing structure 120 includes: a first dielectric layer 121, a second dielectric layer 122 and a third dielectric layer 123, the first dielectric layer 121 is located on the side of the bit line 110, the second dielectric layer 122 is located between the first dielectric layer 121 and the third dielectric layer 123, and the relative dielectric constant of the material of the first dielectric layer 121 is less than the relative dielectric constant of the material of the third dielectric layer 123. The spacing structure 120 is located on the side of the nitride layer 106.

[0088] In some embodiments, the spacer structure 120 is used to isolate the bit lines 110 from each other or from the storage node contact structure.

[0089] refer to Figure 6 , forming a first dielectric layer 121 , wherein the first dielectric layer 121 is located on the side of the bit line 110 and in the first groove 103 .

[0090] In some embodiments, the relative dielectric constant of the material of the first dielectric layer 121 is less than or equal to 4.5.

[0091] In some embodiments, the material of the first dielectric layer 121 includes silicon oxycarbide or silicon boron carbon nitride.

[0092] In some embodiments, the etching resistance of the first dielectric layer 121 is also related to the carbon content in the silicon oxycarbide layer. When the carbon content is above 50%, the etching resistance can be increased to at least above 90%.

[0093] In some embodiments, the carbon content of the first dielectric layer 121 is constant from the inside to the outside. In some embodiments, the carbon content in the first dielectric layer 121 changes in a gradient, and the carbon content gradually increases from the inner layer to the surface layer, thereby reducing the carbon doping amount while also meeting the requirement of improving corrosion resistance with a high carbon content in the surface layer.

[0094] In some embodiments, the thickness of the first dielectric layer 121 ranges from 2.0 nm to 4.0 nm. The thickness of the first dielectric layer 121 can be 2 nm to 2.5 nm, 2.5 nm to 3.1 nm, 3.1 nm to 3.63 nm, or 3.63 nm to 4 nm. The thickness of the first dielectric layer 121 can be 2.1 nm, 2.8 nm, 3.2 nm, 3.4 nm, or 4 nm.

[0095] refer to Figure 7 , forming a filling layer 107, the filling layer 107 completely fills the first groove. The material of the filling layer 107 includes silicon nitride.

[0096] refer to Figure 8 , forming a second dielectric layer 122 , wherein the second dielectric layer 122 covers the surface of the first dielectric layer 121 .

[0097] In some embodiments, the process parameters for forming the second dielectric layer 122 include: a reaction temperature of 270° C. to 330° C. The reaction temperature of the second dielectric layer 122 is relatively low, which reduces the impact on the first dielectric layer 121 during the formation of the second dielectric layer 122 and reduces the degree of oxidation of the first dielectric layer 121 .

[0098] In some embodiments, the material of the second dielectric layer 122 includes silicon oxide. The thickness of the second dielectric layer 122 is 1.0 nm to 3.0 nm.

[0099] In some embodiments, the thickness of the first dielectric layer 121 is greater than the thickness of the second dielectric layer 122. The thickness of the first dielectric layer 121 is greater than the thickness of the second dielectric layer 122 to prevent the oxidation reaction from affecting the first dielectric layer 121, that is, the thickness of the first dielectric layer 121 is increased in a limited area, thereby ensuring that even if the oxidation reaction occurs, the remaining thickness of the first dielectric layer 121 is still large, thereby increasing the first dielectric layer 121 with sufficient thickness to reduce the parasitic capacitance between the bit line and the storage node contact structure.

[0100] The present disclosure also provides a method for preparing a semiconductor structure for forming a first dielectric layer 121 and a second dielectric layer 122, which specifically includes:

[0101] refer to Fig.10, forming a dielectric film, the dielectric film is located on the side of the bit line; forming a second dielectric layer 122, the second dielectric layer 122 is located on the side of the dielectric film; wherein, the reaction source gas for forming the second dielectric layer 122 includes an oxidizing gas, the oxidizing gas oxidizes a portion of the dielectric film and forms a second film layer 109, and the remaining dielectric film serves as the first film layer 108, and the first film layer 108 and the second film layer 109 together constitute a first dielectric layer 121; the oxygen content of the second film layer 109 is greater than the oxygen content of the first film layer 108.

[0102] In some embodiments, the thickness of the dielectric film is greater than the thickness of the second dielectric layer 122. The thickness of the dielectric film is greater than the thickness of the second dielectric layer 122 to prevent the oxidation reaction from affecting the first dielectric layer 121, that is, the thickness of the dielectric film is increased in a limited area, thereby ensuring that even if the oxidation reaction occurs, the thickness of the remaining first film layer is still large, thereby increasing the first dielectric layer 121 with sufficient thickness to reduce the parasitic capacitance between the bit line 110 and the storage node contact structure.

[0103] refer to Fig.11 or Fig. 9 , forming a third dielectric layer 123 , wherein the third dielectric layer 123 is located on a side of the second dielectric layer 122 .

[0104] In some embodiments, the material of the third dielectric layer 123 is silicon nitride, and the thickness of the third dielectric layer 123 is 2.0-6.0 nm.

[0105] refer to Figure 1 to Figure 2 , forming a first through hole, the bottom of which exposes the surface of the active area 101 in the substrate 100, so that the subsequently formed storage node contact structure is connected to the active area 101; forming a polysilicon film, which fills the first through hole; etching the polysilicon film for the first time, and etching a partial thickness of the spacer structure at the same time.

[0106] In some embodiments, the polysilicon film is first etched using dry etching or wet etching.

[0107] Continue to refer Figure 1 to Figure 2 , the polysilicon film is etched for the second time to form a polysilicon layer, which is the capacitor contact structure 124 ; and a conductive film is formed, which is located on the top surface of the capacitor contact structure 124 and the bit line 110 .

[0108] The conductive film is etched in two directions, namely, a first direction and a third direction, to form a capacitor conductive layer 125 with a staggered arrangement or a hexagonal arrangement. The capacitor contact layer 124 and the capacitor conductive layer 125 form a storage node contact structure.

[0109] In some embodiments, the capacitor contact layer 124 can be a polysilicon layer, and N-type doping elements or P-type doping elements can be doped in the polysilicon layer. The doping elements can act as carriers, which can improve the migration and diffusion of carriers between the active area 101 and the storage node contact structure, which is beneficial to improving the conductivity of the active area 101 and the storage node contact structure, and at the same time can reduce the contact resistance of the storage node contact structure.

[0110] In some embodiments, the material of the capacitor conductive layer 125 is a metal such as tungsten, copper, and silver. The metal itself has a low resistance, which is beneficial to improving the conductivity of the storage node contact structure.

[0111] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a plurality of bit lines arranged at intervals; A spacing structure, wherein the spacing structure is located on the surface of the substrate, the spacing structure is located between the bit lines, and the spacing structure is located on the side of each of the bit lines; the spacing structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, the first dielectric layer is located on the side of the bit line, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and the relative dielectric constant of the material of the first dielectric layer is less than the relative dielectric constant of the material of the third dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that: The relative dielectric constant of the material of the first dielectric layer is less than or equal to 4.

5.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

4. The semiconductor structure according to claim 1 or 2, characterized in that: The material of the first dielectric layer includes silicon oxycarbide.

5. The semiconductor structure according to claim 1, characterized in that Also includes: A nitride layer is located between the bit line and the spacer structure.

6. The semiconductor structure according to claim 1, characterized in that The first dielectric layer includes a first film layer and a second film layer, the first film layer is located between the second film layer and the bit line, and the oxygen content of the second film layer is greater than that of the first film layer.

7. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate having a plurality of bit lines arranged at intervals; A spacing structure is formed, wherein the spacing structure is located on the surface of the substrate, the spacing structure is located between the bit lines, and the spacing structure is located on the side of each of the bit lines; the spacing structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, the first dielectric layer is located on the side of the bit line, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, and the relative dielectric constant of the material of the first dielectric layer is smaller than the relative dielectric constant of the material of the third dielectric layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: Before forming the spacing structure, the method further includes: performing nitrogen doping treatment on the bit line to form a nitride layer, wherein the nitride layer covers the top surface and the side surface of the bit line; and the spacing structure is located on the side surface of the nitride layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The nitrogen doping treatment includes a remote plasma nitriding process; the process parameters of the remote plasma nitriding process include: a radio frequency of 50W to 500W, a radio frequency angle of 70 to 110°, and a pressure of 20 to 40 Pa.

10. The method for preparing a semiconductor structure according to claim 7, characterized in that: The process steps of forming the first dielectric layer and the second dielectric layer include: forming a dielectric film, wherein the dielectric film is located on a side of the bit line; forming a second dielectric layer, the second dielectric layer being located on the side of the dielectric film; wherein the reaction source gas for forming the second dielectric layer comprises an oxidizing gas, the oxidizing gas oxidizes a portion of the dielectric film to form a second film layer, and the remaining dielectric film serves as a first film layer, the first film layer and the second film layer together constitute a first dielectric layer; the oxygen content of the second film layer is greater than the oxygen content of the first film layer; The process parameters for forming the second dielectric layer include: a reaction temperature of 270° C. to 330° C.

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