Current mode band-gap reference circuit with full MOS (Metal Oxide Semiconductor) structure

Abstract

The invention discloses a current mode band-gap reference circuit with a full MOS (Metal Oxide Semiconductor) structure, which is suitable for a deep submicron CMOS (Complementary Metal Oxide Semiconductor) process. The circuit comprises a starting circuit, a bias voltage generating circuit, a reference current generating circuit and a self-bias low-voltage Cascode circuit. The starting circuit is ensured to quickly enter a working state through reasonable MOS tube configuration; the bias voltage generation circuit utilizes a multi-stage complementary MOS structure to realize efficient temperature compensation; the reference current generating circuit generates stable reference current through a negative feedback structure of the operational amplifier; according to the self-biased low-voltage Cascode circuit, the power supply rejection ratio and the output impedance are improved through multi-stage stacking, and the precision and the stability of reference voltage are ensured. The reference voltage and current source circuit has the advantages of low power consumption, high precision, strong robustness and the like, and can be widely applied to reference voltage and current source design of analog integrated circuits.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuit design, and specifically relates to a current-mode bandgap reference circuit with a full MOS structure, which is suitable for generating reference voltage and current with high precision, low power consumption and high temperature stability in a deep submicron CMOS process environment. Background Art

[0002] Bandgap reference circuits are widely used in analog and mixed-signal integrated circuits to provide stable reference voltage or current. However, traditional bandgap reference circuits usually rely on BJT devices, which are challenging to implement in deep submicron CMOS processes, including the following issues:

[0003] Poor process compatibility: It is difficult to effectively implement high-performance BJT devices in deep submicron CMOS processes;

[0004] High power consumption: Traditional bandgap reference circuits are difficult to meet the requirements of low power design;

[0005] Limited temperature performance: The temperature compensation mechanism is complex and costly.

[0006] The bandgap reference circuit with a full MOS structure has lower power consumption and higher process compatibility through a design based entirely on MOS devices, and can achieve excellent performance in a deep submicron process environment. Summary of the invention

[0007] The present invention aims to provide a current-mode bandgap reference circuit with a full MOS structure, so as to overcome the problems existing in the traditional bandgap reference circuit, such as poor process compatibility, high power consumption and limited temperature performance.

[0008] The circuit of the present invention includes a startup circuit, a bias voltage generating circuit, a reference current generating circuit and a self-biased low-voltage Cascode circuit. The functions and designs of each module are as follows:

[0009] The startup circuit ensures that the circuit can quickly enter the working state during the startup phase through the reasonable configuration of PMOS and NMOS tubes, avoiding the problem of the circuit not being able to start normally due to the zero power point.

[0010] The bias voltage generating circuit adopts a multi-stage complementary MOS structure and utilizes the size ratio adjustment of the MOS tube to realize the temperature compensation function and provide a stable bias voltage as the input of the subsequent circuit.

[0011] The reference current generation circuit generates a stable reference current through an operational amplifier and a negative feedback structure to ensure that the output current is not affected by changes in power supply voltage and temperature, and distributes the reference current to each module.

[0012] The self-biased low-voltage cascode circuit uses a multi-stage MOS tube stack design to improve the circuit's power supply rejection ratio (PSRR) and output impedance, ensuring the accuracy and stability of the reference voltage output.

[0013] The technical solution of the present invention has the following advantages:

[0014] Full MOS structure design, fully compatible with deep submicron CMOS process;

[0015] The circuit has low power consumption and is suitable for low-power application scenarios;

[0016] Provide high-precision reference voltage and current output with good temperature stability;

[0017] The power supply rejection ratio is high, and the output performance is less affected by power supply voltage fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 : Overall block diagram of the circuit of the present invention;

[0019] Figure 2 : Circuit diagram of the starting circuit;

[0020] Figure 3 : Circuit schematic diagram of bias voltage generating circuit;

[0021] Figure 4 : Circuit schematic diagram of reference current generating circuit;

[0022] Figure 5 : Circuit schematic of self-biased low voltage cascode circuit. DETAILED DESCRIPTION

[0023] 1. Specific implementation of the startup circuit

[0024] The startup circuit is used to ensure that the entire bandgap reference circuit can start quickly and enter the normal working state when powered on, while avoiding stagnation at the zero power point. The startup circuit is composed of PMOS tube M1 and NMOS tubes M2~M5, and the specific implementation method is as follows:

[0025] The source of the M1 tube is connected to the power supply VDD, and the drain is connected to the source of the M2 tube; the gates of M1 and M2 are commonly connected to the reference voltage VREF to ensure the initial current flow of the circuit.

[0026] The drain of the M2 tube is grounded, and the source is connected to the power supply VDD through the M1 tube to ensure the formation of the startup path.

[0027] The gate of M3 is connected to the drain of M1 and M2 to monitor the startup voltage; its source and drain are connected to ground to avoid abnormal state between M1 and M2 due to startup failure.

[0028] The gate of M4 is connected to the drains of M1 and M2 to form an auxiliary startup path; its source is connected to part of the load of the reference current generating circuit (the drains of M20 and M21), and the drain is grounded.

[0029] The gate of M5 is connected to the output terminal VO of the operational amplifier OP, providing a feedback path for quickly controlling the flow of startup current and output voltage stability.

[0030] Through the above design, the startup circuit can quickly activate the circuit and prevent abnormal working state caused by insufficient power or circuit mismatch.

[0031] 2. Specific implementation of the bias voltage generating circuit

[0032] The bias voltage generation circuit realizes the functions of temperature compensation and bias voltage stabilization through a multi-stage MOS structure. The specific implementation method is as follows:

[0033] M6 and M8 tubes: A primary current mirror is formed by connecting the source to the power supply VDD and the drain to each other; the gate of the M6 ​​tube is connected to the gate and drain of the M8 tube to generate an initial bias current.

[0034] M7 and M9 tubes: The drain and gate of the M7 tube are interconnected, and the source is grounded; the drain of the M9 tube is connected to the drain of the M8 tube, and the gate is connected to the gate of the M7. The stability of the bias voltage is achieved by adjusting the tube ratio.

[0035] M11 and M13 tubes: The source of M11 tube is connected to the power supply VDD, the gate is connected to the gates of M6 and M8, and the drain is connected to M13 tube through the drain of M12 tube; M13 tube further extends the current mirror to the subsequent stage to provide basic current for temperature compensation.

[0036] M14 and M15 tubes: The gate and drain of the M14 tube are connected for temperature compensation; the gate of the M15 tube is connected to the M14, and the source is grounded to enhance the ability to suppress temperature changes.

[0037] M16 and M17 tubes: The source of M16 tube is connected to the power supply VDD, the gate is connected to the gates of M6 and M8 tubes, and the drain is connected to the gate and drain of M17 tube; the source of M17 tube is grounded to further enhance the output stability of the bias voltage.

[0038] The bias voltage generating circuit realizes efficient temperature compensation by adjusting the size ratio and connection mode of the MOS tube, and provides a stable input voltage for the reference current generating circuit.

[0039] 3. Specific implementation of the reference current generating circuit

[0040] The reference current generation circuit uses the operational amplifier OP and negative feedback mechanism to generate a stable reference current and distribute it to subsequent modules. The specific implementation method is as follows:

[0041] Operational amplifier OP: Its positive input terminal is connected to the drain of M26 tube, its negative input terminal is connected to the drain of M19 tube, and its output terminal VO controls the gate voltage of M20 and M22 tubes.

[0042] M18 and M19 tubes: The gate and drain of M18 tube are connected, and the source is connected to the gate and drain of M19 tube, which together form a current source to stabilize the input bias point of the op amp.

[0043] M20 and M22 tubes: The source of M20 tube is connected to the power supply VDD, and the drain is connected to the drain of M4 tube and the drain of M21 tube; the source of M22 tube is connected to the power supply VDD, and the drain distributes the current to M23~M26 tubes through the current mirror structure.

[0044] M23~M26 tubes: The gate and drain of M23 tube are connected, and the source is connected to the drain of M24 tube, which is used to further divert the reference current; the drain of M26 tube is connected to the positive input terminal of the op amp, and the source is grounded, and current stabilization is achieved through negative feedback.

[0045] The reference current generation circuit ensures that the output current has high immunity to power supply voltage and temperature changes, providing a stable reference current for use by other modules.

[0046] 4. Specific implementation of the self-biased low-voltage cascode circuit

[0047] The self-biased low-voltage cascode circuit improves the power supply rejection ratio (PSRR) and output impedance of the circuit through a multi-stage MOS stack structure. The specific implementation method is as follows:

[0048] M27 tube: The source of M27 tube is connected to the power supply VDD, and the gate and drain are connected to the drain of M28 tube and the gate of M29 tube; the ability to suppress power supply noise is improved through self-biasing.

[0049] M28 and M29 tubes: The drain of M28 tube is connected to the gate of M27 tube, and the source is connected to the drain of M29 tube; M29 tube enhances the output impedance of the circuit through a stacking structure.

[0050] M30 and M31 tubes: The drain of M30 tube is connected to the power supply VDD, and the gate and source are connected to the drain of M31 tube; the gate of M31 tube is connected to the gate of M28 tube and the gates of M20 and M22 tubes.

[0051] M32 tube: The drain of M32 tube is connected to the source of M31 tube, and the source is grounded; its gate is connected to the gate of M29 tube and the drain of M28 tube, further improving the power supply rejection ratio and temperature stability of the circuit.

[0052] Through the above design, the self-biased low-voltage cascode circuit achieves high output impedance at low power supply voltage, ensuring the accuracy and stability of the reference voltage output.

[0053] This specific implementation method describes in detail the design and implementation of the startup circuit, bias voltage generation circuit, reference current generation circuit and self-biased low-voltage cascode circuit. Each module cooperates to achieve low power consumption, high precision and high stability reference voltage output through reasonable structural design and functional optimization. The present invention is particularly suitable for analog and mixed signal circuit applications under deep submicron CMOS technology.

Claims

1. A current-mode bandgap reference circuit with a full MOS structure, characterized in that: It includes a startup circuit, a bias voltage generating circuit, a reference current generating circuit, and a self-biased low voltage Cascode circuit; The startup circuit includes a PMOS tube M1 and NMOS tubes M2-M5, wherein the source of tube M1 is connected to the power supply VDD, the drain is connected to the source of tube M2, the source of tube M2 is grounded, and the gates of tubes M1 and M2 are connected to the reference voltage VREF; the gate of tube M3 is connected to the drains of tubes M1 and M2, and the source and drain of tube M3 are connected to the ground; the gate of tube M4 is connected to the drains of tubes M1 and M2, the source is connected to the drains of tubes M20 and M21, and the drain is grounded; the drain of tube M5 is connected to the drains of tubes M1 and M2, the source is grounded, and the gate is connected to the output terminal VO of the operational amplifier OP; The bias voltage generating circuit includes PMOS tubes M6, M8, M11, M13, M16 and NMOS tubes M7, M9, M19, M12, M14, M15, M17; The source of the M6 ​​tube is connected to the power supply VDD, the drain is connected to the drain of the M7 tube and the gate of the M9 tube, the gate of the M6 ​​tube is connected to the gate and drain of the M8 tube; the drain and gate of the M7 tube are connected to the gate of the M9 tube, and the source of the M7 is grounded; the source of the M8 tube is connected to the power supply VDD, the gate and drain are connected to the drain of the M9 tube; the gate of the M9 tube is connected to the gate and drain of the M7 tube, and the source is connected to the drain of the M10 tube; the gate of the M10 tube is connected to the drain of the M11 tube, the gate and drain of the M12 tube, and the source of the M10 tube is grounded; the source of the M11 tube is connected to the power supply VDD, the gate is connected to the gates of the M6 ​​and M8 tubes, and the drain is connected to the drain of the M12 tube; the gate and drain of the M12 tube are connected , the source of M12 is connected to the source of M14 and the drain of M15; the gate of M13 is connected to the gates of M6, M8 and M11, the source is connected to the power supply VDD, the drain is connected to the drain and source of M14 and the gate of M15; the gate and drain of M14 are connected and connected to the drain of M13, the source of M14 is connected to the source of M12 and the drain of M15; the gate of M15 is connected to the gate and drain of M14, and the source is grounded; the gate of M16 is connected to the gates of M6, M8, M11 and M13, the source is connected to the power supply VDD, the drain is connected to the gate and drain of M17; the gate and drain of M17 are connected and connected to the drain of M16, and the source is grounded; The reference current generating circuit includes PMOS tubes M20 and M22, NMOS tubes M18, M19, M21, M23-M26, and operational amplifier OP; The source of M20 is connected to the power supply VDD, the gate is connected to the gate of M22 and connected to the output terminal of the operational amplifier OP, the drain is connected to the drain of M4, the drain of M21 and the gate and drain of M18; the gate and drain of M18 are connected and connected to the drains of M20 and M21, the source is connected to the gate and drain of M19 and connected to the negative input terminal of the operational amplifier OP; the gate and drain of M19 are connected and connected to the source of M18 and connected to the negative input terminal of the operational amplifier OP; the drain of M21 is connected to the drain of M20, the gate is connected to the gate of M24 and the drains of M16 and M17, and the source is grounded; the gate of M22 is connected to the gate of M2 The gate of M20 is connected to the gate of M21, the source is connected to the power supply VDD, and the drain is connected to the gate and drain of M23 and M25; the gate and drain of M23 are connected, and the source is connected to the drain of M24; the gate of M24 is connected to the gate of M21 and the drain of M16 and M17, the drain is connected to the source of M23, and the drain is grounded; the gate and drain of M25 are connected and connected to the drain of M22 and the gate and drain of M23, the source is connected to the gate and drain of M26 and connected to the positive input of the operational amplifier OP; the gate and drain of M26 are connected and connected to the source of M25 and the positive input of the operational amplifier OP, and the source is grounded; The self-biased cascode circuit includes a PMOS tube M27 and NMOS tubes M28 to M30; The source of tube M27 is connected to the gates of tubes M20 and M22, the gate and drain are connected and connected to the drain of tube M28 and the gates of tubes M29 and M32; the gate of tube M28 is connected to the gates of tubes M20, M22 and M31, the drain is connected to the gate and drain of tube M27 and the gates of tubes M29 and M32, the source is connected to the drain of tube M29; the gate of tube M29 is connected to the gate of tube M32 and the drain of tube M28, the drain is connected to the source of tube M28, and the source is grounded; the drain of tube M30 is connected to the power supply VDD, the gate and source are connected and connected to the drain of tube M31; the gate of tube M31 is connected to the gate of tube M28 and the gates of tubes M20 and M22, the drain is connected to the source and gate of tube M30, and the source is connected to the drain of tube M32; the gate of tube M32 is connected to the gate of tube M29 and the drain of tube M28, the drain is connected to the source of tube M31, and the source is grounded.

2. A current-mode bandgap reference circuit with a full MOS structure according to claim 1, characterized in that: The startup circuit is used to ensure normal operation of the circuit during startup and prevent the bandgap reference circuit from being in an abnormal state.

3. The current-mode bandgap reference circuit of the full MOS structure according to claim 1, characterized in that: The bias voltage generating circuit utilizes a multi-stage complementary MOS structure to achieve temperature compensation to provide a stable bias voltage.

4. The current-mode bandgap reference circuit of a full MOS structure according to claim 1, characterized in that: The reference current generating circuit stabilizes the reference current through an operational amplifier and a negative feedback structure, so that the reference current has a strong ability to suppress power supply voltage and temperature changes.

5. The current-mode bandgap reference circuit of a full MOS structure according to claim 1, characterized in that: The self-biased low-voltage cascode circuit improves a power supply rejection ratio (PSRR) through a multi-stage structure and achieves high output impedance, thereby ensuring the accuracy and stability of the reference voltage output.

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