Method for verifying digital circuit module in integrated circuit

Abstract

The invention discloses a method for verifying a digital circuit module in an integrated circuit, which belongs to the technical field of circuit testing and comprises the following specific steps: I, analyzing functional requirements and performance indexes of the circuit module and constructing a virtual model; iI, identifying abnormity and boundary conditions in the circuit module and generating a test case; iII, performing function verification on the circuit module and evaluating module performance; iV, optimizing the current circuit configuration according to a performance evaluation result; v, carrying out randomness verification on the circuit to detect potential vulnerability and design defects; according to the method, the circuit performance can be remarkably improved, the workload of manual parameter adjustment is reduced, the design complexity and verification difficulty are reduced, the performance of a circuit module in various scenes is improved, an input area which may cause problems can be focused on under limited test resources, the comprehensiveness and verification efficiency of the verification process are improved, and the verification efficiency is improved. And the stability evaluation of the circuit is more accurate, and the verification can be continuously improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit testing, and in particular to a method for verifying a digital circuit module in an integrated circuit. Background Art

[0002] With the continuous advancement of integrated circuit technology, the complexity of modern digital circuit modules is increasing. Digital circuits play a vital role in various electronic devices and are widely used in communications, computing, control, and consumer electronics. Especially in high-performance computing and embedded systems, the design scale and integration of chips are constantly improving, making the verification and optimization of digital circuit modules an important part of ensuring system reliability and functionality. Traditional verification methods mainly rely on simulation and static analysis. Although some errors can be found in the early design stage, their coverage and efficiency are far from enough for modern complex circuit modules. Due to the extremely complex input signal combinations of digital circuits and their possible working conditions, many potential errors and boundary conditions are difficult to detect in traditional tests. Therefore, there is an urgent need for a method to verify digital circuit modules in integrated circuits to solve these problems and ensure the stability and reliability of circuit modules under different working conditions.

[0003] After searching, Chinese patent number CN103714219A discloses a method and system for verifying a digital circuit module in an integrated circuit. Although the invention can verify the digital circuit module and does not require the establishment of a special verification test case for the module, saving time and effort and shortening the development cycle, the circuit performance is low and the workload of manual parameter adjustment is large, which increases the design complexity and verification difficulty; in addition, the existing method for verifying the digital circuit module in the integrated circuit cannot focus on the input area that may cause problems under limited test resources, reducing the comprehensiveness of the verification process and the verification efficiency; for this reason, we propose a method for verifying the digital circuit module in the integrated circuit. Summary of the invention

[0004] The purpose of the present invention is to solve the defects in the prior art and to propose a method for verifying a digital circuit module in an integrated circuit.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A method for verifying a digital circuit module in an integrated circuit, the specific steps of the verification method are as follows:

[0007] Ⅰ. Analyze the functional requirements and performance indicators of the circuit module and build a virtual model;

[0008] II. Identify anomalies and boundary conditions in circuit modules and generate test cases;

[0009] III. Verify the functionality of the circuit module and evaluate the module performance;

[0010] IV. Optimize the current circuit configuration based on the performance evaluation results;

[0011] V. Perform random verification on circuits to detect potential vulnerabilities and design flaws;

[0012] Ⅵ. Summarize all data during the verification process and provide feedback to staff.

[0013] As a further solution of the present invention, the specific steps of constructing the virtual model in step I are as follows:

[0014] S1.1: Extract the functional requirements of the digital circuit module from the requirements analysis, define the relationship between the input signal and the output signal through a truth table or logic equation, and build a functional model of the digital circuit module based on the input-output relationship and logic expression;

[0015] S1.2: By establishing the relationship between the clock signal and the data path, add timing constraints to the model, and then use the ModelSim simulation tool to build a digital circuit module simulation model with function and timing;

[0016] S1.3 performs various input mode simulations, observes the matching of output waveforms with expected results, records test results, analyzes the performance of the circuit under different input conditions, checks circuit response, checks for potential errors or inconsistencies with the design requirements of building digital circuit modules based on simulation results, and manually modifies the model, processes the model data and its verification process into a set of document data, and saves it.

[0017] As a further solution of the present invention, the specific steps of generating the test case in step II are as follows:

[0018] S2.1: Using the constructed digital circuit module simulation model, the output results of the digital circuit module under various input conditions are collected through simulation, and the collected input and output data are subjected to Max-Min normalization and format conversion processing;

[0019] S2.2: Based on the Bi-GRU neural network architecture, a set of recognition generation models including a GRU layer for processing forward sequences and a GRU layer for processing reverse sequences are constructed through the TensorFlow deep learning framework, and the processed input and output data are divided into a training set and a validation set;

[0020] S2.3: At the beginning of training, the weight matrix and bias of the recognition generation model are randomly initialized, and the input data in the training set is input into the forward and reverse GRU layers of the recognition generation model at different times, and the hidden state of each time is calculated in turn. At each time, the output layer of the recognition generation model generates a predicted output;

[0021] S2.4: Use the MSE loss function to calculate the difference between the predicted input and the actual output, input the calculated difference value from the model output layer, use the back propagation algorithm, use the difference value to derive each network layer parameter, calculate the gradient, and then use the Adam optimization algorithm to update the model's weight matrix and bias vector;

[0022] S2.5: After each training cycle, input the validation set data into the recognition generation model, calculate the validation loss and evaluate the model performance to check whether overfitting occurs. If the difference between the validation loss and the training loss exceeds the preset threshold, adjust the model hyperparameters.

[0023] S2.6: Repeat the forward propagation, loss calculation, back propagation and parameter update process until the verification set loss converges to the preset range, then stop the iteration, input the new circuit signal data into the recognition generation model, and identify the input combination that triggers anomalies or boundary conditions in the input signal. Based on the identified anomalies and boundary conditions, generate test cases that can cover all states of the digital circuit module, including boundary inputs, extreme inputs, and randomly generated groups.

[0024] As a further solution of the present invention, the specific steps of evaluating module performance in step III are as follows:

[0025] S3.1: Generate different input signal sequences according to the generated test cases, input the automatically generated test examples into the digital circuit module simulation model one by one, verify the functions of the digital circuit module in turn, and record the output data corresponding to each input signal sequence;

[0026] S3.2: After each test case is executed, the difference ΔY between the actual output and the expected output of the digital circuit module is compared. If ΔY=0, it means the test has passed. Otherwise, it means there is an error in the function of the digital circuit module. Further debugging is performed and the functional verification results and the specific problems in the case of differences are recorded;

[0027] S3.3: Calculate the pass rate of the test instance to evaluate whether the overall function of the digital circuit module meets the design requirements. If the pass rate is higher than the preset threshold, it means that the circuit function is normal; if the pass rate is lower than the preset threshold, the digital circuit module needs to be modified and debugged;

[0028] S3.4: After completing the functional verification, perform various performance evaluations on latency, throughput, power consumption, and resource utilization. Based on the results of the performance evaluation, analyze the performance limit of the circuit, and organize the results of the functional verification and performance evaluation into a report for the user to review.

[0029] As a further solution of the present invention, the specific steps of optimizing the current circuit configuration in step IV are as follows:

[0030] S4.1: Based on the performance evaluation results, minimizing circuit delay and power consumption, and maximizing circuit throughput are used as optimization goals to construct the corresponding problem space and initialize multiple groups of optimization bodies. At the same time, each group of optimization bodies randomly selects a group of solutions, i.e., the initial circuit parameter configuration, and initializes the pheromone matrix of each group of solutions;

[0031] S4.2: Calculate the heuristic information of each optimization decision point in the problem space, and obtain the selection probability of each optimization decision point according to the heuristic information of each group of optimization decision points and the initial pheromone concentration. Then, each optimization body starts from the starting point and selects the next optimization decision point based on the selection probability;

[0032] S4.3: Each optimization body gradually selects the next optimization decision point until the termination decision point is reached, and the path construction is completed. After each optimization body completes the path selection, the circuit performance is evaluated based on the parameter combination corresponding to each path, and its objective function value is calculated, and the performance index of the current solution is recorded;

[0033] S4.4: Based on the evaluation results of each path, the pheromone concentration on each path is updated. Through multiple iterations, each group of optimization bodies explores the optimization scheme in the problem space until the change in the objective function value reaches the preset range and the iteration is stopped. Then, the path with the highest pheromone concentration is selected as the optimal optimization scheme, which is applied to the actual integrated circuit and the circuit operation information is monitored in real time.

[0034] As a further solution of the present invention, the specific steps of detecting potential vulnerabilities and design defects in step V are as follows:

[0035] S5.1: Model the circuit verification process as a search tree, where each node in the tree represents the state of the circuit under a specific input condition, and the edges between the nodes represent the operation or input signal change from one state to another. The initial state of the circuit is then used as the root node, and the remaining nodes represent the state transitions of the circuit under different input conditions.

[0036] S5.2: Starting from the root node, use the upper confidence interval selection strategy to select the child node with the highest UCB value layer by layer. When a node that is not fully expanded is selected, expand it, create a child node by randomly selecting a new input signal combination, and add the new child node to the tree;

[0037] S5.3: After expansion, a random simulation is performed on the newly generated child nodes, starting from the current node, and a complete verification path is performed using random input signals until the circuit operation is completed. At the same time, the complete input signal path generated during the simulation is extracted, and the behavior of the circuit is verified to meet the design requirements;

[0038] S5.4: After the simulation is completed, evaluate the performance of the circuit under this path and propagate the evaluation results back to all nodes in the tree along this path. Repeat for multiple iterations and analyze the reward value and number of visits of each node to evaluate the performance of the circuit under different input conditions.

[0039] S5.5: Stop the search when the preset maximum number of iterations is reached, and generate a verification report based on the final search tree results, indicating the input conditions under which the circuit performs well and the input conditions that pose potential risks.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] 1. The method for verifying the digital circuit module in the integrated circuit constructs the corresponding problem space according to the performance evaluation results, and initializes multiple groups of optimization bodies. At the same time, each group of optimization bodies randomly selects a group of solutions, that is, the initial circuit parameter configuration, initializes the pheromone matrix of each group of solutions, calculates the heuristic information of each optimization decision point in the problem space, and obtains the selection probability of each optimization decision point according to the heuristic information of each group of optimization decision points and the initial pheromone concentration. After that, each optimization body starts from the starting point and selects the next optimization decision point based on the selection probability. Each optimization body gradually selects the next optimization decision point until the termination decision point is reached, and the path construction is completed. After each optimization body completes the path selection, Based on the parameter combination corresponding to each path, the circuit performance is evaluated, and its objective function value is calculated, and the performance indicators of the current solution are recorded. According to the results of the evaluation of each path, the pheromone concentration on each path is updated. Through multiple iterations, each group of optimization bodies explores the optimization solution in the problem space until the change in the objective function value reaches the preset range, and then the iteration is stopped. Then, the path with the highest pheromone concentration is selected as the optimal optimization solution, and it is applied to actual integrated circuits. The circuit operation information is monitored in real time, which can significantly improve the circuit performance, reduce the workload of manual parameter adjustment, reduce the design complexity and verification difficulty, and improve the performance of the circuit module in various scenarios.

[0042] 2. The method for verifying the digital circuit module in the integrated circuit models the circuit verification process as a search tree, and then takes the initial state of the circuit as the root node, and the remaining nodes represent the state transition of the circuit under different input conditions. Starting from the root node, the upper confidence interval selection strategy is used to select the child node with the highest UCB value layer by layer. When a node that is not fully expanded is selected, it is expanded, and a child node is created by randomly selecting a new input signal combination, and the new child node is added to the tree. After expansion, a random simulation is performed on the newly generated child node. Starting from the current node, a complete verification path is performed using random input signals until the circuit operation is completed, and the complete child node generated during the simulation is extracted. The input signal path is searched and the circuit behavior is verified to meet the design requirements. After the simulation is completed, the performance of the circuit under this path is evaluated and the evaluation results are sent back to all nodes in the path in the tree. Multiple iterations are repeated and the reward value and the number of visits of each node are analyzed to evaluate the performance of the circuit under different input conditions. The search is stopped when the preset maximum number of iterations is reached. A verification report is generated based on the final search tree results, which explains the input conditions under which the circuit performs well and the input conditions with potential risks. With limited test resources, it is possible to focus on input areas that may cause problems, improve the comprehensiveness of the verification process and the verification efficiency, and make the circuit stability evaluation more accurate, ensuring that verification can be continuously improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0044] Figure 1 The present invention is a flowchart of a method for verifying a digital circuit module in an integrated circuit. DETAILED DESCRIPTION

[0045] Example 1

[0046] Reference Figure 1 , a method for verifying a digital circuit module in an integrated circuit, the specific steps of the verification method are as follows:

[0047] Analyze the functional requirements and performance indicators of circuit modules and build virtual models.

[0048] Specifically, the functional requirements of the digital circuit module are extracted from the demand analysis, the relationship between the input signal and the output signal is defined through a truth table or a logic equation, and the functional model of the digital circuit module is constructed based on the input-output relationship and the logic expression. By establishing the relationship between the clock signal and the data path, timing constraints are added to the model. Then, a simulation model of the digital circuit module with function and timing is built through the ModelSim simulation tool, and various input mode simulations are performed. The match between the output waveform and the expected result is observed, the test results are recorded, the performance of the circuit under different input conditions is analyzed, and the circuit response is checked. According to the simulation results, potential errors or inconsistencies with the design requirements of the digital circuit module are checked, and the model is manually corrected. The model data and its verification process are processed into a set of document data and saved.

[0049] Identify anomalies and boundary conditions in circuit modules and generate test cases.

[0050] Specifically, the constructed digital circuit module simulation model is used to collect the output results of the digital circuit module under various input conditions through simulation, and the collected input and output data are Max-Min normalized and format converted. Based on the Bi-GRU neural network architecture, a set of recognition generation models including a GRU layer for processing forward sequences and a GRU layer for processing reverse sequences are constructed through the TensorFlow deep learning framework. The processed input and output data are divided into a training set and a validation set. At the beginning of training, the weight matrix and bias of the recognition generation model are randomly initialized, and the input data in the training set are input into the forward and reverse GRU layers of the recognition generation model according to different times, and the hidden state of each time is calculated in turn. At each time, the output layer of the recognition generation model generates a predicted output, and the MSE loss function is used to calculate the difference between the predicted input and the actual output. The difference value is input from the model output layer, and the back propagation algorithm is used to use the difference value to derive the parameters of each network layer, calculate the gradient, and then use the Adam optimization algorithm to update the weight matrix and bias vector of the model. After each round of training cycle, the verification set data is input into the recognition generation model, the verification loss is calculated and the model performance is evaluated to check whether overfitting occurs. If the difference between the verification loss and the training loss exceeds the preset threshold, the model hyperparameters are adjusted, and the forward propagation, loss calculation, back propagation and parameter update processes are repeated until the verification set loss converges to the preset range. The iteration is stopped, and the new circuit signal data is input into the recognition generation model, and the input combination that triggers anomalies or boundary conditions in the input signal is identified. According to the identified anomalies and boundary conditions, test cases including boundary inputs, extreme inputs and randomly generated groups that can cover all states of the digital circuit module are generated.

[0051] Functionally verify circuit modules and evaluate module performance.

[0052] Specifically, different input signal sequences are generated according to the generated test cases, and the automatically generated test examples are input into the digital circuit module simulation model one by one, the functions of the digital circuit module are verified in turn, and the output data corresponding to each input signal sequence is recorded. After each test case is executed, the difference ΔY between the actual output and the expected output of the digital circuit module is compared. If ΔY=0, it means that the test has passed. Otherwise, it means that there is an error in the function of the digital circuit module. Further debugging is performed, and the function verification results and specific problems in the case of differences are recorded. The pass rate of the test instance is calculated to evaluate whether the overall function of the digital circuit module meets the design requirements. If the pass rate is higher than a preset threshold, it means that the circuit function is normal; if the pass rate is lower than the preset threshold, the digital circuit module needs to be modified and debugged. After completing the functional verification, various performance evaluations of delay, throughput, power consumption and resource utilization are performed. According to the results of the performance evaluation, the performance limit of the circuit is analyzed, and the results of the functional verification and performance evaluation are compiled into a report for users to view.

[0053] Example 2

[0054] Reference Figure 1 , a method for verifying a digital circuit module in an integrated circuit, the specific steps of the verification method are as follows:

[0055] Optimize the current circuit configuration based on the performance evaluation results.

[0056] Specifically, according to the performance evaluation results, minimizing circuit delay and power consumption and maximizing circuit throughput are used as optimization goals to construct the corresponding problem space, and multiple groups of optimization bodies are initialized. At the same time, each group of optimization bodies randomly selects a group of solutions, that is, the initial circuit parameter configuration, initializes the pheromone matrix of each group of solutions, calculates the heuristic information of each optimization decision point in the problem space, and obtains the selection probability of each optimization decision point according to the heuristic information of each group of optimization decision points and the initial pheromone concentration. After that, each optimization body starts from the starting point and selects the next optimization decision point based on the selection probability. Each optimization body gradually selects the next optimization decision point until the termination decision point is reached, and the path construction is completed. After each optimization body completes the path selection, the circuit performance is evaluated based on the parameter combination corresponding to each path, and its objective function value is calculated, and the performance index of the current solution is recorded. According to the evaluation results of each path, the pheromone concentration on each path is updated. Through multiple iterations, each group of optimization bodies explores the optimization scheme in the problem space until the objective function value change value reaches a preset range and stops the iteration. Then, the path with the highest pheromone concentration is selected as the optimal optimization scheme, and it is applied to the actual integrated circuit, and the circuit operation information is monitored in real time.

[0057] Perform random validation on circuits to detect potential vulnerabilities and design flaws.

[0058] Specifically, the circuit verification process is modeled as a search tree, where each node in the tree represents the state of the circuit under specific input conditions, and the edges between the nodes represent the operation or input signal change from one state to another. Then, the initial state of the circuit is used as the root node, and the remaining nodes represent the state transitions of the circuit under different input conditions. Starting from the root node, the upper confidence interval selection strategy is used to select the child node with the highest UCB value layer by layer. When a node that is not fully expanded is selected, it is expanded, and a child node is created by randomly selecting a new input signal combination, and the new child node is added to the tree. After expansion, a random simulation is performed on the newly generated child node , starting from the current node, use random input signals to perform a complete verification path until the circuit runs to the end. At the same time, extract the complete input signal path generated during the simulation process and verify whether the behavior of the circuit meets the design requirements. After the simulation is completed, evaluate the performance of the circuit under this path, and pass the evaluation results back to all nodes in the tree on this path. Repeat multiple iterations and analyze the reward value and number of visits of each node to evaluate the performance of the circuit under different input conditions. Stop the search when the preset maximum number of iterations is reached. Generate a verification report based on the final search tree results, and explain the input conditions under which the circuit performs well and the input conditions with potential risks.

[0059] Summarize all data during the verification process and provide feedback to staff.

Claims

1. A method for verifying a digital circuit module in an integrated circuit, characterized in that: The specific steps of this verification method are as follows: Ⅰ. Analyze the functional requirements and performance indicators of the circuit module and build a virtual model; II. Identify anomalies and boundary conditions in circuit modules and generate test cases; III. Verify the functionality of the circuit module and evaluate the module performance; IV. Optimize the current circuit configuration based on the performance evaluation results; V. Perform random verification on circuits to detect potential vulnerabilities and design flaws; Ⅵ. Summarize all data during the verification process and provide feedback to staff.

2. A method for verifying a digital circuit module in an integrated circuit according to claim 1, characterized in that: The specific steps of building the virtual model described in step Ⅰ are as follows: S1.1: Extract the functional requirements of the digital circuit module from the requirements analysis, define the relationship between the input signal and the output signal through a truth table or logic equation, and build a functional model of the digital circuit module based on the input-output relationship and logic expression; S1.2: By establishing the relationship between the clock signal and the data path, add timing constraints to the model, and then use the ModelSim simulation tool to build a digital circuit module simulation model with function and timing; S1.3 performs various input mode simulations, observes the matching of output waveforms with expected results, records test results, analyzes the performance of the circuit under different input conditions, checks circuit response, checks for potential errors or inconsistencies with the design requirements of building digital circuit modules based on simulation results, and manually modifies the model, processes the model data and its verification process into a set of document data, and saves it.

3. A method for verifying a digital circuit module in an integrated circuit according to claim 1, characterized in that: The specific steps for generating test cases described in step II are as follows: S2.1: Using the constructed digital circuit module simulation model, the output results of the digital circuit module under various input conditions are collected through simulation, and the collected input and output data are subjected to Max-Min normalization and format conversion processing; S2.2: Based on the Bi-GRU neural network architecture, a set of recognition generation models including a GRU layer for processing forward sequences and a GRU layer for processing reverse sequences are constructed through the TensorFlow deep learning framework, and the processed input and output data are divided into a training set and a validation set; S2.3: At the beginning of training, the weight matrix and bias of the recognition generation model are randomly initialized, and the input data in the training set is input into the forward and reverse GRU layers of the recognition generation model at different times, and the hidden state of each time is calculated in turn. At each time, the output layer of the recognition generation model generates a predicted output; S2.4: Use the MSE loss function to calculate the difference between the predicted input and the actual output, input the calculated difference value from the model output layer, use the back propagation algorithm, use the difference value to derive each network layer parameter, calculate the gradient, and then use the Adam optimization algorithm to update the model's weight matrix and bias vector; S2.5: After each training cycle, input the validation set data into the recognition generation model, calculate the validation loss and evaluate the model performance to check whether overfitting occurs. If the difference between the validation loss and the training loss exceeds the preset threshold, adjust the model hyperparameters. S2.6: Repeat the forward propagation, loss calculation, back propagation and parameter update process until the verification set loss converges to the preset range, then stop the iteration, input the new circuit signal data into the recognition generation model, and identify the input combination that triggers anomalies or boundary conditions in the input signal. Based on the identified anomalies and boundary conditions, generate test cases that can cover all states of the digital circuit module, including boundary inputs, extreme inputs, and randomly generated groups.

4. A method for verifying a digital circuit module in an integrated circuit according to claim 3, characterized in that: The specific steps for evaluating module performance in step III are as follows: S3.1: Generate different input signal sequences according to the generated test cases, input the automatically generated test examples into the digital circuit module simulation model one by one, verify the functions of the digital circuit module in turn, and record the output data corresponding to each input signal sequence; S3.2: After each test case is executed, the difference ΔY between the actual output and the expected output of the digital circuit module is compared. If ΔY=0, it means the test has passed. Otherwise, it means there is an error in the function of the digital circuit module. Further debugging is performed and the functional verification results and the specific problems in the case of differences are recorded; S3.3: Calculate the pass rate of the test case to evaluate whether the overall function of the digital circuit module meets the design requirements. If the pass rate is higher than a preset threshold, it means that the circuit function is normal; If the pass rate is lower than the preset threshold, the digital circuit module needs to be modified and debugged; S3.4: After completing the functional verification, perform various performance evaluations on latency, throughput, power consumption, and resource utilization. Based on the results of the performance evaluation, analyze the performance limit of the circuit, and organize the results of the functional verification and performance evaluation into a report for the user to review.

5. A method for verifying a digital circuit module in an integrated circuit according to claim 4, characterized in that: The specific steps of optimizing the current circuit configuration described in step IV are as follows: S4.1: Based on the performance evaluation results, minimizing circuit delay and power consumption, and maximizing circuit throughput are used as optimization goals to construct the corresponding problem space and initialize multiple groups of optimization bodies. At the same time, each group of optimization bodies randomly selects a group of solutions, i.e., the initial circuit parameter configuration, and initializes the pheromone matrix of each group of solutions; S4.2: Calculate the heuristic information of each optimization decision point in the problem space, and obtain the selection probability of each optimization decision point according to the heuristic information of each group of optimization decision points and the initial pheromone concentration. Then, each optimization body starts from the starting point and selects the next optimization decision point based on the selection probability; S4.3: Each optimization body gradually selects the next optimization decision point until the termination decision point is reached, and the path construction is completed. After each optimization body completes the path selection, the circuit performance is evaluated based on the parameter combination corresponding to each path, and its objective function value is calculated, and the performance index of the current solution is recorded; S4.4: Based on the evaluation results of each path, the pheromone concentration on each path is updated. Through multiple iterations, each group of optimization bodies explores the optimization scheme in the problem space until the change in the objective function value reaches the preset range and the iteration is stopped. Then, the path with the highest pheromone concentration is selected as the optimal optimization scheme, which is applied to the actual integrated circuit and the circuit operation information is monitored in real time.

6. A method for verifying a digital circuit module in an integrated circuit according to claim 5, characterized in that: The specific steps for detecting potential vulnerabilities and design flaws described in step V are as follows: S5.1: Model the circuit verification process as a search tree, where each node in the tree represents the state of the circuit under a specific input condition, and the edges between the nodes represent the operation or input signal change from one state to another. The initial state of the circuit is then used as the root node, and the remaining nodes represent the state transitions of the circuit under different input conditions. S5.2: Starting from the root node, use the upper confidence interval selection strategy to select the child node with the highest UCB value layer by layer. When a node that is not fully expanded is selected, expand it, create a child node by randomly selecting a new input signal combination, and add the new child node to the tree; S5.3: After expansion, a random simulation is performed on the newly generated child nodes, starting from the current node, and a complete verification path is performed using random input signals until the circuit operation is completed. At the same time, the complete input signal path generated during the simulation is extracted, and the behavior of the circuit is verified to meet the design requirements; S5.4: After the simulation is completed, evaluate the performance of the circuit under this path and propagate the evaluation results back to all nodes in the tree along this path. Repeat for multiple iterations and analyze the reward value and number of visits of each node to evaluate the performance of the circuit under different input conditions. S5.5: Stop the search when the preset maximum number of iterations is reached, and generate a verification report based on the final search tree results, indicating the input conditions under which the circuit performs well and the input conditions that pose potential risks.

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