Memory fault diagnosis method and circuit, electronic equipment and readable medium

Abstract

The embodiment of the invention provides a fault diagnosis method and circuit of a memory, electronic equipment and a readable medium, and relates to the technical field of integrated circuits, in the method, a test circuit sequentially executes data comparison operation on tested units in the memory according to data comparison operation corresponding to a preset test algorithm. After one-time data comparison operation is executed, a fault capturing circuit generates a single-time fault characteristic value corresponding to target comparison operation under the condition that a comparison result represents that the detected unit has a fault; the target comparison operation is a data comparison operation that the comparison result represents that the tested unit has a fault, and the single fault feature value is used for representing identification information of the target comparison operation; and after all data comparison operations corresponding to the preset test algorithm are executed, identifying the fault type of the tested unit based on all the single fault feature values. Therefore, the fault type of the tested unit can be identified based on all the single fault characteristic values, and then the fault type is determined.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a fault diagnosis method, circuit, electronic device and readable medium of a memory. Background Art

[0002] With the development of integrated circuit technology, there is an increasing demand for chip testing. As an important component in a chip, the memory in the chip is particularly important for testing. In the related art, when testing the memory, the memory cells in the memory are tested through the test circuit integrated in the chip, so as to locate the faulty memory cells.

[0003] In this way, only fault location can be achieved. Therefore, how to determine the fault type of the unit under test becomes a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiment of the present invention provides a fault diagnosis method, circuit, electronic device and readable medium of a memory, which can determine the fault type of a unit under test.

[0005] In order to solve the above problems, an embodiment of the present invention discloses a method for diagnosing a fault of a memory, which is applied to a chip integrated with a test circuit and a fault capture circuit. The method includes:

[0006] The test circuit sequentially performs the data comparison operation on the units under test in the memory according to the data comparison operation corresponding to the preset test algorithm;

[0007] After executing the data comparison operation once, the fault capture circuit generates a single fault characteristic value corresponding to a target comparison operation when the comparison result indicates that the unit under test has a fault; the target comparison operation is the data comparison operation whose comparison result indicates that the unit under test has a fault, and the single fault characteristic value is used to indicate identification information of the target comparison operation;

[0008] After executing all data comparison operations corresponding to the preset test algorithm, the fault type of the unit under test is identified based on all the single fault characteristic values.

[0009] On the other hand, an embodiment of the present invention discloses a fault diagnosis circuit of a memory, wherein the fault diagnosis circuit includes a test circuit and a fault capture circuit;

[0010] The test circuit is used to perform the data comparison operation on the units under test in the memory in sequence according to the data comparison operation corresponding to the preset test algorithm;

[0011] The fault capture circuit is used to generate a single fault characteristic value corresponding to a target comparison operation after performing the data comparison operation once, when the comparison result indicates that the unit under test has a fault; the target comparison operation is the data comparison operation whose comparison result indicates that the unit under test has a fault, and the single fault characteristic value is used to indicate identification information of the target comparison operation;

[0012] After the test circuit executes all data comparison operations corresponding to the preset test algorithm, the single fault characteristic value analysis component executes the operation of identifying the fault type of the unit under test based on all the single fault characteristic values.

[0013] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the aforementioned method.

[0014] The embodiment of the present invention further discloses a machine-readable medium on which instructions are stored. When executed by one or more processors, the processors are enabled to execute the method described above.

[0015] The embodiment of the present invention includes the following advantages: the fault diagnosis method of the memory provided by the embodiment of the present invention, through the chip integrated with the test circuit and the fault capture circuit, firstly, the test circuit performs the data comparison operation on the unit under test in the memory in sequence according to the data comparison operation corresponding to the preset test algorithm. After performing one data comparison operation, the fault capture circuit generates a single fault characteristic value corresponding to the target comparison operation when the comparison result indicates that the unit under test has a fault; the target comparison operation is a data comparison operation in which the comparison result indicates that the unit under test has a fault. Since the single fault characteristic value can represent the identification information of the target comparison operation, accordingly, after performing all the data comparison operations corresponding to the preset test algorithm, based on all the obtained single fault characteristic values, all the data comparison operations that tested the fault in this test process can be known. Therefore, after performing all the data comparison operations corresponding to the preset test algorithm, the fault type of the unit under test can be identified based on all the single fault characteristic values, thereby realizing the determination of the fault type of the unit under test.

[0016] At the same time, by performing data comparison operations on the units under test in the memory in sequence according to the data comparison operations corresponding to the preset test algorithm through the test circuit, the test of the units under test in the memory can be realized, and then the memory test can be realized. In the embodiment of the present invention, by integrating a fault capture circuit in the chip, the fault characteristic value is captured by the fault capture circuit inside, without the need to move out the execution state of the preset test algorithm, and through the moved out execution state and fault address information, the read operation bit where the fault is detected in the preset test algorithm is analyzed, and then the fault characteristic value is formed according to the read operation bit where the fault is detected. Based on the integrated fault capture circuit, the fault characteristic value of the identification information of all data comparison operations that detect the fault at the address where the unit under test is located in this test process can be obtained. In this way, there is no need to perform a large amount of analysis on a large amount of data, and the specific fault type can be determined based on these fault characteristic values, so the efficiency of determining the fault type is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0018] Figure 1 is a flowchart of a method for diagnosing a fault of a memory provided by an embodiment of the present invention;

[0019] Figure 2 is a structural schematic diagram of a test circuit provided by an embodiment of the present invention;

[0020] Figure 3 It is a schematic diagram of a simulation waveform provided by an embodiment of the present invention;

[0021] Figure 4 is a circuit diagram of a fault diagnosis circuit provided by an embodiment of the present invention;

[0022] Figure 5 is a schematic diagram of another fault diagnosis circuit provided by an embodiment of the present invention;

[0023] Figure 6 is a schematic diagram of a fault capture circuit provided by an embodiment of the present invention;

[0024] Figure 7 is a schematic diagram of a capture unit provided by an embodiment of the present invention;

[0025] Figure 8 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] The fault diagnosis method of the memory provided by the embodiment of the present invention can be applied to the scenario of testing the memory in the chip. Among them, the memory can be an embedded memory in the chip, for example, a random access memory (RAM) and the like. In the scenario of testing the memory, the memory built-in self-test (MBIST) technology is a widely used self-test technology, and the MBIST technology generally includes functions such as test vector generation, test vector loading, test algorithm execution and test result analysis. It automatically generates the information required for the test and performs the memory test by integrating the test circuit inside the chip. Since the information required for the test is generated by the test circuit itself during the test process, no external application is required. On the automatic test equipment (ATE) machine, only the test environment needs to be configured and the MBIST configuration needs to be completed to perform the test, thereby improving the test efficiency and reducing the test cost.

[0028] When memory is tested based on test circuit in the MBIST technology, it is also necessary to carry out fault diagnosis to the fault tested simultaneously.At present, the fault diagnosis mechanism of MBIST does not relate to the identification of fault type usually.For this reason, the embodiment of the invention provides a kind of fault diagnosis method of memory, to realize the identification of fault type.

[0029] Reference Figure 1 , shows a flowchart of a method for diagnosing a fault of a memory device according to an embodiment of the present invention, such as Figure 1 As shown, the method specifically comprises the following steps:

[0030] Step 101: The test circuit sequentially performs the data comparison operation on the units under test in the memory according to the data comparison operation corresponding to the preset test algorithm.

[0031] Step 102: After executing the data comparison operation once, the fault capture circuit generates a single fault characteristic value corresponding to the target comparison operation when the comparison result indicates that the unit under test has a fault; the target comparison operation is the data comparison operation whose comparison result indicates that the unit under test has a fault, and the single fault characteristic value is used to characterize the identification information of the target comparison operation.

[0032] Step 103: After executing all data comparison operations corresponding to the preset test algorithm, the fault type of the unit under test is identified based on all the single fault characteristic values.

[0033] The fault diagnosis method of the memory provided in the embodiment of the present invention can be applied to a chip integrated with a test circuit and a fault capture circuit. Among them, the test circuit may include a test controller, a test information generation circuit and a test comparator. The test information generation circuit may include a test vector generation circuit and a test address generation circuit. The test vector generation circuit may also be called a data generation circuit, and the test address generation circuit may also be called an address generation circuit. The test controller may also be called a BIST control circuit. The data generation circuit, the address generation circuit and the BIST control circuit may be collectively referred to as a BIST circuit.

[0034] Figure 2 is a schematic diagram of a test circuit provided by an embodiment of the present invention, such as Figure 2 As shown, Test_data, Test_addr and Test_wen represent the data, address and enable control in the test mode, respectively, and Logic_data, Logic_addr and Logic_wen represent the data, address and enable control in the functional mode, respectively. Among them, the signal in the functional mode comes from the system, and the signal in the test mode comes from the test circuit, and the test does not affect the functional mode. After the multiplexer, the Data, Addr, and Wen input to the memory in the functional mode are Logic_data, Logic_addr, and Logic_wen, respectively. In the scenario of testing the memory, the Data, Addr, and Wen input to the memory in the test mode are Test_data, Test_addr, and Test_wen, respectively.

[0035] Specifically, Test_data, Test_addr and Test_wen respectively represent signals generated by the data generation circuit, the address generation circuit and the BIST control circuit. Test_data represents a signal for writing a test vector to the unit under test in the memory. Test_addr represents a signal for selecting a specific address in the memory. In the test mode, the storage unit in the memory can be located based on the Test_addr signal, and the located storage unit is the unit under test.

[0036] Furthermore, fault diagnosis specifically refers to diagnosing faults detected in memory testing. In the memory test process, if a comparison result indicates that a fault exists in the unit under test, then the fault can be regarded as a fault to be diagnosed, and a fault diagnosis result of the fault can be obtained after fault diagnosis. Among them, the fault diagnosis result may include the type of fault. When performing a memory test, a test instruction for instructing the test to be performed can be input into the test controller in the test circuit. Accordingly, the test controller can execute a preset test algorithm to implement the test. Among them, the preset test algorithm is the test algorithm used in this test process, and the preset test algorithm can be used to detect various fault types in the storage unit.

[0037] The test controller can send the generated Test_addr signal to the memory under test. The Test_addr signal can be used to select a specific word line and a bit line in the memory, and then access the unit under test, so as to perform read and write operations on the unit under test. The memory under test can include multiple storage units, and the unit under test can be a storage unit that needs to be tested among the multiple storage units. Specifically, the unit under test can be any storage unit among the multiple storage units included in the memory under test. The test controller can be responsible for completing the entire test process according to the execution phase of the preset test algorithm and implementing the test based on the preset test algorithm. Specifically, the test controller can control the test information generator according to the preset test algorithm to generate a test vector as the data of Test_data. The test vector is generated by pre-designed generation logic based on the preset test algorithm, and the test vector can be used to detect data of a certain type of fault. Then a write operation is performed on the unit under test, and then a test vector is written to the unit under test. After that, the control performs a read operation on the unit under test, and the previously written data is read from the unit under test to the test comparer, and the test comparer can perform a data comparison operation on the read data (data_out) and the reference data (expect_data) to implement the test. The reference data may also be referred to as expected data, and the reference data may be previously written data. Specifically, if the read data is different from the reference data, a comparison result indicating that the unit under test has a fault may be generated. Conversely, if the read data is the same as the reference data, a comparison result indicating that the unit under test has no fault may be generated.

[0038] Among them, the test algorithm involves multiple sequentially executed read and write operations. Specifically, the test algorithm is often divided into multiple sequentially executed algorithm stages, and each algorithm stage has sequentially executed read operations and / or write operations. The write operation performed on the unit under test and the read operation performed on the unit under test are both read and write operations defined in the algorithm stage in the preset test algorithm. The number of algorithm stages included in the test algorithm and the number of write operations and read operations in each algorithm stage are fixed, and the specific number of algorithm stages, write operations and read operations can be set according to the algorithm design requirements. After each read operation in the test algorithm, a data comparison operation is performed on the unit under test. Specifically, a data comparison operation can be performed once to compare the read data with the reference data, that is, a read operation involved in the test algorithm corresponds to a data comparison operation. Accordingly, the data comparison operation corresponding to the preset test algorithm can refer to the data comparison operation corresponding to all read operations involved in the preset test algorithm. After each read operation is performed, the read data is compared with the reference data, thereby realizing the sequential execution of the data comparison operation corresponding to the preset test algorithm on the unit under test.

[0039] In the embodiment of the present invention, a test flow corresponds to the entire execution process of the test algorithm. That is, after executing all algorithm stages of the test algorithm, a test flow is deemed to be completed. The single fault characteristic value in this test flow is generated based on the data comparison operation involved in this test flow. For any data comparison operation in this test flow, if the comparison result of the data comparison operation indicates that the unit under test has a fault, a single fault characteristic value will be generated accordingly. Assuming that the preset test algorithm has 10 algorithm stages, and these 10 algorithm stages involve 13 read operations in total, then the preset test algorithm corresponds to 13 data comparison operations. In other words, after executing these 10 algorithm stages, this test flow is deemed to be completed. Accordingly, 13 read operations are executed in this test flow, and 13 data comparison operations are executed accordingly. Among them, the data read by each read operation is the data written to the unit under test the most recently. In the entire test flow, after executing a data comparison operation, if the comparison result indicates that the unit under test has no fault, the subsequent test operation can be directly continued, that is, the next operation of the read operation corresponding to the data comparison operation in the preset test algorithm is executed. If the comparison result indicates that there is a fault in the unit under test, after generating and removing the single fault characteristic value, the next read operation corresponding to the data comparison operation in the preset test algorithm can be continued to be executed until all operations in the preset test algorithm are executed, thereby ending this test process.

[0040] For any type of fault that can be distinguished by the test algorithm, if the storage unit has such a fault, then among all the read operations involved in the test algorithm, the data read by a certain number of read operations will be different from the reference data, that is, the comparison results of a certain number of data comparison operations indicate that the unit under test has a fault. The comparison results of the data comparison operation indicate that the unit under test has a fault, which can be regarded as the data comparison operation testing the fault. Exemplarily, for a SAF0 type fault, if the storage unit has a SAF0 type fault, then the data read by the 2nd, 6th-8th, 12th-13th read operations will be different from the reference data.

[0041] In the embodiment of the present invention, after each data comparison operation is performed, that is, after a data comparison operation is performed, it will be determined whether to generate a single fault characteristic value based on the comparison result. Specifically, if the comparison result of the data comparison operation indicates that the unit under test has a fault, the single fault characteristic value of the identification information used to characterize this data comparison operation (that is, the data comparison operation whose comparison result indicates that the unit under test has a fault, and the data comparison operation can be referred to as the target comparison operation for the convenience of description) can be captured based on the pre-integrated fault capture circuit. Among them, the identification information can be information used to distinguish different data comparison operations. In this way, it can be known which data comparison operation has a comparison result indicating that the unit under test has a fault based on the single fault characteristic value. Accordingly, based on all single fault characteristic values, it can be known which data comparison operations in the entire test process have a comparison result indicating that the unit under test has a fault, that is, which data comparison operations have tested a fault. Therefore, the fault type of the unit under test can be identified based on all single fault characteristic values.

[0042] Specifically, after executing all data comparison operations corresponding to the preset test algorithm, this test process can be regarded as completed. At this time, the specific number of single fault characteristic values ​​obtained is related to the number of data comparison operations in this test process whose comparison results indicate that the unit under test has a fault. Exemplarily, assuming that only one data comparison operation has a comparison result that indicates that the unit under test has a fault, then there is only one single fault characteristic value. Assuming that there are multiple data comparison operations whose comparison results indicate that the unit under test has a fault, there are multiple single fault characteristic values.

[0043] In summary, the fault diagnosis method of the memory provided by the embodiment of the present invention, through the chip integrated with the test circuit and the fault capture circuit, firstly, the test circuit performs the data comparison operation on the unit under test in the memory in sequence according to the data comparison operation corresponding to the preset test algorithm. After performing a data comparison operation, the fault capture circuit generates a single fault characteristic value corresponding to the target comparison operation when the comparison result indicates that the unit under test has a fault; the target comparison operation is a data comparison operation whose comparison result indicates that the unit under test has a fault. Since the single fault characteristic value can represent the identification information of the target comparison operation, accordingly, after performing all the data comparison operations corresponding to the preset test algorithm, based on all the obtained single fault characteristic values, all the data comparison operations that tested the fault in this test process can be known. Therefore, after performing all the data comparison operations corresponding to the preset test algorithm, the fault type of the unit under test can be identified based on all the single fault characteristic values, thereby realizing the determination of the fault type of the unit under test.

[0044] At the same time, by performing data comparison operations on the units under test in the memory in sequence according to the data comparison operations corresponding to the preset test algorithm through the test circuit, the test of the units under test in the memory can be realized, and then the memory test can be realized. In the embodiment of the present invention, by integrating a fault capture circuit in the chip, the fault characteristic value is captured by the fault capture circuit inside, without the need to move out the execution state of the preset test algorithm, and through the moved out execution state and fault address information, the read operation bit where the fault is detected in the preset test algorithm is analyzed, and then the fault characteristic value is formed according to the read operation bit where the fault is detected. Based on the integrated fault capture circuit, the fault characteristic value of the identification information of all data comparison operations that detect the fault at the address where the unit under test is located in this test process can be obtained. In this way, there is no need to perform a large amount of analysis on a large amount of data, and the specific fault type can be determined based on these fault characteristic values, so the efficiency of determining the fault type is high.

[0045] Optionally, in the embodiment of the present invention, the identification information can be used to indicate the execution order of the data comparison operation in this test process. Specifically, the identification information of the target comparison operation is used to indicate the execution order of the target comparison operation in this test process. Among them, the execution order indicates that the data comparison operation is the data comparison operation executed in this test process, that is, it indicates that the read operation corresponding to the data comparison operation is the read operation involved in the preset test algorithm. In this way, the identification information of the target comparison operation can intuitively indicate that the read operation corresponding to the comparison operation that tests the fault is the read operation involved in the preset test algorithm, thereby ensuring that the fault type of the unit under test can be accurately identified based on the single fault characteristic value of the identification information used to characterize the target comparison operation. Further, the preset test algorithm corresponds to M data comparison operations, and the single fault characteristic value includes characteristic bits corresponding to the M data comparison operations one by one. The order of the characteristic bits corresponding to the data comparison operation in the single fault characteristic value is the same as the execution order of the data comparison operation. Since the order of the characteristic bits in the single fault characteristic value is the same as the execution order of the data comparison operation, the Xth characteristic bit in the single fault characteristic value can represent the execution of the Xth data comparison operation. In this way, different data comparison operations can be distinguished through different characteristic value values, so that the single fault characteristic value can accurately support the number of data comparison operations to test the fault.

[0046] Wherein, M is the total number of read operations involved in the preset test algorithm, and M is a positive integer. Taking M=13 as an example, a single fault characteristic value generated is 13-bit wide data, and one bit can represent a characteristic bit. Each of the 13 bits corresponds to a data comparison operation, that is, a read operation. Exemplarily, the 1st characteristic bit to the 13th characteristic bit in the single fault characteristic value can be recorded as signature[0] to signature

[12] . Specifically, the characteristic bit representing the Xth data comparison operation is the Xth characteristic bit in the single fault characteristic value. Accordingly, if the Xth data comparison operation tests a fault, that is, the Xth read operation identifies a fault, the value of the Xth characteristic bit can be set to a specific value. Since the order of the characteristic bits in the single fault characteristic value is the same as the execution order of the data comparison operation. Therefore, based on the single fault characteristic value, it can be known that the Xth data comparison operation tests a fault.

[0047] Optionally, the fault capture circuit in the embodiment of the present invention may include M capture units, and the M capture units correspond one-to-one to the M data comparison operations. Specifically, the M capture units correspond to the M data comparison operations in sequence according to the execution order of the M data comparison operations. A capture unit can be used to capture the value of the characteristic bit corresponding to the corresponding data comparison operation in the single fault characteristic value. That is, the value captured by a capture unit constitutes the value of a bit, and the values ​​captured by M capture units constitute a single fault characteristic value. In the embodiment of the present invention, the capture units can be numbered in advance. Capture units 0 to M-1 are set in sequence in the capture unit, and capture units 0 to M-1 represent the 1st capture unit to the Mth capture unit respectively. Among them, the Xth capture unit corresponds to the Xth data comparison operation. The above-mentioned single fault characteristic value corresponding to the target comparison operation is generated by the fault capture circuit when the comparison result indicates that the unit under test has a fault, which may specifically include:

[0048] Step 1021. When the comparison result indicates that the unit under test has a fault, the target capture unit and other capture units in the fault capture circuit respectively capture a first preset value and a second preset value; the other capture units include capture units other than the target capture unit; the target capture unit is a capture unit corresponding to the target comparison operation, the first preset value constitutes a characteristic value of a characteristic bit corresponding to the target comparison operation, and the second preset value constitutes a characteristic value of other characteristic bits except the characteristic bit corresponding to the target comparison operation.

[0049] Among them, the first preset value and the second preset value can be pre-set, and illustratively, the first preset value can be 1, and the second preset value can be 0. The capture unit corresponding to the target comparison operation can be used as the target capture unit, and the target capture unit is controlled to capture 1. Other capture units are controlled to capture 0, that is, the value of the characteristic bit corresponding to the target capture unit is 1, and the value of the characteristic bit corresponding to other capture units is 0. Exemplarily, assuming that the target comparison operation is the Xth data comparison operation, then the Xth capture unit corresponding to the Xth data comparison operation can be controlled to capture 1, and other capture units can capture 0. Correspondingly, in the obtained single fault characteristic value, the characteristic value of the Xth characteristic bit is 1, and the characteristic values ​​of other characteristic bits are all 0. This is equivalent to a capture unit corresponding to a read operation in the preset test algorithm. Accordingly, when a fault is tested when executing the data comparison operation corresponding to a read operation, the corresponding capture unit is controlled to capture 1, and other capture units are captured 0. In this way, the position of 1 in the single fault characteristic value can distinguish the execution order of the data comparison operation tested for the fault, and the position of 1 in the single fault characteristic value captured by the target comparison operation can specifically represent the execution order of the target comparison operation.

[0050] In an embodiment of the present invention, by correspondingly setting M capture units in the fault capture circuit, the target capture unit corresponding to the target comparison operation is controlled to capture the first preset value, and the other capture units are controlled to capture the second preset value, so that a single fault characteristic value for characterizing the execution order of the target comparison operation can be obtained, and the efficiency of obtaining the single fault characteristic value is relatively high.

[0051] Optionally, the fault capture circuit in the embodiment of the present invention further includes a signal generating circuit, wherein the test circuit is connected to the signal generating circuit. Accordingly, the embodiment of the present invention may further include:

[0052] Step S21: When the comparison result indicates that the unit under test has a fault, the test circuit inputs an execution phase signal, an operation sequence signal and a fault indication signal to the signal generating circuit; the execution phase signal is used to characterize the execution sequence of the currently executed algorithm phase, and the operation sequence signal is used to characterize the execution sequence of the currently executed operation.

[0053] Correspondingly, the target capture unit and other capture units in the fault capture circuit respectively capture the first preset value and the second preset value, which may specifically include:

[0054] Step 1021A, the signal generating circuit generates control signals for the target capture unit and the other capture units based on the fault indication signal, the execution stage signal and the operation order signal, so as to control the target capture unit and the other capture units to capture the first preset value and the second preset value respectively.

[0055] Among them, the fault indication signal can be a failure signal. The failure signal can be specifically output by a test comparator in the test circuit. When the failure signal takes the value of 1, it can indicate that the data read this time is different from the reference data, and a fault is detected in the test. Specifically, during the MBIST execution process, after executing the data comparison operation once, if the comparison result indicates that the unit under test has a fault, then failure=1 and hold=1 can be controlled. The execution stage signal can be a tstate signal, and the operation order signal can be an rwstate signal. The specific value of the tstate signal can indicate the execution order of the currently executed algorithm stage, that is, it indicates which algorithm stage the currently executed algorithm stage is in the preset test algorithm. The specific value of the rwstate signal can indicate the execution order of the currently executed operation, that is, it indicates which operation the currently executed operation is in the currently executed algorithm stage. In this way, based on the tstate signal and the rwstate signal, it can be determined which data comparison operation is currently executed, that is, it can be determined which read operation in the preset test algorithm identifies the current fault. The specific bit widths of the tstate signal and the rwstate signal can be set according to the number of algorithm stages included in the preset test algorithm and the maximum number of operations included in the algorithm stage. The bit width of the tstate signal can be the minimum bit width required to represent the number of algorithm stages, and the bit width of the rwstate signal can be the minimum bit width required to represent the maximum number of operations. Exemplarily, assuming that the preset test algorithm includes 10 algorithm stages, the bit width of the tstate signal can be set to 4 bits, and accordingly, the tstate signal can be represented as tstate[3:0]. Assuming that an algorithm stage in the preset test algorithm includes at most 3 read / write operations, the bit width of the rwstate signal can be set to 2 bits, and accordingly, the rwstate signal can be represented as rwstate[1:0].

[0056] Furthermore, the signal generating circuit can determine the capture unit corresponding to the data comparison operation of the currently tested fault among the M capture units based on the fault indication signal, the execution stage signal and the operation order signal, as the target capture unit, and then generate control signals for the target capture unit and other capture units respectively, so as to control the target capture unit and other capture units to capture the first preset value and the second preset value respectively.

[0057] In an embodiment of the present invention, the test circuit inputs an execution phase signal, an operation sequence signal, and a fault indication signal indicating the existence of a fault into the signal generating circuit, that is, the signal generating circuit can be controlled to generate control signals for the target capture unit and other capture units respectively based on the fault indication signal, the execution phase signal, and the operation sequence signal, thereby controlling the target capture unit and other capture units to respectively capture the first preset value and the second preset value.

[0058] Optionally, in an embodiment of the present invention, when the comparison result indicates that the unit under test has a fault, the test circuit can enable the numerical hold signal of the M capture units. Accordingly, after generating the single fault characteristic value corresponding to the target comparison operation, the following operation is performed: remove the single fault characteristic value. Specifically, the single fault characteristic value can be removed to the analysis component. The analysis component performs an operation of identifying the fault type of the unit under test based on all single fault characteristic values. Among them, the analysis component can be a processing unit in a chip. By removing the single fault characteristic value, it is convenient to identify the fault type based on the single fault characteristic value in the subsequent process. Among them, the numerical hold signal can be a hold signal, and the hold signal can also be called an internal state hold signal. Enabling the numerical hold signal can refer to setting hold=1. When the hold signal takes a value of 0, the numerical hold signal does not work. When the hold signal takes a value of 1, the value of the internal register in the capture unit can be controlled to remain unchanged, ensuring that the value captured by the capture unit will not be modified, so that the captured value of the capture unit can be accurately removed. Accordingly, after all the captured values ​​of the capture units are removed, that is, after the single fault characteristic value is removed, the hold signal value may be set to 0, so that subsequent test operations can be continued.

[0059] Optionally, the generating of control signals for the target capture unit and the other capture units based on the fault indication signal, the execution stage signal and the operation order signal may specifically include:

[0060] Step 1021A1, based on the fault indication signal, the execution stage signal and the operation order signal, determine the operation order of the read operation corresponding to the target comparison operation in the M read operations involved in the preset test algorithm as the execution order of the target comparison operation.

[0061] Step 1021A2: determine the capture unit corresponding to the execution order of the target comparison operation as the target capture unit.

[0062] Step 1021A3, generate a first control signal for the target capture unit, and generate a second control signal for each of the other capture units; the first control signal is used to control the capture unit to capture the first preset value, and the second control signal is used to control the capture unit to capture the second preset value.

[0063] Specifically, the signal generating circuit can determine the execution order of the target comparison operation according to the value of the execution stage signal and the value of the operation order signal when the fault indication signal indicates the presence of a fault, that is, when the fault indication signal is equal to 1. Specifically, it is possible to first determine which algorithm stage the currently executed algorithm stage is in the preset test algorithm according to the value of the execution stage signal. Assuming that the value of the execution stage signal is j, it can be determined that the currently executed algorithm stage is the jth algorithm stage in the preset test algorithm. It is possible to determine which operation in the currently executed algorithm stage is based on the value of the operation order signal when the currently executed operation is being determined. Assuming that the value of the operation order signal is k, it can be determined that the currently executed operation is the kth operation in the jth algorithm stage. Wherein, j represents the algorithm stage identifier, and k represents the operation order identifier within the algorithm stage.

[0064] Accordingly, the operation order x of the corresponding read operation can be found from the preset correspondence file based on j and k. The correspondence file may define the operation order of each read operation in the preset test algorithm and the algorithm stage identifier of the algorithm stage to which the read operation belongs and the operation order identifier within the algorithm stage to which it belongs. Accordingly, x may indicate that the kth operation in the jth algorithm stage is the xth read operation among the M read operations involved in the preset test algorithm. Accordingly, x is the operation order of the read operation corresponding to the target comparison operation among the M read operations involved in the preset test algorithm. The capture unit corresponding to the xth data comparison operation may be determined as the target capture unit, that is, the xth capture unit may be determined as the target capture unit. A first control signal is generated for the xth capture unit and input to the xth capture unit, thereby controlling the xth capture unit to capture 1, and a second control signal is generated for the other capture units and input to the other capture units, thereby controlling the other capture units to capture 0. Accordingly, the value of the x-th signature bit (signature[x-1]) corresponding to the subsequent x-th capture unit is set to 1, and the values ​​of the other signature bits except signature[x-1] are all set to 0.

[0065] Among them, the control signal can be expressed as state, the first control signal can be a signal of state=1, and the second control signal can be a signal of state=0. The specific value of State is determined by tstate, rwstate and failure. Assuming tstate=0, rwstate=1 and failure=1, failure=1 can indicate that the current read operation has identified a fault. Accordingly, the operation order of the second operation in the first algorithm stage among the 13 read operations involved in the preset test algorithm can be determined based on tstate=0 and rwstate=1. Exemplarily, it is assumed that the second operation in the first algorithm stage is the first read operation involved in the preset test algorithm. Then the state of the first capture unit can be set to 1, and the state of other capture units can be set to 0. Accordingly, the single fault characteristic value signature[12:0] generated by the fault capture circuit is: 0000000000001. In an embodiment of the present invention, the test circuit determines the operation order of the read operation corresponding to the target comparison operation in the M read operations involved in the preset test algorithm based on the fault indication signal, the execution stage signal and the operation order signal as the execution order of the target comparison operation. The capture unit corresponding to the execution order of the target comparison operation is determined as the target capture unit, and a first control signal is generated for the target capture unit, and a second control signal is generated for each other capture unit. In this way, the target capture unit and other capture units can be accurately controlled to capture the first preset value and the second preset value respectively, so that the single fault feature can accurately characterize the number of read operations to identify the fault.

[0066] For example, the comparison results of the data comparison operations corresponding to the 1st to 13th read operations indicate that the unit under test has a fault, that is, the 1st to 13th read operations identify a fault. When a fault is identified in each read operation, the values ​​of tstate, rwstate, and failure input to the signal generation circuit, and the single fault characteristic value finally obtained can be shown in the following Table 1:

[0067]

[0068]

[0069] Table 1

[0070] Optionally, the identifying the fault type of the unit under test based on all the single fault characteristic values ​​may specifically include:

[0071] Step 1031: Generate a target fault characteristic value corresponding to the current test process based on all the single fault characteristic values; the target fault characteristic value is used to characterize the execution order of all data comparison operations that test the fault in the current test process.

[0072] Step 1032: Based on the target fault feature value and the fault dictionary of the preset test algorithm, determine the fault type represented by the target fault feature value as the fault type of the unit under test; the fault dictionary includes different fault types and their corresponding fault feature values, and the fault feature value corresponding to the fault type is used to represent: when the fault type exists, the execution order of all data comparison operations corresponding to the preset test algorithm to the fault.

[0073] Specifically, each captured single fault characteristic value can represent that the comparison result of a certain data comparison operation performed in this test process represents that the unit under test has a fault, that is, it represents that a certain read operation can identify the fault. Therefore, all single fault characteristic values ​​can be summarized to obtain a target fault characteristic value, based on which all comparison results in this test process represent the data comparison operations that represent the existence of a fault in the unit under test, that is, based on the target fault characteristic value, all read operations that can identify faults in this test process can be known.

[0074] In an embodiment of the present invention, the diagnostic resolution of each alternative test algorithm can be determined based on a preset analysis script. The alternative test algorithm can be a test algorithm for testing a memory. Exemplarily, the preset analysis script can count the repetition rate of fault feature values ​​in the fault dictionary of the alternative test algorithm. The diagnostic resolution is generated for each alternative test algorithm in a manner that the diagnostic resolution is positively correlated with the repetition rate. The higher the repetition rate, the higher the proportion of the same fault feature values ​​corresponding to different fault types in the fault dictionary, and the higher the difficulty in distinguishing different fault types based on the alternative test algorithm. Therefore, the diagnostic resolution is lower. Then, the alternative test algorithm with the highest diagnostic resolution can be determined as the preset test algorithm. In the case where there are multiple alternative test algorithms with the highest diagnostic resolution, the alternative test algorithm with the smallest algorithm complexity and / or the smallest required test time can be selected as the preset test algorithm among the multiple alternative test algorithms with the highest diagnostic resolution.

[0075] Optionally, the preset test algorithm in the embodiment of the present invention may be a March19N test algorithm. Among them, the March19N test algorithm is an algorithm in the memory March test algorithm. Since the March19N test algorithm can distinguish a variety of fault types, for example, all fixed faults, conversion faults, coupling faults, fixed open circuit faults and address decoding faults. And there are differences in the fault characteristic values ​​corresponding to different fault types in the March19N test algorithm, that is, the fault characteristic values ​​corresponding to different fault types are different. Therefore, by using the March19N test algorithm as the preset test algorithm, a high fault identification accuracy can be ensured. At the same time, the algorithm complexity of the March19N test algorithm is relatively small, and the required test time is relatively short. Therefore, using the March19N test algorithm as the preset test algorithm can reduce the test time cost.

[0076] Further, the fault dictionary of the preset test algorithm can be obtained by analyzing each fault type separately according to the preset test algorithm. The fault characteristic value corresponding to the fault type in the fault dictionary can specifically represent the execution order of all data comparison operations that can test the fault in a test process based on the preset test algorithm when the fault type exists. Exemplarily, for any fault type, the fault of the fault type can be injected into the preset storage unit in the memory in advance to simulate the fault of the fault type. Among them, the preset storage unit can be a storage unit that does not have a fault itself, and the injected fault refers to controlling the storage unit to show the fault phenomenon that occurs when the fault type exists according to the fault phenomenon represented by the fault type. For example, for a stuck-at 0 fault, the bit corresponding to the preset storage unit can be forced to 0, so that no matter whether 0 or 1 is written, the data finally read out is 0, and other bits are not affected, so that the storage unit shows the fault phenomenon of the stuck-at 0 fault.

[0077] Then, the preset storage unit can be tested according to the preset test algorithm. Specifically, each time a fault occurs (i.e., a comparison result occurs that indicates that the preset storage unit has a fault), the operation order of the currently executed read operation is recorded once. After the preset test algorithm is executed (i.e., all data comparison operations corresponding to the preset test algorithm are executed), according to the operation order of all recorded read operations, the initial fault characteristic value of M bits and the value of the characteristic bit corresponding to the operation order of each read operation are set to the first preset value in sequence, and the other characteristic bits are set to the second preset value, so as to obtain the fault characteristic value corresponding to the injected fault type. Among them, the value of each characteristic bit in the initial fault characteristic value can be empty or 1. For example, assuming that for the Stuck-at 0 fault, the data read by the 2nd, 6th-8th, 12th-13th read operations are different from the reference data, then the operation order of all recorded read operations is: 2, 6, 7, 8, 12, 13 respectively. Accordingly, the values ​​of the 2nd, 6th-8th, 12th-13th characteristic bits can be set to 1, and the values ​​of other characteristic bits can be set to 0, thereby obtaining the fault characteristic value corresponding to the Stuck-at0 fault: 0100011100011. Furthermore, after obtaining the fault characteristic values ​​corresponding to all fault types, each fault type and the fault characteristic value corresponding to each fault type can be stored correspondingly, thereby obtaining the fault dictionary of the preset test algorithm. Among them, the fault type in the fault dictionary is represented by the indicator of the fault type. For example, taking the preset test algorithm as the March19N test algorithm as an example, the fault dictionary can be shown in Table 2 below:

[0078]

[0079]

[0080] Table 2

[0081] Furthermore, the target fault feature value can be compared with each fault feature value in the fault dictionary. Then, the fault type corresponding to the fault feature value that is consistent with the target fault feature value is obtained as the fault type represented by the target fault feature value. For example, assuming that the target fault feature value is 0100011100011, SAF0 can be obtained as the fault type represented by the target fault feature value after comparison. Among them, SAF0 is specifically used to represent the Stuck-at 0 fault, and SAF0 is the representation symbol of the Stuck-at 0 fault.

[0082] In an embodiment of the present invention, a target fault characteristic value corresponding to this test process is first generated based on all single fault characteristic values. By combining the target fault characteristic value and the fault dictionary of the preset test algorithm, the fault type of the unit under test can be identified, and the efficiency of fault type determination is relatively high. And because the target fault characteristic value can characterize the execution order of all data comparison operations that test the fault in this test process, therefore, based on the target fault characteristic value, it can be known in this test process which data comparison operations have comparison results that characterize the existence of a fault in the unit under test. Based on the foregoing description, it can be known that for any type of fault that can be distinguished by the preset test algorithm, in a test process implemented by executing the preset test algorithm, there will be a specific number of data comparison operations whose comparison results characterize the existence of a fault in the unit under test. Therefore, the fault type can be determined more accurately based on the target fault characteristic value.

[0083] Optionally, the above-mentioned generating a target fault characteristic value corresponding to the current test process based on all the single fault characteristic values ​​includes:

[0084] Step 1031a: perform an XOR operation on all the single fault characteristic values ​​to obtain a first fault characteristic value.

[0085] Step 1031b: If the sorting method of the characteristic bits in the first fault characteristic value is consistent with the target sorting method, the first fault characteristic value is directly determined as the target fault characteristic value; the target sorting method is the sorting method of the characteristic bits in the fault characteristic value in the fault dictionary.

[0086] Step 1031c: If the ordering method of the characteristic bits in the first fault characteristic value is inconsistent with the target ordering method, the characteristic values ​​in the first fault characteristic value are rearranged according to the target ordering method to obtain the target fault characteristic value.

[0087] In an embodiment of the present invention, an XOR operation is first performed on all single fault characteristic values ​​to obtain a first fault characteristic value. Specifically, each characteristic bit in the single fault characteristic value includes two values: 0 and 1. There is a characteristic bit with a value of 1 in a single fault characteristic value, and the position of the characteristic bit of different single fault characteristic values ​​is different. The XOR operation is a bit operation. After the XOR operation, if the values ​​of the same bit are the same, 0 is generated for the corresponding characteristic bit, and if the values ​​of the same bit are different, 1 is generated for the corresponding characteristic bit. In this way, the XOR operation can make the first fault characteristic value finally obtained include the same number of 1s for the single fault characteristic values, and the position of each 1 corresponds to the position of the characteristic bit with a value of 1 in all single fault characteristic values. The characteristic bit of 1 indicates all read operations that have identified faults in the preset test algorithm, and the characteristic bit of 0 indicates all read operations that have not identified faults in the preset test algorithm. Accordingly, the first fault characteristic value can represent the data comparison operation that characterizes that all comparison results in this test process characterize the existence of faults in the unit under test.

[0088] Furthermore, the ordering method of the characteristic bits in the fault characteristic value in the fault dictionary can be preset as needed. For example, the target ordering method can be to arrange the 1st to M characteristic bits corresponding to the 1st to Mth data comparison operations in sequence from left to right. That is, in the target ordering method, the Xth characteristic bit from left to right corresponds to the Xth data comparison operation. Since the order of the characteristic values ​​of each characteristic bit in the single fault characteristic value is removed, it may be different from the target ordering method. Therefore, the ordering method of the characteristic bits in the first fault characteristic value obtained by the XOR operation will be inconsistent with the target ordering method. For example, when removing the single fault characteristic value, the value captured by the capture unit corresponding to the last data comparison operation is removed first, that is, the values ​​captured by the M capture units are removed in sequence in the order of Mth to 1st as the single fault characteristic value. In this way, the ordering method of the characteristic bits in the first fault characteristic value will be opposite to the target ordering method. For example, assuming that in this test process, the data read by the 2nd, 6th-8th, 12th-13th read operations are different from the reference data, accordingly, the following 6 single fault characteristic values ​​can be removed in this test process: 0000000000010 0000000100000 0000001000000 0000010000000 0100000000000 1000000000000

[0095] Performing an XOR operation on these six single fault characteristic values ​​can obtain the first fault characteristic value: 1100011100010. The sorting method of the first fault characteristic value is inconsistent with the target sorting method, and the sorting method of the first fault characteristic value is opposite to the target sorting method. Specifically, the first fault characteristic value is to arrange the 1st to M characteristic bits corresponding to the 1st to Mth data comparison operations in sequence from right to left, while the target sorting method is to arrange the 1st to M characteristic bits corresponding to the 1st to Mth data comparison operations in sequence from left to right. Therefore, the characteristic values ​​in the first fault characteristic value can be rearranged according to the target sorting method, so that the sorting method of the characteristic bits in the first fault characteristic value is consistent with the target sorting method. Exemplarily, the first fault characteristic value can be negated to obtain the target fault characteristic value. Wherein, negation can refer to setting the value of the i-th characteristic bit from left to right in the first fault characteristic value to the value of the i-th characteristic bit from right to left. Wherein, the value of i is 1 to M. Corresponding to the above example, the target fault characteristic value obtained after negation is: 0100011100011.

[0096] Of course, if the values ​​captured by the M capture units are removed in sequence from 1st to Mth as single fault characteristic values, then the sorting method of the characteristic bits in the first fault characteristic value is consistent with the target sorting method. Accordingly, the first fault characteristic value can be directly determined as the target fault characteristic value.

[0097] In an embodiment of the present invention, an XOR operation is first performed on all single fault feature values ​​to obtain a first fault feature value. Then, when the ordering method of the feature bits in the first fault feature value is consistent with the target ordering method, the first fault feature value is directly determined as the target fault feature value; the target ordering method is the ordering method of the feature bits in the fault feature value in the fault dictionary. When the ordering method of the feature bits in the first fault feature value is inconsistent with the target ordering method, the feature values ​​in the first fault feature value are rearranged according to the target ordering method to obtain the target fault feature value. In this way, it can be ensured that the ordering method of the feature bits in the target fault feature value is consistent with the target ordering method, avoiding the problem of failed search in the fault dictionary due to inconsistent ordering methods.

[0098] Optionally, in an embodiment of the present invention, when it is detected that the comparison result indicates that the unit under test has a fault, the fault address and fault data bit of the unit under test can be obtained; the fault address, the fault data bit and the single fault characteristic value are used as diagnostic information. Accordingly, the fault position of the current fault can be located based on the fault address and the fault data bit, and the fault type can be identified based on the single fault characteristic value, thereby realizing the built-in self-diagnosis of the memory. Since a memory is equivalent to a storage matrix composed of multiple storage units, when performing a memory test, multiple storage units in each memory are usually tested. In an embodiment of the present invention, the fault address can be used to indicate a faulty memory, and the fault data bit can be used to indicate a faulty storage unit in the memory. Therefore, based on the fault location information composed of the fault address and the fault data bit, the unit under test that has a fault in the current memory under test can be uniquely located.

[0099] Among them, the diagnostic information may be information that needs to be observed, and the diagnostic information may be collected on demand. For example, the diagnostic information may also include the current algorithm operation steps, etc. The diagnostic information may also be referred to as fault detection information. The test controller of the test circuit may include a diagnostic chain composed of test registers, and the test controller may collect diagnostic information of the unit under test based on the diagnostic chain. Among them, different registers may be selected to be added to the diagnostic chain in advance according to the fault location requirements, so that the diagnostic chain can collect diagnostic information of corresponding accuracy. For example, a fault address register and a fault bit register may be added. Specifically, the diagnostic chain may include a fault address register and a fault bit register, and the fault address register and the fault bit register are respectively used to collect and obtain the fault address and fault data bit of the unit under test.

[0100] Among them, the test circuit may include an address record register, and the address record register will traverse from 0 to the highest bit of the address value, thereby realizing the traversal of the storage unit in the memory. In the embodiment of the present invention, the storage unit is distinguished based on the address, and each address corresponds to a number of storage units. In the memory, an address may correspond to multiple words (Word), and a word is a data unit composed of multiple bits (bit). Accordingly, the address that can point to a certain storage unit can be represented in the form of Addr[][]. The first [] in Addr[][] can represent the selected word, and the second [] can represent the selected bit. Exemplarily, Addr[0][1] can represent the storage unit corresponding to the 4th bit in the first word. The address recorded by the address record register is the address in the above Test_addr. In the event of a fault (the comparison result indicates that the unit under test has a fault), the address record register stores the address and data bit of the storage unit that currently has a fault. Accordingly, the current value of the address record register can be moved into the fault address register and the fault bit register.

[0101] Furthermore, the diagnostic information in the diagnostic chain can be output through the test data output (TDO) port of the joint test action group (JTAG). Exemplarily, the test controller can be controlled based on custom instructions to output the diagnostic information in the diagnostic chain to the analysis component in the chip for analysis. Specifically, the analysis component can determine the storage location indicated by the fault address and the fault data bit as the fault location of the current fault, and determine the fault type of the unit under test based on the single fault characteristic value and the fault dictionary of the preset test algorithm. In the fault diagnosis mechanism provided by the embodiment of the present invention, by determining the fault location and the fault type, it is possible to locate the fault of the unit under test with a fault and identify the fault type, thereby providing sufficient fault diagnosis results for subsequent fault repair, so that the fault repair personnel can make quick and correct remedial measures.

[0102] The fault diagnosis method provided by the embodiment of the present invention is described below in conjunction with a simulation example. For example, to implement the simulation, a stuck-at 0 fault can be injected into Addr[0][1] first. By injecting the stuck-at 0 fault, no matter whether the storage unit at the address of Addr[0][1] performs a write 0 operation or a write 1 operation, the value read from Addr[0][1] always remains 0. The storage unit at the address of Addr[0][1] is used as the unit under test. According to the data comparison operation corresponding to the preset test algorithm, the data comparison operation is performed on the unit under test in sequence. After performing a data comparison operation, if a fault is detected, failure=1 and hold=1 are set, and at the same time, a tstate signal indicating that the currently executed algorithm stage is the number of algorithm stages in the preset test algorithm, and an rwstate signal indicating that the currently executed operation is the number of operations in the currently executed algorithm stage are input to the signal generation circuit. The signal generation circuit controls the capture unit to capture the value according to the state signal. During the hold=1 period, the fault data is held and the diagnostic data can be removed. The diagnostic data may include the above-mentioned fault address, fault data bit and single fault characteristic value. The diagnostic data shifted out each time may be packaged with the same start bit and the same end bit. For example, the diagnostic data shifted out each time may be packaged with the start bit 2'b11 and the end bit 3'b110. In this way, it is convenient to align the diagnostic data shifted out multiple times later.

[0103] Figure 3 is a schematic diagram of a simulation waveform provided by an embodiment of the present invention, such as Figure 3 As shown in the figure, the multi-bit data (signature[12:0], Error_bit[127:0], Addr[5:0] and Algo_state[3:0]) are all represented by decimal numbers. Based on the simulation waveform diagram, the execution state of the test algorithm that detects the fault and the retention process of the fault data can be observed. Among them, Algo_state[3:0] represents the algorithm stage, Bist_end represents the end signal, Error_bit[127:0] represents the fault data bit, and Addr[5:0] represents the address. When Algo_state[3:0] is 0, it represents the ready to start state. After that, the value of Algo_state[3:0] indicates the number of algorithm stages of the preset test algorithm to be executed. When the last algorithm stage is completed, the value of Algo_state[3:0] can become 11 ( Figure 3 ), represents the state of MBIST termination in turn. After all operations of the preset test algorithm are completed (i.e., all algorithm stages are completed), MBIST end signal Bist_end is pulled high, representing that the MBIST operation is completely completed.

[0104] When a fault is detected, that is, the comparison result of the currently executed data comparison operation indicates that the unit under test has a fault (that is, the data read by the currently executed read operation is different from the reference data), Figure 3 In the failure signal, the value is 1. Correspondingly, the hold signal becomes 1, and the diagnosis can be removed during the interval in which the hold signal remains 1. After removing the removed diagnosis, the hold signal becomes 0, and the next operation in the preset test algorithm can be continued. Figure 3 , in the 3rd, 5th, 6th, 7th, 9th and 10th algorithm stages of the preset test algorithm, there are 6 cases in which the data read by the currently executed read operation is different from the reference data. Accordingly, the diagnostic data finally removed can be shown in the following Table 3:

[0105] Start position Addr Error_bit signature End bit 11 000000 128’d2 0000000000010 110 11 000000 128’d2 0000000100000 110 11 000000 128’d2 0000001000000 110 11 000000 128’d2 0000010000000 110 11 000000 128’d2 0100000000000 110 11 000000 128’d2 1000000000000 110

[0106] Among them, the start bit and the end bit respectively represent the start bit and the end bit used when the diagnostic data is shifted out, and Addr, Error_bit and signature respectively represent the above-mentioned fault address, fault data bit and single fault characteristic value. 128'd2 is used to indicate that the second bit from the right to the left in the 128-bit data corresponding to the tested address is 1. Correspondingly, corresponding to these 6 groups of diagnostic data, Addr is 0 and Error_bit is 1. Since Addr is 0 and Error_bit is 1, it is possible to determine the fault location Addr[0][1] where the current fault occurs, that is, it is possible to determine that the storage unit corresponding to Addr[0][1] fails. Further, performing an XOR operation on the signature in these 6 groups of diagnostic data can obtain the first fault characteristic value: 1100011100010. Since the value captured by the capture unit corresponding to the last data comparison operation is first shifted out when the single fault characteristic value is currently shifted out, the target fault characteristic value can be obtained by inverting the first fault characteristic value: 0100011100011. Next, the target fault characteristic value: 0100011100011 can be compared with each fault characteristic value in the fault dictionary to determine the fault type represented by the target fault characteristic value. For example, for the above Table 2, it can be obtained that the fault type represented by the target fault characteristic value: 0100011100011 is: SAF0, and SAF0 represents a Stuck-at 0 fault. Therefore, it can be determined that the fault diagnosis method can accurately identify the fault type.

[0107] In an embodiment of the present invention, for any fault, it can be determined which read operations in the preset test algorithm identify the fault, and then all single fault characteristic values ​​in a test process can be obtained. A test process can correspond to a detection process of a certain type of fault of a unit under test using a preset test algorithm, and in this detection process, all algorithm steps defined by the preset test algorithm are executed (that is, all operations in all algorithm stages of the preset test algorithm are executed). Accordingly, after all data comparison operations are executed, based on all single fault characteristic values ​​obtained in this test process, the target fault characteristic value corresponding to the same fault can be obtained. In this way, a series of operations of distinguishing faults and then analyzing their fault characteristic values ​​according to the algorithm execution state can be avoided.

[0108] In the embodiment of the present invention, the test circuit and the fault capture circuit can be integrated into a chip as a circuit. Figure 4 , shows a circuit diagram of a fault diagnosis circuit provided by an embodiment of the present invention, the fault diagnosis circuit includes the above-mentioned test circuit and a fault capture circuit, such as Figure 4 As shown, the test circuit 01 can be connected to the fault capture circuit 02. The test circuit 01 can also be connected to the memory to facilitate testing the memory. In the embodiment of the present invention, a characteristic value capture function can be added to the test controller in the test circuit 01, so that the test controller can control the fault capture circuit to capture the fault characteristic value accordingly, thereby collecting the required fault data. Specifically, the test circuit 01 is used to perform the data comparison operation on the units under test in the memory in sequence according to the data comparison operation corresponding to the preset test algorithm;

[0109] The fault capture circuit test circuit 02 is used to generate a single fault characteristic value corresponding to a target comparison operation after performing the data comparison operation once, if the comparison result indicates that the unit under test has a fault; the target comparison operation is the data comparison operation whose comparison result indicates that the unit under test has a fault, and the single fault characteristic value is used to indicate identification information of the target comparison operation;

[0110] After the test circuit 01 executes all data comparison operations corresponding to the preset test algorithm, the single fault characteristic value is executed by the analysis component: based on all the single fault characteristic values, the fault type of the unit under test is identified. The analysis component may be other processing units on the chip.

[0111] Furthermore, the fault capture circuit may include a signal generating circuit and M capture units, and the M capture units correspond one-to-one to M data comparison operations. The preset test algorithm corresponds to M data comparison operations, and the single fault characteristic value includes characteristic bits corresponding one-to-one to the M data comparison operations, and the order of the characteristic bits corresponding to the data comparison operations in the single fault characteristic value is the same as the execution order of the data comparison operations. Among them, the fault diagnosis circuit can achieve the same technical effect as the aforementioned fault diagnosis method, which will not be repeated here.

[0112] Figure 5 is a schematic diagram of another fault diagnosis circuit provided by an embodiment of the present invention, such as Figure 5 As shown, the structure of the test circuit can be the same as that Figure 2 The structures are consistent. The test circuit inputs the execution phase signal tstate[3:0], the operation order signal rwstate[1:0], the fault indication signal failure and the value holding signal hold to the fault capture circuit.

[0113] Further, the test circuit may include an execution phase signal output terminal, an operation sequence signal output terminal, and a fault indication signal output terminal for outputting an execution phase signal, an operation sequence signal, and a fault indication signal to the signal generation circuit, the signal generation circuit includes a signal input terminal for receiving an execution phase signal, an operation sequence signal, and a fault indication signal, the signal generation circuit includes M control signal output terminals, the capture unit includes a control signal input terminal, one control signal output terminal is connected to a control signal input terminal of a capture unit, that is, the M control signal output terminals are respectively connected to the control signal input terminals of the M capture units. Among them, a control signal output terminal of the signal generation circuit is used to input a control signal to the connected control signal input terminal. The signal generation circuit specifically generates a control signal based on the fault indication signal, the execution phase signal, and the operation sequence signal. Among them, the control signal may include the aforementioned first control signal and the second control signal.

[0114] The test circuit further includes a value holding signal output terminal for outputting a value holding signal to the signal generating circuit, and the capture unit further includes a value holding signal input terminal for receiving the value holding signal. The capture unit can receive the value holding signal input by the test circuit based on the value holding signal input terminal. The capture unit further includes an output terminal for outputting the captured value.

[0115] Take M=13 as an example, Figure 6 is a schematic diagram of a fault capture circuit provided by an embodiment of the present invention, such as Figure 6As shown, the fault capture circuit includes a signal generation circuit and 13 capture units (capture unit [0], capture unit [1], ..., capture unit

[12] ). The input of the fault capture circuit includes the execution phase signal tstate[3:0], the operation order signal rwstate[1:0] and the fault indication signal failure input to the signal generation circuit. The signal generation circuit can provide control signals (i.e., state signals) to the 13 capture units based on these input signals. The signal generation circuit can be a combinational circuit, which has the function of implementing the above steps 1021A1 to 1021A3. The input of the fault capture circuit also includes the value holding signal hold input to each capture unit and the working clock signal bist_clk. The output of the fault capture circuit is a single fault characteristic value, which includes the value of the characteristic bits captured by each capture unit: signature[0], signature[1], ..., signature

[12] .

[0116] Furthermore, each capture unit has the same structure, and the capture unit may include a register and a multiplexer. The value hold signal input terminal is set on the multiplexer, and when the value hold signal input terminal inputs an enabled value hold signal, the multiplexer controls the value of the register in the capture unit to remain unchanged. Furthermore, the multiplexer also includes a 0 input terminal. After a fault is detected and the current diagnostic information is removed, the hold signal drops to 0. At this time, the multiplexer can AND the 0 input at the 0 input terminal with the state signal to make the value of the register become 0, thereby resetting the registers in all capture units to 0. Figure 7 is a schematic diagram of a capture unit provided by an embodiment of the present invention, such as Figure 7 As shown, for the capture unit [0], the capture unit includes a control signal input terminal D, a clock signal input terminal X, a value holding signal input terminal Y and an output terminal Q, and the value output by the output terminal Q is the characteristic value of the signature [0] characteristic bit (i.e., the first characteristic bit) in the single fault characteristic value. In the case of state = 1, the value of the register in the capture unit is set to 1, and the capture unit captures 1. Correspondingly, the output terminal Q can output 1, so that the characteristic value of the signature [0] characteristic bit is 1. At the same time, the multiplexer is connected to the input terminal D and the output terminal Q respectively, so that when the input multiplexer hold = 1, the value of the register in the capture unit is maintained as the captured value. For example, in the case of state = 1, by controlling hold = 1, the value of the register in the capture unit signature [0] can be maintained at 1.

[0117] Reference Figure 8, is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 8 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the memory fault diagnosis method of the above embodiment. The executable instructions can form a program.

[0118] An embodiment of the present invention provides a machine-readable medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the memory fault diagnosis method of the aforementioned embodiment.

[0119] An embodiment of the present invention provides a timing module, which includes a timing function register, and the timing function register is configured to support scan testing; the timing module is tested according to the fault diagnosis method of the memory of the above embodiment.

[0120] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0121] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0122] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0123] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0124] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0126] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0127] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0128] The above describes in detail a memory fault diagnosis method, a memory fault diagnosis circuit, an electronic device and one or more readable media provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for diagnosing a fault of a memory, characterized in that: Applied to a chip integrated with a test circuit and a fault capture circuit, the method comprises: The test circuit sequentially performs the data comparison operation on the units under test in the memory according to the data comparison operation corresponding to the preset test algorithm; After executing the data comparison operation once, the fault capture circuit generates a single fault characteristic value corresponding to a target comparison operation when the comparison result indicates that the unit under test has a fault; the target comparison operation is the data comparison operation whose comparison result indicates that the unit under test has a fault, and the single fault characteristic value is used to indicate identification information of the target comparison operation; After executing all data comparison operations corresponding to the preset test algorithm, the fault type of the unit under test is identified based on all the single fault characteristic values.

2. The method according to claim 1, characterized in that The identification information is used to indicate the execution order of the data comparison operations in this test process. The preset test algorithm corresponds to M data comparison operations. The single fault characteristic value includes characteristic bits that correspond one-to-one to the M data comparison operations. The order of the characteristic bits corresponding to the data comparison operations in the single fault characteristic value is the same as the execution order of the data comparison operations.

3. The method according to claim 2, characterized in that The fault capture circuit includes M capture units, and the M capture units correspond one-to-one to the M data comparison operations; The fault capture circuit generates a single fault characteristic value corresponding to a target comparison operation when the comparison result indicates that the unit under test has a fault, including: When the comparison result indicates that the unit under test has a fault, the target capture unit and other capture units in the fault capture circuit respectively capture a first preset value and a second preset value; the other capture units include capture units other than the target capture unit; the target capture unit is a capture unit corresponding to the target comparison operation, the first preset value constitutes a feature value of a feature bit corresponding to the target comparison operation, and the second preset value constitutes a feature value of other feature bits except the feature bit corresponding to the target comparison operation.

4. The method according to claim 3, characterized in that: The fault capture circuit further includes a signal generating circuit; the method further includes: In the case where the comparison result indicates that the unit under test has a fault, the test circuit inputs an execution phase signal, an operation sequence signal and a fault indication signal to the signal generation circuit; the execution phase signal is used to indicate the execution sequence of the currently executed algorithm phase, and the operation sequence signal is used to indicate the execution sequence of the currently executed operation; The target capture unit and other capture units in the fault capture circuit respectively capture the first preset value and the second preset value, including: The signal generating circuit generates control signals for the target capture unit and the other capture units respectively based on the fault indication signal, the execution stage signal and the operation order signal, so as to control the target capture unit and the other capture units to capture the first preset value and the second preset value respectively.

5. The method according to claim 4, characterized in that The generating control signals for the target capture unit and the other capture units respectively based on the fault indication signal, the execution stage signal and the operation order signal comprises: Based on the fault indication signal, the execution stage signal and the operation order signal, determining the operation order of the read operation corresponding to the target comparison operation in the M read operations involved in the preset test algorithm as the execution order of the target comparison operation; Determine the capture unit corresponding to the execution order of the target comparison operation as the target capture unit; A first control signal is generated for the target capture unit, and a second control signal is generated for each of the other capture units; the first control signal is used to control the capture unit to capture the first preset value, and the second control signal is used to control the capture unit to capture the second preset value.

6. The method according to any one of claims 1 to 5, characterized in that: The identifying the fault type of the unit under test based on all the single fault characteristic values ​​includes: Based on all the single fault characteristic values, a target fault characteristic value corresponding to the current test process is generated; the target fault characteristic value is used to characterize the execution order of all data comparison operations for the fault tested in the current test process; Based on the target fault characteristic value and the fault dictionary of the preset test algorithm, determining the fault type represented by the target fault characteristic value as the fault type of the unit under test; Among them, the fault dictionary includes different fault types and their corresponding fault characteristic values, and the fault characteristic values ​​corresponding to the fault types are used to characterize: when the fault types exist, the execution order of all data comparison operations corresponding to the preset test algorithm to the fault.

7. The method according to claim 6, characterized in that The generating, based on all the single fault characteristic values, a target fault characteristic value corresponding to the current test process includes: Performing an XOR operation on all the single fault characteristic values ​​to obtain a first fault characteristic value; If the sorting mode of the characteristic bits in the first fault characteristic value is consistent with the target sorting mode, the first fault characteristic value is directly determined as the target fault characteristic value; the target sorting mode is the sorting mode of the characteristic bits in the fault characteristic value in the fault dictionary; If the ordering method of the characteristic bits in the first fault characteristic value is inconsistent with the target ordering method, the characteristic values ​​in the first fault characteristic value are rearranged according to the target ordering method to obtain the target fault characteristic value.

8. A fault diagnosis circuit, characterized in that: The fault diagnosis circuit includes a test circuit and a fault capture circuit; The test circuit is used to perform the data comparison operation on the units under test in the memory in sequence according to the data comparison operation corresponding to the preset test algorithm; The fault capture circuit is used to generate a single fault characteristic value corresponding to a target comparison operation after performing the data comparison operation once, when the comparison result indicates that the unit under test has a fault; the target comparison operation is the data comparison operation whose comparison result indicates that the unit under test has a fault, and the single fault characteristic value is used to indicate identification information of the target comparison operation; After the test circuit executes all data comparison operations corresponding to the preset test algorithm, the single fault characteristic value analysis component executes the operation of identifying the fault type of the unit under test based on all the single fault characteristic values.

9. The circuit according to claim 8, characterized in that The preset test algorithm corresponds to M data comparison operations, the fault capture circuit includes a signal generating circuit and M capture units, the M capture units correspond one-to-one to the M data comparison operations; the single fault characteristic value includes characteristic bits corresponding one-to-one to the M data comparison operations, and the order of the characteristic bits corresponding to the data comparison operations in the single fault characteristic value is the same as the execution order of the data comparison operations.

10. The circuit according to claim 8, characterized in that The test circuit comprises an execution phase signal output terminal, an operation sequence signal output terminal and a fault indication signal output terminal for outputting an execution phase signal, an operation sequence signal and a fault indication signal to the signal generation circuit; The signal generating circuit comprises a signal input terminal for receiving the execution phase signal, the operation sequence signal and the fault indication signal, an execution phase signal input terminal, an operation sequence signal input terminal and a fault indication signal input terminal; The signal generating circuit comprises M control signal output terminals, and the capturing unit comprises a control signal input terminal; one of the control signal output terminals is connected to a control signal input terminal of the capturing unit.

11. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the method according to any one of claims 1 to 7.

12. One or more machine-readable media, characterized in that Instructions are stored thereon, which, when executed by one or more processors, cause the processors to perform the method according to any one of claims 1 to 7.

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