Agent receiving module verification system and method based on UVM verification platform

Abstract

The invention relates to a system and a method for verifying an agent receiving module based on a UVM (Universal Verification Module) verification platform, which support to use a design code module of the agent receiving module to be verified as a verification object by constructing a module-level agent receiving module verification system, and only need to integrate the agent receiving module as a design to be tested. Due to the fact that the whole electronic control unit chip or other design components do not need to be integrated, the system can start verification in the design stage of the current receiving module, verification intervention time is greatly advanced, and dependence conditions are reduced. Moreover, the system combines a random error generator to carry out random error injection, so that random correct data and error data can be generated, the error state in the agent protocol is effectively completed, the randomness and completeness of excitation of the agent receiving module are finally realized, and the verification quality of the agent receiving module is greatly improved.

Description

Technical Field

[0001] The invention belongs to the technical field of chip verification, and relates to a sent receiving module verification system and method based on a UVM verification platform. Background Art

[0002] The sent (single edge nibble transmission) protocol is a single-line data transmission protocol, which is currently widely used as a communication protocol between automotive sensors and electronic control units. The sent protocol can send frame data or packet data, and each frame of data consists of pulses of different widths. The sent module in the electronic control unit chip is usually the receiving end, and the receiving module must have the ability to receive and parse data packets and parse error information. The current verification technology for the sent receiving module is mainly: based on the entire electronic control unit chip, using an external sensor or an external sent protocol simulator to send the expected stimulus to the pad (i.e., the input / output part) of the electronic control unit chip, and then reading the data parsed by the sent receiving module through the CPU core, and checking whether it is consistent with the expected sent data to achieve the verification purpose.

[0003] However, the current verification technology for the sent receiving module needs to rely on the integration of the entire chip and the realization of other module functions, and the expected stimulus sent only contains all legal data and partially directed illegal data, resulting in a technical problem of low verification quality of the sent receiving module. Summary of the invention

[0004] In view of the problems existing in the above-mentioned traditional technology, the present invention proposes a sent receiving module verification system based on a UVM verification platform and a sent receiving module verification method based on the UVM verification platform, which can effectively improve the verification quality of the sent receiving module.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] On the one hand, a sent receiving module verification system based on a UVM verification platform is provided, comprising a sequence model, an input agent, a reference model, a scoreboard and a design to be tested, wherein the sequence model, the input agent, the reference model and the scoreboard are components based on the UVM verification platform, and the design to be tested is a design code module of a sent receiving module to be verified;

[0007] The sequence model is used to derive a target sequence for functional verification of a sent receiving module based on a basic sequence of a UVM verification platform and output it to an input agent. The input agent includes a driver and a random error generator. The driver is used to generate a data packet according to the target sequence through the random error generator and drive it to the interface of the design under test and a reference model. The random error generator is used to inject random errors into the data packet. The reference model is used to output expected results to a scoreboard according to the data packet. The design under test is used to output actual test results to a scoreboard according to the data packet. The scoreboard is used to compare the sent data and error status received in the expected result and the actual test result to obtain a verification result of the design under test.

[0008] In one of the embodiments, the data type of the target sequence includes a packet data type, a frame data type, or a frame data random error type in a sent protocol.

[0009] In one embodiment, the input agent collects the random completeness of the random error generator by means of functional coverage.

[0010] On the other hand, a sent receiving module verification method based on a UVM verification platform is also provided, which is applied to a sent receiving module verification system based on the UVM verification platform, wherein the sent receiving module verification system comprises a sequence model, an input agent, a reference model, a scoreboard and a design to be tested, wherein the sequence model, the input agent, the reference model and the scoreboard are components based on the UVM verification platform, and the design to be tested is a design code module of the sent receiving module to be verified;

[0011] The sequence model is used to derive a target sequence for functional verification of a sent receiving module based on a basic sequence of a UVM verification platform and output it to an input agent. The input agent includes a driver and a random error generator. The driver is used to generate a data packet according to the target sequence through the random error generator and drive it to the interface of the design to be tested and a reference model. The random error generator is used to perform random error injection on the data packet. The reference model is used to output an expected result to a scoreboard according to the data packet. The design to be tested is used to output an actual test result to a scoreboard according to the data packet. The scoreboard is used to compare the sent data and error status received in the expected result and the actual test result to obtain a verification result of the design to be tested.

[0012] The sent receiving module verification method based on the UVM verification platform comprises the following steps:

[0013] Power on and initialize the sent receiving module verification system;

[0014] The input agent generates the data signal of the sent protocol according to the target sequence output by the sequence model;

[0015] Using a random error generator to randomly inject errors into frames of data signals;

[0016] The reference model parses the data signal according to the sent protocol to obtain the expected sent data and error status as the expected result, and sends the expected result to the scoreboard;

[0017] The design to be tested analyzes the data signal to obtain the sent data and error status of the actual test as the actual test result, and sends the actual test result to the scoreboard;

[0018] The scoreboard compares the expected results with the actual test results to obtain the verification results of the design under test.

[0019] In one of the embodiments, the data type of the target sequence includes a packet data type, a frame data type, or a frame data random error type in a sent protocol.

[0020] In one embodiment, the sent receiving module verification method based on the UVM verification platform further includes the steps of:

[0021] The input agent collects the random completeness of the random error generator through functional coverage.

[0022] One of the above technical solutions has the following advantages and beneficial effects:

[0023] The sent receiving module verification system and method based on the UVM verification platform above supports the use of the design code module of the sent receiving module to be verified as the verification object by constructing a module-level sent receiving module verification system, and no longer needs to integrate the entire chip as the design to be tested. Therefore, it is only necessary to integrate the sent receiving module itself as the design to be tested, thereby reducing the dependency of the design to be tested and executing the verifiable nodes of the design to be tested in advance. Since it is no longer necessary to integrate the entire electronic control unit chip or other design components, the above system can start verification in the design stage of the sent receiving module, greatly advancing the verification intervention time and reducing the dependency conditions. Moreover, the system combines a random error generator to perform random error injection, thereby being able to generate random correct data and error data, so as to effectively complete the error state in the sent protocol, and finally realize the randomness and completeness of the excitation of the sent receiving module, greatly improving the verification quality of the sent receiving module. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 It is a structural flowchart of a sent receiving module verification system based on a UVM verification platform in one embodiment;

[0026] Figure 2 A schematic flow chart of a sent receiving module verification method based on a UVM verification platform in one embodiment;

[0027] Figure 3 The present invention is a flowchart of an implementation example of a sent receiving module verification method based on a UVM verification platform in an embodiment. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0029] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0030] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0031] The current verification technology for the sent receiving module requires the design code of the entire electronic control unit chip, and relies on the integration of the entire chip and the implementation of other module functions. For example, the CPU is needed to read data, and the path between the pad of the electronic control unit chip and the sent receiving module must be complete; at the same time, the sending of the stimulus also depends on the host computer, etc. These shortcomings will lead to a significant reliance on the verification of the sent receiving module, causing its verification stage to be postponed and increasing the risk of project delivery.

[0032] In addition, in the current verification technology for the sent receiving module, when sending preset data to the sent receiving module, its preset is limited, that is, it only contains all legal data and partially directional illegal data. However, the sent receiving module can parse various error signals of the protocol in each frame and generate corresponding error states. Therefore, it is necessary to have more random and complete error protocol stimuli sent to the sent receiving module. In order to overcome the above-mentioned shortcomings of verification dependence, postponement of the verification stage and incomplete protocol stimuli, the present application will provide a new technical solution as shown below.

[0033] In one embodiment, Figure 1 As shown, a sent receiving module verification system based on a UVM verification platform is provided, including a sequence model, an input agent, a reference model, a scoreboard and a design to be tested. The sequence model, the input agent, the reference model and the scoreboard are components based on the UVM verification platform. The design to be tested is a design code module (i.e., dut) of the sent receiving module to be verified. The sequence model is used to derive a target sequence for functional verification of the sent receiving module based on the basic sequence of the UVM verification platform and output it to the input agent. The input agent includes a driver and a random error producer, the driver is used to generate a data packet according to the target sequence through the random error producer to drive the interface and the reference model of the design to be tested, and the random error producer is used to inject random errors into the data packet. The reference model is used to output the expected result to the scoreboard according to the data packet, and the design to be tested is used to output the actual test result to the scoreboard according to the data packet. The scoreboard is used to compare the sent data and the error state received in the expected result and the actual test result to obtain the verification result of the design to be tested.

[0034] It can be understood that the design of each component in the sent receiving module verification system based on the UVM verification platform follows the existing UVM verification methodology. According to the verification of the sent receiving module to be verified, the component configuration of the corresponding function needs to be performed based on the UVM verification platform and the connection between the components, connectivity testing and other basic operations are completed to ensure that the data flow between the components during the verification process is normal.

[0035] Specifically, the verification object of the sent receiving module verification system based on UVM verification platform is the design code of sent receiving module, and there is no need to integrate the whole chip as the design to be tested. In the architecture of the sent receiving module verification system based on UVM verification platform, only the sent receiving module (coded dut) to be verified needs to be integrated, and there is no need to integrate the whole electronic control unit chip or other design components, therefore verification can be started in the design phase of sent receiving module, thereby greatly advancing the verification intervention time and reducing the dependent condition.

[0036] The input agent (i.e. component in_agent) in the sent receiving module verification system based on the UVM verification platform, the driver (i.e. component driver) therein drives the data signal line of the sent receiving module according to the data packet generated by the sequence model sequence (i.e. component Seq_base), to produce sent protocol data. Meanwhile, the driver here is sent to the interface of the design to be tested through a random error producer (i.e. component Gen_rand_err), so as to complete all error states in the sent protocol by means of random error injection, and overcome the shortcomings of the incomplete error incentive in the verification technology for the sent receiving module at present. The reference model (i.e. component rm) in the sent receiving module verification system based on the UVM verification platform, parses the data signal of the sent protocol as the design to be tested (dut), parses the sent (protocol) data and the error state in each frame data signal, and then sends to the scoreboard (i.e. component scb), compares the sent data and the error state received in the reference model (rm) and the design to be tested (dut) in the scoreboard, thereby realizing the verification of the design to be tested. Among them, the sequence model in the sent receiving module verification system based on the UVM verification platform can derive target sequence sequences (such as Seq_a and Seq_b) for various scenarios based on the base sequence, and the specific target sequence type can be configured according to the verification needs of the sent receiving module.

[0037] The sent receiving module verification system based on the UVM verification platform can send various data types of the sent protocol through the driver in the input agent, and randomly inject error information through the random error generator. Finally, the verification of the design to be tested is realized by comparing the results of the reference model and the design to be tested in the scoreboard. The addition of components such as the driver and the random error generator here, the output data contains random correct data signals and error data signals, which can well solve the problem of input stimulus completeness.

[0038] The sent receiving module verification system based on the UVM verification platform supports the use of the design code module of the sent receiving module to be verified as the verification object by constructing a module-level sent receiving module verification system, and no longer needs to integrate the whole chip as the design to be tested. Therefore, it is only necessary to integrate the sent receiving module itself as the design to be tested, thereby reducing the dependence of the design to be tested and executing the verifiable nodes of the design to be tested in advance. Since it is no longer necessary to integrate the entire electronic control unit chip or other design components, the above system can start verification in the design stage of the sent receiving module, greatly advancing the verification intervention time and reducing the dependent conditions. Moreover, the system combines a random error generator to perform random error injection, so that random correct data and error data can be generated to effectively complete the error state in the sent protocol, and finally realize the randomness and completeness of the excitation of the sent receiving module, greatly improving the verification quality of the sent receiving module.

[0039] In one embodiment, the data type of the target sequence includes a packet data type, a frame data type, or a frame data random error type in a sent protocol.

[0040] It can be understood that in this embodiment, the sequence model in the sent receiving module verification system based on the UVM verification platform can derive target sequence sequences for various scenarios based on the base sequence, for example, target sequences such as packet data types, frame data types or frame data random error types in the sent protocol may be included, thereby helping to more accurately perform verification of various functions of the sent receiving module.

[0041] In one embodiment, the input agent collects the random completeness of the random error generator by means of functional coverage.

[0042] It can be understood that in this embodiment, errors are randomly injected into the target sequence of numbers to be driven by the driver through a random error generator, and the random completeness is collected through the existing functional coverage method, so as to facilitate the confirmation or adjustment of the random degree of error injection of the random error generator, so as to more reliably overcome the shortcomings of incomplete error excitation in traditional technologies.

[0043] Each component in the sent receiving module verification system based on the UVM verification platform can be implemented in whole or in part by software, hardware and a combination thereof. Each of the components can be embedded in or independent of a device with a data processing function in the form of hardware, or can be stored in a memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. The aforementioned device can be, but is not limited to, various types of chip verification computers already available in the art.

[0044] In one embodiment, a sent receiving module verification method based on a UVM verification platform is provided, which is applied to a sent receiving module verification system based on a UVM verification platform, and the sent receiving module verification system includes a sequence model, an input agent, a reference model, a scoreboard and a design to be tested. The sequence model, the input agent, the reference model and the scoreboard are components based on the UVM verification platform. The design to be tested is a design code module of the sent receiving module to be verified. The sequence model is used to derive a target sequence for functional verification of the sent receiving module based on the basic sequence of the UVM verification platform and output it to the input agent, the input agent includes a driver and a random error generator, the driver is used to generate a data packet according to the target sequence through the random error generator to drive the interface and the reference model of the design to be tested, and the random error generator is used to inject random errors into the data packet. The reference model is used to output the expected result to the scoreboard according to the data packet, and the design to be tested is used to output the actual test result to the scoreboard according to the data packet. The scoreboard is used to compare the sent data and error status received in the expected result and the actual test result to obtain the verification result of the design to be tested.

[0045] like Figure 2 As shown, the sent receiving module verification method based on the UVM verification platform may include the following processing steps S10 to S20:

[0046] S10, power on and initialize the sent receiving module verification system;

[0047] S12, the input agent generates a data signal of the sent protocol according to the target sequence output by the sequence model;

[0048] S14, randomly injecting errors into the frame of the data signal using a random error generator;

[0049] S16, the reference model parses the data signal according to the sent protocol to obtain the expected sent data and error status as the expected result, and sends the expected result to the scoreboard;

[0050] S18, the design to be tested analyzes the data signal to obtain the sent data and error status of the actual test as the actual test result, and sends the actual test result to the scoreboard;

[0051] S20, the scoreboard compares the expected results with the actual test results to obtain the verification results of the design to be tested.

[0052] Specifically, Figure 3As shown, the input agent generates corresponding data packets according to the target sequence provided by the sequence model, and then generates the sent (protocol) data signal based on it. The random error generator is used to randomly insert errors in the frame of the data signal before sending it to the design under test and the reference model for processing. The reference model parses the received data according to the sent protocol, and sends the expected sent data and error status to the scoreboard; the scoreboard reads the parsed (actually tested) sent data and error status in the design under test, and finally compares the results obtained by the reference model and the design under test in the scoreboard, thereby realizing the verification of the design under test.

[0053] The sent receiving module verification method based on the UVM verification platform above supports the use of the design code module of the sent receiving module to be verified as the verification object by constructing a module-level sent receiving module verification system, and no longer needs to integrate the whole chip as the design to be tested, so only the sent receiving module itself needs to be integrated as the design to be tested, thereby reducing the dependence of the design to be tested and executing the verifiable nodes of the design to be tested in advance. Since it is no longer necessary to integrate the entire electronic control unit chip or other design components, the above system can start verification in the design stage of the sent receiving module, greatly advancing the verification intervention time and reducing the dependent conditions. Moreover, the system combines a random error generator to perform random error injection, so that random correct data and error data can be generated to effectively complete the error state in the sent protocol, and finally realize the randomness and completeness of the excitation of the sent receiving module, greatly improving the verification quality of the sent receiving module.

[0054] In one embodiment, the data type of the target sequence includes a packet data type, a frame data type, or a frame data random error type in a sent protocol.

[0055] In one embodiment, the above-mentioned sent receiving module verification method based on the UVM verification platform also includes the steps of:

[0056] The input agent collects the random completeness of the random error generator through functional coverage.

[0057] For the specific limitations of the sent receiving module verification method based on the UVM verification platform, please refer to the corresponding limitations of the sent receiving module verification system based on the UVM verification platform above, which will not be repeated here.

[0058] It should be understood that although Figure 2 and Figure 3The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 2 and Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0059] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0060] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A sent receiving module verification system based on UVM verification platform, characterized in that, It includes a sequence model, an input agent, a reference model, a scoreboard and a design to be tested, wherein the sequence model, the input agent, the reference model and the scoreboard are components based on a UVM verification platform, and the design to be tested is a design code module of a sent receiving module to be verified; The sequence model is used to derive a target sequence for functional verification of the sent receiving module based on a basic sequence of the UVM verification platform and output it to the input agent. The input agent includes a driver and a random error generator. The driver is used to generate a data packet according to the target sequence through the random error generator and drive it to the interface of the design to be tested and the reference model. The random error generator is used to inject random errors into the data packet. The reference model is used to output an expected result to the scoreboard according to the data packet. The design to be tested is used to output an actual test result to the scoreboard according to the data packet. The scoreboard is used to compare the sent data and the error status received in the expected result and the actual test result to obtain a verification result of the design to be tested.

2. the sent receiving module verification system based on UVM verification platform according to claim 1, is characterized in that, The data type of the target sequence includes a packet data type, a frame data type, or a frame data random error type in the sent protocol.

3. according to the sent receiving module verification system based on UVM verification platform according to claim 1 and 2, it is characterized in that, The input agent collects the random completeness of the random error generator by means of functional coverage.

4. A sent receiving module verification method based on UVM verification platform, characterized in that, The invention is applied to a sent receiving module verification system based on a UVM verification platform, wherein the sent receiving module verification system comprises a sequence model, an input agent, a reference model, a scoreboard and a design to be tested, wherein the sequence model, the input agent, the reference model and the scoreboard are components based on the UVM verification platform, and the design to be tested is a design code module of a sent receiving module to be verified; The sequence model is used to derive a target sequence for functional verification of the sent receiving module based on the basic sequence of the UVM verification platform and output it to the input agent, the input agent includes a driver and a random error generator, the driver is used to generate a data packet according to the target sequence through the random error generator to drive to the interface of the design to be tested and the reference model, the random error generator is used to perform random error injection on the data packet, the reference model is used to output an expected result to the scoreboard according to the data packet, the design to be tested is used to output an actual test result to the scoreboard according to the data packet, and the scoreboard is used to compare the sent data and the error state received in the expected result and the actual test result to obtain a verification result of the design to be tested; The sent receiving module verification method based on the UVM verification platform comprises the steps: Power on and initialize the sent receiving module verification system; The input agent generates a data signal of the sent protocol according to the target sequence output by the sequence model; randomly injecting errors into frames of the data signal using the random error generator; The reference model parses the data signal according to the sent protocol to obtain expected sent data and error status as expected results, and sends the expected results to the scoreboard; The design under test parses the data signal to obtain sent data and error status of actual test as actual test results, and sends the actual test results to the scoreboard; The scoreboard compares the expected result with the actual test result to obtain a verification result of the design to be tested.

5. the sent receiving module verification method based on UVM verification platform according to claim 4, is characterized in that, The data type of the target sequence includes a packet data type, a frame data type, or a frame data random error type in the sent protocol.

6. according to the sent receiving module verification method based on UVM verification platform described in claim 4 or 5, it is characterized in that, Also includes the steps: The input agent collects the random completeness of the random error generator by means of functional coverage.

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