Groove type PMOS (P-channel Metal Oxide Semiconductor) tube and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a groove type PMOS (P-channel Metal Oxide Semiconductor) tube, which comprises a P type substrate, a P type epitaxial layer, a cellular region and a terminal region surrounding the cellular region, the P-type epitaxial layer is located on the P-type substrate; the cellular region and the terminal region are located on the P-type epitaxial layer; a cellular groove of the cellular region comprises a cellular groove, a gate oxide layer and gate polycrystalline silicon; the grid electrode oxide layer is located at the bottom and on the side wall of the cellular groove, the grid electrode polycrystalline silicon is filled in a space formed by the grid electrode oxide layer, the grid electrode oxide layer is a boron-rich oxide layer, and the boron-rich oxide layer is formed by injecting boron ions into the oxide layer. The PMOS transistor has the advantages of low on-resistance, high avalanche tolerance EAS capability, low voltage creep and the like, so that the reliability is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench type PMOS tube and a manufacturing method thereof. Background Art

[0002] Trench PMOS (Positive channel Metal Oxide Semiconductor) tube is a trench-type P-type channel field effect transistor. When the Trench PMOS tube is turned on, it is mainly the majority carrier holes that participate in the conduction. Its driving circuit is simpler than that of the NMOS tube. It does not require a charge pump to boost the voltage. The I / O port output of the control unit (such as MCU) can drive the Trench PMOS tube to turn on and off. Therefore, Trench PMOS tubes are often used in applications such as load switches, battery protection, upper tubes of motor drives, and power reverse protection.

[0003] At present, the structure design and process flow of the trench PMOS tube are usually directly adopted from the NMOS tube. The general manufacturing process of the trench PMOS tube is to first form a trench in the cell area and the terminal area using a trench mask, then grow a gate oxide and deposit gate polysilicon in the trench, and then use a well area mask to form a well area. However, the existing trench PMOS tube does not take its own special effects into consideration, resulting in the existing trench PMOS tube having a higher on-resistance, which causes the trench PMOS tube to have a low reliability problem. Summary of the invention

[0004] The embodiment of the present application provides a trench PMOS tube and a manufacturing method, thereby solving the technical problem in the prior art that the trench PMOS tube has a high on-resistance, resulting in low reliability of the trench PMOS tube. The on-resistance of the trench PMOS tube is reduced, the reliability of the trench PMOS tube is improved, the conduction loss of the trench PMOS tube is saved, and the trench PMOS tube has technical effects such as high avalanche withstand EAS capability and low voltage creep.

[0005] In a first aspect, an embodiment of the present invention provides a trench PMOS transistor, comprising: a P-type substrate, a P-type epitaxial layer, a cell region, and a terminal region surrounding the cell region; The P-type epitaxial layer is located on the P-type substrate; The cell region and the terminal region are located on the P-type epitaxial layer; The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon; The gate oxide layer is located at the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

[0006] Preferably, the boron ion implantation energy range is 10keV-30keV, and the boron ion implantation dose range is 1E10cm -2 ~2E12cm -2 .

[0007] Preferably, the cell region includes: n cell trenches, n+1 electrode regions, an N-type well region, a P+ contact region and a cell region dielectric layer, where n is a positive integer greater than 3; The cell region dielectric layer is located on the P-type epitaxial layer; The N-type well region is located in the P-type epitaxial layer, and the N-type well region is extended to contact a designated terminal groove of the terminal region, and the designated terminal groove is a terminal groove adjacent to the cell region; The cell grooves and the electrode regions are alternately arranged, the cell grooves pass through the N-type well region and are located in the P-type epitaxial layer, and the electrode region passes through the cell region dielectric layer and is located in the N-type well region, wherein the depth of the cell grooves in the P-type epitaxial layer is greater than the depth of the N-type well region, and the upper surface of the N-type well region and the upper surface of the cell grooves are on the same horizontal plane as the upper surface of the P-type epitaxial layer; The P+ contact region is located in the N-type well region, and the upper surface of the P+ contact region is at the same horizontal plane as the upper surface of the P-type epitaxial layer; the electrode regions except the electrode region adjacent to the designated cell groove all pass through the P+ contact region in the N-type well region, and the depth of the electrode region is greater than the junction depth of the P+ contact region, and the designated cell groove is the cell groove adjacent to the terminal region.

[0008] Preferably, the doping concentration range of the N-type well region is 2E16cm-3-1E17cm-3 to ensure that the voltage threshold of the trench PMOS tube reaches the target voltage value.

[0009] Preferably, each of the electrode regions comprises: a contact hole, a contact electrode and an N+ contact region; The N+ contact region is located at the bottom of the contact hole; The contact electrode is filled in the contact hole and is located on the N+ contact region.

[0010] Preferably, it further comprises: a source metal layer; the source metal layer is located on the cell region dielectric layer and covers the cell trench and the electrode region.

[0011] Preferably, the terminal region comprises: a plurality of terminal grooves and a terminal region dielectric layer; The plurality of terminal grooves are distributed outward in sequence from the cell region, each of the terminal grooves is located in the P-type epitaxial layer, and the upper surface of each terminal groove is in the same horizontal plane as the upper surface of the P-type epitaxial layer; The terminal region dielectric layer is located on the P-type epitaxial layer and covers each of the terminal trenches.

[0012] Preferably, each of the terminal trenches comprises: a terminal groove, a terminal oxide layer and a terminal polysilicon; The terminal oxide layer is located on the bottom and sidewalls of the terminal groove, wherein the terminal oxide layer is the boron-rich oxide layer; The terminal polysilicon fills the space formed by the terminal oxide layer.

[0013] Preferably, it further comprises: a drain metal layer, wherein the drain metal layer is located below the P-type substrate.

[0014] Based on the same inventive concept, in a second aspect, the present invention further provides a method for manufacturing a trench PMOS transistor, which is used to manufacture the trench PMOS transistor described in the first aspect, and the manufacturing method comprises: forming a P-type epitaxial layer on a P-type substrate; forming a cell region and a terminal region on the P-type epitaxial layer; The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon; The gate oxide layer is located at the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

[0015] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: An embodiment of the present invention provides a trench PMOS tube, which includes a P-type substrate, a P-type epitaxial layer, a cell region, and a terminal region surrounding the cell region. The P-type epitaxial layer is located on the P-type substrate. The cell region and the terminal region are located on the P-type epitaxial layer. A cell trench is provided in the cell region. The cell trench includes a cell groove, a gate oxide layer, and a gate polysilicon. The gate oxide layer is located on the inner wall of the cell groove, and the gate polysilicon is filled in the space formed by the gate oxide layer. Among them, the gate oxide layer is a boron-rich oxide layer, and the boron-rich oxide layer is formed by injecting boron ions into the oxide layer. Therefore, low-energy boron ions are injected into the oxide layer formed by the oxide to obtain a gate oxide layer, that is, a boron-rich oxide layer. In this way, the on-resistance of the trench PMOS tube is reduced without introducing oxide layer defects, and the avalanche tolerance EAS (Energy of Avalanchein Single Pulse, single avalanche energy) capability and negative voltage creep of the trench PMOS tube are also optimized. Through the structural design of the trench PMOS tube in the embodiment of the present invention, the reliability of the trench PMOS tube is greatly improved and the conduction loss of the trench PMOS tube is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, throughout the accompanying drawings, the same reference figures are used to represent the same components. In the drawings: Figure 1 A schematic diagram of the structure of a trench PMOS tube in an embodiment of the present invention is shown; Figure 2 A schematic structural diagram of a junction surface between an N-type well region and a P-type epitaxial layer of an existing trench PMOS tube in an embodiment of the present invention is shown; Figure 3 A schematic structural diagram showing a conventional trench PMOS tube in an embodiment of the present invention in which a built-in electric field between an N-type well region and a P-type epitaxial layer causes hot carrier injection into a gate oxide layer when avalanche breakdown occurs; Figure 4 An on-resistance curve diagram of a trench gate PMOS tube in which both the gate oxide layer of the cell trench and the terminal oxide layer of the terminal trench are oxide layers not implanted with low-energy boron ions and a trench gate PMOS tube in which both the gate oxide layer of the cell trench and the terminal oxide layer of the terminal trench are boron-rich oxide layers in an embodiment of the present invention is shown; Figure 5 A schematic structural diagram of a junction surface between an N-type well region and a P-type epitaxial layer of a trench PMOS tube in an embodiment of the present invention is shown; Figure 6A schematic diagram of the structure of forming a P-type epitaxial layer on a P-type substrate, and forming a cell groove and a terminal groove in the P-type epitaxial layer in an embodiment of the present invention is shown; Figure 7 A schematic diagram of the structure of forming a cell groove and a terminal groove in an embodiment of the present invention is shown; Figure 8 A schematic diagram of a structure for forming an N-type well region in an embodiment of the present invention is shown; Fig. 9 A schematic diagram of the structure of forming a P+ contact region in an embodiment of the present invention is shown; Fig.10 A schematic diagram showing the structure of forming a dielectric layer in a terminal region and a dielectric layer in a cell region in an embodiment of the present invention is shown; Fig.11 A schematic diagram of a structure for forming a contact hole in an embodiment of the present invention is shown; Fig.12 A schematic diagram of a structure for forming an N+ contact region and a contact electrode in a contact hole in an embodiment of the present invention is shown; Fig.13 A schematic flow chart of the steps of a method for manufacturing a trench PMOS tube in an embodiment of the present invention is shown.

[0017] In the figure, 101, P-type substrate; 102, P-type epitaxial layer; 200, cell region; 300, terminal region; 400, source metal layer; 500, drain metal layer; 210, cell trench; 220, electrode region; 230, N-type well region; 240, P+ contact region; 250, cell region dielectric layer; 211, cell groove; 212, gate oxide layer; 213, gate polysilicon; 221, contact hole; 222, contact electrode; 223, N+ contact region; 310, terminal groove; 320, terminal region dielectric layer; 311, terminal groove; 312, terminal oxide layer; 313, terminal polysilicon. DETAILED DESCRIPTION

[0018] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0019] Embodiment 1 The first embodiment of the present invention provides a trench type PMOS transistor, such as Figure 1As shown, it includes: a P-type substrate 101, a P-type epitaxial layer 102, a cell region 200 and a terminal region 300 surrounding the cell region 200. The P-type epitaxial layer 102 is located on the P-type substrate 101. The cell region 200 and the terminal region 300 are located on the P-type epitaxial layer 102. The cell trench 210 of the cell region 200 includes a cell groove 211, a gate oxide layer 212 and a gate polysilicon 213. The gate oxide layer 212 is located on the bottom and sidewalls of the cell groove 211, and the gate polysilicon 213 is filled in the space formed by the gate oxide layer 212. Among them, the gate oxide layer 212 is a boron-rich oxide layer, and the boron-rich oxide layer is formed by injecting boron ions into the oxide layer.

[0020] It should be noted that the structure shown in the accompanying drawings of this embodiment is a schematic structure of the minimum repeating unit of a trench-type PMOS tube device. The P-type substrate 101 is a silicon-based substrate. The material of the P-type epitaxial layer 102 includes, but is not limited to, a silicon-based epitaxial layer. The cell trench 210 is located in the cell region 200. The cell trench 210 includes a cell groove 211, a gate oxide layer 212, and a gate polysilicon 213. The gate oxide layer 212 is located at the bottom and sidewall of the cell groove 211, and the gate oxide layer 212 is a boron-rich oxide layer, which is formed by injecting boron ions into the oxide layer. The material of the oxide layer includes oxide, and the material of the boron-rich oxide layer includes oxide and boron ions. The gate polysilicon 213 is filled in the space formed by the gate oxide layer 212, and the material of the gate polysilicon 213 is a combination of polysilicon. The cell trench 210 is the gate of the trench-type PMOS tube. In the accompanying drawings, the black and white checkered pattern area represents the boron-rich oxide layer.

[0021] The present embodiment provides a trench-type PMOS tube, which includes a P-type substrate 101, a P-type epitaxial layer 102, a cell region 200, and a terminal region 300 surrounding the cell region 200. The P-type epitaxial layer 102 is located on the P-type substrate 101. The cell region 200 and the terminal region 300 are located on the P-type epitaxial layer 102. A cell trench 210 is provided in the cell region 200. The cell trench 210 includes a cell groove 211, a gate oxide layer 212, and a gate polysilicon 213. The gate oxide layer 212 is located on the inner wall of the cell groove 211, and the gate polysilicon 213 is filled in the space formed by the gate oxide layer 212. Among them, the gate oxide layer 212 is a boron-rich oxide layer, and the boron-rich oxide layer is formed by injecting boron ions into the oxide layer. Therefore, low-energy boron ions are injected into the oxide layer formed by the oxide to obtain the gate oxide layer 212, that is, the boron-rich oxide layer. In this way, the on-resistance of the trench PMOS tube is reduced without introducing oxide layer defects, and the avalanche withstand EAS (Energy of Avalanche in Single Pulse) capability and negative voltage creep of the trench PMOS tube are optimized. The structural design of the trench PMOS tube in this embodiment greatly improves the reliability of the trench PMOS tube and saves the conduction loss of the trench PMOS tube.

[0022] Next, combine Figure 1 The structure of the trench PMOS tube of this embodiment is described in detail: The gate oxide layer 212 of the cell trench 210 is a boron-rich oxide layer. The boron-rich oxide layer is formed after the oxide layer is implanted with low-energy boron ions. The implantation energy of the boron ions ranges from 10keV to 30keV, and the implantation dose of the boron ions ranges from 1E10cm -2 ~2E12cm -2 . The implantation energy and implantation dose of the boron ions indicate that the implanted boron ions are low-energy boron ions. Since boron ions are relatively light, that is, boron ions are light ions, most of the implantation damage can be repaired in the subsequent thermal process. At the same time, the boron ions will diffuse into the silicon near the grooves to increase the P-type doping concentration (the P-type doping concentration only refers to the doping concentration near the grooves in the P-type epitaxial layer 102, where the grooves are the cell grooves 210 and the terminal grooves 310). For the cell region 200, the increase in the P-type doping concentration at the bottom of the cell groove 210 is conducive to expanding the current path and reducing the on-resistance. In addition, low-energy boron ions are injected into the oxide layer, so that the implantation damage is small, and the sensitive gate oxide layer is prevented from being subjected to large implantation damage, which affects the quality of the gate oxide layer. Through low-energy boron ions, the reliability of the gate oxide layer 212 and the reliability of the trench-type PMOS tube are guaranteed.

[0023] In addition, the boron-rich oxide layer is formed by performing a low-energy boron ion implantation on the oxide layer in the trench without a mask, thereby forming the boron-rich oxide layer simply and efficiently. Moreover, this formation process is also cost-saving.

[0024] The cell region 200 includes: n cell trenches 210, n+1 electrode regions 220, an N-type well region 230, a P+ contact region 240 and a cell region dielectric layer 250, where n is a positive integer greater than 3. The cell region dielectric layer 250 is located on the P-type epitaxial layer 102. The N-type well region 230 is located in the P-type epitaxial layer 102, and the N-type well region 230 is extended to contact the designated terminal trench 310 of the terminal region 300, and the designated terminal trench 310 is the terminal trench 310 adjacent to the cell region 200. The cell trenches 210 and the electrode regions 220 are alternately arranged. The cell trenches 210 pass through the N-type well region 230 and are located in the P-type epitaxial layer 102, and the electrode region 220 passes through the cell region dielectric layer 250 and is located in the N-type well region 230. The depth of the cell groove 210 in the P-type epitaxial layer 102 is greater than the depth of the N-type well region 230, and the upper surface of the N-type well region 230 and the upper surface of the cell groove 210 are at the same level as the upper surface of the P-type epitaxial layer 102. The P+ contact region 240 is located in the N-type well region 230, and the upper surface of the P+ contact region 240 is at the same level as the upper surface of the P-type epitaxial layer 102. The electrode regions 220 except the electrode region 220 adjacent to the designated cell groove 210 all pass through the P+ contact region 240 in the N-type well region 230, and the depth of the electrode region 220 is greater than the junction depth of the P+ contact region 240, and the designated cell groove 210 is the cell groove 210 adjacent to the terminal region 300.

[0025] Specifically, Figure 1The cell region 200 shown includes: two cell trenches 210, three electrode regions 220, an N-type well region 230, a P+ contact region 240 and a cell region dielectric layer 250. The N-type well region 230 is located in the P-type epitaxial layer 102, and the N-type well region 230 is an N-type doped region. The white background dot pattern area in the figure represents the N-type well region 230. The junction depth of the N-type well region 230 ranges from 0.5um to 1.5um, and the doping material of the N-type well region 230 includes but is not limited to phosphorus P. The two cell trenches 210 are spaced apart and are both located in the P-type epitaxial layer 102 and the N-type well region 230, and the depth of each cell trench 210 in the P-type epitaxial layer 102 is greater than the depth of the N-type well region 230. The P+ contact region 240 is located in the N-type well region 230 and is located on the left side of the cell trench 210 away from the terminal region 300. The P+ contact region 240 is a P-type heavily doped well region, and the doping material of the P+ contact region 240 includes but is not limited to boron B and / or boron difluoride. The upper surface of the N-type well region 230, the upper surfaces of the two cell trenches 210, the upper surface of the P+ contact region 240 and the upper surface of the P-type epitaxial layer 102 are at the same level.

[0026] The cell region dielectric layer 250 is located on the P-type epitaxial layer 102. The cell region dielectric layer 250 covers the P+ contact region 240 and each cell groove 210. The material of the cell region dielectric layer 250 is nitride or oxide. The three electrode regions 220 all pass through the cell region dielectric layer 250 and are located in the N-type well region 230. The depth of each electrode region 220 is greater than the junction depth of the P+ contact region 240. Among them, the upper surfaces of the three electrode regions 220 are at the same horizontal plane as the upper surface of the cell region dielectric layer 250. The three electrode regions 220 are respectively the first electrode region, the second electrode region and the third electrode region. The first electrode region is located on the left side of the cell groove 210 away from the terminal region 300, and passes through the P+ contact region 240 in the N-type well region 230. The second electrode region is located between the two cell grooves 210, and the third electrode region is located on the right side of the cell groove 210 of the adjacent terminal region 300, that is, the second electrode region and the third electrode region are respectively distributed on both sides of the designated cell groove 210 and are adjacent to the designated cell groove 210, so the two do not need to pass through the P+ contact region 240.

[0027] The doping concentration range of the N-type well region 230 is 2E16cm -3 -1E17cm -3 Since the oxide layer is injected with low-energy boron ions to form a boron-rich oxide layer, i.e., the gate oxide layer 212, the injection of boron ions will neutralize the doping concentration near a portion of the channel of the N-type well region 230. Therefore, compared with the N-type well region 230 of the existing PMOS tube with the same voltage specification and grain size, the doping concentration of the N-type well region 230 of this embodiment needs to be increased to ensure that the voltage threshold of the trench PMOS tube of this embodiment reaches the target voltage value.

[0028] In this way, the oxide layer becomes a boron-rich oxide layer after low-energy boron ion implantation. Since boron ions are relatively light, most of the implantation damage can be repaired in the subsequent thermal process. At the same time, the boron ions will diffuse into the silicon near the trench, increasing the P-type doping concentration. For the cell region 200, the increase in the P-type doping concentration at the bottom of the cell trench 210 is conducive to expanding the current path and reducing the on-resistance. At the same time, in order to compensate for the decrease in the relative doping concentration of the channel caused by the diffusion of boron ions, the doping concentration of the N-type well region 230 can be increased accordingly during the design; this not only ensures that the voltage threshold of the trench PMOS tube reaches the target voltage value, but also brings the additional benefits of reducing the parasitic transistor base resistance and improving the avalanche tolerance EAS capability of the trench PMOS tube device. This further improves the reliability of the trench PMOS tube.

[0029] It should be noted that the voltage threshold of the trench PMOS transistor can be set according to actual needs. The voltage threshold of the trench PMOS transistor is proportional to the doping concentration of the N-type well region 230 .

[0030] Each electrode region 220 includes: a contact hole 221, a contact electrode 222 and an N+ contact region 223. In the accompanying drawings, the black dot pattern area represents the N+ contact region 223, and the diamond pattern area represents the contact electrode 222. The N+ contact region 223 is located at the bottom of the contact hole 221. The N+ contact region 223 is an N-type heavily doped region, and the doping concentration of the N+ contact region 223 is greater than the doping concentration of the N-type well region 230. The doping material of the N+ contact region 223 includes but is not limited to arsenic As. The contact electrode 222 is filled in the contact hole 221 and is located above the N+ contact region 223. The material of the contact electrode 222 includes but is not limited to metal tungsten.

[0031] The trench type PMOS transistor further includes: a source metal layer 400. The source metal layer 400 is located on the P-type epitaxial layer 102 and covers the cell trench 210 and the electrode region 220. The material of the source metal layer 400 includes but is not limited to aluminum copper.

[0032] The terminal region 300 includes: a plurality of terminal grooves 310 and a terminal region dielectric layer 320. The plurality of terminal grooves 310 are sequentially distributed outward from the cell region 200, each terminal groove 310 is located in the P-type epitaxial layer 102, and the upper surface of each terminal groove 310 is at the same level as the upper surface of the P-type epitaxial layer 102. The terminal region dielectric layer 320 is located on the P-type epitaxial layer 102 and covers each terminal groove 310.

[0033] Specifically, Figure 1The terminal region 300 shown includes: three terminal grooves 310 and a terminal region dielectric layer 320. The number of terminal grooves 310 can also be set according to actual needs. The three terminal grooves 310 are respectively a first terminal groove, a second terminal groove and a third terminal groove. Each terminal groove 310 is located in the P-type epitaxial layer 102, and the upper surface of each terminal groove 310 is at the same horizontal plane as the upper surface of the P-type epitaxial layer 102. The first terminal groove is close to the adjacent cell region 200, that is, the first terminal groove is the designated terminal groove 310, the third terminal groove is far away from the cell region 200, and the second terminal groove is located between the first terminal groove and the third terminal groove. In the terminal region 300, the terminal groove 310 farthest away from the cell region 200 is also called a cut-off groove, and the third terminal groove is also called a cut-off groove. The terminal region dielectric layer 320 is located on the P-type epitaxial layer 102 and covers each terminal groove 310. In addition, both the terminal region dielectric layer 320 and the cell region dielectric layer 250 are ILD (Inter Layer Dielectric) dielectric layers, which refer to dielectric materials formed between the device and the metal layer to form electrical isolation. The ILD dielectric layer can effectively reduce the parasitic capacitance between the metal and the substrate, and improve the parasitic field effect transistor formed by the metal crossing different regions.

[0034] Each terminal groove 310 includes: a terminal groove 311, a terminal oxide layer 312 and a terminal polysilicon 313. The terminal oxide layer 312 is located at the bottom and sidewalls of the terminal groove 311, wherein the terminal oxide layer 312 is a boron-rich oxide layer. The terminal polysilicon 313 fills the space formed by the terminal oxide layer 312, and the material of the terminal polysilicon 313 is a combination of polysilicon.

[0035] The terminal oxide layer 312 of the terminal groove 310 of this embodiment is a boron-rich oxide layer. For the terminal region 300, the boron-rich oxide layer reaches the saturated solubility of boron, and the "boron absorption" phenomenon will be greatly improved. The junction surface of the N-type well region 230 and the P-type epitaxial layer 102 is close to the ideal plane junction state, perpendicular to the gate oxide layer 212 and the terminal oxide layer 312 (i.e., the boron-rich oxide layer), and the built-in electric field direction of the depletion layer (i.e., the depletion layer formed at the metallurgical interface of the PN junction) is changed from the traditional oblique direction to the longitudinal direction, thereby reducing the hot carrier injection of the terminal oxide layer 312, and greatly improving the voltage creep of the device. This further improves the reliability of the trench PMOS tube.

[0036] The trench PMOS transistor further includes: a drain metal layer 500, and the drain metal layer 500 is located under the P-type substrate 101. The material of the drain metal layer 500 is titanium nickel silver.

[0037] In order to better understand the structural principle of the trench PMOS tube of this embodiment, it is necessary to explain the existing trench PMOS tube: For existing trench-type PMOS tubes, since PMOS tubes conduct electricity mainly through hole carriers with slow mobility and saturation drift velocity, compared with NMOS devices with the same voltage specifications and grain sizes, the on-resistance of PMOS tubes with the same design structure is higher. In addition, due to the "boron absorption and phosphorus removal" phenomenon of the oxide layer of the PMOS tube, the junction surface between the N-type well region N-Body and the P-type epitaxial layer P-EPI is not ideally perpendicular to the trench, but will bend toward the bottom of the trench (i.e., the cell trench 210 and the terminal trench 310), such as Figure 2 As shown in the figure. From the curvature effect, it can be seen that the curved junction surface will lead to electric field concentration, thereby reducing the withstand voltage of the device. At the same time, since the direction of the electric field in the depletion layer of the PMOS tube is from the ionized donor in the N-type well region to the ionized acceptor in the P-epitaxial layer, when the device undergoes avalanche breakdown, the terminal oxide layer 312 near the N-body of the N-type well region and the P-epitaxial layer P-EPI will be severely injected with hot carriers (electrons), as shown in the figure. Figure 3 As shown. This makes the electric field distribution at the junction of the N-type well region, the P-type epitaxial layer and the terminal oxide layer 312 more concentrated, which ultimately leads to a further reduction in the withstand voltage of the device after each avalanche breakdown. At the same time, in order to ensure that the voltage threshold reaches the target voltage value, the doping concentration of the N-type well region of the existing trench PMOS tube is usually low, which can easily cause the parasitic transistor composed of the P+ contact region 240, the N-type well region and the P-type epitaxial layer to turn on during the non-embedded inductive load switching process, causing the device avalanche withstand EAS failure.

[0038] The structural principle of the trench-type PMOS tube of the present embodiment: the gate oxide layer 212 of the cell trench 210 and / or the terminal oxide layer 312 of the terminal trench 310 of the trench-type PMOS tube of the present embodiment is a boron-rich oxide layer, that is, the oxide layer of the trench is formed by injecting low-energy boron ions into the boron-rich oxide layer. Since boron ions are relatively light, most of the implantation damage can be repaired in the subsequent thermal process. At the same time, boron ions will diffuse into the silicon near the trench to increase the P-type doping concentration. In addition, the junction surface between the N-type well region 230 and the P-type epitaxial layer 102 is close to an ideal planar junction state, perpendicular to the gate oxide layer 212 and the terminal oxide layer 312, especially perpendicular to the terminal oxide layer 312, and the direction of the built-in electric field in the depletion layer is changed from the traditional oblique direction to the longitudinal direction, thereby ensuring the withstand voltage performance of the device.

[0039] For the cell region 200, the increase of the P-type doping concentration at the bottom of the cell trench 210 is beneficial to expand the current path and reduce the on-resistance. Figure 4At the same time, in order to compensate for the decrease in the relative doping concentration of the channel caused by the diffusion of boron ions, the doping concentration of the N-type well region 230 can be increased accordingly during design. This not only ensures that the voltage threshold of the trench PMOS tube reaches the target voltage value, but also brings the additional benefits of reducing the base resistance of the parasitic transistor and improving the avalanche withstand EAS capability of the device. For the terminal region 300, the boron-rich oxide layer has reached the saturated solubility of boron, and the "boron absorption" phenomenon will be greatly improved, such as Figure 5 As shown, the junction surface between the N-type well region 230 and the P-type epitaxial layer 102 is close to an ideal planar junction state, which is perpendicular to the terminal oxide layer 312. The direction of the built-in electric field in the depletion layer is changed from the traditional oblique direction to the vertical direction, which reduces the hot carrier injection of the terminal oxide layer 312 and greatly improves the voltage creep of the device.

[0040] Among them, Figure 4 As shown, the present trench gate PMOS tube in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both oxide layers not implanted with low-energy boron ions is compared with the present trench gate PMOS tube in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both boron-rich oxide layers. The yellow dotted curve represents the present trench gate PMOS tube in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both boron-rich oxide layers, and the blue solid curve represents the present trench gate PMOS tube in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both oxide layers not implanted with low-energy boron ions. Figure 4 In the figure, the abscissa represents the drain-source voltage Vds, and the ordinate represents the drain current Id. It can be seen from the slopes of the two curves that the on-resistance of the yellow curve is obviously lower than that of the blue curve, indicating that the on-resistance of the present trench gate PMOS transistor in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both boron-rich oxide layers is lower than the on-resistance of the present trench gate PMOS transistor in which the gate oxide layer 212 of the cell trench 210 and the terminal oxide layer 312 of the terminal trench 310 are both oxide layers not implanted with low-energy boron ions.

[0041] Therefore, since boron ions are relatively light, most of the implantation damage can be repaired in the subsequent thermal process, and at the same time, boron ions will diffuse into the silicon near the trench to increase the P-type doping concentration. For the cell region 200, the increase in the P-type doping concentration at the bottom of the cell trench 210 is conducive to expanding the current path and reducing the on-resistance. At the same time, in order to compensate for the decrease in the relative doping concentration of the channel caused by the diffusion of boron ions, the doping concentration of the N-type well region 230 can be increased accordingly during the design, which not only ensures that the voltage threshold reaches the target voltage value, but also brings the additional benefits of reducing the parasitic transistor base resistance and improving the device avalanche tolerance EAS capability.

[0042] The manufacturing process of the trench PMOS tube of this embodiment is described below: like Figure 6 As shown, a P-type epitaxial layer 102 is grown on the surface of a P-type substrate 101 (i.e., a silicon substrate). Photolithography, epitaxial layer etching and other processes are performed at designated positions on the P-type epitaxial layer 102 to form a plurality of grooves, thereby obtaining a cell groove 211 and a terminal groove 311. The depth of the groove (i.e., the cell groove 211 and the terminal groove 311) ranges from 0.8um to 2um, and the width of the groove ranges from 0.18um to 3um. Usually, the depth of the terminal groove 311 is greater than the depth of the cell groove 211.

[0043] like Figure 7 As shown, a gate dielectric layer is deposited on the surface of the wafer (specifically, on the surface of the P epitaxial layer), and low-energy boron ion implantation without a mask is performed to form a boron-rich oxide layer, that is, a gate oxide layer 212 and a terminal oxide layer 312. The material of the gate dielectric layer is oxide, the thickness of the gate dielectric layer ranges from 0.03um to 0.08um, the implantation energy of the boron ions ranges from 10keV to 30keV, and the implantation dose of the boron ions ranges from 1E10 to 2E12cm -2 Polysilicon is deposited on the surface of the gate dielectric layer and etched back to be flush with the silicon plane to form a dielectric trench, that is, a cell trench 210 and a terminal trench 310 are formed.

[0044] like Figure 8 As shown, photolithography and N-type ion implantation are performed at designated positions through a mask to form an N-type well region 230. The junction depth of the N-type well region 230 ranges from 0.5um to 1.5um.

[0045] like Fig. 9 As shown, photolithography and P-type ion implantation are performed at a designated position in the N-type well region 230 through a mask, and the ion concentration after implantation is higher than the doping concentration of the P-type epitaxial layer, forming a P+ contact region 240. The junction depth of the P+ contact region 240 ranges from 0.15um to 0.3um.

[0046] like Fig.10 As shown, an ILD dielectric layer is deposited on the P-type epitaxial layer 102 to obtain a terminal region dielectric layer 320 and a cell region dielectric layer 250. The material of the ILD dielectric layer is nitride or oxide, and the thickness of the ILD dielectric layer ranges from 0.4um to 1um, that is, the thickness of the terminal region dielectric layer 320 and the cell region dielectric layer 250 ranges from 0.4um to 1um.

[0047] like Fig.11 As shown, photolithography and dielectric layer etching are performed at designated positions through a mask to form contact holes 221, and the etching depth is greater than the junction depth of the P+ contact region 240. The width of the contact hole 221 ranges from 0.2um to 0.6um.

[0048] like Fig.12 As shown, by maskless N-type ion implantation, the implantation dose is higher than the implantation dose of the N-type well region 230 to form an N+ contact region 223 to reduce the contact resistance of the electrode. A contact electrode 222 is filled in the contact hole 221, and the contact electrode 222 is located above the N+ contact region 223.

[0049] like Figure 1 As shown, a source metal layer 400 is formed on the cell region dielectric layer 250 , and a drain metal layer 500 is formed under the P-type substrate 101 .

[0050] The manufacturing process of this embodiment can perform boron ion implantation on the oxide layer without adding an additional mask, saving manufacturing time and cost and improving manufacturing efficiency. The trench PMOS tube formed by the manufacturing process of this embodiment reduces the on-resistance of the trench PMOS tube, improves the reliability of the trench PMOS tube, saves the conduction loss of the trench PMOS tube, and also enables the trench PMOS tube to have high avalanche withstand EAS capability and low voltage creep.

[0051] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: By performing low-energy boron ion implantation without a mask on the traditional gate oxide layer, it becomes a boron-rich gate oxide layer. Since the solubility of boron ions in the oxide layer reaches saturation, the curvature effect caused by the "boron absorption" phenomenon is greatly improved. At the same time, the direction of the electric field in the depletion layer is changed from oblique to longitudinal, which greatly reduces the hot carrier injection of the oxide layer. In addition, the diffusion of boron in the silicon near the trench can increase the current diffusion path and reduce the on-resistance of the trench PMOS tube on the one hand, and increase the doping concentration of the N-type well region during design on the other hand. Finally, while reducing the on-resistance of the trench PMOS tube, the avalanche withstand EAS capability and negative voltage creep of the device are also optimized.

[0052] Embodiment 2 Based on the same inventive concept, the second embodiment of the present invention also provides a method for manufacturing a trench PMOS transistor, such as Fig.13 As shown, the manufacturing method for manufacturing the trench PMOS transistor as described in the first embodiment includes: S601, forming a P-type epitaxial layer on a P-type substrate; S602, forming a cell region and a terminal region on the P-type epitaxial layer; The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon; The gate oxide layer is located at the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

[0053] Since the manufacturing method of the trench PMOS tube introduced in this embodiment is the manufacturing method adopted by the trench PMOS tube in the first embodiment of the present application, based on the trench PMOS tube introduced in the first embodiment of the present application, the technicians in this field can understand the specific implementation method and various variations of the manufacturing method of the trench PMOS tube in this embodiment, so how the manufacturing method of the trench PMOS tube implements the trench PMOS tube in the first embodiment of the present application is not described in detail here. As long as the technicians in this field implement the manufacturing method adopted by the trench PMOS tube in the first embodiment of the present application, it belongs to the scope of protection of the present application.

[0054] Those skilled in the art will appreciate that, although the preferred embodiments of the present invention have been described, those skilled in the art, once informed of the basic creative concept, may make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0055] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A trench PMOS tube, characterized in that: include: A P-type substrate, a P-type epitaxial layer, a cell region, and a terminal region surrounding the cell region; The P-type epitaxial layer is located on the P-type substrate; The cell region and the terminal region are located on the P-type epitaxial layer; The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon; The gate oxide layer is located at the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

2. The trench PMOS transistor according to claim 1, characterized in that: The boron ion implantation energy range is 10keV-30keV, and the boron ion implantation dose range is 1E10cm -2 ~2E12cm -2 .

3. The trench PMOS transistor according to claim 2, characterized in that: The cell region includes: n cell grooves, n+1 electrode regions, an N-type well region, a P+ contact region and a cell region dielectric layer, where n is a positive integer greater than 3; The cell region dielectric layer is located on the P-type epitaxial layer; The N-type well region is located in the P-type epitaxial layer, and the N-type well region is extended to contact a designated terminal groove of the terminal region, and the designated terminal groove is a terminal groove adjacent to the cell region; The cell grooves and the electrode regions are alternately arranged, the cell grooves pass through the N-type well region and are located in the P-type epitaxial layer, and the electrode region passes through the cell region dielectric layer and is located in the N-type well region, wherein the depth of the cell grooves in the P-type epitaxial layer is greater than the depth of the N-type well region, and the upper surface of the N-type well region and the upper surface of the cell grooves are on the same horizontal plane as the upper surface of the P-type epitaxial layer; The P+ contact region is located in the N-type well region, and the upper surface of the P+ contact region is at the same horizontal plane as the upper surface of the P-type epitaxial layer; the electrode regions except the electrode region adjacent to the designated cell groove all pass through the P+ contact region in the N-type well region, and the depth of the electrode region is greater than the junction depth of the P+ contact region, and the designated cell groove is the cell groove adjacent to the terminal region.

4. The trench PMOS transistor according to claim 3, characterized in that: The doping concentration range of the N-type well region is 2E16cm -3 -1E17cm -3 , to ensure that the voltage threshold of the trench PMOS tube reaches the target voltage value.

5. The trench PMOS transistor according to claim 3, characterized in that: Each of the electrode regions comprises: a contact hole, a contact electrode and an N+ contact region; The N+ contact region is located at the bottom of the contact hole; The contact electrode is filled in the contact hole and is located on the N+ contact region.

6. The trench PMOS transistor according to claim 3, characterized in that: Also includes: source metal layer; The source metal layer is located on the cell region dielectric layer and covers the cell trench and the electrode region.

7. The trench PMOS transistor according to claim 1, characterized in that: The terminal area includes: a plurality of terminal grooves and a terminal area dielectric layer; The plurality of terminal grooves are distributed outward in sequence from the cell region, each of the terminal grooves is located in the P-type epitaxial layer, and the upper surface of each terminal groove is in the same horizontal plane as the upper surface of the P-type epitaxial layer; The terminal region dielectric layer is located on the P-type epitaxial layer and covers each of the terminal trenches.

8. The trench PMOS transistor according to claim 7, characterized in that: Each of the terminal grooves comprises: a terminal groove, a terminal oxide layer and a terminal polysilicon; The terminal oxide layer is located on the bottom and sidewalls of the terminal groove, wherein the terminal oxide layer is the boron-rich oxide layer; The terminal polysilicon fills the space formed by the terminal oxide layer.

9. The trench PMOS transistor according to claim 1, characterized in that: Also includes: A drain metal layer is located below the P-type substrate.

10. A method for manufacturing a trench PMOS tube, characterized in that: Used to manufacture the trench PMOS transistor according to any one of claims 1 to 9, the manufacturing method comprising: forming a P-type epitaxial layer on a P-type substrate; forming a cell region and a terminal region on the P-type epitaxial layer; The cell trench of the cell region includes a cell groove, a gate oxide layer and a gate polysilicon; The gate oxide layer is located at the bottom and sidewalls of the cell groove, and the gate polysilicon fills the space formed by the gate oxide layer, wherein the gate oxide layer is a boron-rich oxide layer formed by injecting boron ions into the oxide layer.

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