Self-aligned double-epitaxial super-junction IGBT and manufacturing method thereof

Abstract

The invention discloses a self-aligned double-epitaxial super-junction IGBT and a manufacturing method, the self-aligned double-epitaxial super-junction IGBT comprises a semiconductor layer arranged on the front surface of a substrate, a plurality of body regions distributed along the surface of the semiconductor layer are arranged in the semiconductor layer, and a source region located below the surface of the semiconductor layer is arranged in each body region; the pair of first side walls are arranged on the surface of the semiconductor layer above each source region in a self-aligned manner; the super junction groove is arranged in the semiconductor layer in a penetrating manner between each pair of first side walls; the first epitaxial layer of the first conductive type and the second epitaxial layer of the second conductive type are arranged in the super junction groove and are connected with the body region; the gate oxide layer and the gate electrode are arranged on the surface of the semiconductor layer between two adjacent pairs of first side walls; the collector region layer and the buffer region layer are sequentially arranged below the surface of the back surface of the substrate. According to the invention, the range of ion implantation can be accurately adjusted while the number of photomasks is reduced and self-alignment is realized, the drift region can be changed into the intrinsic semiconductor layer, and the on-resistance is reduced while the withstand voltage is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a self-aligned dual epitaxial super junction IGBT and a manufacturing method thereof. Background Art

[0002] Compared with planar MOSFET, super junction (SJ) MOSFET has the characteristics of low on-resistance, fast switching speed, small chip size and low heat generation. Super junction has smaller junction capacitance. For super junction MOSFET, the reduction of resistance will bring obvious benefits, such as lower conduction loss or smaller die at the same on-resistance (Ron). In addition, the reduction of chip area will lead to lower junction capacitance and gate and output charge, which can reduce dynamic loss. Using the super junction MOSFET structure, super junction IGBT devices can be further formed.

[0003] However, as the device area continues to shrink, the number of processing steps and the number of masks in the manufacturing process also increase, which undoubtedly increases the manufacturing cost. In addition, due to the existence of overlay error, the short-circuit resistance also increases.

[0004] On the other hand, there is often a need to adjust the size of the ion implantation area during the manufacturing process. However, due to the continuous reduction of device area and the existence of overlay errors, it will become very difficult to use a mask to adjust the size of the ion implantation area, thus affecting the reliability of the device.

[0005] In addition, how to improve the charge balance of the device, further increase the withstand voltage, and reduce the on-resistance has also become an important and ongoing issue. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a self-aligned dual epitaxial super junction IGBT and a manufacturing method thereof.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] The present invention provides a self-aligned dual epitaxial super junction IGBT, comprising:

[0009] A semiconductor layer disposed on the front side of the substrate, wherein the semiconductor layer is provided with a plurality of body regions of the second conductivity type distributed along the surface of the semiconductor layer, and each of the body regions is provided with a source region of the first conductivity type located below the surface of the semiconductor layer;

[0010] A pair of first spacers self-aligned and disposed on the surface of the semiconductor layer above each of the source regions;

[0011] A super junction trench is provided in the semiconductor layer between each pair of the first sidewalls;

[0012] A first epitaxial layer of a first conductivity type disposed on an inner wall of the super junction trench, and a second epitaxial layer of a second conductivity type disposed in the super junction trench within the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are connected to the body region through a top portion facing a surface of the semiconductor layer;

[0013] A gate oxide layer and a gate electrode which are sequentially disposed on the surface of the semiconductor layer between two adjacent pairs of the first sidewalls and partially overlap the source region;

[0014] And a collector region layer and a buffer region layer are sequentially arranged below the back surface of the substrate.

[0015] Further, a drift region of the first conductivity type is provided in the semiconductor layer, and the body region, the source region, the first epitaxial layer and the second epitaxial layer are located in the drift region; or, the semiconductor layer is an intrinsic semiconductor layer.

[0016] Furthermore, the bottom of the super junction trench is located at the interface between the semiconductor layer and the substrate.

[0017] Furthermore, the first epitaxial layer and the second epitaxial layer are connected to the body region through a transition connection region of a second conductivity type provided on the top facing the surface of the semiconductor layer; and / or the second epitaxial layer has a gradient doping concentration inwardly along the inner wall of the super junction trench.

[0018] Furthermore, it also includes: a source region contact metal separated between each pair of the first side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, and a gate metal separated between two adjacent pairs of the first side walls and connected to the gate; an interlayer dielectric layer arranged on the first side walls, the source region contact metal and the gate metal; and a collector layer arranged on the back surface of the substrate.

[0019] The present invention also provides a method for manufacturing a self-aligned dual epitaxial super junction IGBT, comprising:

[0020] providing a substrate, and forming a semiconductor layer on a front surface of the substrate;

[0021] Forming a plurality of first hard mask layer patterns, second hard mask layer patterns contacting both sides of the first hard mask layer patterns, and a third hard mask layer pattern contacting between two of the second hard mask layer patterns on adjacent sides on the surface of the semiconductor layer;

[0022] removing the second hard mask layer pattern, and forming a first implantation window between the first hard mask layer pattern and the third hard mask layer pattern;

[0023] forming a first ion implantation region as a body region below the surface of the semiconductor layer below each of the first implantation windows;

[0024] Forming second sidewalls on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern, respectively, so as to form a pair of second sidewalls formed by two adjacent second sidewalls on the surface of the semiconductor layer within each first ion implantation region, and forming a second implantation window between each pair of the second sidewalls;

[0025] forming a second ion implantation region below the surface of the semiconductor layer below each of the second implantation windows and located in the corresponding first ion implantation region and serving as a source region;

[0026] A first side wall is formed on the inner side surface of each pair of the second side walls to form a pair of the first side walls;

[0027] Forming a super junction trench downward from the surface of the semiconductor layer between each pair of the first sidewalls, passing through the corresponding second ion implantation region and the first ion implantation region;

[0028] Forming a first epitaxial layer of a first conductivity type on the inner wall of the super junction trench, and filling a second epitaxial layer of a second conductivity type in the super junction trench within the first epitaxial layer, and then etching back so that the tops of the first epitaxial layer and the second epitaxial layer are lower than the surface of the semiconductor layer;

[0029] forming a fourth hard mask layer pattern between each pair of the first spacers, and then removing the third hard mask layer pattern, the first hard mask layer pattern and the second spacers;

[0030] sequentially forming a gate oxide layer and a gate on the surface of the semiconductor layer between two adjacent pairs of the first sidewalls, and making the gate oxide layer and the gate partially overlap with the second ion implantation region, and then removing the fourth hard mask layer pattern;

[0031] And, forming a third ion implantation region of the second conductivity type connected to the first ion implantation region and serving as a transition connection region on top of the first epitaxial layer and the second epitaxial layer by forming a third implantation window between each pair of the first sidewalls;

[0032] Also includes:

[0033] The back side of the substrate is thinned, and a collector region layer and a buffer region layer are sequentially formed below the back side surface of the thinned substrate.

[0034] Further, forming a plurality of first hard mask layer patterns on the surface of the semiconductor layer, contacting second hard mask layer patterns located on both sides of the first hard mask layer patterns, and contacting a third hard mask layer pattern between two of the second hard mask layer patterns located on adjacent sides, specifically includes:

[0035] Using a patterning process to form a plurality of first hard mask layer patterns on the surface of the semiconductor layer;

[0036] Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form a second hard mask layer pattern that contacts the first hard mask layer pattern on both sides, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between two second hard mask layer patterns on adjacent sides;

[0037] A third hard mask layer is formed on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and is back-etched to form a third hard mask layer pattern that contacts two of the second hard mask layer patterns located on adjacent sides and exposes the tops of the first hard mask layer pattern and the second hard mask layer pattern.

[0038] Furthermore, by sequentially forming a plurality of second sub-epitaxial layers of a second conductivity type having a gradient doping concentration in the super junction trench within the first epitaxial layer, the second epitaxial layer formed by the plurality of second sub-epitaxial layers has a gradient doping concentration inwardly along the inner wall of the super junction trench.

[0039] Further, the third ion implantation region connected to the first ion implantation region is first formed on the top of the first epitaxial layer and the second epitaxial layer, and then the fourth hard mask layer pattern is formed; or, after removing the fourth hard mask layer pattern, the third ion implantation region connected to the first ion implantation region is formed on the top of the first epitaxial layer and the second epitaxial layer.

[0040] Furthermore, after removing the fourth hard mask layer pattern and forming the third ion implantation region, the method further includes:

[0041] Filling the gaps between the first sidewalls with metal layer material, and removing the excess metal layer material on the top surface of the first sidewalls, to form a source contact metal separated between each pair of the first sidewalls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, and a gate metal separated between two adjacent pairs of the first sidewalls and connected to the gate;

[0042] forming an interlayer dielectric layer on the first sidewall spacer, the source region contact metal and the gate metal;

[0043] And forming a collector layer on the back surface of the substrate after forming the collector region layer and the buffer layer.

[0044] It can be seen from the above technical scheme that the present invention adopts multiple self-aligned patterning and sidewall processes (including forming the first hard mask layer pattern to the third hard mask layer pattern and the second sidewall and the first sidewall), and can reduce the mask while adjusting the width of the first implantation window to the third implantation window, so as to achieve accurate adjustment of the ion implantation range (i.e., the width of the body region, the source region and the transition connection region) of the first ion implantation region as the body region, the second ion implantation region as the source region and the third ion implantation region as the transition connection region, and can form self-alignment between the body region, the source region, the super junction and the gate. At the same time, by adding a first epitaxial layer of the first conductivity type in the super junction trench, the doping concentration and thickness of the second epitaxial layer of the second conductivity type and the first epitaxial layer can be easily controlled to achieve a perfect charge balance. In this way, the drift region of the first conductivity type that originally needs to be set in the semiconductor layer of the first conductivity type can be omitted by increasing the doping concentration of the first epitaxial layer, and thus the semiconductor layer of the first conductivity type can be directly changed to an intrinsic semiconductor layer, so that the on-resistance can be reduced while the withstand voltage is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic structural diagram of a self-aligned dual epitaxial super junction IGBT according to a preferred embodiment of the present invention;

[0046] Figure 2-Figure 11 The present invention is a process flow chart of a method for manufacturing a self-aligned dual-epitaxial super junction IGBT according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0048] Unless otherwise specified below, the various parts of the IGBT device can be made of materials known to those skilled in the art. Semiconductor materials may include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate conductor may be formed of various materials that can conduct electricity, such as metal, doped polysilicon layer, or a stacked gate conductor including a metal and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x 、Ni 3 Si, Pt, Ru, W, and combinations of the above-mentioned various conductive materials. The gate dielectric (gate oxide layer) can be made of SiO 2 Or the dielectric constant is greater than SiO 2 The gate dielectric may be formed of materials such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Furthermore, the gate dielectric may be formed of not only materials known to those skilled in the art, but also materials for gate dielectrics to be developed in the future.

[0049] The first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of N-type and P-type. N-type may be formed by implanting N-type dopants (e.g., P, As, etc.) into a semiconductor material. P-type may be formed by implanting P-type dopants (e.g., B, etc.) into a semiconductor material. The above may be understood with reference to known techniques.

[0050] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0051] refer to Figure 1 A self-aligned dual epitaxial superjunction IGBT of the present invention comprises a substrate 10, a semiconductor layer 24 disposed on the front surface (the upper surface in the figure) of the substrate 10, and a collector layer 30 and a buffer layer 29 disposed below (inside) the back surface of the substrate 10 in sequence.

[0052] The semiconductor layer 24 is provided with a plurality of independent body regions 12 of the second conductivity type distributed along the surface of the semiconductor layer 24 (the upper surface away from the front surface of the substrate 10). Each body region 12 is provided with an independent source region 18 of the first conductivity type located below (inside) the surface of the semiconductor layer 24. Figure 1 2 source regions 18 and 2 body regions 12 are shown as examples, but are not limited thereto). That is, the body region 12 and the source region 18 are both located below (inside) the surface of the semiconductor layer 24 , and the body region 12 is disposed around the source region 18 .

[0053] A pair of first spacers 15 are respectively provided on the surface of the semiconductor layer 24 above each source region 18, and are self-aligned with the source region 18 and the body region 12. Each pair of first spacers 15 can be vertically provided on the surface of the semiconductor layer 24, and are spaced a certain distance apart, and the distance should ensure that the pair of first spacers 15 are located above the same source region 18.

[0054] A super junction trench 26 is disposed between each pair of first spacers 15 and extends from the surface of the semiconductor layer 24 to the semiconductor layer 24 ; and the super junction trench 26 passes through a source region 18 and a body region 12 at a corresponding position. The width of the super junction trench 26 is determined by the distance between the pair of first spacers 15 .

[0055] A first epitaxial layer 28 of a first conductivity type is provided on the inner wall of the super junction trench 26; a second epitaxial layer 27 of a second conductivity type is filled in the super junction trench 26 within the first epitaxial layer 28. The first epitaxial layer 28 and the second epitaxial layer 27 are used to form a double epitaxial super junction. The first epitaxial layer 28 and the second epitaxial layer 27 are connected to the body region 12 through the top facing the surface of the semiconductor layer 24.

[0056] A gate oxide layer 13 and a gate electrode 14 are sequentially disposed on the surface of the semiconductor layer 24 between two adjacent pairs of first spacers 15. Moreover, each gate electrode 14 and gate oxide layer 13 partially overlaps with two adjacent source regions 18 located on both sides below.

[0057] The following description is made by taking the case where the first conductivity type is N type and the second conductivity type is P type as an example.

[0058] refer to Figure 1 In some embodiments, the substrate 10 may be a heavily doped N+ silicon substrate 10 (N+ substrate) of the first conductivity type.

[0059] In some embodiments, the semiconductor layer 24 may be an epitaxial N-type silicon semiconductor layer 24 of the first conductivity type disposed on the surface of the substrate 10, and an epitaxial N-type drift region 11 (N driftEPI) of the first conductivity type is formed in the semiconductor layer 24. The body region 12, the source region 18, the first epitaxial layer 28, and the second epitaxial layer 27 are located in the drift region 11.

[0060] In some embodiments, the bottom of the super junction trench 26 is located at the interface between the semiconductor layer 24 and the substrate 10 (ie, located on the surface of the substrate 10 ).

[0061] The body region 12 may be a lightly doped P-type body region 12 (P-body) of the second conductivity type.

[0062] The source region 18 may be a heavily doped N+ type source region 18 (N+ body) of the first conductivity type.

[0063] The first epitaxial layer 28 may be a first conductivity type medium-doped N-type silicon first epitaxial layer 28 (N EPI).

[0064] The second epitaxial layer 27 may be a P-type silicon second epitaxial layer 27 (PEPI) doped with a second conductivity type.

[0065] In some embodiments, the second epitaxial layer 27 has a gradient doping concentration along the inner wall of the super junction trench 26 toward the inside of the super junction trench 26 .

[0066] In some embodiments, the second epitaxial layer 27 is composed of multiple second sub-epitaxial layers formed sequentially in the super junction trench 26 within the first epitaxial layer 28, and the doping concentration of each second sub-epitaxial layer is different, thereby forming a second epitaxial layer 27 with a gradient doping concentration along the inner wall of the super junction trench 26 toward the inside of the super junction trench 26.

[0067] In some embodiments, since an N-type first epitaxial layer 28 is added between the N-type drift region 11 and the P-type second epitaxial layer 27 in the super junction trench 26, the doping concentration and thickness of the P-type second epitaxial layer 27 and the N-type first epitaxial layer 28 can be easily controlled to achieve a perfect charge balance, so that the N-type semiconductor layer 24 with the N-type drift region 11 can be directly changed to the intrinsic semiconductor layer 24 by increasing the doping concentration of the first epitaxial layer 28, thereby eliminating the need to set the drift region 11 in the intrinsic semiconductor layer 24. In this way, the on-resistance can be reduced while the withstand voltage is increased.

[0068] In some embodiments, the first epitaxial layer 28 and the second epitaxial layer 27 are connected to the body region 12 exposed at the sidewall of the super junction trench 26 through a transition connection region 25 of the second conductivity type provided on the top facing the surface of the semiconductor layer 24. The transition connection region 25 can be a heavily doped P+ type transition connection region 25 of the second conductivity type to increase the P-type doping concentration at the top of the second epitaxial layer 27 and improve the dynamic reliability of the formed device.

[0069] In some embodiments, the gate 14 may be a heavily doped N+ type polysilicon gate 14 (poly) of the first conductivity type; the gate oxide layer 13 (Gate OX) may be made of silicon dioxide.

[0070] In some embodiments, a metal layer is further provided between each first spacer 15. The metal layer includes a source contact metal 17 that fills and separates between each pair of first spacers 15 and ohmically connects the corresponding source region 18, the body region 12, the first epitaxial layer 28, and the second epitaxial layer 27 (connected through the transition connection region 25), and a gate metal 16 that is separated between two adjacent pairs of first spacers 15 and connected to the gate 14. That is, the gate metal 16 in the metal layer is isolated from the source contact metal 17 by the first spacer 15.

[0071] In some embodiments, an interlayer dielectric layer 22 is further provided on the surface of the metal layer. Furthermore, a metal interconnection layer 21 may be provided on the interlayer dielectric layer 22. The gate 14 may be interconnected with the metal interconnection layer 21 through the gate metal 16 and the conductive contact hole 23 provided in the interlayer dielectric layer 22; the source region 18, the body region 12, the first epitaxial layer 28 and the second epitaxial layer 27 (transition connection region 25) may be interconnected with the metal interconnection layer 21 through the source region contact metal 17 and the conductive contact hole 23 provided in the interlayer dielectric layer 22.

[0072] In some embodiments, a dielectric passivation layer 20 (Passivation) may be further provided on the metal interconnection layer 21; a pad window 19 connected to the metal interconnection layer 21 may be provided on the surface of the passivation layer 20 for forming a pad (not shown).

[0073] refer to Figure 1 In some embodiments, the collector region layer 30 is located below (inside) the back surface of the substrate 10, and the buffer layer 29 is further located in the substrate 10 below (inside) the collector region layer 30. The collector region layer 30 may be a heavily doped P+ type collector region layer 30; and the buffer layer 29 may be a heavily doped N+ type buffer layer 29.

[0074] In some embodiments, a collector layer 31 is further disposed on the back surface of the substrate 10 ; the collector layer 31 is in contact with the collector region layer 30 .

[0075] In some embodiments, the collector layer 31 material includes at least one of Al, Ti, NiV, and Ag.

[0076] In some embodiments, the first spacer 15 may be formed of a dielectric material.

[0077] In some embodiments, the gate metal 16 and the source contact metal 17 materials (metal layer materials) include at least one of Au, Ag, Pt, Al, and W.

[0078] Adhesion layers (not shown) may be provided respectively between the gate metal 16 and the first spacer 15 and the top of the gate 14, and between the source contact metal 17 and the first spacer 15, the exposed sidewall of the super junction trench 26 and the top of the transition connection region 25. The adhesion layer material includes at least one of Ti, TiN and TaN.

[0079] It can be seen that, by self-aligning a pair of first spacers 15 disposed above each source region 18 , each super junction trench 26 can be self-aligned with the corresponding source region 18 , and the gate 14 can be self-aligned to be located between two adjacent super junctions.

[0080] A method for manufacturing a self-aligned dual epitaxial super junction IGBT of the present invention is described in detail below through specific implementation modes and in conjunction with the accompanying drawings.

[0081] refer to Figure 2-Figure 11 The self-aligned dual epitaxial super junction IGBT manufacturing method of the present invention can be used to manufacture the above-mentioned Figure 1 A self-aligned dual epitaxial super junction IGBT of the present invention may include the following steps:

[0082] Step S1 : providing a substrate 10 , and forming a semiconductor layer 24 on the front surface of the substrate 10 .

[0083] like Figure 2 As shown, a heavily doped N+ silicon substrate 10 (N+ substrate) can be used, and an N-type epitaxial silicon semiconductor layer 24 is formed on the front side (the upper surface is shown) of the silicon substrate 10, and an epitaxial N-type drift region 11 (N driftEPI) is also formed.

[0084] Step S2: forming a plurality of first hard mask layer patterns 32, second hard mask layer patterns 33 contacting both sides of the first hard mask layer patterns 32, and third hard mask layer patterns 34 contacting between two second hard mask layer patterns 33 on adjacent sides on the surface of the semiconductor layer 24.

[0085] like Figure 2 As shown, a first hard mask layer material may be deposited on the surface of the semiconductor layer 24. Then, a photoresist layer is formed on the first hard mask layer. Next, a plurality of first hard mask layer patterns 32 (HM1) are formed on the surface of the semiconductor layer 24 through photolithography and etching patterning processes. Figure 2 FIG. 2 exemplarily shows that two first hard mask layer patterns 32 are formed, but the present invention is not limited thereto. Afterwards, the photoresist remaining on the first hard mask layer patterns 32 is removed.

[0086] The first hard mask layer material may be a conventional hard mask layer material, for example, the first hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0087] like Figure 3 As shown, a conformal CVD process can be used to form a second hard mask layer on the surface of the semiconductor layer 24 to cover the first hard mask layer pattern 32. Then, the second hard mask layer is etched back to form a second hard mask layer pattern 33 (HM2) on both sides of each first hard mask layer pattern 32, which is in contact with the side surface of the first hard mask layer pattern 32, and exposes the top of the first hard mask layer pattern 32 and the two second hard mask layer patterns 33 located on the adjacent sides (i.e., located at Figure 3The surface of the semiconductor layer 24 is shown between two second hard mask layer patterns 33 inside two adjacent first hard mask layer patterns 32.

[0088] When the second hard mask layer is deposited, the thickness during deposition can be controlled to reserve a width for subsequent deposition of the third hard mask layer.

[0089] The second hard mask layer material may be a conventional hard mask layer material, for example, one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0090] like Figure 3 As shown, a deposition process may be used to form a third hard mask layer on the surface of the semiconductor layer 24, covering the first hard mask layer pattern 32 and the second hard mask layer pattern 33, and completely filling the gap between the two second hard mask layer patterns 33 on the adjacent sides. Then, the third hard mask layer material may be etched back to form a third hard mask layer pattern 34 (HM3) in contact with the side surface of the second hard mask layer pattern 33 between the two second hard mask layer patterns 33 on the adjacent sides, and expose the tops of the first hard mask layer pattern 32 and the second hard mask layer pattern 33.

[0091] By conformally forming a second hard mask layer on the first hard mask layer pattern 32 and back-etching to form a second hard mask layer pattern 33 on both sides of the first hard mask layer pattern 32, a third hard mask layer pattern 34 can be self-aligned between the second hard mask layer patterns 33, thereby saving one photomask and achieving a reduction in pitch.

[0092] The third hard mask layer material may be a conventional hard mask layer material, for example, the third hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.

[0093] Step S3 : removing the second hard mask layer pattern 33 , and forming a first implantation window 35 between the first hard mask layer pattern 32 and the third hard mask layer pattern 34 .

[0094] like Figure 4 As shown, then, the second hard mask layer pattern 33 can be removed by utilizing different etching selectivity ratios between the second hard mask layer material and the first hard mask layer material and the third hard mask layer material to expose the surface of the semiconductor layer 24 located between the first hard mask layer pattern 32 and the third hard mask layer pattern 34, thereby forming a first implantation window 35 between the first hard mask layer pattern 32 and the third hard mask layer pattern 34. Figure 4 FIG. 4 exemplarily shows that two first implantation windows 35 are formed, but the present invention is not limited thereto.

[0095] Step S4 : forming a first ion implantation region 121 as a body region 12 below the surface of the semiconductor layer 24 under each first implantation window 35 .

[0096] like Figure 4 As shown, then, through the first implantation window 35, and using a multi-directional ion implantation process, a lightly doped P-type first ion implantation region 121 is formed below the surface of the semiconductor layer 24 below each first implantation window 35 and serves as the body region 12 (P-body).

[0097] For example, by adopting an inclined implantation angle in the surrounding directions of the first implantation window 35, a lightly doped P-type first ion implantation region 121 with a width greater than the width of the first implantation window 35 can be formed below the surface of the semiconductor layer 24 below the first implantation window 35 and serve as the body region 12.

[0098] It can be seen that by adjusting the formation thickness of the second hard mask layer and adjusting the width of the second hard mask layer pattern 33 formed after back etching, the width of the first implantation window 35 defined by the distance between the first hard mask layer pattern 32 and the third hard mask layer pattern 34 can be adjusted, and by adopting a multi-directional ion implantation process, the width of the first ion implantation area 121 is made greater than the width of the first implantation window 35, thereby achieving accurate adjustment of the width of the first ion implantation area 121 formed through the first implantation window 35 (the range of ion implantation).

[0099] Step S5: forming second spacers 36 on both sides of the first hard mask layer pattern 32 and on both sides of the third hard mask layer pattern 34, respectively, so as to form a pair of second spacers 36 formed by two second spacers 36 on adjacent sides on the surface of the semiconductor layer 24 within each first ion implantation region 121, and forming a second implantation window 37 between each pair of second spacers 36;

[0100] like Figure 4 As shown, then, a second spacer 36 material is deposited on the surface of the semiconductor layer 24 exposed between the first hard mask layer pattern 32 and the third hard mask layer pattern 34, and the first hard mask layer pattern 32 and the third hard mask layer pattern 34 are covered. Then, a spacer process is adopted and back-etching is performed to form a second spacer 36 (Spacer) structure on both sides of each first hard mask layer pattern 32 and each third hard mask layer pattern 34. Among them, the second spacers 36 located on two adjacent sides between the first hard mask layer pattern 32 and the third hard mask layer pattern 34 are simultaneously located on the surface of the semiconductor layer 24 above the same first ion implantation region 121, forming a pair of second spacers 36, and a second implantation window 37 is formed between each pair of second spacers 36.

[0101] The second spacer 36 material may be made of a conventional spacer material having a different etching selectivity ratio with the first hard mask layer material and the third hard mask layer material.

[0102] Step S6 : forming a second ion implantation region 181 below the surface of the semiconductor layer 24 under each second implantation window 37 and located in the corresponding first ion implantation region 121 and serving as the source region 18 .

[0103] like Figure 4 As shown, then, through the second implantation window 37, and using a multi-directional ion implantation process, a heavily doped N+ type second ion implantation region 181 is formed below the surface of the semiconductor layer 24 below each second implantation window 37 and serves as the source region 18 (N+ body).

[0104] For example, by adopting an inclined implantation angle in the surrounding directions of the second implantation window 37, a heavily doped N+ type second ion implantation region 181 with a width greater than the width of the second implantation window 37 can be formed below the surface of the semiconductor layer 24 below the second implantation window 37 and serve as the source region 18.

[0105] It can be seen that when forming the second side wall 36, the horizontal width of the second side wall 36 formed by back-etching can be adjusted by controlling the deposition thickness of the second side wall 36 material, so as to adjust the spacing between a pair of second side walls 36, that is, adjust the width of the second implantation window 37 defined by the distance between a pair of second side walls 36, and by adopting a multi-directional ion implantation process, make the width of the second ion implantation area 181 larger than the width of the second implantation window 37, thereby achieving accurate adjustment of the width of the second ion implantation area 181 formed through the second implantation window 37 (the range of ion implantation).

[0106] Step S7: forming a first side wall 15 on the inner side surface of each pair of second side walls 36 to form a pair of first side walls 15 .

[0107] like Figure 5 As shown, then, the first spacer 15 material is deposited on the surface of the semiconductor layer 24 exposed between the second spacers 36, and the first hard mask layer pattern 32, the third hard mask layer pattern 34 and the second spacer 36 are covered. Then, the spacer process is adopted, and back etching is performed to form a first spacer 15 (Spacer) structure on the inner side surface of each pair of second spacers 36. Among them, the first spacers 15 located on two adjacent sides between the first hard mask layer pattern 32 and the third hard mask layer pattern 34 are simultaneously located on the surface of the semiconductor layer 24 within the same second ion implantation region 181, forming a pair of first spacers 15, and a third implantation window 38 is also formed between each pair of first spacers 15.

[0108] The material of the first spacer 15 can be a conventional spacer material having different etching selectivities with the material of the second spacer 36 , the material of the first hard mask layer, and the material of the third hard mask layer.

[0109] Step S8 : forming a super junction trench 26 downward from the surface of the semiconductor layer 24 between each pair of first spacers 15 and passing through the corresponding second ion implantation region 181 and the first ion implantation region 121 .

[0110] like Figure 5 As shown, then, using the first hard mask layer pattern 32 and the combined pattern of the second side walls 36 and the first side walls 15 on both sides and the third hard mask layer pattern 34 and the combined pattern of the second side walls 36 and the first side walls 15 on both sides as a common mask, etching is performed downward on the surface of the semiconductor layer 24 between a pair of first side walls 15 to form a super junction trench 26 in the semiconductor layer 24 that passes through the corresponding second ion implantation region 181 and the first ion implantation region 121. Figure 5 Two parallel super junction trenches 26 are formed, and the bottom of the super junction trench 26 can be located on the surface of the substrate 10 by etching.

[0111] Step S9: forming a first epitaxial layer 28 of a first conductivity type on the inner wall of the super junction trench 26, and filling a second epitaxial layer 27 of a second conductivity type in the super junction trench 26 within the first epitaxial layer 28, and then, by back etching, making the tops of the first epitaxial layer 28 and the second epitaxial layer 27 lower than the surface of the semiconductor layer 24.

[0112] like Figure 6 As shown, a doping epitaxial process is adopted to first form an N-type silicon first epitaxial layer 28 on the inner wall of the super junction trench 26. Then, the epitaxial process is continued to be adopted to fill the super junction trench 26 within the formed first epitaxial layer 28 to form a P-type silicon second epitaxial layer 27, and the super junction trench 26 is filled. When the second epitaxial layer 27 is formed by epitaxy, a plurality of P-type silicon second sub-epitaxial layers can be sequentially formed in the super junction trench 26 within the first epitaxial layer 28, and a gradient doping concentration can be provided between each second sub-epitaxial layer, so that the second epitaxial layer 27 formed by the plurality of second sub-epitaxial layers has a gradient doping concentration along the inner wall of the super junction trench 26 inward, thereby forming a second epitaxial layer 27 with a doping concentration gradient.

[0113] In other embodiments, an undoped epitaxial process may be used to first form an undoped silicon second epitaxial layer 27, and then, through multiple steps of ion implantation with different doping doses, a P-type silicon second epitaxial layer 27 having a doping concentration gradient inwardly along the inner wall of the super junction trench 26 is formed.

[0114] Next, the first epitaxial layer 28 and the second epitaxial layer 27 may be etched back so that the top of the first epitaxial layer 28 and the second epitaxial layer 27 is lower than the surface of the semiconductor layer 24 to form a super junction. By controlling the etch-back time, the top of the first epitaxial layer 28 and the second epitaxial layer 27 may be located at a height position flush with or close to the bottom of the source region 18, so that the source region 18 is exposed on the sidewall of the super junction trench 26.

[0115] It can be seen that when forming the first sidewall spacer 15, the deposition thickness of the first sidewall spacer 15 material can be controlled to adjust the horizontal width of the first sidewall spacer 15 formed by back etching, so as to adjust the spacing between a pair of first sidewall spacers 15, that is, to adjust the width of the surface of the semiconductor layer 24 exposed between the pair of first sidewall spacers 15, so as to adjust the horizontal width of the super junction trench 26 formed by etching later and the horizontal width of the corresponding super junction formed. At the same time, the horizontal width of the third implantation window 38 can also be accurately adjusted.

[0116] Step S10: By forming a third implantation window 38 between each pair of first spacers 15 , a third ion implantation region 251 of the second conductivity type connected to the first ion implantation region 121 and serving as a transition connection region 25 is formed on top of the first epitaxial layer 28 and the second epitaxial layer 27 .

[0117] like Figure 6 As shown, through the third implantation window 38 and by using an ion implantation process, a heavily doped P+ type third ion implantation region 251 is formed on the top of the first epitaxial layer 28 and the second epitaxial layer 27 exposed at the super junction trench 26, serving as a transition connection region 25, and the third ion implantation region 251 is connected to the first ion implantation region 121 exposed on the side wall of the super junction trench 26.

[0118] In other embodiments, since the doping concentration and thickness of the P-type second epitaxial layer 27 and the N-type first epitaxial layer 28 can be easily controlled and a perfect charge balance can be achieved by adding an N-type first epitaxial layer 28, the N-type semiconductor layer 24 having the N-type drift region 11 can be directly changed to the intrinsic semiconductor layer 24 by increasing the doping concentration of the first epitaxial layer 28, thereby eliminating the need to set the drift region 11 in the intrinsic semiconductor layer 24 (i.e., forming the intrinsic semiconductor layer 24 on the surface of the substrate 10, and no longer forming the N-type drift region 11).

[0119] Step S11: forming a fourth hard mask layer pattern 39 between each pair of first spacers 15, and then removing the third hard mask layer pattern 34, the first hard mask layer pattern 32 and the second spacers 36.

[0120] like Figure 6As shown, the fourth hard mask layer material can be filled between each pair of first spacers 15 through a deposition process to cover the first spacers 15, the second spacers 36, the first hard mask layer pattern 32, and the third hard mask layer pattern 34. Then, the fourth hard mask layer is etched back to remove the excess fourth hard mask layer material on the top surfaces of the first spacers 15, the second spacers 36, the first hard mask layer pattern 32, and the third hard mask layer pattern 34, thereby forming a fourth hard mask layer pattern 39 (HM4) located between a pair of first spacers 15 and covering the top of the super junction.

[0121] The fourth hard mask layer material includes tetraethyl orthosilicate oxide (ie, CVD oxide using tetraethyl orthosilicate TEOS precursor, TEOS OX for short), but is not limited thereto.

[0122] like Figure 7 As shown, then, the third hard mask layer pattern 34 and the first hard mask layer pattern 32 are removed by etching back.

[0123] It should be noted that, for the two first hard mask layer patterns 32 located at the outermost edges of both sides of the device, whether they need to be removed or partially removed depends on how the function of the device edge is defined, and this should not be used as an improper limitation on the present invention.

[0124] Then, the second sidewall spacers 36 are further removed to expose the surface of the semiconductor layer 24 between two adjacent pairs of first sidewall spacers 15 .

[0125] Step S12: sequentially forming a gate oxide layer 13 and a gate electrode 14 on the surface of the semiconductor layer 24 between two adjacent pairs of first spacers 15, and making the gate oxide layer 13 and the gate electrode 14 partially overlap with the second ion implantation region 181, and then removing the fourth hard mask layer pattern 39.

[0126] like Figure 8 As shown, a gate 14 manufacturing process may be used, firstly forming a gate oxide layer 13 on the surface of the semiconductor layer 24 exposed between two adjacent pairs of first sidewalls 15, and then depositing a gate 14 material on the gate oxide layer 13, for example, a polysilicon gate 14 material may be deposited, and the fourth hard mask layer pattern 39 and the first sidewalls 15 are covered. Next, by back-etching the polysilicon gate 14 material, a polysilicon gate 14 is formed on the gate oxide layer 13, and the top of the polysilicon gate 14 is made lower than the top of the first sidewalls 15. Then, the fourth hard mask layer pattern 39 is removed, leaving a metal layer deposition space between each first sidewall 15.

[0127] In other embodiments, the third ion implantation region 251 formed in step S10 may also be formed after removing the fourth hard mask layer pattern 39 in this step and formed on top of the first epitaxial layer 28 and the second epitaxial layer 27 using the same ion implantation process.

[0128] Afterwards, a metal layer may be formed between the first spacers 15 , and an interlayer dielectric layer 22 may be formed on the surface of the metal layer.

[0129] like Fig. 9 As shown, an adhesion layer (not shown) can be formed on the exposed surface of each first sidewall 15, on the sidewall of the exposed super junction trench 26, on the top of the super junction, and on the top of the gate 14 through a deposition process, and a metal layer material is filled in the gaps between the first sidewalls 15 on the adhesion layer to fill the gaps between the first sidewalls 15. Then, by etching back or chemical mechanical polishing (CMP) the metal layer material and the adhesion layer, the excess metal layer material on the top surface of the first sidewall 15 is removed to form a source region contact metal 17 separated between each pair of first sidewalls 15 and connected to a corresponding source region 18, body region 12, first epitaxial layer 28 and second epitaxial layer 27 (transition connection region 25), and a gate metal 16 separated between two adjacent pairs of first sidewalls 15 and connected to the gate 14, thereby forming a metal layer.

[0130] Then, an interlayer dielectric layer 22 (ILD) may be formed on the top surfaces of the first spacer 15 , the gate metal 16 and the source contact metal 17 (ie, the top surface of the metal layer) through a deposition process.

[0131] like Fig.10 As shown, then, a conductive contact hole 23 (eg, a tungsten contact hole) whose bottom is respectively connected to the gate metal 16 and the source contact metal 17 can be formed in the interlayer dielectric layer 22 through photolithography, etching, filling and planarization processes.

[0132] Then, a metal interconnection layer 21 connected to the top of the conductive contact hole 23 may be formed on the interlayer dielectric layer 22 through an interconnection process.

[0133] Next, a dielectric passivation layer 20 (Passivation) may be formed on the metal interconnection layer 21 through a deposition process, and a pad window 19 connected to the metal interconnection layer 21 may be formed on the surface of the passivation layer 20 through a photolithography and etching process, and the pad window 19 may be filled with pad metal and planarized to form a pad (not shown). No further details will be given.

[0134] Step S13: thinning the back side of the substrate 10 , and sequentially forming a collector region layer 30 and a buffer region layer 29 below the back side surface of the thinned substrate 10 .

[0135] refer to Fig.11The front side of the substrate 10 is turned upside down, so that the back side of the substrate 10 faces upward and the front side faces downward. Then, the front side of the substrate 10 can be fixed by using existing technology (i.e., the surface of the passivation layer 20 is fixed). For example, the front side of the substrate 10 can be fixed by using a blue tape or bonding with another substrate.

[0136] Next, the back side of the substrate 10 may be thinned using existing technology. For example, the back side of the substrate 10 may be thinned using a combination of chemical etching (wet etching) and mechanical grinding.

[0137] In a preferred embodiment, the back side of the substrate 10 may be ground and thinned to a thickness of 60-200 μm, and then chemical etching may be used to thin the back side of the substrate 10 to a final thickness.

[0138] Then, conventional ion implantation can be used to form a heavily doped P+ collector layer 30 below the back surface of the substrate 10. For example, B implantation can be used, and an implantation energy of 20 to 80 KeV can be used to form a heavily doped P+ collector layer 30 (P+imp) on the back side of the substrate 10.

[0139] Next, conventional ion implantation can be used to continue to form a heavily doped N+ type buffer layer 29 from deep to shallow in the back side of the substrate 10 below the collector region layer 30. For example, a multi-step implantation of H deep implantation (Himp deep) with an implantation energy of 0.8 to 2 MeV and H shallow implantation (H imp shallow) with an implantation energy of 0.3 to 0.8 MeV can be used to form a heavily doped N+ type buffer layer 29 (N+H imp) in the back side of the substrate 10 below the collector region layer 30. Afterwards, annealing is performed. For example, furnace annealing can be used.

[0140] Finally, conventional metal electrode manufacturing processes may be used to deposit and pattern electrode metal on the collector region layer 30 to form a collector layer 31. For example, the collector layer 31 may be formed by using at least one of Al, Ti, NiV, Ag, etc.

[0141] In summary, the present invention adopts multiple self-aligned patterning and sidewall processes (including forming the first hard mask layer pattern 32 to the fourth hard mask layer pattern 39 and the second sidewall 36, the first sidewall 15), and can reduce the mask while adjusting the width of the first implantation window 35 to the third implantation window 38, so as to achieve accurate adjustment of the ion implantation range (i.e., the width of the body region 12, the source region 18 and the transition connection region 25) of the first ion implantation region 121 as the body region 12, the second ion implantation region 181 as the source region 18 and the third ion implantation region 251 as the transition connection region 25, and can form self-alignment between the body region 12, the source region 18, the super junction and the gate 14. At the same time, by adding the first epitaxial layer 28 of the first conductivity type in the super junction trench 26, the doping concentration and thickness of the second epitaxial layer 27 of the second conductivity type and the first epitaxial layer 28 can be easily controlled to achieve a perfect charge balance. In this way, the doping concentration of the first epitaxial layer 28 can be increased to eliminate the need for the drift region 11 (drift) of the first conductive type that is originally required to be set in the first conductive type semiconductor layer 24, and thus the first conductive type semiconductor layer 24 can be directly changed to an intrinsic semiconductor layer 24, thereby improving the withstand voltage while reducing the on-resistance, laying the foundation for further optimization of device performance.

[0142] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A self-aligned dual epitaxial super junction IGBT, characterized in that: include: A semiconductor layer disposed on the front side of the substrate, wherein the semiconductor layer is provided with a plurality of body regions of the second conductivity type distributed along the surface of the semiconductor layer, and each of the body regions is provided with a source region of the first conductivity type located below the surface of the semiconductor layer; A pair of first spacers self-aligned and disposed on the surface of the semiconductor layer above each of the source regions; A super junction trench is provided in the semiconductor layer between each pair of the first sidewalls; A first epitaxial layer of a first conductivity type disposed on an inner wall of the super junction trench, and a second epitaxial layer of a second conductivity type disposed in the super junction trench within the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are connected to the body region through a top portion facing a surface of the semiconductor layer; A gate oxide layer and a gate electrode which are sequentially disposed on the surface of the semiconductor layer between two adjacent pairs of the first sidewalls and partially overlap the source region; And a collector region layer and a buffer region layer are sequentially arranged below the back surface of the substrate.

2. The self-aligned dual epitaxial super junction IGBT according to claim 1, characterized in that: A drift region of the first conductivity type is provided in the semiconductor layer, and the body region, the source region, the first epitaxial layer and the second epitaxial layer are located in the drift region; or, the semiconductor layer is an intrinsic semiconductor layer.

3. The self-aligned dual epitaxial super junction IGBT according to claim 1, characterized in that: The bottom of the super junction trench is located at the interface between the semiconductor layer and the substrate.

4. The self-aligned dual epitaxial super junction IGBT according to claim 1, characterized in that: The first epitaxial layer and the second epitaxial layer are connected to the body region through a transition connection region of a second conductivity type provided on the top facing the surface of the semiconductor layer; and / or the second epitaxial layer has a gradient doping concentration inwardly along the inner wall of the super junction trench.

5. The self-aligned dual epitaxial super junction IGBT according to claim 1, characterized in that: Also includes: A source contact metal separated between each pair of the first side walls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, and a gate metal separated between two adjacent pairs of the first side walls and connected to the gate; an interlayer dielectric layer arranged on the first side walls, the source contact metal and the gate metal; and a collector layer arranged on the back surface of the substrate.

6. A method for manufacturing a self-aligned dual epitaxial super junction IGBT, characterized in that: include: providing a substrate, and forming a semiconductor layer on a front surface of the substrate; Forming a plurality of first hard mask layer patterns, second hard mask layer patterns contacting both sides of the first hard mask layer patterns, and a third hard mask layer pattern contacting between two of the second hard mask layer patterns on adjacent sides on the surface of the semiconductor layer; removing the second hard mask layer pattern, and forming a first implantation window between the first hard mask layer pattern and the third hard mask layer pattern; forming a first ion implantation region as a body region below the surface of the semiconductor layer below each of the first implantation windows; Forming second sidewalls on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern, respectively, so as to form a pair of second sidewalls formed by two adjacent second sidewalls on the surface of the semiconductor layer within each first ion implantation region, and forming a second implantation window between each pair of the second sidewalls; forming a second ion implantation region below the surface of the semiconductor layer below each of the second implantation windows and located in the corresponding first ion implantation region and serving as a source region; A first side wall is formed on the inner side surface of each pair of the second side walls to form a pair of the first side walls; Forming a super junction trench downward from the surface of the semiconductor layer between each pair of the first sidewalls, passing through the corresponding second ion implantation region and the first ion implantation region; Forming a first epitaxial layer of a first conductivity type on the inner wall of the super junction trench, and filling a second epitaxial layer of a second conductivity type in the super junction trench within the first epitaxial layer, and then etching back so that the tops of the first epitaxial layer and the second epitaxial layer are lower than the surface of the semiconductor layer; forming a fourth hard mask layer pattern between each pair of the first spacers, and then removing the third hard mask layer pattern, the first hard mask layer pattern and the second spacers; sequentially forming a gate oxide layer and a gate on the surface of the semiconductor layer between two adjacent pairs of the first sidewalls, and making the gate oxide layer and the gate partially overlap with the second ion implantation region, and then removing the fourth hard mask layer pattern; And, forming a third ion implantation region of the second conductivity type connected to the first ion implantation region and serving as a transition connection region on top of the first epitaxial layer and the second epitaxial layer by forming a third implantation window between each pair of the first sidewalls; Also includes: The back side of the substrate is thinned, and a collector region layer and a buffer region layer are sequentially formed below the back side surface of the thinned substrate.

7. The method for manufacturing a self-aligned dual epitaxial super junction IGBT according to claim 6, characterized in that: The forming of a plurality of first hard mask layer patterns on the surface of the semiconductor layer, contacting second hard mask layer patterns located on both sides of the first hard mask layer patterns, and contacting a third hard mask layer pattern between two of the second hard mask layer patterns located on adjacent sides specifically includes: Using a patterning process to form a plurality of first hard mask layer patterns on the surface of the semiconductor layer; Forming a second hard mask layer on the surface of the semiconductor layer to cover the first hard mask layer pattern, and performing back etching to form a second hard mask layer pattern that contacts the first hard mask layer pattern on both sides, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between two second hard mask layer patterns on adjacent sides; A third hard mask layer is formed on the surface of the semiconductor layer to cover the first hard mask layer pattern and the second hard mask layer pattern, and is back-etched to form a third hard mask layer pattern that contacts two of the second hard mask layer patterns located on adjacent sides and exposes the tops of the first hard mask layer pattern and the second hard mask layer pattern.

8. The method for manufacturing a self-aligned dual epitaxial super junction IGBT according to claim 6, characterized in that: By sequentially forming a plurality of second sub-epitaxial layers of a second conductivity type having a gradient doping concentration in the super junction trench within the first epitaxial layer, the second epitaxial layer formed by the plurality of second sub-epitaxial layers has a gradient doping concentration inwardly along the inner wall of the super junction trench.

9. The method for manufacturing a self-aligned dual epitaxial super junction IGBT according to claim 6, characterized in that: First, the third ion implantation region connected to the first ion implantation region is formed on the top of the first epitaxial layer and the second epitaxial layer, and then the fourth hard mask layer pattern is formed; or, after removing the fourth hard mask layer pattern, the third ion implantation region connected to the first ion implantation region is formed on the top of the first epitaxial layer and the second epitaxial layer facing the surface of the semiconductor layer.

10. The method for manufacturing a self-aligned dual epitaxial super junction IGBT according to claim 6, characterized in that: After removing the fourth hard mask layer pattern and forming the third ion implantation region, the method further includes: Filling the gaps between the first sidewalls with metal layer material, and removing the excess metal layer material on the top surface of the first sidewalls, to form a source contact metal separated between each pair of the first sidewalls and connected to the source region, the body region, the first epitaxial layer and the second epitaxial layer, and a gate metal separated between two adjacent pairs of the first sidewalls and connected to the gate; forming an interlayer dielectric layer on the first sidewall spacer, the source region contact metal and the gate metal; And forming a collector layer on the back surface of the substrate after forming the collector region layer and the buffer layer.

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