TBC battery and preparation method thereof

Abstract

The invention relates to a TBC battery and a preparation method thereof. The preparation method comprises the following steps: S1, forming a dielectric region and a polycrystalline silicon layer; s2, forming a dopant source layer of the first conductive type impurities; s3, opening the film and cleaning; s4, one-step co-doping of impurities of different conductive types; the thickness of the dopant source layer of the first conductive type impurities is 10 nm to 100 nm. According to the invention, the dopant source layer of the first conductive type impurities is formed firstly, so that the high-temperature doping times, the cleaning times and the film opening times are reduced, the doping temperature is reduced, the process time is shortened, the process flow is simplified, the equipment investment cost is reduced, and the internal composite action of the cell is reduced, thereby improving the photoelectric conversion efficiency.

Description

Technical Field

[0001] The present invention relates to the field of TBC batteries, and in particular to a TBC battery and a preparation method thereof. Background Art

[0002] The IBC (Interdigitated Back Contact) cell and the TOPcon (Tunnel Oxide Passivated Contact) cell can be superimposed to form a TBC (Tunnel Back Contact) cell. The TBC cell absorbs the tunnel oxide passivation contact technology of the TOPCon cell and the P and N regions arranged in interdigital shapes on the back of the IBC cell. The structure of the TBC cell is: the back PN region is prepared by mask and furnace tube doping, and an ultra-thin tunnel oxide layer is formed between the PN region and the base region; the P region and the N region are isolated and contacted with the metal electrode respectively, and single-sided screen printing (no main grid or multi-grid). The BC cell transfers all the electrode grid lines on the front of the cell to the back of the cell, reducing the blocking of the electrode grid lines to the sunlight, maximizing the use of sunlight, doping a large effective power generation area, and thus improving the cell conversion efficiency.

[0003] The common process route for mass production equipment in the industry at present is: cleaning → LPCVD (low pressure chemical vapor deposition) to form a tunneling oxide layer and an intrinsic amorphous silicon layer → high temperature boron doping to complete doping and crystallization → masking → laser opening of BSG (borosilicate glass) (N area) and cleaning → reverse etching → LPCVD to form an intrinsic amorphous silicon layer → high temperature phosphorus doping to complete doping → laser opening of the gap area → texturing → removal of silicon oxides and RCA (industrial standard wet cleaning process) standard cleaning → passivation anti-reflection layer formation → metallization. In order to prepare the N+ region, the local P+ region and the isolation region therebetween (the structure combining these three is usually called a PIN structure), the existing process route requires two high-temperature doping processes, two amorphous silicon formation processes, two laser processes and multiple mask processes. The process is cumbersome and the process time is long, which seriously affects the production capacity and causes additional manufacturing costs. In addition, the existing process route has too many high-temperature processes, and two high-temperature dopings (phosphorus doping temperature 800-1000°C, boron doping temperature 900-1200°C) greatly affect the minority carrier lifetime of the substrate silicon wafer and thus have an adverse effect on the battery efficiency. In addition, the existing technology TBC preparation process route is complex, the process window is small, and a large amount of additional equipment costs are added, resulting in insufficient product competitiveness. Since the BSG thickness is relatively thick to block the alkaline polishing and the alkaline washing tank in the RCA, high-energy laser film opening is required for film opening, but high-energy laser film opening will cause recombination, and low-energy laser film opening cannot completely remove the BSG layer. In the limited acid washing time, it cannot be cleaned by acid, which will also cause recombination, thereby affecting the conversion efficiency of the battery. Summary of the invention

[0004] The present invention is aimed at the above problems, makes up for the deficiencies of the prior art, and provides a TBC battery and a preparation method to solve the problems arising from the above background technology.

[0005] A first aspect of the present invention provides a method for preparing a TBC battery, comprising the following steps: S1 forms a dielectric region and a polysilicon layer; S2 forms a dopant source layer of first conductivity type impurities; S3 film opening and cleaning; S4 co-doping of impurities of different conductivity types in one step; The thickness of the dopant source layer of the first conductive type impurities is 10 nm-100 nm.

[0006] Preferably, the thickness of the dopant source layer of the first conductive type impurities is 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm. More preferably, the thickness of the dopant source layer of the first conductive type impurities is 50nm-100nm.

[0007] In the present invention, the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm. When the thickness is less than 10nm, it cannot serve as a barrier layer for the second conductive type impurities, and serious recombination will occur, resulting in a decrease in photoelectric conversion efficiency. When the thickness is greater than 100nm, the oxygen content of the silicon wafer will be high, and serious recombination will occur, resulting in a decrease in photoelectric conversion efficiency and photoinduced degradation.

[0008] Preferably, the TBC cell includes a substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, a dielectric region and a polysilicon layer being sequentially arranged on the back side of the substrate silicon wafer in a direction away from the substrate silicon wafer, and an impurity source layer of the first conductive type impurities being formed outside the polysilicon layer.

[0009] Preferably, in the preparation method, before forming the dielectric region in S1, it also includes the steps of cleaning and polishing the substrate silicon wafer, and the substrate silicon wafer is N-type or P-type.

[0010] Preferably, in the preparation method, after the S4 conductive dopant is co-doped in one step, it also includes laser selective doping, preparation of the Gap region (i.e., the PN region junction and isolation region), a texturing step, removal of the dopant source layer of the first conductive type impurities and an RCA cleaning step, a dielectric layer formation step, and a metallization step.

[0011] Preferably, in the preparation method, in the step of forming the dielectric region and the polysilicon layer in S1, CVD (Chemical Vapor Deposition) is used at a formation temperature of 300° C.-650° C.

[0012] Preferably, the S2 is formed in the doping source layer of the first conductive type impurities by CVD method, with a formation temperature of 300°C-800°C and a time of 300s-750s. The forming raw materials include boron source gas or phosphorus source gas, the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0013] Preferably, the forming raw material also includes other gases, and the other gases are one or more gases of SiH4, N2O, NH3, Ar.

[0014] Preferably, in the step of forming a dopant source layer of first conductive type impurities in S2, the dopant source layer of the first conductive type impurities is a silicon-containing compound layer containing first conductive type impurities, and the first conductive type impurities are boron, gallium or phosphorus.

[0015] Preferably, in the step of film opening and cleaning S3, the film opening method adopts at least one of laser, etching slurry, and photolithography.

[0016] Preferably, in the step of film opening and cleaning S3, the cleaning method includes one of acid cleaning, alkali cleaning, or acid cleaning followed by alkali cleaning.

[0017] Preferably, the film opening method in the S3 film opening and cleaning is laser film opening, and the parameters of the laser film opening are set as: wavelength 200nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, frequency 200kHz-2000kHz.

[0018] By adopting the above technical solution, the c-Si region or polysilicon layer region where the second conductive type impurity region will be formed in the future is laser-opened. The local dopant source layer of the first conductive type impurity is removed or thinned, and in this process, no doping is caused to the polysilicon region or c-Si region, or only a low concentration doping of one order of magnitude lower than the future doping concentration of this area is caused.

[0019] More preferably, the cleaning method is acid cleaning.

[0020] The acid washing is performed using hydrofluoric acid with a concentration of 0.5%-50%. After washing, the first dopant source layer in the non-film-opening area is retained by at least 2nm; and there is no first dopant source layer remaining in the film-opening area, that is, the residual first dopant source concentration after washing is less than 1×10 19 cm -3 .

[0021] By adopting the above technical solution, the film-opening area formed by laser film-opening provides a reserved area for the second conductive type impurity layer to be formed in the future. After cleaning the film-opening area, a polysilicon area or a c-Si area is reserved for forming the second conductive type impurity doping. The main purpose of cleaning here is to remove the doping source layer of the first doped conductive type impurity remaining on the surface of the polysilicon layer in the film-opening area or the doping source layer of the first doped conductive type impurity remaining on the surface of the c-Si, so as to ensure that the non-film-opening area and the film-opening area form a single conductive type impurity doping during one-step co-diffusion; and after cleaning, the doping source layer of the first doped conductive type impurity in the non-laser film-opening area needs to retain a sufficient thickness, in order to ensure that the first doping area has a sufficient doping concentration after one-step co-doping, and as a mask layer to prevent the doping material of the second conductive type impurity from being doped into the first doping area. The complete removal of the doping source layer of the first doped conductive type impurity and the doping source layer of the second doped conductive type impurity in the non-film-opening area will be completely removed in the subsequent RCA cleaning step.

[0022] Preferably, the doping temperature of the S4 different conductive type impurities co-doped in one step is 600°C-1000°C, more preferably, the doping temperature is 600°C-980°C, and the doping time is 5min-180min, and the doping time does not include the time required for heating and cooling.

[0023] Preferably, in the one-step co-doping of different conductive type impurities in S4, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used to simultaneously form a first conductive type impurity region and a second conductive type impurity region, the first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the one-step co-doping of different conductive type impurities is performed at least once.

[0024] Preferably, the doping sources of the second conductive type impurities are boron source gas and phosphorus source gas, the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0025] Preferably, after the S4 conductive dopant is co-doped in one step, a laser selective doping step is also included, and the wavelength of the laser selective doping is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, and the frequency is 200kHz-2000kHz. The laser selective doping obtains a local heavily doped region of the conductive type impurity region.

[0026] Preferably, after the S4 step of co-doping impurities of different conductive types in one step, a preparation step of the Gap region is also included, and the Gap region preparation step is automatically formed by executing the S4 step of co-doping impurities of different conductive types in one step or is prepared by laser, and the setting parameters of the laser preparation are: wavelength 200nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, frequency 200kHz-2000kHz.

[0027] Preferably, the preparation step of the Gap area further includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer or a Gap area texturing surface on the back side, and the morphology and size of the front texturing surface and the Gap area texturing surface are the same or different.

[0028] Another aspect of the present invention provides a TBC cell, comprising a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer comprising a front velvet surface and a second dielectric layer; the back side of the substrate silicon wafer comprising a dielectric region, a second conductive type impurity region, a first conductive type impurity region, a first dielectric layer, a metal electrode and a Gap region; The dielectric region is a tunnel oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm; The second conductive type impurity region and the first conductive type impurity region are formed simultaneously in one or more conductive dopant one-step co-doping steps; In the conductive dopant co-doping step, at least once, a doping source having impurities of a second conductivity type opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the local area of ​​the metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0029] Preferably, the c-Si region or polysilicon layer of the second conductive type impurity region is formed by film opening and cleaning, the film opening method is at least one of laser, etching slurry, and photolithography, the cleaning method includes at least one of acid washing, alkaline washing, and acid washing followed by alkaline washing, and the one-step co-doping is to achieve the doping of the doping sources of the first conductive type impurities and the second conductive type impurities under the same high temperature conditions.

[0030] Preferably, the film opening method in the S3 film opening and cleaning is laser film opening, and the cleaning method is acid cleaning.

[0031] The acid washing is performed using hydrofluoric acid with a concentration of 0.5%-50%. After washing, the first dopant source layer in the non-film-opening area is retained by at least 2nm, that is, the residual first dopant source concentration after washing is less than 1×10 19 cm -3 ; and there is no residue of the first dopant source layer in the film opening area.

[0032] Preferably, a Gap area velvet surface is also provided on the back side of the substrate silicon wafer, and the Gap area velvet surface has the same or different morphology and size as the front velvet surface; the first conductive type impurity region, and / or the second conductive type impurity region is also provided with a heavily doped region.

[0033] Another aspect of the present invention provides another TBC cell, comprising a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer comprising a front velvet surface and a second dielectric layer; the back side of the substrate silicon wafer comprising a dielectric region, a second conductivity type impurity region, a first conductivity type impurity region, a first dielectric layer, a metal electrode and a Gap region; The local region of the electrode penetrates the first dielectric layer to form an ohmic contact with the second conductive type impurity region; the local region of the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity region; The dielectric region is a tunneling oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities.

[0034] Compared with the prior art, the present invention has the following beneficial effects: The present invention reduces the number of high-temperature doping times, cleaning times, and film opening times by first forming a dopant source layer of the first conductive type impurity, reduces the doping temperature, shortens the process time, simplifies the process flow, reduces the equipment investment cost, reduces the internal recombination of the battery, and thus improves the photoelectric conversion efficiency. Specifically, when different conductive type impurities are co-doped in one step, the dopant source layer of the first conductive type impurity formed can be used as a doping source and also as a barrier layer when another element is doped, so that different conductive type impurities are doped at the same time in one step at high temperature to form the first conductive type impurity region and the second conductive type impurity region, and only one high temperature step is required. doping, reducing the number of high-temperature doping times; since the present invention only has one step of co-doping, alkali polishing and alkali washing tank in RCA are not required before phosphorus doping, so there is no need to form a thicker BSG layer to block alkali polishing and alkali washing tank in RCA, so the oxygen content of the silicon wafer is reduced, reducing the recombination inside the solar cell and thus improving the photoelectric conversion efficiency; since the conventional production line route is boron doping before phosphorus doping, the boron doping temperature is as high as 1000°C, and high temperature is required to grow a thicker oxide layer and promote boron doping, while the preparation route of the present invention does not require the growth of a thicker oxide layer, eliminates the high-temperature boron doping process, simplifies the process flow, and reduces equipment investment costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the TBC battery structure in Example 1; Figure 2 This is a process flow chart of TBC battery preparation in Example 1; Figure 3 This is a schematic diagram of the TBC battery structure in Example 8; Figure 4 This is a process flow chart of TBC battery preparation in Example 8; Figure 5 This is a schematic diagram of the TBC battery structure in Example 14; Figure 6 This is a process flow chart of TBC battery preparation in Example 14; Figure 7 This is a schematic diagram of the TBC battery structure in Example 20; Figure 8 This is a process flow chart for preparing TBC batteries in Example 20.

[0036] In the figure: 1-second dielectric layer; 2-front velvet surface, 3-N-type silicon wafer; 4-tunneling oxide layer, 5-second conductivity type impurity polysilicon region and heavily doped region, 6-first dielectric layer, 7-electrode, 8-gap region, 9-first conductivity type impurity polysilicon region, 10-second conductivity type impurity c-Si region and heavily doped region. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings in the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0038] This embodiment provides a method for preparing a TBC battery, comprising the following steps: S1 forms a dielectric region and a polysilicon layer; S2 forms a dopant source layer of first conductivity type impurities; S3 film opening and cleaning; S4 co-doping of impurities of different conductivity types in one step; The thickness of the dopant source layer of the first conductive type impurities is 10 nm-100 nm.

[0039] The present invention reduces the number of high-temperature doping times, cleaning times, and film opening times by first forming a dopant source layer of the first conductive type impurity, reduces the doping temperature, shortens the process time, simplifies the process flow, reduces the equipment investment cost, reduces the internal recombination of the battery, and thus improves the photoelectric conversion efficiency. Specifically, when different conductive type impurities are co-doped in one step, the dopant source layer of the first conductive type impurity formed can be used as a doping source and also as a barrier layer when another element is doped, so that different conductive type impurities are doped at the same time in one step at high temperature to form the first conductive type impurity region and the second conductive type impurity region, and only one high temperature step is required. doping, reducing the number of high-temperature doping times; since the present invention only has one step of co-doping, alkali polishing and alkali washing tank in RCA are not required before phosphorus doping, so there is no need to form a thicker BSG layer to block alkali polishing and alkali washing tank in RCA, so the oxygen content of the silicon wafer is reduced, reducing the recombination inside the solar cell and thus improving the photoelectric conversion efficiency; since the conventional production line route is boron doping before phosphorus doping, the boron doping temperature is as high as 1000°C, and high temperature is required to grow a thicker oxide layer and promote boron doping, while the preparation route of the present invention does not require the growth of a thicker oxide layer, eliminates the high-temperature boron doping process, simplifies the process flow, and reduces equipment investment costs.

[0040] As a preferred embodiment, the thickness of the dopant source layer of the first conductive type impurity is 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm. More preferably, the thickness of the dopant source layer of the first conductive type impurity is 50nm-100nm.

[0041] In the present invention, the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm. When the thickness is less than 10nm, it cannot serve as a barrier layer for the second conductive type impurities, and serious recombination will occur, resulting in a decrease in photoelectric conversion efficiency. When the thickness is greater than 100nm, the oxygen content of the silicon wafer will be high, and serious recombination will occur, resulting in a decrease in photoelectric conversion efficiency and photoinduced degradation.

[0042] As a preferred embodiment, the TBC cell includes a substrate silicon wafer, wherein the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, a dielectric region and a polysilicon layer are sequentially arranged on the back side of the substrate silicon wafer in a direction away from the substrate silicon wafer, and an impurity source layer of the first conductive type impurity is formed outside the polysilicon layer.

[0043] As a preferred embodiment, in the preparation method, before S1 forms the dielectric region, it also includes the steps of cleaning and polishing the substrate silicon wafer, the substrate silicon wafer is N-type or P-type, has a resistivity of 0.1Ωcm-3.0Ωcm, and a thickness of 100μm-200μm.

[0044] As a preferred embodiment, the cleaning and polishing utilizes acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer and to perform etching and polishing on the surface of the single crystal silicon wafer.

[0045] As a preferred embodiment, in the preparation method, after S4 co-doping with impurities of different conductive types in one step, it also sequentially includes laser selective doping, preparation of Gap area, texturing step, removal of the dopant source layer of the first conductive type impurities and RCA cleaning step, dielectric layer formation step, and metallization step.

[0046] As a preferred embodiment, the tunneling oxide layer and the polysilicon layer are formed by CVD in S1. In the CVD furnace tube, N2O is used as an oxidant, the oxidation temperature is 300℃-650℃, and the time is 60s-600s to form a tunneling oxide layer with a thickness of 1nm-3nm; SiH4 is used as a reaction gas and Ar is used as a dilution gas. The formation temperature is 300℃-650℃ and the time is 300s-3600s to form a polysilicon layer on the surface of the tunneling oxide layer with a thickness of 50 nm-400nm. The CVD method is PECVD or LPCVD.

[0047] As a preferred embodiment, the S2 forms a dopant source layer of the first conductive type impurities, and is formed by CVD, with a formation temperature of 300°C-800°C and a time of 1min-90min. The forming raw materials include a boron source gas or a phosphorus source gas, and the boron source gas is at least one of BH3, TMB, BCl3, and BBr3; the phosphorus source gas is at least one of PH3 and POCl3; and the CVD method is PECVD (Plasma Enhanced Chemical Vapor Deposition) or LPCVD.

[0048] As a preferred embodiment, the forming raw material also includes other gases, and the other gases are one or more gases of SiH4, N2O, NH3, Ar.

[0049] As a preferred embodiment, in the step of forming a dopant source layer of first conductive type impurities in S2, the dopant source layer of the first conductive type impurities is a silicon-containing compound layer containing first conductive type impurities, and the first conductive type impurities are boron, gallium or phosphorus.

[0050] As a preferred embodiment, in the step of film opening and cleaning in S3, the film opening method adopts at least one of laser, etching slurry, and photolithography. More preferably, laser film opening is adopted, and the parameters of laser film opening are set as follows: wavelength 200nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, and frequency 200kHz-2000kHz.

[0051] By adopting the above technical solution, the c-Si region or polysilicon layer region where the second conductive type impurity region will be formed in the future is laser-opened. The local dopant source layer of the first conductive type impurity is removed or thinned, and in this process, no doping is caused to the polysilicon region or c-Si region, or only a low concentration doping of one order of magnitude lower than the future doping concentration of this area is caused.

[0052] As a preferred embodiment, in the step of film opening and cleaning S3, the cleaning method includes one of acid cleaning, alkali cleaning, or acid cleaning followed by alkali cleaning.

[0053] More preferably, the cleaning method is acid cleaning.

[0054] The acid washing is performed using hydrofluoric acid with a concentration of 0.5%-50%. After washing, the first dopant source layer in the non-film-opening area is retained by at least 2nm, that is, the residual first dopant source concentration after washing is less than 1×10 19 cm -3 ; and there is no residue of the first dopant source layer in the film opening area.

[0055] By adopting the above technical solution, the film-opening area formed by laser film-opening provides a reserved area for the second conductive type impurity layer to be formed in the future. After cleaning the film-opening area, a polysilicon area or a c-Si area is reserved for forming the second conductive type impurity doping. The main purpose of cleaning here is to remove the doping source layer of the first doped conductive type impurity remaining on the surface of the polysilicon layer in the film-opening area or the doping source layer of the first doped conductive type impurity remaining on the surface of the c-Si, so as to ensure that the non-film-opening area and the film-opening area form a single conductive type impurity doping during one-step co-diffusion; and after cleaning, the doping source layer of the first doped conductive type impurity in the non-laser film-opening area needs to retain a sufficient thickness, in order to ensure that the first doping area has a sufficient doping concentration after one-step co-doping, and as a mask layer to prevent the doping material of the second conductive type impurity from being doped into the first doping area. The complete removal of the doping source layer of the first doped conductive type impurity and the doping source layer of the second doped conductive type impurity in the non-film-opening area will be completely removed in the subsequent RCA cleaning step.

[0056] As a preferred embodiment, the S4 different conductive type impurities are co-doped in one step, the silicon wafer is placed in a doping tube for doping, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used, and the doping temperature is 600℃-1000℃. As a more preferred embodiment, the doping temperature is 600℃-980℃, and the doping time is 5min-180min. The dopant source layer of the first conductive type impurity formed on the back of the silicon wafer can be used as a doping source and as a barrier layer for doping with another element during doping, so that different conductive type impurities are simultaneously doped at high temperature in one step to form a first conductive type impurity region and a second conductive type impurity region. The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the number of times the different conductive type impurities are co-doped in one step is at least once.

[0057] As a preferred embodiment, the doping source of the second conductive type impurity is a boron source gas or a phosphorus source gas, the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0058] As a preferred embodiment, before the S4 different conductive type impurities are co-doped in one step, it also includes laser selective doping, the wavelength of the laser selective doping is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, the frequency is 200kHz-2000kHz, and the laser selective doping obtains a local heavily doped area of ​​the conductive type impurity area.

[0059] As a preferred embodiment, after the laser selective doping, it also includes the preparation of the Gap area. The preparation of the Gap area is automatically formed by co-doping S4 impurities of different conductive types in one step or prepared by laser. The setting parameters of the laser preparation are: wavelength 200nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, frequency 200kHz-2000kHz.

[0060] As a preferred embodiment, the preparation step of the Gap area also includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer or a Gap area texturing surface on the back side, and the morphology and size of the front texturing surface and the Gap area texturing surface are the same or different.

[0061] As a preferred embodiment, the texturing step uses 0.5-2wt% of KOH, NaOH or one or more of them to perform texturing by corrosion, and the corrosion time is 400s-600s.

[0062] As a preferred embodiment, the step of removing the dopant source layer of the first conductive type impurities and the RCA cleaning step is to place the silicon wafer in a hydrofluoric acid concentration of 0.5%-50% for pickling, and the pickling time is 10s-1200s to remove the dopant source layer of the first conductive type impurities of the silicon wafer; and then perform standard RCA cleaning on the silicon wafer to remove surface contaminants.

[0063] As a preferred embodiment, in the step of forming a dielectric layer, the dielectric layer is at least composed of an anti-reflection film, and a 50-120nm anti-reflection film layer is formed by CVD. The reflective film layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0064] As a preferred implementation, the dielectric layer further includes a passivation film layer, the thickness of the passivation film layer is 2-15 nm, and the passivation film layer is aluminum oxide.

[0065] As a preferred embodiment, in the metallization step, a back metal electrode is provided on the silicon wafer, and the metal electrode is preferably a silver electrode, to obtain the TBC battery structure.

[0066] As a preferred implementation, the polysilicon layer is formed in S1, the dopant source layer of the first conductive type impurities is formed in S2, and the doping in S4 is all in dual insertion mode.

[0067] Since many working sections of the present invention are changed from a single-insertion mode to a double-insertion mode, production costs are saved, output is increased, and large-scale production is facilitated.

[0068] This embodiment also provides a TBC cell, comprising a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer comprising a front velvet surface and a second dielectric layer; the back side of the substrate silicon wafer comprising a dielectric region, a second conductive type impurity region, a first conductive type impurity region, a first dielectric layer, a metal electrode and a Gap region; The dielectric region is a tunnel oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm; The second conductive type impurity region and the first conductive type impurity region are formed simultaneously in one or more conductive dopant one-step co-doping steps; In the conductive dopant co-doping step, at least once, a doping source having impurities of a second conductivity type opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the local area of ​​the metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0069] As a preferred embodiment, the c-Si region or polysilicon layer of the second conductive type impurity region is formed by film opening and cleaning, the film opening method is at least one of laser, etching slurry, and photolithography, the cleaning method includes at least one of acid washing, alkali washing, and acid washing followed by alkali washing, and the one-step co-doping includes a high-temperature process using a doping source of a second conductive type impurity with opposite electrical properties to the first conductive type impurity. The one-step co-doping is to achieve doping of the doping sources of the first conductive type impurity and the second conductive type impurity under the same high temperature conditions.

[0070] Preferably, the film opening method in the S3 film opening and cleaning is laser film opening, and the cleaning method is acid cleaning.

[0071] As a preferred embodiment, a Gap area velvet is also provided on the back side of the substrate silicon wafer, and the Gap area velvet has the same or different morphology and size as the front velvet; the first conductive type impurity region, and / or the second conductive type impurity region is also provided with a heavily doped region.

[0072] This embodiment also provides another TBC cell, comprising a substrate silicon wafer, wherein the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, wherein the front side of the substrate silicon wafer comprises a front velvet surface and a second dielectric layer; and the back side of the substrate silicon wafer comprises a dielectric region, a second conductive type impurity region, a first conductive type impurity region, a first dielectric layer, a metal electrode and a Gap region; The local region of the electrode penetrates the first dielectric layer to form an ohmic contact with the second conductive type impurity region; the local region of the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity region; The dielectric region is a tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities.

[0073] The TBC battery and the preparation method thereof of the present invention are further described below through specific examples and comparative examples.

[0074] Example 1

[0075] like Figure 1 As shown, an N-type TBC battery includes an N-type silicon wafer 3, which is a substrate silicon wafer, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3; a local area of ​​the electrode penetrates the first dielectric layer and forms an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; a local area of ​​the electrode penetrates the first dielectric layer and forms an ohmic contact with the first conductive type impurity polysilicon region.

[0076] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0077] like Figure 2 As shown, the method for preparing an N-type TBC battery in this embodiment includes the following steps: ① Select a P-doped N-type silicon wafer with a resistivity of 1.5Ωcm and a thickness of 150μm; use acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0078] ② In the PECVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 500℃, and the time is 300s. A tunneling oxide layer with a thickness of 3nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas, Ar is used as the dilution gas, the formation temperature is 500℃, and the time is 1800s. A polysilicon layer with a thickness of 250nm is formed on the surface of the tunneling oxide layer.

[0079] ③ In a PECVD furnace tube, PH3, SiH4, N2O, Ar, and NH3 are used as raw materials, the formation temperature is 600°C, and the time is 50 minutes to form a phosphorus-containing silicon oxide layer with a thickness of 50nm on the polysilicon layer.

[0080] ④ Use laser to open the film of silicon wafer. The laser setting parameters are wavelength 200nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz, and then clean it in a cleaning machine. The cleaning method is acid pickling and drying after cleaning to expose the local polysilicon layer on the back of the silicon wafer.

[0081] ⑤ Place the silicon wafer into a boron-doped tube for one-step co-doping of boron and phosphorus. The doping temperature is 800°C, the doping time is 100 minutes, the boron doping source is BBr3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. At the same time, the phosphorus-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a barrier layer for boron doping. The number of one-step co-doping of boron and phosphorus is 2 times. When laser selective doping is performed, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz to produce a heavily doped region of the second conductive type impurity polysilicon region.

[0082] ⑥ Use laser to prepare Gap area on silicon wafer, the laser setting parameters are wavelength 600nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz, and then pickling, water washing and drying in a cleaning machine.

[0083] ⑦ Use 1.3% NaOH solution for etching for 500s to prepare the front velvet surface on the front side of the silicon wafer and the Gap area velvet surface on the back side (not shown in the figure), and then use acid and alkali solution to polish the pyramid velvet surface in the Gap area to make the pyramid velvet surface in the Gap area smooth and flat.

[0084] ⑧Put the silicon wafer in 25% HF for pickling for 600s to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0085] ⑨ The ALD atomic layer formation method is adopted, TMA is used as the precursor, and the reaction temperature is controlled at 300°C to form a dense Al2O3 passivation layer with a thickness of 10nm on the front and back of the silicon wafer. The LPCVD method is then used to form a 100nm SiNx anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0086] ⑩ Print Ag paste on the back of the silicon wafer, dry and sinter to obtain the back metal electrode.

[0087] Example 2

[0088] An N-type TBC battery comprises an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3.

[0089] The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0090] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 10 nm.

[0091] The method for preparing an N-type TBC battery in this embodiment comprises the following steps: ① Select a P-doped N-type silicon wafer with a resistivity of 0.1Ωcm and a thickness of 100μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0092] ② In the LPCVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 300℃, and the time is 600s. A tunneling oxide layer with a thickness of 2nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas and Ar is used as the dilution gas. The formation temperature is 300℃ and the time is 3600s. A polysilicon layer with a thickness of 50nm is formed on the surface of the tunneling oxide layer.

[0093] ③ In a PECVD furnace tube, POCl3, SiH4, N2O, Ar, and NH3 are used as raw materials, the formation temperature is 300°C, and the time is 5 minutes. A phosphorus-containing silicon oxide layer with a thickness of 10 nm is deposited on the polysilicon layer.

[0094] ④ Use laser to open the film of silicon wafer. The laser setting parameters are wavelength 200nm, power ≥1W, scanning speed 5m / s, frequency 2000kHz, and then clean it in a cleaning machine. The cleaning method is acid pickling and drying after cleaning to expose the local polysilicon layer on the back of the silicon wafer.

[0095] ⑤ Place the silicon wafer into a boron-doped tube for one-step co-doping of boron and phosphorus. The doping temperature is 600°C, the doping time is 180 minutes, the boron doping source is BBr3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. The phosphorus-containing silicon oxide layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a barrier layer for boron doping. The number of one-step co-doping of boron and phosphorus is 4 times. When laser selective doping is performed, the wavelength is set to 1064nm, the scanning speed is 50m / s, and the frequency is 2000kHz to produce a heavily doped region of the second conductive type impurity polysilicon region.

[0096] ⑥ Use laser to prepare Gap area on silicon wafer with wavelength of 200nm, power ≥1W, scanning speed of 5m / s and frequency of 2000kHz, and then pickle, wash and dry in a cleaning machine.

[0097] ⑦ Use 0.5% NaOH solution for etching for 600s to prepare the front velvet surface on the front side of the silicon wafer and the Gap area velvet surface on the back side (not shown in the figure), and then use acid and alkali solution to polish the pyramid velvet surface in the Gap area to make the pyramid velvet surface in the Gap area smooth and flat.

[0098] ⑧Put the silicon wafer in 0.5% HF for pickling for 1200s to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0099] ⑨ A 50nm SiNx anti-reflection layer is formed on the front and back surfaces of the silicon wafer by using the PECVD method, and the anti-reflection layer forms a dielectric layer.

[0100] ⑩ Print Ag paste on the back of the silicon wafer, dry and sinter to obtain the back metal electrode.

[0101] Example 3

[0102] An N-type TBC battery comprises an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3.

[0103] The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0104] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 100 nm.

[0105] The method for preparing an N-type TBC battery in this embodiment comprises the following steps: ① Select a P-doped N-type single crystal silicon wafer with a resistivity of 3Ωcm and a thickness of 200μm; use acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0106] ② In the LPCVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 650℃, the time is 60s, and a tunneling oxide layer with a thickness of 4nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas, Ar is used as the dilution gas, the formation temperature is 650℃, the time is 300s, and a polysilicon layer with a thickness of 400nm is formed on the surface of the tunneling oxide layer.

[0107] ③ In the LPCVD furnace tube, PH3, SiH4, N2O, Ar, and NH3 are used as raw materials, the formation temperature is 800°C, and the time is 90 minutes to form a phosphorus-containing silicon oxide layer with a thickness of 100nm on the polysilicon layer.

[0108] ④ Use laser to open the film of silicon wafer. The laser setting parameters are wavelength 1064nm, power ≥1W, scanning speed 50m / s, frequency 200kHz, and then clean it in a cleaning machine. The cleaning method is acid pickling and drying after cleaning to expose the local polysilicon layer on the back of the silicon wafer.

[0109] ⑤ Place the silicon wafer into a boron-doped tube for one-step co-doping of boron and phosphorus. The doping temperature is 1000°C, the doping time is 5 minutes, the boron doping source is BBr3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. The phosphorus-containing silicon oxide layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a barrier layer for boron doping. The number of one-step co-doping of boron and phosphorus is 1. When laser selective doping is performed, the wavelength is set to 200nm, the scanning speed is 5m / s, and the frequency is 200kHz to produce a heavily doped region of the second conductive type impurity polysilicon region.

[0110] ⑥ Use laser to prepare Gap area on silicon wafer, with wavelength of 1064nm, power ≥1W, scanning speed of 50m / s, frequency of 200kHz, and then pickle, wash and dry in a cleaning machine.

[0111] ⑦ Use 2% NaOH solution for etching for 400s to prepare the front velvet surface on the front side of the silicon wafer and the Gap area velvet surface on the back side (not shown in the figure), and then use acid and alkali solution to polish the pyramid velvet surface in the Gap area to make the pyramid velvet surface in the Gap area smooth and flat.

[0112] ⑧Put the silicon wafer in 50% HF for pickling for 10 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0113] ⑨ The ALD atomic layer formation method is adopted, TMA is used as the precursor, and the reaction temperature is controlled at 300°C to form a dense Al2O3 passivation layer with a thickness of 15nm on the front and back of the silicon wafer. The PECVD method is then used to form a 120nm SiNx anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0114] ⑩ Print Ag paste on the back of the silicon wafer, dry and sinter to obtain the back metal electrode.

[0115] Example 4

[0116] An N-type TBC battery, comprising an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0117] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0118] The preparation method of this embodiment is different from that of embodiment 1 in that: the doping temperature in ⑤ is 950°C.

[0119] Example 5

[0120] A P-type TBC battery, comprising a P-type silicon wafer, a second dielectric layer arranged on the front side of the P-type silicon wafer, a front velvet surface; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of the P-type silicon wafer, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0121] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0122] The preparation method of this embodiment is different from that of embodiment 1 in that: ① The single crystal silicon wafer is a B-doped P-type single crystal silicon wafer; ③ Using BH3, SiH4, N2O, Ar, and NH3 as formation sources, a boron-containing silicon oxide layer with a thickness of 50 nm is formed; ⑤ Place the silicon wafer into a phosphorus-doped tube for boron-phosphorus co-doping, the doping temperature is 800°C, the doping time is 100 minutes, the phosphorus doping source is POCl3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. The boron-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a barrier layer for phosphorus doping. During laser selective doping, a heavily doped region of the second conductive type impurity polysilicon region is produced; The rest are the same.

[0123] Example 6

[0124] An N-type TBC battery, comprising an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0125] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 8 nm.

[0126] The preparation method of this embodiment is different from that of embodiment 2 in that: ③ A phosphorus-containing silicon oxide layer with a thickness of 8 nm formed; The rest are the same.

[0127] Example 7

[0128] An N-type TBC battery, comprising an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0129] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 103 nm.

[0130] The preparation method of this embodiment is different from that of embodiment 3 in that: ③ The phosphorus-containing silicon oxide layer formed in the step has a thickness of 103 nm; The rest are the same.

[0131] Example 8

[0132] like Figure 3 As shown, an N-type TBC battery comprises an N-type silicon wafer 3, a front velvet surface 2 and a second dielectric layer 1 are sequentially arranged on the front side of the N-type silicon wafer 3 from the inside to the outside; a tunneling oxide layer 4 is arranged on the back side of the N-type silicon wafer 3, a second conductive type impurity polysilicon region and a heavily doped region 5 are arranged outside the tunneling oxide layer 4, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 is arranged in the tunneling oxide layer 4, the second conductive type impurity polysilicon region and the heavily doped region 5 and the first conductive type impurity polysilicon region 9 are respectively arranged between the tunneling oxide layer 4, and the Gap region 8 is arranged, and the impurity electrical properties of the second conductive type impurity polysilicon region and the heavily doped region 5 and the first conductive type impurity polysilicon region 9 are different; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0133] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0134] A method for preparing an N-type TBC battery Figure 4 As shown, the preparation method of this embodiment is different from that of embodiment 1 in that: ⑤ The gap area does not require laser formation: when boron and phosphorus are co-doped in one step, there is a large amount of boron and phosphorus compound in the adjacent parts of the first conductive type impurity region and the second conductive type impurity region, which is basically non-conductive and automatically forms a gap area.

[0135] Missing ⑥; The rest are the same.

[0136] Example 9

[0137] An N-type TBC battery, comprising an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0138] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 10 nm.

[0139] The preparation method of this embodiment is different from that of embodiment 2 in that: ⑤ The gap area does not require laser formation: when boron and phosphorus are co-doped in one step, there is a large amount of boron and phosphorus compound in the adjacent parts of the first conductive type impurity region and the second conductive type impurity region, which is basically non-conductive and automatically forms a gap area.

[0140] Missing ⑥; The rest are the same.

[0141] Example 10

[0142] An N-type TBC battery, comprising an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0143] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 100 nm.

[0144] The preparation method of this embodiment is different from that of embodiment 3 in that: ⑤ The gap area does not require laser formation: when boron and phosphorus are co-doped in one step, there is a large amount of boron and phosphorus compound in the adjacent parts of the first conductive type impurity region and the second conductive type impurity region, which is basically non-conductive and automatically forms a gap area.

[0145] Missing ⑥; The rest are the same.

[0146] Embodiment 11

[0147] A P-type TBC battery, comprising a P-type silicon wafer, a second material layer and a front velvet surface arranged on the front side of the P-type silicon wafer; a tunneling oxide layer, a second conductive type impurity polysilicon region and a heavily doped region arranged on the back side of an N-type silicon wafer 3, a first dielectric layer, an electrode, a gap region, and a first conductive type impurity polysilicon region; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0148] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0149] The preparation method of this embodiment is different from that of embodiment 8 in that: ① The single crystal silicon wafer is a B-doped P-type single crystal silicon wafer; ③ Using TMB, SiH4, N2O, Ar, and NH3 as formation sources, a boron-containing silicon-oxygen compound layer with a thickness of 50 nm is formed; ⑤ Place the silicon wafer into a phosphorus-doped tube for boron-phosphorus co-doping, the doping temperature is 800°C, the doping time is 100 minutes, the phosphorus doping source is POCl3, and a second conductive type impurity polysilicon region is formed on the back of the silicon wafer. The boron-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity region to form the first conductive type impurity polysilicon region, and can also be used as a barrier layer for phosphorus doping. During laser selective doping, a heavily doped region of the second conductive type impurity polysilicon region is produced; The rest are the same.

[0150] Example 12

[0151] An N-type TBC battery, comprising an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0152] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 8 nm.

[0153] The preparation method of this embodiment is different from that of embodiment 9 in that: The thickness of the phosphorus-containing silicon oxide compound layer formed in ③ is 8nm; The rest are the same.

[0154] Embodiment 13

[0155] An N-type TBC battery, comprising an N-type silicon wafer 3, a second dielectric layer 1 and a front velvet surface 2 arranged on the front side of the N-type silicon wafer 3; a tunneling oxide layer 4, a second conductive type impurity polysilicon region and a heavily doped region 5, a first dielectric layer 6, an electrode 7, a gap region 8, and a first conductive type impurity polysilicon region 9 arranged on the back side of the N-type silicon wafer 3; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon region; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0156] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 103 nm.

[0157] The preparation method of this embodiment is different from that of embodiment 10 in that: The thickness of the phosphorus-containing silicon oxide compound layer formed in ③ is 103nm; The rest are the same.

[0158] Embodiment 14

[0159] like Figure 5As shown, an N-type TBC battery comprises an N-type silicon wafer 3, a second dielectric layer 1 arranged on the front side of the N-type silicon wafer 3, a front velvet surface 2, a second conductive type impurity c-Si region and a heavily doped region 10 arranged on the back side of the N-type silicon wafer 3, a first dielectric layer 6, a tunneling oxide layer 4, a first conductive type impurity polysilicon region 9, a gap region 8, and an electrode 7; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0160] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0161] A method for preparing an N-type TBC battery Figure 6 As shown, the preparation method of this embodiment is different from that of embodiment 1 in that: ④ Laser film opening and cleaning of the back of the silicon wafer to expose the c-Si area on the back of the silicon wafer; ⑥The location and depth of the Gap area are different; The rest are the same.

[0162] Embodiment 15

[0163] An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0164] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 10 nm.

[0165] The preparation method of this embodiment is different from that of embodiment 2 in that: ④ Laser film opening and cleaning of the back of the silicon wafer to expose the c-Si area on the back of the silicon wafer; ⑥The location and depth of the Gap area are different; The rest are the same.

[0166] Example 16

[0167] An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0168] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 100 nm.

[0169] The preparation method of this embodiment is different from that of embodiment 3 in that: ④ Laser film opening and cleaning of the back of the silicon wafer to expose the c-Si area on the back of the silicon wafer; ⑥The location and depth of the Gap area are different; The rest are the same.

[0170] Embodiment 17

[0171] A P-type TBC battery, comprising a P-type silicon wafer, a second dielectric layer arranged on the front side of the P-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the P-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0172] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0173] The preparation method of this embodiment is different from that of embodiment 14 in that: ① The single crystal silicon wafer is a B-doped P-type single crystal silicon wafer; ③ Using BH3, SiH4, N2O, Ar, and NH3 as formation sources, a boron-containing silicon oxide layer with a thickness of 50 nm is formed; ⑤ Place the silicon wafer into a phosphorus-doped tube for boron-phosphorus co-doping, the doping temperature is 800°C, the doping time is 100 minutes, the phosphorus doping source is POCl3, and a second conductive type impurity c-Si region is formed on the back of the silicon wafer. The boron-containing silicon oxide layer on the back can be used as a doping source for the first conductive type impurity region to form a first conductive type impurity polysilicon region, and can also be used as a barrier layer for phosphorus doping. During laser selective doping, a heavily doped region of the second conductive type impurity c-Si region is produced; The rest are the same.

[0174] Embodiment 18

[0175] An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0176] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 8 nm.

[0177] The preparation method of this embodiment is different from that of embodiment 15 in that: ③ The thickness of the phosphorus-containing silicon oxide compound layer formed is 8nm; The rest are the same.

[0178] Embodiment 19

[0179] An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, a gap region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0180] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 103 nm.

[0181] The preparation method of this embodiment is different from that of embodiment 16 in that: ③ The thickness of the phosphorus-containing silicon oxide compound layer formed is 103nm; The rest are the same.

[0182] Embodiment 20

[0183] like Figure 7 As shown, an N-type TBC battery comprises an N-type silicon wafer 3, a second dielectric layer 1 arranged on the front side of the N-type silicon wafer 3, a front velvet surface 2, a second conductive type impurity c-Si region and a heavily doped region 10 arranged on the back side of the N-type silicon wafer 3, a first dielectric layer 6, a tunneling oxide layer 4, a first conductive type impurity polysilicon region 9, and an electrode 7; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0184] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0185] A preparation process of an N-type TBC battery is as follows Figure 8 shown.

[0186] The preparation method of this embodiment is different from that of embodiment 14 in that: Missing ⑥; The rest are the same.

[0187] Embodiment 21

[0188] An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0189] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 10 nm.

[0190] The preparation method of this embodiment is different from that of embodiment 15 in that: Missing ⑥; The rest are the same.

[0191] Embodiment 22

[0192] An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0193] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 100 nm.

[0194] The preparation method of this embodiment is different from that of embodiment 16 in that: Missing ⑥; The rest are the same.

[0195] Embodiment 23

[0196] An N-type TBC battery, comprising a P-type silicon wafer, a second dielectric layer arranged on the front side of the P-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0197] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0198] The preparation method of this embodiment is different from that of embodiment 20 in that: ① The single crystal silicon wafer is a B-doped P-type single crystal silicon wafer; ③ Using BH3, SiH4, N2O, Ar, and NH3 as formation sources, a boron-containing silicon-oxygen compound layer with a thickness of 50 nm is formed; ⑤ Place the silicon wafer into a phosphorus-doped tube for boron-phosphorus co-doping, the doping temperature is 800°C, the doping time is 100 minutes, the phosphorus doping source is POCl3, and a second conductive type impurity c-Si region is formed on the back of the silicon wafer. The boron-containing silicon oxide layer on the back can be used as a doping source for the first conductive type impurity region to form a first conductive type impurity polysilicon region, and can also be used as a barrier layer for phosphorus doping. During laser selective doping, a heavily doped region of the second conductive type impurity c-Si region is produced; The rest are the same.

[0199] Embodiment 24

[0200] An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0201] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 8 nm.

[0202] The preparation method of this embodiment is different from that of embodiment 21 in that: ③ The thickness of the phosphorus-containing silicon oxide compound layer formed is 8nm; The rest are the same.

[0203] Embodiment 25

[0204] An N-type TBC battery, comprising an N-type silicon wafer, a second dielectric layer arranged on the front side of the N-type silicon wafer, a front velvet surface, a second conductive type impurity c-Si region and a heavily doped region arranged on the back side of the N-type silicon wafer, a first dielectric layer, a tunneling oxide layer, a first conductive type impurity polysilicon region, and electrodes; The local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped c-Si region of the second conductive type impurity; the local area of ​​the electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon region.

[0205] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 103 nm.

[0206] The preparation method of this embodiment is different from that of embodiment 22 in that: ③ The thickness of the phosphorus-containing silicon oxide compound layer formed is 103nm; The rest are the same.

[0207] Comparative Example 1 This comparative example is a conventional TBC battery preparation method: S1 selects a P-doped N-type silicon wafer with a resistivity of 1.5Ωcm and a thickness of 150μm; uses acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, and performs 2 etching and polishing on the surface of the single crystal silicon wafer.

[0208] S2 is oxidized in an LPCVD furnace tube with N2O as the oxidant, an oxidation temperature of 600°C, and a time of 3 minutes to form a tunneling oxide layer with a thickness of 3nm on the back of the silicon wafer; SiH4 is used as the reaction gas and Ar is used as the dilution gas, a formation temperature of 600°C, and a time of 90 minutes to form a polysilicon layer with a thickness of 250nm on the surface of the tunneling oxide layer.

[0209] S3: Put the silicon wafer into a boron doping tube for boron doping, using boron trichloride as the boron source, and doping for 180 minutes at 1000°C. The thickness of the formed BSG layer is 150nm. S4 forms a 50nm oxide layer as a mask layer by thermal oxidation; S5 uses laser to open the film of silicon wafer. The laser setting parameters are wavelength 200nm, power ≥1W, scanning speed 5m / s, frequency 1000kHz, and then it is cleaned in a cleaning machine. The cleaning method is acid pickling and drying after cleaning.

[0210] S6 uses LPCVD to form a 3nm tunnel oxide layer and a 250nmnm polysilicon layer.

[0211] S7 puts the silicon wafer into a phosphorus doping tube for phosphorus doping, using phosphorus oxychloride as the phosphorus source, and doping is carried out at 800-900°C for 120 minutes. During sintering, the wavelength is set to 532nm and the pulse energy is set to 300μJ to produce P+ and P++ polysilicon layers in the P zone.

[0212] S8 uses laser to prepare Gap area on silicon wafer, with wavelength of 200nm, power ≥1W, scanning speed of 5m / s, frequency of 2000kHz, and then pickling, washing and drying in a cleaning machine.

[0213] S9 uses a 0.5% NaOH solution for etching, with an etching time of 600 seconds, to prepare a velvet surface on the front side of the silicon wafer.

[0214] S10: The silicon wafer is placed in 0.5% HF for pickling for 1200 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; the silicon wafer is then cleaned according to the RCA standard to remove surface contaminants.

[0215] S11 adopts the ALD atomic layer formation method, with TMA as the precursor. The reaction temperature is controlled at 300°C to form a dense Al2O3 passivation layer with a thickness of 6nm on the front and back of the silicon wafer. The PECVD method is used to form a 70nm SiO2 anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0216] S12 prints Ag paste on the back of the silicon wafer, and after drying and sintering, obtains the back metal electrode.

[0217] The batteries in Examples 1-25 and Comparative Example 1 were tested under the same conditions. The test results are shown in Table 1.

[0218] Table 1 Test results of battery of embodiment and comparative example ; As can be seen from Table 1, from the comparison of the test data of Examples 1-25 and Comparative Example 1, it can be seen that when the TBC battery adopts a dopant source layer that first forms a layer of first conductive type impurities, the open circuit voltage, short circuit current and fill factor of the battery are improved, thereby improving the conversion efficiency of the battery; the process time for battery preparation is also shortened. It can be seen from the test data of Examples 1-5 and 6-7 that when the thickness of the dopant source layer of the first conductive type impurity is between 10nm and 100nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better; it can be seen from the test data of Examples 8-11 and 12-13 that when the thickness of the dopant source layer of the first conductive type impurity is between 10nm and 100nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better; it can be seen from the test data of Examples 14-17 and 18-19 that when the thickness of the dopant source layer of the first conductive type impurity is between 10nm and 100nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better; it can be seen from the test data of Examples 20-23 and 24-25 that when the thickness of the dopant source layer of the first conductive type impurity is between 10nm and 100nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better.

[0219] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description here should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in the field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that: The steps include: S1 forms a dielectric region and a polysilicon layer; S2 forms a dopant source layer of first conductivity type impurities; S3 film opening and cleaning; S4 co-doping of impurities of different conductivity types in one step; The thickness of the dopant source layer of the first conductive type impurity is 10nm-100nm; The TBC cell includes a substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, a dielectric region and a polysilicon layer being sequentially arranged on the back side of the substrate silicon wafer in a direction away from the substrate silicon wafer, and an impurity source layer of the first conductive type impurities being formed outside the polysilicon layer.

2. The method for preparing a TBC battery according to claim 1, characterized in that: In the step of forming the dielectric region and the polysilicon layer in S1, the formation is carried out by CVD at a temperature of 300° C.-650° C.

3. The method for preparing a TBC battery according to claim 1, characterized in that: The S2 forms a dopant source layer of first conductivity type impurities, which is formed by CVD at a temperature of 300° C. to 800° C. and the raw materials include boron source gas or phosphorus source gas; The boron source gas is at least one of BH3, TMB, BCl3, and BBr3; The phosphorus source gas is at least one of PH3 and POCl3.

4. The method for preparing a TBC battery according to claim 1, characterized in that: In the step of forming a dopant source layer of first conductivity type impurities in S2, the dopant source layer of the first conductivity type impurities is a silicon-containing compound layer containing first conductivity type impurities, and the first conductivity type impurities are boron, gallium or phosphorus.

5. The method for preparing a TBC battery according to claim 1, characterized in that: The film opening method in the S3 film opening and cleaning is laser film opening, and the parameters of the laser film opening are set as: wavelength 200nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, frequency 200kHz-2000kHz.

6. The method for preparing a TBC battery according to claim 5, characterized in that: The cleaning method in the S3 film opening and cleaning is pickling, using hydrofluoric acid with a concentration of 0.5%-50% for pickling.

7. The method for preparing a TBC battery according to claim 1, characterized in that: The doping temperature of the S4 different conductivity type impurities co-doped in one step is 600° C.-1000° C., and the doping time is 5 min-180 min.

8. The method for preparing a TBC battery according to claim 1, characterized in that: In the S4 one-step co-doping of different conductive type impurities, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used to simultaneously form a first conductive type impurity region and a second conductive type impurity region, the first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the number of times the different conductive type impurities are co-doped in one step is at least once.

9. The method for preparing a TBC battery according to claim 1, characterized in that: After the S4 step of co-doping different conductive type impurities in one step, it also includes a step of preparing a Gap area. In the preparation step of the Gap area, the Gap area is automatically formed by executing the S4 step of co-doping different conductive type impurities in one step or is prepared by laser. The setting parameters of the laser preparation are: wavelength 200nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, and frequency 200kHz-2000kHz.

10. The method for preparing a TBC battery according to claim 9, characterized in that: The preparation step of the Gap area also includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer or a Gap area texturing surface on the back side, and the morphology and size of the front texturing surface and the Gap area texturing surface are the same or different.

11. The method for preparing a TBC battery according to claim 1, characterized in that: Before the S4 step of co-doping different conductive type impurities, it also includes a laser selective doping step, the wavelength of the laser selective doping is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, the frequency is 200kHz-2000kHz, and the laser selective doping obtains a local heavily doped region of the conductive type impurity region.

12. A TBC battery prepared by the method for preparing a TBC battery according to any one of claims 1 to 11, characterized in that: The invention comprises a substrate silicon wafer, wherein the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, wherein the front side of the substrate silicon wafer comprises a front velvet surface and a second dielectric layer; and the back side of the substrate silicon wafer comprises a dielectric region, a second conductive type impurity region, a first conductive type impurity region, a first dielectric layer, a metal electrode and a Gap region; The dielectric region is a tunnel oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm; The second conductive type impurity region and the first conductive type impurity region are formed simultaneously in one or more conductive dopant one-step co-doping steps; In the conductive dopant co-doping step, at least once, a doping source having impurities of a second conductivity type opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the local area of ​​the metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

13. A TBC battery according to claim 12, characterized in that: The c-Si region or polysilicon layer of the second conductive type impurity region is formed by film opening and cleaning, the film opening method is at least one of laser, etching slurry, and photolithography, the cleaning method includes at least one of acid washing, alkaline washing, and acid washing followed by alkaline washing, and the one-step co-doping is to achieve the doping of the doping sources of the first conductive type impurities and the second conductive type impurities under the same high temperature conditions.

14. A TBC battery according to claim 12, characterized in that: A Gap region velvet surface is also provided on the back side of the substrate silicon wafer, and the Gap region velvet surface has the same or different morphology and size as the front velvet surface; the first conductive type impurity region and / or the second conductive type impurity region are also provided with a heavily doped region.

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